Semiconductor devices and their manufacturing methods

Abstract

A passivation layer and conductive vias are provided, wherein the transmittance of imaging energy is increased within the material of the passivation layer. This increased transmittance allows for greater cross-linking, which helps to increase control over the profile of the openings formed within the passivation layer. Once the openings are formed, conductive vias can be formed within them. Embodiments of the invention also relate to semiconductor devices and methods of manufacturing the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this increase in integration density stems from iterative reductions in the smallest component size (e.g., shrinking semiconductor process nodes towards sub-20nm nodes), allowing more components to be integrated into a given area. With the recent growth in demand for miniaturization, higher speeds and greater bandwidth, as well as lower power consumption and latency, there is a growing need for smaller and more innovative packaging technologies for semiconductor dies.

[0003] With the further development of semiconductor technology, stacked and bonded semiconductor devices have emerged as an effective alternative to further reduce the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, and processor circuits are at least partially fabricated on separate substrates and then physically and electrically bonded together to form a functional device. Such bonding processes utilize complex techniques and are expected to be improved. Summary of the Invention

[0004] An embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising: forming a redistribution layer over a substrate; applying a first dielectric material to the redistribution layer and the substrate, wherein the first dielectric material has a transmittance to a first energy greater than 0.5%; and imaging the first dielectric material with the first energy.

[0005] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising: applying a dielectric coating onto a carrier substrate; initiating crosslinking within the dielectric coating by exposing the dielectric coating to a patterned energy source, wherein, after initiating crosslinking, a first region of the dielectric coating has a higher degree of crosslinking than a second region of the dielectric coating, the first region being located between the second region and the carrier substrate; developing the dielectric coating to form a via; and forming a conductive via in the via.

[0006] Another embodiment of the present invention provides a semiconductor device comprising: a first dielectric layer; a first via extending through the first dielectric layer, the first via having a tapered sidewall angle between 55° and 78°; a second via extending through a carrier substrate, the second via being electrically connected to the first via; and a first semiconductor die located above the side of the carrier substrate opposite to the first via, the first semiconductor die being electrically connected to the second via. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 A carrier according to some embodiments is shown.

[0009] Figure 2 The formation of a redistribution layer according to some embodiments is illustrated.

[0010] Figure 3 The formation of a first passivation layer according to some embodiments is shown.

[0011] Figures 4A to 4B The patterning of the first passivation layer according to some embodiments is shown.

[0012] Figure 5 The formation of a second redistribution layer according to some embodiments is shown.

[0013] Figure 6 The formation of a third redistribution layer according to some embodiments is shown.

[0014] Figure 7 The formation of a third passivation structure according to some embodiments is shown.

[0015] Figure 8 The removal of the film strip according to some embodiments is shown.

[0016] Figure 9 The attachment of a carrier wafer according to some embodiments is shown.

[0017] Figure 10 The formation of a fourth redistribution layer according to some embodiments is shown.

[0018] Figure 11 The placement of a first semiconductor device according to some embodiments is shown.

[0019] Figure 12 The placement of the sealant according to some embodiments is shown.

[0020] Figure 13 The formation of a first set of redistribution layers according to some embodiments is shown.

[0021] Figure 14 The placement of a second semiconductor device according to some embodiments is shown.

[0022] Figure 15 The attachment of a ring structure according to some embodiments is shown.

[0023] Figure 16 The formation of a second external connection according to some embodiments is shown.

[0024] Figure 17 A system-on-a-wafer according to some embodiments is shown.

[0025] Figure 18 An integrated substrate-on-a-system is shown according to some embodiments. Detailed Implementation

[0026] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the individual embodiments and / or configurations discussed.

[0027] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0028] Embodiments will now be described with reference to specific structures and materials, such as integrated fan-out packages. However, the embodiments described herein can be used in various embodiments, and all such embodiments are fully intended to be included within the scope of these embodiments.

[0029] Now for reference Figure 1 The diagram illustrates a carrier 101, a thin film strip 103 located on a first side of the carrier 101, and a first seed layer 105 formed on the carrier 101. In embodiments, the carrier may comprise materials such as aluminum nitride (AlN), silicon oxide, silicon, aluminum oxide, or combinations thereof. Furthermore, the carrier 101 is shaped to accommodate the formation of the layers above. However, any suitable material and shape can be utilized.

[0030] Furthermore, the carrier 101 includes a first opening 107 extending through the carrier 101. The first opening 107 is positioned to facilitate the formation of a conductive via 203 (in... Figure 1Not shown in the image, but referenced below. Figure 2 (Further illustration and discussion will follow). In one embodiment, photolithography and etching processes can be used to form the first opening 107. However, any suitable process can be utilized.

[0031] The film tape 103 is placed and positioned along a first side of the carrier 101. In an embodiment, the film tape 103 may be a UV tape, which loses its adhesive properties when exposed to ultraviolet light. However, other types of tapes, such as pressure-sensitive tapes, radiation-curable tapes, combinations thereof, etc., may also be used. Any suitable film tape 103 may be utilized.

[0032] A first seed layer 105 is formed over the carrier 101 and within the first opening 107. In an embodiment, the first seed layer 105 is a thin layer of conductive material that facilitates the formation of a thicker layer during subsequent processing steps. The first seed layer 105 may include a titanium layer approximately 1000 angstroms thick and a subsequent copper layer approximately 5000 angstroms thick. Depending on the desired material, the first seed layer 105 may be produced using processes such as sputtering, evaporation, or PECVD. The first seed layer 105 may be formed to have a thickness between approximately 0.3 μm and approximately 1 μm, such as approximately 0.5 μm.

[0033] Figure 2 This illustrates the formation of a first redistribution layer 201 and through-holes 203 on and through the carrier 101. In an embodiment, this is achieved by first forming photoresist on the first seed layer 105. Figure 2 (Not shown separately) to form the first redistribution layer 201 and the through-hole 203. In an embodiment, photoresist can be placed on the first seed layer 105 at a height between about 50 μm and about 250 μm, such as about 120 μm, using, for example, spin coating techniques. Once in place, the photoresist can then be patterned by exposing it to a patterned energy source (e.g., a patterned light source) to induce a chemical reaction, thereby causing physical changes in those portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to utilize the physical changes and selectively remove the exposed or unexposed portions of the photoresist according to the desired pattern.

[0034] In an embodiment, the pattern formed in the photoresist is a pattern for the through-hole 203 and the first redistribution layer 201. Once the photoresist is in place, the through-hole 203 and the first redistribution layer 201 are formed within the photoresist. In an embodiment, the through-hole 203 and the first redistribution layer 201 comprise one or more conductive materials, such as copper, tungsten, other conductive metals, etc., and can be formed, for example, by electroplating, electroless plating, etc. In an embodiment, an electroplating process is used, wherein the first seed layer 105 and the photoresist are immersed or submerged in an electroplating solution. The surface of the first seed layer 105 is electrically connected to the negative side of an external DC power supply, such that the first seed layer 105 serves as a cathode in the electroplating process. A solid conductive anode (such as a copper anode) is also immersed in the solution and attached to the positive side of the power supply. Atoms from the anode dissolve into the solution, and the cathode (e.g., the first seed layer 105) acquires the dissolved atoms from the solution, thereby plating the exposed conductive region of the first seed layer 105 within the opening of the photoresist.

[0035] Once the through-hole 203 and the first redistribution layer 201 have been formed using photoresist and the first seed layer 105, the photoresist can be removed using a suitable removal process. In this embodiment, a plasma ashing process can be used to remove the photoresist, thereby increasing the temperature of the photoresist until it undergoes thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, can be utilized. Removal of the photoresist can expose portions of the underlying first seed layer 105.

[0036] Once exposed, the exposed portion of the first seed layer 105 can be removed. In an embodiment, the exposed portion of the first seed layer 105 (e.g., those not covered by the through-hole 203 and the first redistribution layer 201) can be removed by, for example, a wet or dry etching process. For example, in a dry etching process, the through-hole 203 and the first redistribution layer 201 can be used as a mask to direct reactants toward the first seed layer 105. In another embodiment, an etchant can be sprayed or otherwise brought into contact with the first seed layer 105 to remove the exposed portion of the first seed layer 105. After the exposed portion of the first seed layer 105 has been etched away, a portion of the carrier 101 is exposed between the through-hole 203 and the first redistribution layer 201.

[0037] In an embodiment, the first redistribution layer 201 (with or without the first seed layer 105) can be formed to have a thickness greater than about 20 μm, such as between about 20 μm and about 70 μm. By utilizing such a large thickness, transmittance loss can be reduced, which also leads to improved power efficiency. However, any suitable thickness can be used.

[0038] Figure 3The placement of the first passivation layer 301 above the first redistribution layer 201 is shown. In embodiments, the first passivation layer 301 comprises a material that does not shrink significantly during subsequent processes and will also have high transmittance during subsequent exposure processes (e.g., photolithography). For example, in some embodiments, the first passivation layer 301 may be a material such as polyimide, polybenzoxazole (PBO), epoxy resin, bismaleimide triazine (BT), poly(p-phenylene ether), combinations thereof, etc. However, any suitable material may be used.

[0039] In embodiments where the first passivation layer 301 is a polyimide material, the first passivation layer 301 can be formed by first generating a polyimide composition, which may include a polyimide resin and a photosensitive component (PAC) placed in a polyimide solvent. In embodiments, the polyimide resin may include a polymer composed of monomers of the following formula:

[0040]

[0041] Furthermore, while the polyimide resin may be one of the embodiments described above, the polyimide resin is not intended to be limited to the specific examples presented herein. Rather, any suitable polyimide resin may be used, and all such photosensitive polyimide resins are fully intended to be included within the scope of the embodiments.

[0042] PACs can be photoactive components, such as photoacid generators, photoalkalizers, free radical generators, etc., and PACs can have positive or negative effects. In embodiments, a PAC may comprise a first PAC mixture of one or more compounds (such as a first PAC compound, a second PAC compound, a third PAC compound, and a fourth PAC compound). However, any suitable amount of PAC compound can be used.

[0043] In embodiments, the first PAC compound may include a polycyclic compound having a phosphine group. In some embodiments, the polycyclic compound comprises three or more carbocyclic rings, wherein one or more carbocyclic rings are linked to each other by a phosphine group. In a particular embodiment, the first PAC compound comprises the following structure:

[0044]

[0045] However, any suitable structure can be used.

[0046] In embodiments, the second PAC compound may include another polycyclic compound having a phosphine group. In some embodiments, the other polycyclic compound comprises three or more carbocyclic rings, wherein one or more carbocyclic rings are linked to each other by a phosphine group, and the structure of the carbocyclic rings differs from that of the first PAC compound. In particular embodiments, the second PAC compound comprises the following structure:

[0047]

[0048] However, any suitable structure can be used.

[0049] In embodiments, the third PAC compound may include another polycyclic compound, but without a phosphine group. Conversely, in embodiments, the third PAC compound comprises three or more carbocyclic rings directly connected to each other without a phosphine group. In some embodiments, the third PAC compound comprises three or more carbocyclic rings, wherein one or more carbocyclic rings are connected to each other without a phosphine group, and the structure of the carbocyclic rings differs from that of the first PAC compound. In particular embodiments, the third PAC compound comprises the following structure:

[0050]

[0051] However, any suitable structure can be used.

[0052] In embodiments, the fourth PAC compound may include another ring structure, but in this embodiment, the number of rings is less than 3, such as having a single carbocyclic ring. Additionally, the fourth PAC compound may include an amino group attached to the carbocyclic ring. Thus, in embodiments, the fourth PAC compound includes the following structure:

[0053]

[0054] Where n is between 1 and 1000. However, any suitable structure can be used.

[0055] In the embodiments, the first PAC compound, the second PAC compound, the third PAC compound, and the fourth PAC compound together form a first PAC mixture. For example, within the first PAC mixture, the concentration of the first PAC compound may be between about 0.03 wt% and about 1.0 wt%, the concentration of the second PAC compound may be between about 0.03 wt% and about 1.0 wt%, the concentration of the third PAC compound may be between about 0.03 wt% and about 1.0 wt%, and the concentration of the fourth PAC compound may be between about 0.03 wt% and about 1.0 wt%. However, any suitable concentration can be used.

[0056] By utilizing the material proposed herein for the first PAC mixture, the total transmittance of the first passivation layer 301 can be increased. This increased transmittance improves subsequent imaging (see below). Figure 4A (Further description) This allows for deeper cross-linking within the first passivation layer 301. This cross-linking allows for better chemical resistance during development, thereby allowing for vias with more controllable angles.

[0057] In another embodiment, instead of using the material composition of the first PAC mixture as described above, a second PAC mixture can be used, which allows for a reduction in the total concentration of PAC within the first passivation layer 301. In this embodiment, the second PAC mixture may include a fifth, sixth, seventh, eighth, ninth, and tenth PAC compound. In this embodiment, one or more of the fifth, sixth, seventh, eighth, ninth, and tenth PAC compounds include carbon rings (including saturated and unsaturated rings) with a ring number of less than or equal to 2.

[0058] For example, in an embodiment, the fifth PAC compound may include a ring structure, and in this embodiment, the number of rings is less than or equal to two, such as having two carbon rings. Thus, in an embodiment, the fifth PAC compound includes the following structure:

[0059]

[0060] However, any suitable structure can be used.

[0061] Additionally, in the embodiments, the sixth PAC compound may also include a ring structure, and in this embodiment, the number of rings is less than or equal to two, such as having two carbon rings. Thus, in the embodiments, the sixth PAC compound comprises the following structure:

[0062]

[0063] However, any suitable structure can be used.

[0064] In embodiments, the seventh PAC compound may include yet another ring structure, wherein the number of rings is less than or equal to two, such as having two carbon rings. Additionally, in this embodiment, the rings are linked by a structure comprising a methoxy group. For example, in embodiments, the seventh PAC compound includes the following structure:

[0065]

[0066] However, any suitable structure can be used.

[0067] In this embodiment, the eighth PAC compound may include a ring structure; however, in this embodiment, the number of rings is less than or equal to two, such as having a single carbon ring. Thus, in this embodiment, the eighth PAC compound comprises the following structure:

[0068]

[0069] However, any suitable structure can be used.

[0070] In this embodiment, the ninth PAC compound may include a ring structure; however, in this embodiment, the number of rings is equal to or greater than three, such as having three carbon rings. Thus, in this embodiment, the ninth PAC compound comprises the following structure:

[0071]

[0072] However, any suitable structure can be used.

[0073] Finally, in the embodiments, the tenth PAC compound may include the following structure:

[0074]

[0075] Where A includes -(CH2) n - where n is between 1 and 1000, and can have the following structure:

[0076]

[0077] However, any suitable structure can be used.

[0078] In the embodiments, the fifth, sixth, seventh, eighth, ninth, and tenth PAC compounds collectively form a second PAC mixture. For example, within the second PAC mixture, the concentration of the fifth PAC compound may be between about 0.03 wt% and about 1 wt%, the concentration of the sixth PAC compound may be between about 0.03 wt% and about 1 wt%, the concentration of the seventh PAC compound may be between about 0.03 wt% and about 1 wt%, the concentration of the eighth PAC compound may be between about 0.03 wt% and about 1 wt%, the concentration of the ninth PAC compound may be between about 0.03 wt% and about 1 wt%, and the concentration of the tenth PAC compound may be between about 0.03 wt% and about 1 wt%. However, any suitable concentration can be used.

[0079] By utilizing the material proposed herein for the second PAC mixture, a lower total PAC concentration can be achieved, thereby increasing the total transmittance of the first passivation layer 301 by reducing the amount of PAC present. This increased transmittance improves subsequent imaging (see below). Figure 4A (Further description) This allows for deeper cross-linking within the first passivation layer 301. This cross-linking allows for better chemical resistance during development, thereby allowing for vias with more controllable angles.

[0080] In the embodiments, the polyimide solvent may be an organic solvent and may include any suitable solvent, such as ketones, alcohols, polyols, ethers, ethylene glycol ethers, cyclic ethers, aromatic hydrocarbons, esters, propionates, lactates, lactates, alkylene glycol monoalkyl ethers, alkyl lactates, alkyl alkoxy propionates, cyclic lactones, cyclic monoketone compounds, alkylene carbonates, alkyl alkoxy acetates, alkyl pyruvate, ethylene glycol alkyl ether acetates, diethylene glycol, propylene glycol alkyl ether acetates, alkylene glycol alkyl ether esters, alkylene glycol monoalkyl esters, etc.

[0081] Specific examples of materials that can be used as polyimide solvents for polyimide compositions include acetone, methanol, ethanol, toluene, xylene, 4-hydroxy-4-methyl-2-pentanone, tetrahydrofuran, methyl ethyl ketone, cyclohexanone, methyl isopentyl ketone, 2-heptanone, ethylene glycol, ethylene glycol monoacetate, ethylene glycol dimethyl ether, ethylene glycol methyl ethyl ether, ethylene glycol monoethyl ether, methyl cellulose acetate, ethyl cellosolve acetate, diethylene glycol, diethylene glycol monoacetate, diethylene glycol monomethyl ether, diethylene glycol diethyl ether, diethylene glycol ethyl methyl ether, diethylene glycol monoethyl ether, diethylene glycol monobutyl ether, ethyl 2-hydroxypropionate, methyl 2-hydroxy-2-methylpropionate, 2-hydroxy-2-methylpropionate, etc. Ethyl propionate, ethyl ethoxylate, ethyl hydroxylate, methyl 2-hydroxy-2-methylbutyrate, methyl 3-methoxypropionate, ethyl 3-methoxypropionate, methyl 3-ethoxypropionate, ethyl 3-ethoxypropionate, ethyl acetate, butyl acetate, methyl lactate and ethyl lactate, propylene glycol, propylene glycol monoacetate, propylene glycol monoethyl ether acetate, propylene glycol monomethyl ether acetate, propylene glycol monopropyl methyl ether acetate, propylene glycol monobutyl ether acetate, propylene glycol monomethyl ether propionate, propylene glycol monoethyl ether propionate, propylene glycol methyl ether acetate, propylene glycol ethyl ether acetate, ethylene glycol monomethyl ether acetate, ethylene glycol monoethyl ether acetate, propylene glycol monomethyl ether, propylene glycol monoethyl ether, propylene glycol monopropyl ether Propylene glycol monobutyl ether, ethylene glycol monomethyl ether, ethylene glycol monoethyl ether, propyl lactate and butyl lactate, ethyl 3-ethoxypropionate, methyl 3-methoxypropionate, methyl 3-ethoxypropionate and ethyl 3-methoxypropionate, β-propiolactone, β-butyrolactone, γ-butyrolactone, α-methyl-γ-butyrolactone, β-methyl-γ-butyrolactone, γ-pentanolactone, γ-caprolactone, γ-octanolactone, α-hydroxy-γ-butyrolactone, 2-butanone, 3-methylbutanone, pinacolone, 2-pentanone, 3-pentanone, 4-methyl-2-pentanone, 2-methyl-3-pentanone, 4,4-dimethyl-2-pentanone, 2,4-dimethyl-3-pentanone, 2,2,4,4-tetramethyl-3- Pentanone, 2-hexanone, 3-hexanone, 5-methyl-3-hexanone, 2-heptanone, 3-heptanone, 4-heptanone, 2-methyl-3-heptanone, 5-methyl-3-heptanone, 2,6-dimethyl-4-heptanone, 2-octanone, 3-octanone, 2-nonanone, 3-nonanone, 5-nonanone, 2-decanone, 3-decanone, 4-decanone, 5-hexen-2-one, 3-penten-2-one, cyclopentanone, 2-methylcyclopentanone, 3-methylcyclopentanone, 2,2-dimethylcyclopentanone, 2,4,4-trimethylcyclopentanone, cyclohexanone, 3-methylcyclohexanone, 4-methylcyclohexanone, 4-ethylcyclohexanone, 2,2-dimethylcyclohexanone, 2,6-dimethylcyclohexanone, 2,2,6-Trimethylcyclohexanone, cycloheptanone, 2-methylcycloheptanone, 3-methylcycloheptanone, diphenyl carbonate, vinylene carbonate, ethylene carbonate and butyl carbonate, 2-methoxyethyl acetate, 2-ethoxyethyl acetate, 2-(2-ethoxyethoxy)ethyl acetate, 3-methoxy-3-methylbutyl acetate, 1-methoxy-2-propyl acetate, dipropylene glycol, monomethyl ether, monoethyl ether, monopropyl ether, monobutyl ether, monophenyl ether, dipropylene glycol monoacetate, dioxane, ethyl lactate, methyl acetate, ethyl acetate, butyl acetate, methyl pyruvate, ethyl pyruvate, propyl pyruvate, methyl methoxypropionate, ethyl ethoxypropionate, n-methylpyrrolidone (NMP), 2-methoxyethyl ether (diethylene glycol dimethyl ether), ethylene glycol monoethyl ether Propylene glycol monomethyl ether; methyl propionate, ethyl propionate and ethyl ethoxypropionate, methyl ethyl ketone, cyclohexanone, 2-heptanone, carbon dioxide, cyclopentanone, cyclohexanone, ethyl 3-ethoxypropionate, propylene glycol methyl ether acetate (PGMEA), methylene cellosolve, butyl acetate and 2-ethoxyethanol, N-methylformamide, N,N-dimethylformamide, N-methylformaniline, N-methylacetamide, N,N-dimethylacetamide, N-methylpyrrolidone, dimethyl sulfoxide, benzyl ethyl ether, dihexyl ether, acetone-acetone, isophorone, hexanoic acid, octanoic acid, 1-octanol, 1-nonanol, benzyl alcohol, benzyl acetate, ethyl benzoate, diethyl oxalate, diethyl maleate, γ-butyrolactone, ethylene carbonate, propylene carbonate, phenyl cellosolve acetate, etc.

[0082] In the embodiments, polyimide resin and PAC (e.g., a first PAC mixture and / or a second PAC mixture), along with any desired additives or other reagents, are added to a polyimide solvent for application. For example, the concentration of the polyimide resin can be between about 15% and about 25%. Additionally, in embodiments utilizing a first PAC mixture, the total concentration of PAC can be between about 0.1 wt% and about 15 wt%. In other embodiments, such as those utilizing a second PAC mixture, the total concentration of PAC can be less than about 5 wt%. However, any suitable concentration can be used.

[0083] Once added, the mixture is then blended to obtain a homogeneous composition throughout the polyimide composition, ensuring the absence of defects caused by uneven mixing or a non-constant composition. Once mixed together, the polyimide composition can be stored before use or used immediately.

[0084] Once ready, the first passivation layer 301 can be utilized by first applying the polyimide composition to the first redistribution layer 201. In embodiments where the polyimide composition is a varnish, the first passivation layer 301 can be applied to the first redistribution layer 201 such that the first passivation layer 301 coats the upper exposed surface of the first redistribution layer 201, and processes such as spin coating, dip coating, air knife coating, curtain coating, wire rod coating, gravure coating, lamination, extrusion coating, and combinations thereof can be used.

[0085] Once applied, the first passivation layer 301 can be baked to cure and dry it before exposure (described further below). Curing and drying the first passivation layer 301 removes the solvent components, leaving behind the resin, PAC, and any other optional additives. In embodiments, pre-baking can be performed at temperatures suitable for solvent evaporation, such as between about 40°C and 150°C, e.g., about 150°C, but the precise temperature depends on the material chosen for the first passivation layer 301. The pre-baking time is sufficient to cure and dry the first passivation layer 301, such as between about 10 seconds and about 5 minutes, e.g., about 270 seconds.

[0086] Figure 4A As shown, once cured and dried, the first passivation layer 301 can be patterned to form a first opening 401 (e.g., a via opening) to the first redistribution layer 201. In an embodiment, the first passivation layer 301 can be placed on an imaging device for exposure ( Figure 4A Patterning is initiated in a manner not shown separately. The imaging device may include a support plate, an energy source, and a patterned mask located between the support plate and the energy source.

[0087] In one embodiment, an energy source supplies energy, such as light, to the first passivation layer 301 to induce a reaction in the PAC, which in turn reacts with the resin to chemically alter those portions of the first passivation layer 301 impacted by the energy. In another embodiment, the energy can be electromagnetic radiation, such as gamma rays (wavelength approximately 436 nm), i-rays (wavelength approximately 365 nm), ultraviolet radiation, far-ultraviolet radiation, X-rays, electron beams, etc. The energy source can be an electromagnetic radiation source, and can be a KrF excimer laser (wavelength 248 nm), an ArF excimer laser (wavelength 193 nm), an F2 excimer laser (wavelength 157 nm), etc., but any other suitable energy source can also be used, such as a mercury vapor lamp, a xenon lamp, a carbon arc lamp, etc.

[0088] A patterned mask is positioned between the energy source and the first passivation layer 301 to block portions of the energy before it actually impacts the first passivation layer 301, thus forming patterned energy. In embodiments, the patterned mask may include a series of layers (e.g., a substrate, an absorbing layer, an anti-reflective coating, a shielding layer, etc.) to reflect, absorb, or otherwise block portions of the energy from reaching those undesired portions of the first passivation layer 301. The desired pattern can be formed in the patterned mask by forming openings through it in a desired illumination shape.

[0089] In one embodiment, a first passivation layer 301 is placed on a support plate. Once the pattern has been aligned with the first passivation layer 301, an energy source generates the desired energy (e.g., light), which travels through the patterned mask on its way to the first passivation layer 301. For example, in an embodiment where the PAC includes a first PAC mixture, the patterned energy may include light with wavelengths between about 380 nm and about 440 nm (e.g., G / H lines), while in an embodiment where the PAC includes a second PAC mixture, the patterned energy may include light with wavelengths between about 200 nm and about 380 nm (e.g., I lines). However, any suitable wavelength of light may be used.

[0090] The patterned energy impacting portions of the first passivation layer 301 causes a reaction of the PAC within the first passivation layer 301. The chemical reaction products (e.g., acids / bases / free radicals) of the PAC absorbing the patterned energy then react with the resin, chemically altering the first passivation layer 301 in those portions irradiated through the patterned mask. In some embodiments, the chemical alteration includes crosslinking between individual polymers of the polymer resin.

[0091] However, due to the increased transmittance caused by the first PAC mixture or the decreased concentration of the second PAC mixture (e.g., transmittance greater than about 0.5% to about 1%), more patterning energy will be transmitted through the first passivation layer 301 during the exposure process. This patterning energy will then reach the underlying conductive material (e.g., copper) and be scattered. The scattered light then regenerates even more free radicals in the PAC, thereby inducing a greater degree of crosslinking near the underlying conductive material. Thus, after the exposure process induces crosslinking, a first region of the first passivation layer 301, located between the second region and the carrier 101, has a higher degree of crosslinking than a second region of the first passivation layer 301.

[0092] Following exposure of the first passivation layer 301, a first post-exposure bake (PEB) can be used to assist the generation, dispersion, and reaction of acids / bases / free radicals generated during exposure by energy bombardment of the PAC. This assistance helps to generate or enhance chemical reactions that create chemical differences and different polarities between those regions bombarded and those not bombarded. These chemical differences also result in differences in solubility between the bombarded and unbombarded regions. In embodiments, the temperature of the first passivation layer 301 can be raised to between approximately 70°C and approximately 150°C for a period between approximately 40 seconds and approximately 120 seconds (e.g., approximately 2 minutes). However, any suitable temperature and time can be utilized.

[0093] Once the first passivation layer 301 has been exposed and baked, it can be developed using a developer. In embodiments where the first passivation layer 301 is polyimide, the first developer can be an organic solvent, or a critical fluid can be used to remove those portions of the first passivation layer 301 that are not exposed to energy and thus retain their original solubility. Specific examples of materials that can be used include hydrocarbon solvents, alcohol solvents, ether solvents, ester solvents, critical fluids, combinations thereof, etc. Specific examples of materials that can be used as negative solvents include cyclopentanone, hexane, heptane, octane, toluene, xylene, dichloromethane, chloroform, carbon tetrachloride, trichloroethylene, methanol, ethanol, propanol, butanol, critical carbon dioxide, diethyl ether, dipropyl ether, dibutyl ether, ethyl vinyl ether, dioxane, propylene oxide, tetrahydrofuran, cellosolve, methyl cellosolve, butyl cellosolve, methyl carbitol, diethylene glycol monoethyl ether, acetone, methyl ethyl ketone, methyl isobutyl ketone, isophorone, cyclohexanone, methyl acetate, ethyl acetate, propyl acetate, butyl acetate, pyridine, formamide, N,N-dimethylformamide, etc.

[0094] The first developer can be applied to the first passivation layer 301 using, for example, a spin coating process. In this process, the first developer is applied to the first passivation layer 301 from above while the first passivation layer 301 is rotated. In embodiments, the first developer can be at a temperature between about 10°C and about 80°C, such as about 50°C, and development can last between about 1 minute and about 60 minutes, such as about 30 minutes.

[0095] However, while the spin coating method described herein is a suitable method for developing the first passivation layer 301 after exposure, it is intended to be exemplary and not to limit the embodiments. Rather, any suitable method for development may be optionally used, including immersion processes, stirring processes, spraying processes, combinations thereof, etc. All such development processes are fully intended to be included within the scope of the embodiments.

[0096] Once the first passivation layer 301 has been developed, it can be rinsed. In an embodiment, the first passivation layer 301 can be rinsed with a rinsing solution such as propylene glycol monomethyl ether acetate (C260), but any suitable rinsing solution, such as water, can be used.

[0097] After development, a post-development baking process can be used to help polymerize and stabilize the first passivation layer 301 after the development process. In an embodiment, the post-development baking process can be performed at a temperature between about 80°C and about 200°C (such as about 140°C) for a time between about 60 seconds and about 300 seconds, such as about 2 minutes.

[0098] After development and baking, the first passivation layer 301 can be cured. In embodiments where the first passivation layer 301 comprises polyimide, the curing process can be performed at a temperature less than about 230°C (such as a temperature between about 200°C and 230°C, such as about 220°C) for a time between about 1 hour and about 2 hours. However, any suitable temperature and time can be used.

[0099] Figure 4B It shows the result of Figure 4A An enlarged view of one of the first openings 401 surrounded by a dashed box 403. By utilizing a first passivation layer 301 as described herein, the first opening 401 can be formed with a first angle θ1 (e.g., a cone angle) between about 55° and about 78°, such as about 78°. For example, when using a first PAC mixture, the first angle θ1 can be about 78°, while when using a second PAC mixture, the first angle θ1 can be between about 55° and about 78°. However, any suitable angle can be used.

[0100] In a specific embodiment utilizing the second PAC mixture, the first opening 401 may have a width of approximately 45 μm. Additionally, the first passivation layer 301 may have a thickness of approximately 30 μm. At these dimensions, the taper of the first angle θ1 may be between approximately 55° and approximately 78°, rather than a taper greater than 78° (such as 100°), which would actually cause the formation of a concave surface.

[0101] In another specific embodiment utilizing the first PAC mixture, the first opening 401 can have a width of approximately 40 μm. Additionally, the first passivation layer 301 can have a thickness of approximately 28 μm. Under these dimensions, the taper of the first angle θ1 can be approximately 78°. However, the dimensions used for the first opening 401 are not limited to those described herein, as the first opening 401 can also have a width of 7 μm when the first passivation layer 301 is 5 μm or 5.5 μm thick, or a width of 21 μm when the first passivation layer 301 is 19 μm thick. Any suitable dimensions can be used.

[0102] Additionally, during the formation of the first passivation layer 301, the first passivation layer 301 will undergo some shrinkage. However, by utilizing the embodiments described herein, the shrinkage rate can be limited to between about 1% and about 5%. This allows for the application of a thinner first passivation layer 301 while still ensuring sufficient coverage and isolation. In some embodiments, after formation, the first passivation layer 301 may have a thickness between about 10 μm and about 60 μm.

[0103] Figure 5 As shown, after the first passivation layer 301 has been patterned, the second redistribution layer 501 can be formed to extend through an opening formed within the first passivation layer 301, having the shape of a first opening 401, and being electrically connected to the first redistribution layer 201. In embodiments, the second redistribution layer 501 can be formed using materials and processes similar to those used for the first redistribution layer 201, having via portions and line portions. For example, a seed layer can be applied, and the seed layer can be covered by patterned photoresist. A conductive material, such as copper, can be applied to the seed layer, the patterned photoresist can be removed, and the seed layer can be etched using the conductive material as a mask. However, any suitable materials or manufacturing processes can be used.

[0104] However, in this embodiment, the second redistribution layer 501 can be formed to be thinner than the first redistribution layer 201. Thus, the second redistribution layer 501 can be formed to a thickness between approximately 5 μm and approximately 8 μm. However, any suitable thickness can be used.

[0105] After the second redistribution layer 501 has been formed, a second passivation layer 503 is applied, exposed, and developed over the second redistribution layer 501 to help isolate and protect the second redistribution layer 501. In an embodiment, the second passivation layer 503 may be formed from a similar material and in a similar manner to the first passivation layer 301. For example, the second passivation layer 503 may be formed from polyimide applied and patterned as described above with respect to the first passivation layer 301.

[0106] However, in another embodiment, the second passivation layer 503 can be formed using a second PAC mixture at a higher concentration than the first passivation layer 301. For example, in this embodiment, the second passivation layer 503 is formed using the same materials as the first passivation layer 301 (e.g., polymer resin, solvent, PAC), but the concentration of the second PAC mixture is increased to about 15 wt%, which produces about 65% transmittance (using I-line). Thus, in this embodiment, the thickness of the second passivation layer 503 can be reduced to less than about 10 μm, such as between about 5 μm and about 7 μm. However, any suitable thickness can be utilized.

[0107] Figure 6As shown, after the second passivation layer 503 has been patterned, a third redistribution layer 601 with vias can be formed, the vias extending through openings formed in the second passivation layer 503 and electrically connected to the second redistribution layer 501. In embodiments, the third redistribution layer 601 can be formed using materials and processes similar to those used for the first redistribution layer 201. For example, a seed layer can be applied and covered by patterned photoresist; a conductive material such as copper can be applied to the seed layer; the patterned photoresist can be removed; and the seed layer can be etched using a conductive material as a mask. However, any suitable materials or manufacturing processes can be used.

[0108] However, in embodiments where the second passivation layer 503 is formed from an increased amount of the second PAC mixture (e.g., about 15 wt% of the second PAC mixture), the vias through the second passivation layer 503 can be formed with a height of about 7 μm and an aspect ratio between about 0.8 and about 1.0, as well as a taper angle of about 78°. Thus, the difference in taper angle between the vias extending through the first passivation layer 301 and the vias extending through the second passivation layer 503 is between about 0° and about 20°.

[0109] In addition, in this embodiment, the via extending through the second passivation layer 501 has a step coverage (e.g., the ratio of the thinned thickness of the seed layer within the second passivation layer 503 to the thickness of the seed layer above the second passivation layer 503) of about 30%. However, the seed layer extending through the via through the first passivation layer 301 has a step coverage greater than 30%.

[0110] Figure 7 As shown, after the third redistribution layer 601 has been formed, a third passivation layer 701 is applied, exposed, and developed over the third redistribution layer 601 to help isolate and protect the third redistribution layer 601. In embodiments, the third passivation layer 701 can be formed from a similar material and in a similar manner to the second passivation layer 503. For example, the third passivation layer 701 can be formed from polyimide applied and patterned as described above with respect to the second passivation layer 503. However, any suitable material or manufacturing process can be utilized.

[0111] Figure 8 Debonding from the carrier 101 of the film strip 103 is illustrated. In embodiments where the film strip 103 is an ultraviolet strip, an energy source such as an ultraviolet (UV) laser, a carbon dioxide (CO2) laser, or an infrared (IR) laser is used to irradiate and heat the film strip 103 until the film strip 103 loses at least some of its adhesive properties. Once performed, the carrier 101 and the film strip 103 can be physically separated.

[0112] Figure 9As shown, once the thin film strip 103 has been removed, the carrier substrate 901 is attached to the third passivation layer 701. In embodiments, the carrier substrate 901 may be a glass wafer, a silicon wafer, a silicon-germanium wafer, a combination thereof, etc., and may be bonded using methods such as fusion bonding, dielectric-to-dielectric bonding, combinations thereof. In other embodiments, adhesive layers such as UV strips, pressure-sensitive strips, radiation-curable strips, combinations thereof may also be used to attach the carrier substrate 901. However, any suitable materials and bonding methods may be utilized.

[0113] Figure 10 As shown, after the carrier wafer 901 has been bonded, the structure is flipped, and a fourth redistribution layer 1001 can be formed to contact the now exposed through-hole 203. In an embodiment, the fourth redistribution layer 1001 can be formed using materials and processes similar to those used for the first redistribution layer 201. For example, a seed layer can be applied, and the seed layer is covered with patterned photoresist. A conductive material, such as copper, can be applied to the seed layer, the patterned photoresist can be removed, and the seed layer can be etched using the conductive material as a mask. However, any suitable materials or manufacturing processes can be used.

[0114] Figure 11 The placement of a first semiconductor die 1101 between portions of a fourth redistribution layer 1001 is illustrated. In an embodiment, the first semiconductor die 1101 may be designed and manufactured to face an upper second semiconductor die 1403 (e.g., a sensor die - not in...). Figure 11 As shown in the image, but below regarding... Figure 14 (Further illustrated and described) to provide the desired functionality. For example, the first semiconductor die 1101 may be a digital signal processing die, an I / O die, a high-voltage die (for increasing the sensitivity of the sensor die above), a combination of these, etc. However, any suitable die may be used.

[0115] In an embodiment, the first semiconductor die 1101 may include a semiconductor substrate (not shown separately), active devices (not shown separately), a metallization layer (not shown separately) for interconnecting the active devices of the first semiconductor die 1101, and a first external interconnect 1103 for interconnecting the first semiconductor die 1101. The semiconductor substrate may include doped or undoped bulk silicon, or an active layer of a silicon-on-insulator (SOI) substrate. Typically, an SOI substrate includes a layer of semiconductor material such as silicon, germanium, silicon-germanium, SOI, silicon-germanium-on-insulator (SGOI), or combinations thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0116] Active devices include a wide variety of active and passive devices, such as capacitors, resistors, and inductors, which can be used to generate the desired structural and functional requirements for the design of the first semiconductor die 1101. Active devices can be formed in or on a semiconductor substrate using any suitable method.

[0117] A metallization layer is formed over the semiconductor substrate and active devices of the first semiconductor die 1101 and is designed to connect various active devices to form a functional circuit. In an embodiment, the metallization layer is formed by alternating layers of dielectric and conductive materials and can be formed by any suitable process, such as deposition, damascene, dual damascene, etc. In an embodiment, four metallization layers may be present, separated from the semiconductor substrate by at least one interlayer dielectric (ILD), but the exact number of metallization layers depends on the design of the first semiconductor die 1101.

[0118] The first external connector 1103 can be configured to interconnect the first semiconductor die 1101 to other structures. Thus, in some embodiments, the first external connector 1103 can be, for example, a conductive pillar, such as a copper pillar. However, any suitable connector, such as a contact bump, can be used.

[0119] A first protective layer 1105 may be formed additionally around the first external connector 1103. The first protective layer 1105 may be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics (such as carbon-doped oxides), very low-k dielectrics (such as porous carbon-doped silicon dioxide), combinations thereof, etc. The first protective layer 1105 may be formed by a process such as chemical vapor deposition (CVD), but any suitable process may be used.

[0120] Figure 12 This illustrates sealing a first semiconductor die 1101 and a fourth redistribution layer 1001 with a sealant 1201. This sealing can be applied to molded devices (…). Figure 12 Performed in (not shown), the molding device may include a top molding portion and a bottom molding portion separable from the top molding portion. When the top molding portion descends to be adjacent to the bottom molding portion, a molding cavity may be formed for a structure including a first semiconductor die 1101 and a fourth redistribution layer 1001.

[0121] During the sealing process, the top molding portion can be placed adjacent to the bottom molding portion to enclose the structure including the first semiconductor die 1101 and the fourth redistribution layer 1001 within the molding cavity. Once sealed, the top and bottom molding portions can form an hermetically tight seal to control the inflow and outflow of gas from the molding cavity. Once sealed, a sealant 1201 can be placed within the molding cavity. The sealant 1201 can be a molding compound resin, such as polyimide, PPS, PEEK, PES, heat-resistant crystalline resin, combinations thereof, etc. The sealant 1201 can be placed within the molding cavity before the top and bottom molding portions are aligned, or it can be injected into the molding cavity through an injection port.

[0122] Once the sealant 1201 is placed in the molding cavity to seal the structure comprising the first semiconductor die 1101 and the fourth redistribution layer 1001, the sealant 1201 can be cured to harden it for optimal protection. While the exact curing process depends at least in part on the specific material chosen for the sealant 1201, in embodiments where a molding compound is chosen as the sealant 1201, curing can be performed via a process such as heating the sealant 1201 to between about 100°C and about 130°C (e.g., about 125°C) for about 60 seconds to about 3000 seconds (e.g., about 600 seconds). Additionally, an initiator and / or catalyst may be included within the sealant 1201 for better control of the curing process.

[0123] However, as those skilled in the art will recognize, the above-described curing process is merely exemplary and is not intended to limit the current embodiments. Other curing processes may be optionally used, such as irradiation or even allowing the sealant 1201 to harden at ambient temperature. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.

[0124] Figure 12 Thinning of the sealant 1201 is also shown to expose the first semiconductor die 1101 and the fourth redistribution layer 1001 for further processing. Thinning can be performed, for example, using mechanical polishing or chemical mechanical polishing (CMP) processes, whereby chemical etchants and abrasives are used to react and polish away the sealant 1201, the first semiconductor die 1101, and the fourth redistribution layer 1001 until the first semiconductor die 1101 and the fourth redistribution layer 1001 are exposed. Thus, the structure including the first semiconductor die 1101 and the fourth redistribution layer 1001 can have a flat surface that is also flat with respect to the sealant 1201.

[0125] However, while the CMP process described above is presented as an exemplary embodiment, it is not intended to be limited to the embodiments. Any other suitable removal process may optionally be used to thin the sealant 1201, the first semiconductor die 1101, and the fourth redistribution layer 1001. For example, a series of chemical etching processes may be utilized. This process and any other suitable process may be used to thin the sealant 1201, the first semiconductor die 1101, and the fourth redistribution layer 1001, and all such processes are fully intended to be included within the scope of the embodiments.

[0126] Figure 13 As shown, once the sealant 1201 has been placed, a first set of redistribution layers 1301 can be formed over the sealant 1201. In an embodiment, the first set of redistribution layers 1301 includes a plurality of conductive layers separated by a plurality of dielectric passivation layers (not individually labeled for clarity). Each of the plurality of dielectric passivation layers can be placed and patterned as described above with respect to the second passivation layer 503, and each of the plurality of conductive redistribution layers can be formed as described above with respect to the second redistribution layer 501. However, any suitable method and material can be used.

[0127] exist Figure 14 In this process, a through-hole 1401 is formed, extending away from the topmost dielectric layer of the first redistribution layer 1301. As an example of forming the through-hole 1401, a seed layer (not shown) is formed on the first redistribution layer 1301. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In a particular embodiment, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD. Photoresist is formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the layout of the through-hole 1401. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. Remove the photoresist and the portion of the seed layer where no conductive material has formed. The photoresist can be removed by an acceptable ashing or stripping process (such as using oxygen plasma). Once the photoresist is removed, remove the exposed portion of the seed layer, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material form a through-hole 1401.

[0128] Figure 14The placement of a second semiconductor die 1403 between through-holes 1401 is also shown. The second semiconductor die 1403 may be a sensor die designed to work in conjunction with a first semiconductor die 1101. In some embodiments, the sensor chip may be a fingerprint sensor, image sensor, MEMS sensor, or a combination thereof, placed using, for example, a pick-and-place process. However, any suitable process may be utilized.

[0129] In an embodiment, the second semiconductor die 1403 includes a second semiconductor substrate, a sensing element formed within or on the second semiconductor substrate, circuitry, and contact pads. The second semiconductor substrate, circuitry, and contact pads can be similar in structure to those discussed above with respect to the first semiconductor die 1101, and the sensing element can be formed using any suitable method and process based on the desired sensor type. However, any suitable structure and method can be utilized.

[0130] Once the second semiconductor die 1403 has been placed, a sealant 1405 is formed on and around the various components. After formation, the sealant 1405 seals the through-hole 1401 and the second semiconductor die 1403. The sealant 1405 can be a molding compound, epoxy resin, etc. The sealant 1405 can be applied by compression molding, transfer molding, etc., and can be positioned or formed to bury or cover the through-hole 1401 and / or the second semiconductor die 1403. The sealant 1405 can be applied in liquid or semi-liquid form and then subsequently cured.

[0131] After the sealant 1405 has been applied, a planarization process is performed on the sealant 1405 to expose the through-hole 1401 and the second semiconductor die 1403. The planarization process may also remove material from the through-hole 1401 until it is exposed. Within the process variation, after the planarization process, the top surfaces of the through-hole 1401 and the sealant 1405 are substantially coplanar. The planarization process may be, for example, chemical mechanical polishing (CMP), grinding, etc. In some embodiments, for example, if the through-hole 1401 is already exposed, planarization may be omitted.

[0132] Once the sealant 1405 has been planarized, a front redistribution structure 1407 is formed over the sealant 1405, the via 1401, and the integrated circuit die 1403. The front redistribution structure 1407 includes a dielectric layer and a metallization pattern. The metallization pattern may also be referred to as a redistribution layer or redistribution line. The front redistribution structure 1407 is shown as an example with one metallization pattern. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

[0133] In an embodiment, a first dielectric layer is deposited on the sealant 1405 and the through-hole 1401. In some embodiments, the first dielectric layer is formed of a photosensitive material such as PBO, polyimide, BCB, etc., which can be patterned using a photolithographic mask. The first dielectric layer can be formed by spin coating, lamination, CVD, or combinations thereof. In some embodiments, a planarization process is performed to give the first dielectric layer a substantially flat upper surface.

[0134] Once in place, the first dielectric layer is then patterned. The patterning forms openings that expose portions of the through-hole 1401, openings that expose the contact pads, and openings that expose the sensing elements. Patterning can be performed using acceptable processes, such as by exposing and developing the first dielectric layer when it is a photosensitive material, or by etching, for example, anisotropic etching. In other embodiments, a mask layer (not specifically shown) can be formed over the first dielectric layer and patterned, and the exposed portions of the first dielectric layer can be removed, for example, by etching.

[0135] Once the first dielectric layer is patterned, a metallization pattern is formed. The metallization pattern includes conductive elements that extend along the main surface of the first dielectric layer and through the first dielectric layer to be physically and electrically coupled to the contact pads of the through-hole 1401 and the integrated circuit die 1403. As an example, to form the metallization pattern, a seed layer (not specifically shown) is formed over the first dielectric layer and in an opening extending through the first dielectric layer. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD. Photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern. Patterning is used to form openings through the photoresist to expose the seed layer (including portions of the seed layer within the opening above the via 1401 and the opening above the contact pads). A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the underlying portions of the seed layer forms a metallization pattern. The photoresist and portions of the seed layer on which no conductive material is formed are removed (including portions of the photoresist and seed layer within the opening above the sensing element). The photoresist can be removed by an acceptable ashing or stripping process (such as using oxygen plasma). Once the photoresist is removed, the exposed portions of the seed layer are removed, for example by using an acceptable etching process, such as wet etching or dry etching.

[0136] Once the metallization pattern has been formed, a second dielectric layer is deposited on the metallization pattern and on the first dielectric layer beneath it. The second dielectric layer can be formed in a manner similar to the first dielectric layer beneath the metallization pattern and can be formed from a similar material. Additionally, the second dielectric layer can be patterned to form openings to expose sensing elements. For example, it can be patterned using acceptable processes, such as by exposing the second dielectric layer to light and developing it when it is a photosensitive material, or by etching, for example, anisotropic etching. The openings can have a different or substantially the same lateral width than the openings through the first dielectric layer beneath the metallization pattern, and in some embodiments, a larger lateral width. Additional metallization patterns and dielectric layers, if present, can then be formed.

[0137] Figure 15 The structure is shown attached to ring structure 1501. Ring structure 1501 may be a metal ring designed to provide support and stability to the structure during and after the debonding process. In this embodiment, for example, a UV strip is used to attach the front redistribution structure 1407 to the ring structure, but any other suitable adhesive or attachment may be used.

[0138] Figure 16 As shown, once the front redistribution structure 1407 is attached to the ring structure 1501, the carrier substrate 901 can be detached using processes such as altering the adhesive properties of the adhesive layer (in embodiments where the carrier substrate 901 is attached using an adhesive layer). In a particular embodiment where the adhesive layer is an ultraviolet adhesive, the adhesive is irradiated and heated using an energy source such as an ultraviolet (UV) laser, a carbon dioxide (CO2) laser, or an infrared (IR) laser until the adhesive layer loses at least some of its adhesive properties. Once performed, the carrier substrate 901 and the adhesive layer can be physically separated from and removed from the third passivation layer 701.

[0139] Figure 16 The patterning of the third passivation layer 701 is also shown to expose the third redistribution layer 601. In an embodiment, the third passivation layer 701 can be patterned using, for example, a laser drilling method. In this method, a layer such as a photothermal conversion (LTHC) layer or a hoomax layer (not present on the third passivation layer 701) is first deposited over the third passivation layer 701. Figure 16 A protective layer (shown separately) is present. Once protected, the laser is directed toward the portions of the third passivation layer 701 that are desired to be removed, in order to expose the underlying third redistribution layer 601. During the laser drilling process, the drilling energy can range from 0.1 mJ to approximately 30 mJ, and the drilling angle relative to the normal of the third passivation layer 701 is from approximately 0 degrees (perpendicular to the third passivation layer 701) to approximately 85 degrees.

[0140] In another embodiment, it can be achieved by first applying photoresist ( Figure 16 (Not shown separately) A third passivation layer 701 is applied, and then the photoresist is exposed to a patterned energy source (e.g., a patterned light source) to induce a chemical reaction, thereby causing physical changes in the portions of the photoresist exposed to the patterned light source to pattern the third passivation layer 701. A developer is then applied to the exposed photoresist to utilize the physical changes and, depending on the desired pattern, selectively removes either the exposed or unexposed portions of the photoresist, and removes the exposed portions of the underlying third passivation layer 701 using, for example, a dry etching process. However, any other suitable method for patterning the third passivation layer 701 may be used.

[0141] Additionally, in embodiments where the carrier substrate 901 is held in place by an adhesive layer, once the third passivation layer 701 has been patterned, a cleaning process can be performed to ensure that any remaining portions of the adhesive layer can be removed. In embodiments, the cleaning process may include suitable solvents, etchants, combinations thereof, etc., to clean and prepare the surface for additional manufacturing steps.

[0142] Figure 16 The placement of a second external connector 1601 is also illustrated. In embodiments, the second external connector 1601 may be a contact bump, such as a microbump or a controlled collapse chip connection (C4) bump, and may comprise a material such as tin, or other suitable materials such as silver or copper. In embodiments where the second external connector 1601 is a contact bump, the second external connector 1601 may comprise a material such as tin, or other suitable materials such as silver, lead-free tin, or copper. In embodiments where the second external connector 1601 is a solder bump, the second external connector 1601 may be formed by first forming a tin layer of, for example, a thickness of about 100 μm by common methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the tin layer has been structurally formed, reflow may be performed to shape the material into a desired bump shape, the critical dimensions of which may be between about 60 μm and about 100 μm, and may be formed as a circle or an ellipse.

[0143] Once the second external connector 1601 has been placed, the package can be divided. In an embodiment, division can be performed by cutting through the structure using a saw blade (not shown), thereby separating one part from another. However, as those skilled in the art will recognize, using a saw blade to divide the structure is merely an exemplary embodiment and is not intended to be limiting. Other methods for dividing the structure can also be used, such as using one or more etching processes to separate the structure. These methods and any other suitable methods can be used to divide the structure.

[0144] By altering the transmittance of the material used to form the first passivation layer 301, a more controllable via shape can be obtained. Specifically, by achieving higher transmittance, more energy is scattered during the imaging process, inducing greater cross-linking in the lower region of the material. This cross-linking results in a more controllable shape than can be achieved through other methods.

[0145] Figure 17 The embodiments described herein are shown to be applicable to other embodiments, such as those including System-on-Wafer (SoC) embodiments. In these embodiments, one or more SoCs 1701 are located on a carrier 1703 and embedded within a sealant 1705. A first series of metallization layers 1707 (having redistribution and passivation layers formed as described herein) and a second series of metallization layers 1709 (having redistribution and passivation layers formed as described herein) are formed over the sealant 1705. However, any suitable structure may be utilized.

[0146] Figure 18 The embodiments described herein are also shown to be applicable to other embodiments, such as those including systems-on-integrated substrates (SOI). In these embodiments, for example, solder balls and underfill are used to attach a redistribution structure 1803 having multiple redistribution layers, vias, and dielectric layers (all formed using one or more methods described herein). However, any suitable structure may be utilized.

[0147] In one embodiment, a method of manufacturing a semiconductor device includes: forming a redistribution layer over a substrate; applying a first dielectric material to the redistribution layer and the substrate, wherein the first dielectric material has a transmittance to a first energy greater than about 0.5%; and imaged the first dielectric material with the first energy. In one embodiment, the first dielectric material has a thickness between about 20 μm and about 60 μm. In one embodiment, the redistribution layer has a thickness greater than or equal to about 20 μm. In one embodiment, the first dielectric material has a concentration of less than 15 wt% of a photoactive component. In one embodiment, the method further includes developing the first dielectric material, wherein after developing the first dielectric material, a first opening has a taper angle between about 55° and about 78°. In one embodiment, the first dielectric material has a concentration of less than 5 wt% of a photoactive component. In one embodiment, the method further includes developing the first dielectric material, wherein after developing the first dielectric material, the first opening has a taper angle of about 78°.

[0148] In an embodiment, a method of manufacturing a semiconductor device includes: applying a dielectric coating to a carrier substrate; initiating crosslinking within the dielectric coating by exposing the dielectric coating to a patterned energy source, wherein after initiation of crosslinking, a first region of the dielectric coating has a higher degree of crosslinking than a second region of the dielectric coating, the first region being located between the second region and the carrier substrate; developing the dielectric coating to form a via; and forming a conductive via in the via. In an embodiment, the via has a taper angle between about 55° and about 78°. In an embodiment, the taper angle is about 78°. In an embodiment, the dielectric coating has a photoactive component concentration of less than about 15 wt%. In an embodiment, the dielectric coating has a photoactive component concentration of less than about 5 wt%. In an embodiment, the photoactive component includes amine and phosphine groups. In an embodiment, the photoactive component includes a chemical substance having a first carbon ring and a second carbon ring, the first carbon ring being saturated and the second carbon ring being unsaturated.

[0149] In one embodiment, a semiconductor device includes: a first dielectric layer; a first via extending through the first dielectric layer, the first via having a tapered sidewall angle between about 55° and about 78°; a second via extending through a carrier substrate, the second via being electrically connected to the first via; and a first semiconductor die located above a side of the carrier substrate opposite to the first via, the first semiconductor die being electrically connected to the second via. In one embodiment, the tapered sidewall angle is about 78°. In one embodiment, the first dielectric layer has a thickness between about 20 μm and about 60 μm. In one embodiment, the semiconductor device further includes a redistribution layer located between the first dielectric layer and the first via, the redistribution layer having a thickness greater than or equal to about 20 μm. In one embodiment, the semiconductor device further includes a second dielectric layer adjacent to the first dielectric layer, wherein the second dielectric layer has a thickness between about 5 μm and about 7 μm. In one embodiment, the semiconductor device further includes a second redistribution layer located between the second dielectric layer and the first dielectric layer, the second redistribution layer having a thickness between 5 μm and 8 μm.

[0150] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a base to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A method of fabricating a semiconductor device, the method comprising: forming a redistribution layer over a substrate; applying a first dielectric material to the redistribution layer and the substrate, wherein the first dielectric material has a transmittance of greater than 0.5% to a first energy, the first dielectric material comprising: a first photoactive component compound having the following structure: ； a second photoactive component compound having at least two rings, the second photoactive component compound having the following structure: ; and imaging the first dielectric material with the first energy.

2. The method of manufacturing a semiconductor device according to claim 1, wherein, the first dielectric material has a thickness between 20 pm and 60 pm.

3. The method of manufacturing a semiconductor device according to claim 2, wherein, the redistribution layer has a thickness greater than or equal to 20 pm.

4. The method of manufacturing a semiconductor device according to claim 1, wherein, the first dielectric material has a concentration of photoactive component less than 15 wt%.

5. The method of fabricating a semiconductor device according to claim 4, further comprising developing the first dielectric material, wherein, after developing the first dielectric material, a first opening has a taper angle between 55° and 78°.

6. The method of manufacturing a semiconductor device according to claim 1, wherein, the first dielectric material has a concentration of photoactive component less than 5 wt%.

7. The method of fabricating a semiconductor device according to claim 6, further comprising developing the first dielectric material, wherein, after developing the first dielectric material, a first opening has a taper angle of 78°.

8. A method of fabricating a semiconductor device, the method comprising: applying a dielectric coating to a carrier substrate; inducing cross-linking within the dielectric coating by exposing the dielectric coating to a patterned energy source, wherein, after inducing the cross-linking, a first region of the dielectric coating has a higher degree of cross-linking than a second region of the dielectric coating, the first region being between the second region and the carrier substrate; developing the dielectric coating to form a via; forming a conductive via in the via, wherein the dielectric coating comprises: a first photoactive component compound having the following structure: ； a second photoactive component compound having at least two rings, the second photoactive component compound having the following structure: 。 9. The method of manufacturing a semiconductor device according to claim 8, wherein, the conductive material of the conductive via comprises copper.

10. The method of manufacturing a semiconductor device according to claim 8, wherein, the conductive via has a taper angle of 78°.

11. The method of manufacturing a semiconductor device according to claim 8, wherein, the dielectric coating has a photoactive component concentration less than 15 wt%.

12. The method of manufacturing a semiconductor device according to claim 11, wherein, the dielectric coating has a photoactive component concentration less than 5 wt%.

13. The method of manufacturing a semiconductor device according to claim 11, wherein, the photoactive component comprises an amine group and a phosphine group.

14. The method of manufacturing a semiconductor device according to claim 11, wherein, the photoactive component comprises a chemical having a first carbon ring and a second carbon ring, the first carbon ring being saturated, the second carbon ring being unsaturated.

15. A semiconductor device, comprising: a first dielectric layer; a first via extending through the first dielectric layer, the first via having a tapered sidewall angle of 78°; a second via extending through a carrier substrate, the second via electrically connected to the first via; and a first semiconductor die over a side of the carrier substrate opposite the first via, the first semiconductor die electrically connected to the second via, wherein a dielectric material of the first dielectric layer comprises: a first photoactive component compound having the following structure: ； a second photoactive component compound having at least two rings, the second photoactive component compound having the following structure: 。 16. The semiconductor device of claim 15, wherein, the material of the first via comprises copper.

17. The semiconductor device of claim 15, wherein, the first dielectric layer has a thickness between 20 pm and 60 pm.

18. The semiconductor device of claim 17, further comprising a redistribution layer between the first dielectric layer and the first via, the redistribution layer having a thickness greater than or equal to 20 pm.

19. The semiconductor device of claim 17, further comprising a second dielectric layer adjacent to the first dielectric layer, wherein, the second dielectric layer has a thickness between 5 pm and 7 pm.

20. The semiconductor device of claim 19, further comprising a second redistribution layer between the second dielectric layer and the first dielectric layer, the second redistribution layer having a thickness between 5 pm and 8 pm.

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