Bulk semiconductor structure and method with multilayer polycrystalline semiconductor regions

Abstract

This invention discloses a bulk semiconductor structure and method having multiple polycrystalline semiconductor regions. The bulk semiconductor structure includes a semiconductor substrate having multiple polycrystalline semiconductor regions, comprising one or more first layer portions (i.e., buried portions) and one or more second layer portions (i.e., non-buried portions). Each first layer portion may be buried below the top surface of the semiconductor substrate at a distance (i.e., buried), may be aligned below the single-crystal semiconductor region and / or trench isolation region, and may have a first maximum depth. Each second layer portion may be located within the top surface of the semiconductor substrate, may be laterally adjacent to the trench isolation region, and may have a second maximum depth less than the first maximum depth. An embodiment of a method for forming the bulk semiconductor structure is also disclosed, wherein the first and second layer portions of the multiple polycrystalline semiconductor regions are formed simultaneously (e.g., using a single module).

Description

Technical Field

[0001] The present invention relates to the isolation of semiconductor devices on a bulk semiconductor substrate, and more specifically, to embodiments of a bulk semiconductor structure having multi-level polycrystalline semiconductor regions and embodiments of a method for forming such a structure. Background Technology

[0002] Integrated circuit (IC) designs for bulk semiconductor substrates may include buried high-resistivity polycrystalline semiconductor regions located beneath certain types of semiconductor devices (e.g., radio frequency (RF) switches) within the semiconductor substrate to reduce harmonic and / or parasitic losses. They may also include non-buried high-resistivity polycrystalline semiconductors within the semiconductor substrate immediately adjacent to the top surface. Conventional techniques for forming buried high-resistivity polycrystalline semiconductor regions are typically performed before semiconductor device formation or even before well region formation; however, conventional techniques for forming non-buried high-resistivity polycrystalline semiconductor regions are typically performed later in the manufacturing process (e.g., after semiconductor device formation, particularly after silicide formation on the semiconductor device). Summary of the Invention

[0003] In view of the foregoing, this document discloses an embodiment of a bulk semiconductor structure comprising a semiconductor substrate having a multilayer polycrystalline semiconductor region, the multilayer polycrystalline semiconductor region including one or more first layer portions (i.e., buried portions) and one or more second layer portions (i.e., unburied portions). Each first layer portion may be embedded below the top surface of the semiconductor substrate at a distance (i.e., buried), aligned below a single-crystal semiconductor region and / or a trench isolation region, and may have a first maximum depth. Each second layer portion may be located at the top surface of the semiconductor substrate, laterally adjacent to the trench isolation region, and may have a second maximum depth less than the first maximum depth. This document also discloses an embodiment of a method for forming a bulk semiconductor structure, wherein the first and second layer portions of the multilayer polycrystalline semiconductor region are formed simultaneously (e.g., using a single module).

[0004] More specifically, embodiments of a bulk semiconductor structure are disclosed herein. The bulk semiconductor structure may include a bulk semiconductor substrate. The bulk semiconductor substrate may have a bottom surface and a top surface opposite the bottom surface. The bulk semiconductor structure may also include a trench isolation region located in the semiconductor substrate at the top surface. Furthermore, the bulk semiconductor substrate may include a single-crystal semiconductor region and a multilayer polycrystalline semiconductor region. The single-crystal semiconductor region may be located within the semiconductor substrate at the top surface and laterally adjacent to a first side of the first trench isolation region. The multilayer polycrystalline semiconductor region may include one or more first layer portions (i.e., one or more buried portions). Each first layer portion may be within the semiconductor substrate, physically separable from the top surface of the semiconductor substrate, and may have a first maximum depth. One of the first layer portions may be specifically located below the single-crystal semiconductor region. The multilayer polycrystalline semiconductor region may also include one or more second layer portions (i.e., one or more non-buried portions). Each second layer portion may be located within the semiconductor substrate immediately adjacent to the top surface and may have a second maximum depth less than the first maximum depth. One of the second layer portions may specifically be laterally adjacent to the second side of the first trench isolation area opposite to the first side.

[0005] This document also discloses method embodiments for forming a bulk semiconductor structure. Typically, the method embodiments may include providing a bulk semiconductor substrate. A trench isolation region may be formed at the top surface of the semiconductor substrate. After forming the trench isolation region, a multilayer polycrystalline semiconductor region may be formed within the semiconductor substrate. The multilayer polycrystalline semiconductor region may be formed by simultaneously forming one or more first layer portions (i.e., one or more buried portions) and one or more second layer portions (i.e., one or more unburied portions). The first layer portions may be formed physically separated from the top surface of the semiconductor substrate and have a first maximum depth. A first layer portion may be specifically formed below a single-crystal semiconductor region, located at the top surface of the semiconductor substrate and laterally adjacent to a first side of the first trench isolation region. The second layer portion may be formed at the top surface of the semiconductor substrate and have a second maximum depth less than the first maximum depth. A second layer portion may be specifically formed laterally adjacent to a second side of the first trench isolation region opposite the first side.

[0006] More specifically, embodiments of the method for forming a bulk semiconductor structure may include providing a bulk semiconductor substrate. A protective layer may be formed on the semiconductor substrate. Trench isolation regions may be formed such that they extend through the protective layer and into the semiconductor substrate. Subsequently, multiple polycrystalline semiconductor regions may be formed in the semiconductor substrate. To form the multiple polycrystalline semiconductor regions, an opening may be formed in the protective layer on a first side of a first trench isolation region, leaving a remainder of the protective layer above the semiconductor substrate on at least a second side of the first trench isolation region opposite to the first side. Doped regions may then be formed within the semiconductor substrate such that the doped regions have a modified crystal structure. During the formation of the doped regions, the remainder of the protective layer locally restricts the depth of the doped regions. After the doping implantation process, the doped regions may be recrystallized. This recrystallization of the doped regions produces a single-crystal semiconductor region at the top surface of the semiconductor substrate laterally adjacent to the first side of the first trench isolation region. The recrystallization of the doped region also produces a multilayer polycrystalline semiconductor region, which includes a first layer portion located below the single-crystal semiconductor region and having a first maximum depth, and a second layer portion located at the top surface of the semiconductor substrate laterally adjacent to the second side of the first trench isolation region and having a second maximum depth less than the first maximum depth. Attached Figure Description

[0007] The invention will be better understood through the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, wherein:

[0008] Figure 1A A cross-sectional view of an embodiment of a bulk semiconductor structure having multiple polycrystalline semiconductor regions;

[0009] Figure 1B A cross-sectional view of an additional embodiment of a bulk semiconductor structure having multilayer polycrystalline semiconductor regions;

[0010] Figure 2 A flowchart illustrating an embodiment of a method for forming a bulk semiconductor structure having multiple polycrystalline semiconductor regions; and

[0011] Figures 3 to 13 According to Figure 2 The flowchart forms a partially completed structure.

[0012] Symbol Explanation

[0013] 100A and 100B semiconductor structures

[0014] 101 Semiconductor Substrate

[0015] 102 Bottom

[0016] 103 Top surface

[0017] 104 dielectric layer

[0018] 110 First Section

[0019] 111 First STI Region

[0020] 112 Single-crystal semiconductor region

[0021] 113 Semiconductor Devices

[0022] 120 Second Section

[0023] 121 Second STI Region

[0024] 130 Third Section

[0025] 131 Third STI Region

[0026] 133 Additional Semiconductor Devices

[0027] 140 Fourth Section

[0028] 141 Fourth STI Region

[0029] 143 Passive Device

[0030] 150 multilayer polycrystalline semiconductor regions

[0031] 151 First layer

[0032] 152 Second layer

[0033] Area 153

[0034] 160 Additional single-crystal semiconductor region

[0035] 180 doped region

[0036] 181 First District

[0037] 182 Second District

[0038] 185 crystal layers

[0039] 191 First protective layer

[0040] 191a Part 1

[0041] 191b Part Two

[0042] 192 Mask layer

[0043] 193 Second protective layer

[0044] Processing steps for numbers 202, 204, 206, 208, and 210

[0045] Processing steps for 212, 214, 216, 218, and 220

[0046] Processing steps for numbers 222, 224, 226, 228, 230, and 232.

[0047] 501, 601, 901 openings

[0048] d1 First maximum depth

[0049] d2 is the second maximum depth. Detailed Implementation

[0050] As described above, integrated circuit (IC) designs for bulk semiconductor substrates may include buried high-resistivity polycrystalline semiconductor regions located beneath certain types of semiconductor devices (e.g., radio frequency (RF) switches) within the semiconductor substrate to reduce harmonic and / or parasitic losses. Conventional techniques for forming buried high-resistivity polycrystalline semiconductor regions include: implanting ions of inert dopant into the semiconductor substrate to create doped implanted regions with modified crystal structures (e.g., amorphous crystal structures); and performing a rapid thermal anneal (RTA) process to recrystallize the doped implanted regions, particularly by forming a single-crystal semiconductor region on the top surface of the semiconductor substrate and burying a polycrystalline semiconductor region below the single-crystal semiconductor region but above the remaining single crystal portion of the semiconductor substrate. Such buried high-resistivity polycrystalline semiconductor regions are typically formed before semiconductor device formation or even before well region formation. IC designs for bulk semiconductor substrates may also include non-buried high-resistivity polycrystalline semiconductors within the semiconductor substrate immediately adjacent to the top surface. These non-buried high-resistivity polycrystalline semiconductor regions are typically formed later in the manufacturing process (e.g., after the semiconductor device is formed, especially after the silicide is formed on the semiconductor device).

[0051] In view of the foregoing, this document discloses an embodiment of a bulk semiconductor structure comprising a semiconductor substrate having multiple polycrystalline semiconductor regions, each polycrystalline semiconductor region including one or more first layer portions (i.e., buried portions) and one or more second layer portions (i.e., unburied portions). Each first layer portion may be embedded (i.e., buried) within the semiconductor substrate at a distance below the top surface, may be aligned below a single-crystal semiconductor region and / or a trench isolation region, and may have a first maximum depth. Each second layer portion may be located at the top surface within the semiconductor substrate, may be laterally adjacent to the trench isolation region, and may have a second maximum depth less than the first maximum depth. This document also discloses an embodiment of a method for forming a bulk semiconductor structure, wherein the first and second layer portions of the multiple polycrystalline semiconductor regions are formed simultaneously (e.g., using a single module).

[0052] refer to Figure 1A and Figure 1B This document discloses embodiments of bulk semiconductor structures 100A and 100B, respectively. The structures 100A and 100B may include a bulk semiconductor substrate 101 (e.g., a bulk silicon substrate).

[0053] Structures 100A and 100B may include a first section 110, particularly an active semiconductor device section, and one or more additional sections, including a second section 120 (e.g., a dummy fill topography section), a third section 130 (e.g., an additional active semiconductor device section), and / or a fourth section 140 (e.g., a passive device section). For illustrative purposes, structures 100A and 100B are described below and illustrated in the accompanying drawings as having all four sections 110, 120, 130, and 140. However, it should be understood that these drawings are not intended to be limiting. Structures 100A and 100B may include only the first section 110 and the second section 120. Alternatively, structures 100A and 100B may include the first section 110, the second section 120, and either the third section 130 or the fourth section 140. Alternatively, structures 100A and 100B may include only the first section 110 and the fourth section 140. Alternatively, structures 100A and 100B may include a first segment 110, a third segment 130, and a fourth segment 140. Alternatively, structures 100A and 100B may include a first segment 110, a second segment 120, a third segment 130, and a fourth segment 140 (as shown in the figure).

[0054] In any case, structures 100A and 100B may also include trench isolation regions, such as shallow trench isolation (STI) regions. These STI regions may include trenches patterned and etched into the top surface 103 of the semiconductor substrate 101 by photolithography, and the trenches are filled with a first dielectric material. The first dielectric material may be, for example, silicon dioxide (SiO2). The bottom surfaces of the STI regions may be substantially at the same level (e.g., from the top surface 103 of the semiconductor substrate 101 to a predetermined depth above the bottom surface 102 of the semiconductor substrate 101).

[0055] The STI region may specifically include a first STI region 111 that defines the limitation of the first segment 110 (e.g., an active semiconductor device segment). That is, the first STI region 111 may be laterally adjacent to the upper portion of the semiconductor substrate 101 in the first segment 110, and optionally, may be laterally surrounding the upper portion of the semiconductor substrate 101. The first STI region 111 may have a first width sufficient to provide lateral electrical isolation between the first segment and any adjacent segments.

[0056] An STI region may further include one or more additional STI regions, each associated with one or more additional segments.

[0057] For example, when structures 100A and 100B include a second segment 120 (e.g., a dummy fill topography segment), the STI region may include a plurality of second STI regions 121 located over the entire upper portion of the semiconductor substrate 101 within the second segment 120. The second STI regions 121 may be (e.g., substantially uniformly) distributed over the second segment 120. The second STI regions 121 may, for example, be substantially square or circular (when viewed in a horizontal cross-section). Additionally, the second STI regions 121 may have a relatively small width. That is, each of the second STI regions 121 may have a second width smaller than the first width of the STI region 111. For the purposes of this invention, it should be understood that a dummy fill topography segment refers to a segment of a semiconductor structure without an active semiconductor device. Instead, a dummy fill topography segment includes semiconductor and isolation fill topography, and more specifically, includes distributed isolation fill topography (e.g., substantially uniformly) passing through the semiconductor region such that portions of the semiconductor region laterally surrounding and extending between the isolation fill topography constitute a semiconductor fill topography. The specific arrangement of semiconductor and isolation fill morphologies can be used to optimize chemical mechanical planarization (CMP) processes.

[0058] When structures 100A and 100B include a third segment 130 (e.g., an additional active semiconductor device segment), the STI region may include a third STI region 131 that defines the third segment 130. That is, the third STI region 131 may be laterally adjacent to the upper portion of the semiconductor substrate 101 in the third segment 130, and optionally, may laterally surround the upper portion of the semiconductor substrate 101. For example, the third STI region 131 may have a first width substantially the same as the first STI region 111. Alternatively, the third STI region 131 may have any other width sufficient to provide the required lateral electrical isolation.

[0059] When structures 100A and 100B include a fourth segment 140 (e.g., a passive device segment), the STI region may include a fourth STI region 141 that defines the boundaries of the fourth segment 140. That is, the fourth STI region 141 may be laterally adjacent to the upper portion of the semiconductor substrate 101 in the fourth segment 140, and optionally, may be laterally surrounding the upper portion of the semiconductor substrate 101. For example, the fourth STI region 141 may have a first width substantially the same as the first STI region 111. Alternatively, the fourth STI region 141 may have any other width sufficient to provide the required lateral electrical isolation. Optionally, the STI regions may be patterned such that STI regions are shared between adjacent segments (e.g., see shared STI regions 131 / 141 between segments 130 and 140).

[0060] The semiconductor substrate 101 may also include an isolated single-crystal semiconductor region 112 (e.g., a single-crystal silicon region). This single-crystal semiconductor region 112 may be located in the first segment 110, particularly in the semiconductor substrate 101 immediately adjacent to the top surface 103, and laterally adjacent to a first side (e.g., the inner side) of the first STI region 111.

[0061] The semiconductor substrate 101 may also include a high-resistivity multilayer polycrystalline semiconductor region 150 (e.g., a high-resistivity multilayer polycrystalline silicon region). The multilayer polycrystalline semiconductor region 150 may include one or more first layer portions (i.e., one or more buried portions) 151 and one or more second layer portions (i.e., one or more unburied portions).

[0062] Each first layer portion 151 may be located within the semiconductor substrate 101, physically separable from the top surface 103 of the semiconductor substrate 101, and may have a first maximum depth (d1). The first maximum depth (d1) refers to the distance from the bottom (i.e., lowest point) of the first layer portion 151 measured from the top surface 103 of the semiconductor substrate 101. It should be noted that, as shown, the first maximum depth (d1) of the different first layer portions 151 is approximately the same; however, some variations across substrate processes may occur. For example, the maximum depth of the first layer portion below the STI region may be slightly different compared to the single-crystal semiconductor region. One of the first layer portions 151 may be specifically aligned below the single-crystal semiconductor region 112 in the first segment 110. As shown, the first layer portion may also extend laterally below the first trench isolation region 111. When structures 100A, 100B include the second segment 120, the first layer portion 151 may be further aligned below each of the second STI regions 121. When structures 100A and 100B include a third segment 130, the first layer portion 151 may be further aligned below the third STI region 131. When structures 100A and 100B include a fourth segment 140, the first layer portion 151 may be aligned below the fourth STI region 141.

[0063] Each second layer portion 152 may be adjacent to the top surface 103 of the semiconductor substrate 101 and may have a second maximum depth (d2) less than the first maximum depth (d1). The second maximum depth (d2) refers to the distance from the bottom (i.e., lowest point) of the second layer portion 152 measured from the top surface 103 of the semiconductor substrate 101. It should be noted that the second maximum depth (d2) of the different second layer portions is approximately the same; however, some variations may occur across substrate processes. In any case, the second maximum depth (d2) of all second layer portions 152 is less than the first maximum depth (d1) of all first layer portions 151. One of the second layer portions 152 may specifically be laterally adjacent to a second side (e.g., the outer side) of the first STI region 111 relative to the first side, such that the first STI region 111 is laterally located between the second layer portions 152 of the single-crystal semiconductor region 112 and the multilayer polycrystalline semiconductor region 150. When structures 100A and 100B include a second segment 120 (e.g., a virtual fill topography segment), the second layer portion 152 may also laterally surround and extend between each of the second STI regions 121 within the second segment 120. That is, the second layer portion 152 may constitute a semiconductor fill topography within the second segment 120. Furthermore, when structures 100A and 100B include a fourth segment, the second layer portion 152 may be located within the fourth segment 140 and laterally adjacent to the fourth STI region 141.

[0064] It should be noted that, due to the method used to form the multilayer polycrystalline semiconductor region 150 (discussed in more detail below with reference to method embodiments), at least adjacent lower portions of the multilayer polycrystalline semiconductor region 150 and the single-crystal semiconductor region 112 will be doped (i.e., contain) with inert dopants. For the purposes of this invention, an inert dopant refers to a type of dopant that is not generally considered chemically reactive (i.e., neutral) relative to the single-crystal semiconductor material (e.g., single-crystal silicon) in which it is implanted during processing, capable of altering the crystal structure of the single-crystal semiconductor material during implantation (e.g., forming amorphous regions), and does not prevent recrystallization of the doped region in a subsequent rapid thermal annealing (RTA) process (e.g., forming polycrystalline and / or single-crystal regions), and does not significantly affect the electrical properties of the resulting polycrystalline and / or single-crystal regions. Such inert dopants include, but are not limited to, inert gases (also known as rare gases) (e.g., argon, xenon, helium, neon, krypton, radon, etc.), silicon, or any other suitable inert dopant. Furthermore, depending on the specific technology used to form the multilayer polycrystalline semiconductor region 150 (as discussed in more detail below with respect to the method), the multilayer polycrystalline semiconductor region 150 may include a single, relatively thick layer of polycrystalline semiconductor material. For example, as Figure 1A As shown in structure 100A, each of the first layer portion 151 and the second layer portion 152 is fully polycrystalline. Alternatively, the multilayer polycrystalline semiconductor region 150 can be multilayered. For example, as... Figure 1B As shown in structure 100B, each of the first layer portion 151 and the second layer portion 152 may include multiple defined layers of polycrystalline semiconductor material separated by thin layers of crystalline semiconductor material.

[0065] It should be noted that the semiconductor substrate 101 may or may not include processing artifacts, particularly in relatively thin regions 153 of high-resistivity polycrystalline semiconductor material (e.g., relatively thin regions of high-resistivity polycrystalline silicon) arranged beneath the multilayer polycrystalline semiconductor region 150. The morphology of the relatively thin regions 153 can vary. For example, it may have multilayer portions (similar to the cross-section shown or having some other cross-section), or it may be substantially planar.

[0066] The semiconductor substrate 101 may also include an additional single-crystal semiconductor region 160. In the first section 110 and (if present) in the second section 120 and / or in the fourth section 140, the additional single-crystal semiconductor region 160 may surround the lower portion of the semiconductor substrate, extending from the bottom of the multilayer polycrystalline semiconductor region 150 (in particular, from the bottom of the different layers 151-152 of the multilayer polycrystalline semiconductor region (150)) to the bottom surface 102 of the semiconductor substrate 101. In the third section 130 (if present), the additional single-crystal semiconductor region 160 may extend from the top surface 103 of the semiconductor substrate 101 to the bottom surface 102 of the semiconductor substrate 101.

[0067] The first segment 110 may also include one or more active semiconductor devices 113. Specifically, the single-crystal semiconductor region 112 in the first segment 110 may include an active device region for at least one semiconductor device 113. The semiconductor device 113 may be, for example, a radio frequency (RF) device, such as an RF switch. In this case, a first layer portion 151 specifically aligned below the single-crystal semiconductor region 112 and the first STI region 111 provides isolation between the RF switch and an additional single-crystal semiconductor region 160 of the underlying semiconductor substrate 101, thereby reducing harmonics. Alternatively, the semiconductor device 113 may be any other type of RF device and / or any other type of semiconductor device (e.g., a bipolar junction transistor, etc.) that similarly benefits from such buried isolation.

[0068] The third segment 130 (if present) may also include one or more additional active semiconductor devices 133. Specifically, the single-crystal semiconductor material at the top surface 103 of the semiconductor substrate 101 in the additional single-crystal semiconductor region 160 may include an active device region for at least one additional semiconductor device 133. The additional semiconductor device 133 may be a complementary metal-oxide-semiconductor (CMOS) device, a bipolar junction transistor, etc., which may be designed to not require or significantly benefit from this buried isolation.

[0069] Semiconductor devices, such as the aforementioned semiconductor devices 113 and 133, are well known in the art, and various well-known configurations of these devices can be used in semiconductor structures 100A and 100B. Therefore, details of the semiconductor devices and their configurations are omitted in the specification to allow the reader to focus on the significant aspects of the disclosed semiconductor structures.

[0070] It should be noted that the second segment 120 (e.g., a dummy fill topography segment) and the fourth segment 140 (e.g., a passive device segment) may not have active semiconductor devices. As described above, a dummy fill topography segment refers to a segment of semiconductor structure without active semiconductor devices. Instead, a dummy fill topography segment includes semiconductor and isolation fill topography, and more specifically, includes distributed isolation fill topography (e.g., substantially uniform) across the semiconductor region such that portions of the semiconductor region laterally surrounding and extending between the isolation fill topography constitute semiconductor fill topography. The specific arrangement of the semiconductor and isolation fill topography can be used for chemical mechanical planarization (CMP) process optimization. The passive device segment may include at least one passive device 143 (e.g., a resistor, capacitor, inductor, etc.) located above the top surface 103 of the semiconductor substrate 101 (e.g., at the gate polysilicon layer, as shown, or at the back-end-of-the-line (BEOL) metal layer (not shown). Such a passive device 143 may benefit from the additional isolation provided by the second layer portion 152 of the high-resistivity polysilicon region 150 within the fourth segment 140, and may exhibit, in particular, reduced parasitic losses due to said region 150.

[0071] This document also discloses method embodiments for forming bulk semiconductor structures 100A and 100B, as described above and as follows. Figure 1A and 1B As shown. Typically, the method embodiments may include providing a bulk semiconductor substrate. Trench isolation regions, such as shallow trench isolation (STI) regions, may be formed at the top surface of the semiconductor substrate. After forming the trench isolation regions, multilayer polycrystalline semiconductor regions may be formed within the semiconductor substrate. The multilayer polycrystalline semiconductor regions may be formed by simultaneously forming one or more first layer portions (i.e., one or more buried portions) and one or more second layer portions (i.e., one or more unburied portions). The first layer portions may be formed to be physically separated from the top surface of the semiconductor substrate and have a first maximum depth. A first layer portion may be specifically formed below a single-crystal semiconductor region located at the top surface of the semiconductor substrate and laterally adjacent to a first side of the first trench isolation region. A second layer portion may be formed on the top surface of the semiconductor substrate and have a second maximum depth less than the first maximum depth. Specifically, a second layer portion may be formed such that it laterally adjacent to a second side of the first trench isolation region opposite to the first side (e.g., such that the first trench isolation region is laterally located between the single-crystal semiconductor region and the second layer portion of the multilayer polycrystalline semiconductor region).

[0072] More specifically, see reference Figure 2 The flowchart illustrates a method embodiment for forming a bulk semiconductor structure, such as the one described in detail above. Figure 1AThe bulk semiconductor structure 100A shown or such Figure 1B The bulk semiconductor structure 100B shown may include providing a bulk semiconductor substrate (e.g., a bulk single-crystal silicon substrate (see processing step 202 and...)). Figure 3 ).

[0073] A thin dielectric layer 104 of the first dielectric material can be formed on the top surface 103 of the substrate 101 (see processing step 204 and...). Figure 3 The first dielectric material may be, for example, a silicon dioxide (SiO2) layer deposited on the top surface of the substrate 101 (e.g., by thermal oxidation).

[0074] A first protective layer 191 of the second dielectric material (also referred to herein as a doping implantation confinement layer) may be formed on the thin dielectric layer 104 (see processing steps 206 and...). Figure 3 The second dielectric material may differ from the first dielectric material. For example, the second dielectric material may be silicon nitride (SiN) deposited on the top surface of dielectric layer 104 by, for example, chemical vapor deposition (CVD) or plasma-enhanced CVD (PECVD). A first protective layer 191 may be deposited to have a thickness sufficient to confine the implantation of dopant to a predetermined depth during the doping implantation process of step 222 (discussed in more detail below). For example, the first protective layer 191 may have a thickness ranging from 30 to 250 nm.

[0075] Trench isolation regions, such as shallow trench isolation (STI) regions, can then be formed, such that they extend through the first protective layer 191 and the dielectric layer 104 and into the semiconductor substrate 101 (see processing steps 208 and 209). Figure 4 ).

[0076] It should be noted that the disclosed method embodiments may include integration processing steps for forming multiple different design segments in the same semiconductor structure. These segments may include a first segment 110 (e.g., an active semiconductor device segment) and one or more additional segments, including a second segment 120 (e.g., a dummy fill topography segment), a third segment 130 (e.g., an additional active semiconductor device segment), and / or a fourth segment 140 (e.g., a passive device segment). For illustrative purposes, the method is described below and illustrated in the accompanying drawings relating to the formation of all four segments on the same semiconductor substrate. However, it should be understood that the description and drawings are not intended to be limiting. The method may include forming a semiconductor structure having only the first segment 110 (e.g., a semiconductor device segment) and the second segment 120 (e.g., a dummy fill topography segment). Alternatively, the method may form a semiconductor structure having the first segment 110, the second segment 120, and the third segment 130 (e.g., an additional active semiconductor device segment) or the fourth segment 140 (e.g., a passive device segment). Alternatively, the method may include forming a semiconductor structure having a first segment 110 and a fourth segment 140. Alternatively, the method may include forming a semiconductor structure having a first segment 110, a third segment 130, and a fourth segment 140. Alternatively, the method may include forming a semiconductor structure having a first segment 110, a second segment 120, a third segment 130, and a fourth segment 140.

[0077] Therefore, in processing step 208, a first STI region 111 can be formed such that it defines the boundary of the first segment 110 (e.g., an active semiconductor device segment). That is, the first STI region 111 can be formed (e.g., patterned, etched, and filled) such that it laterally abuts the upper portion of the semiconductor substrate 101 in the first segment 110, and optionally, such that it laterally surrounds the upper portion of the semiconductor substrate 101 in the first segment 110. Furthermore, the first STI region 111 can be formed such that it has a first width sufficient to provide lateral electrical isolation between the first segment and any adjacent segments.

[0078] Additionally, in processing step 208, one or more additional STI regions associated with one or more additional segments can be formed respectively.

[0079] For example, when structures 100A and 100B include a second segment 120 (e.g., a virtual fill topography segment), a plurality of second STI regions 121 can be formed (e.g., patterned, etched, and filled) such that they are located over the entire upper portion of the semiconductor substrate 101 within the second segment 120. The second STI regions 121 can be formed such that they are distributed within the second segment 120 (e.g., substantially uniformly distributed). The second STI regions 121 can be further formed such that they are substantially square or circular (when viewed in a horizontal cross-section). Additionally, the second STI regions 121 can be formed such that they have a relatively small width. That is, each of the second STI regions 121 can be formed such that it has a second width smaller than the first width of the STI region 111. As described above, with respect to the structural embodiments, a virtual fill topography segment refers to a segment of a semiconductor structure without an active semiconductor device. Conversely, the virtual fill topography segment includes semiconductor and isolation fill topography, and more specifically, includes isolation fill topography distributed (e.g., substantially uniformly) within the semiconductor region, such that portions of the semiconductor region laterally surrounded and extended between the isolation fill topography constitute the semiconductor fill topography. The specific arrangement of the semiconductor and the isolation fill topography can be designed for chemical mechanical planarization (CMP) process optimization.

[0080] When structures 100A and 100B include a third segment 130 (e.g., an additional active semiconductor device segment), a third STI region 131 may be formed to define the boundaries of the third segment 130. That is, the third STI region 131 may be formed such that it laterally approaches and (optionally) laterally surrounds the upper portion of the semiconductor substrate 101 in the third segment 130. The third STI region 131 may be formed such that it has substantially the same first width as the first STI region 111. Alternatively, the third STI region 131 may be formed such that it has any other width sufficient to provide the required lateral electrical isolation.

[0081] When structures 100A and 100B include a fourth segment 140 (e.g., a passive device segment), a fourth STI region 141 may be formed to define the boundaries of the fourth segment 140. That is, the fourth STI region 141 may be formed such that it laterally proximities and (optionally) laterally surrounds the upper portion of the semiconductor substrate 101 in the fourth segment 140. The fourth STI region 141 may be formed such that it has a first width substantially the same as the first STI region 111. Alternatively, the fourth STI region 141 may be formed such that it has any other width sufficient to provide the required lateral electrical isolation. It should be noted that, optionally, the STI regions may be patterned such that STI regions are shared between adjacent segments (e.g., see the shared STI region 131 / 141 between segments 130 and 140).

[0082] In processing step 208, the aforementioned STI regions can be formed using conventional STI formation techniques. Specifically, trenches can be photolithographically patterned and etched such that they extend substantially perpendicularly through layers 191 and 104 and into the semiconductor substrate 101, with the bottom of each trench located below the top surface 103 of the semiconductor substrate 101 and further above the bottom surface 102 of the semiconductor substrate 101 at a predetermined distance. Next, one or more layers of isolation material can be deposited to fill the trenches. In an exemplary embodiment, the isolation material can be a first dielectric material (e.g., SiO2). After the isolation material deposition, a chemical mechanical polishing (CMP) process can be performed to remove any isolation filler material from the top surface of the first protective layer 191, such that the top surface of the STI region and the top surface of the first protective layer 191 are substantially coplanar.

[0083] A mask layer 192 can be formed on the exposed surface of the first protective layer 191 and on the STI region (see processing step 210 and...). Figure 5 The mask layer 192 may be made of, for example, the same first dielectric material (e.g., SiO2) used for the dielectric layer 104, and may be deposited, for example, by PECVD. Alternatively, the mask layer 192 may be made of any suitable dielectric material other than the second dielectric material. The mask layer 192 may also be patterned to have an opening that exposes a first portion 191a of the first protective layer 191, the opening being located in a first segment 110 above the semiconductor substrate 101 and laterally adjacent to a first side of the first STI region 11, such that a second portion 191b of the first protective layer 191 is covered (see processing steps 212 and...). Figure 5 Specifically, using conventional photolithography patterning and anisotropic etching techniques, an opening 501 can be formed in the mask layer 192, extending substantially perpendicularly through the mask layer 192, where the mask layer 192 stops and exposes a first portion 191a of the first protective layer 191. After the opening is formed at processing step 212, a second portion 191b of the first protective layer 191 adjoins a second side of the first STI region 111 and is further adjacent to any other STI region that can hold the mask.

[0084] The exposed first portion 191a of the first protective layer 191 may be selectively removed from the first segment 110 (i.e., removed from above the dielectric layer 104 on the first side of the first STI region 111), thereby forming an opening 601 in the first protective layer 191 (see processing step 214 and...). Figure 6For example, if the dielectric layer 104, the STI region, and the mask layer 192 are all made of the same first dielectric material (e.g., SiO2), and if the first protective layer 191 is made of a second dielectric material (e.g., SiN), any suitable process that selectively etches the exposed SiN onto the exposed SiO2 can be used. For example, a thermal phosphoric acid etching process can be used. The second portion 191b of the first protective layer 191 is protected from etching by the remaining portion of the mask layer 192 at processing step 214, and thus remains intact.

[0085] Optionally, the remainder of mask layer 192 can be selectively removed (see processing step 216 and...). Figure 7 For example, if the mask layer 192 is made of a first dielectric material (e.g., SiO2), it can be selectively removed by a selective oxidation wet etching process (e.g., hydrofluoric acid (HF) etching) or a reactive ion etching (RIE) process. It should be noted that if the dielectric layer 104 and the mask layer 192 are made of the same first dielectric material (e.g., SiO2), then processing step 216 will also etch the dielectric layer 104 from the first segment 110, thereby exposing the top surface 103 of the semiconductor substrate 101, as shown below. Figure 7 As shown. Therefore, before performing additional processing, the first dielectric material of dielectric layer 104 should be redeposited (e.g., regrowed) on the exposed semiconductor surface within the first segment 110 (see Figure 104). Figure 8 ).

[0086] Optionally, a second protective layer 193 (also referred to herein as a doping implantation barrier layer) may be formed on the partially completed structure. The second protective layer 193 may be, for example, a photoresist mask layer, a nitride mask layer, or a layer of any other suitable mask material. It should be noted that the second protective layer should be deposited to be sufficiently thick (given its material composition) to prevent inert dopants from entering the semiconductor substrate 101 at processing step 222, as discussed in more detail below. For example, if the second protective layer 193 is a photoresist layer, it should be at least 2 nm and preferably 4 nm or greater to prevent doping of the substrate at processing step 222. The second protective layer 193 can then be photolithographically patterned and etched to form openings 901 aligned with the first segment 110 and the second segment 120 and / or the fourth segment 140, while protecting the third segment 130 (see processing steps 218-220 and...). Figure 9Specifically, processing step 220 may be performed such that the first dielectric material of the dielectric layer 104 in the first segment 110 remains exposed, and the second portion 191b of the first protective layer 191 in the second segment 120 and / or the fourth segment 140 also remains exposed (i.e., not covered or protected by the second protective layer 193). It should be noted that the second protective layer 193 may be relatively thick (e.g., thicker than the first protective layer 191) and particularly thick enough to prevent (i.e., completely block) the implantation of dopant into the semiconductor substrate 101 during the doping implantation process in processing step 222 below.

[0087] Subsequently, a doped region 180 with a modified crystal structure can be formed within the semiconductor substrate 101 (see processing steps 222 and 223). Figure 10 Specifically, a doping implantation process can be performed to implant an inert dopant into a semiconductor substrate 101, thereby forming a doped region 180 within the semiconductor substrate 101 having a modified crystal structure (e.g., an amorphous crystal structure). For the purposes of this invention, an inert dopant refers to a type of dopant that is generally not considered chemically reactive (i.e., neutral) relative to the single-crystal semiconductor material (e.g., single-crystal silicon) in which it is implanted in step 222, capable of modifying the crystal structure of the single-crystal semiconductor material at step 222, and not preventing recrystallization of the doped region 180 during the subsequent rapid thermal annealing (RTA) process at step 226, as discussed further in detail below, without significantly affecting the electrical properties of the resulting polycrystalline and / or single-crystal semiconductor region. Such inert dopants include, but are not limited to, inert gases (also known as rare gases) (e.g., argon, xenon, helium, neon, krypton, radon, etc.), silicon, or any other suitable inert dopant. Step 222 may include a single doping implantation process for creating a doped region having a modified crystal structure. Alternatively, processing step 222 may include multiple successive doping implantation processes, each of which may implant dopant ions with different kinetic energies and / or different doses to optimize the modified crystal structure within the doped region, and may potentially achieve greater implantation depths in both the first region 181 and the second region 182.

[0088] In any case, during the doping implantation process, an optional second protective layer 193 covering a portion of the first protective layer 191 in the third segment 130 prevents inert dopants from implanting into the region of the semiconductor substrate 101 within the third segment 130. That is, it completely prevents inert dopants from entering the semiconductor substrate in this region. Because of the presence of the second protective layer 193 in the third segment 130 during the doping implantation process, the doped region 180 does not extend laterally through the third segment 130. In other words, the semiconductor substrate maintains its crystal structure within the third segment 130.

[0089] Furthermore, during the doping implantation process, the exposed second portion 191b of the first protective layer 191 within the second segment 120 and / or the fourth segment 140 can locally limit the doping implantation depth in these portions compared to the doping implantation depth in the first segment 110 and below the STI region (which is not masked by the first protective layer 191). That is, the second portion 191b of the first protective layer 191 can partially protect the region beneath the semiconductor substrate, and more specifically, can hinder the doping implantation process. Therefore, when the inert dopant still penetrates the semiconductor substrate in the protected region, its depth is different from the depth in the unprotected region. It should be noted that the inert dopant typically reaches the same depth in the unprotected region—whether implanted into the semiconductor substrate 101 through the thin dielectric layer 104 or through the thicker STI region. In any case, due to the presence of the second portion 191b of the first protective layer 191 during the doping implantation process in the second segment 120 and / or the fourth segment 140, the doped region 180 will have a first region 181 and a second region 182 with a depth shallower than the first region 181. The first region 181 will laterally adjoin a first side of the first STI region 111 in the first segment 110 and be located below STI regions 111, 121, 131, and 141. The second region 182 will laterally adjoin a second side of the first STI region 111, laterally surround the second STI region 121 in the second segment 120, and / or laterally adjoin a fourth STI region 141 in the fourth segment 140. Finally, since the first segment 110 is not protected by any portion of the first protective layer 191 during the doping implantation process, the top of the doped region 180 will be located at a short distance (e.g., less than 5 nm) below the top surface 103 of the semiconductor substrate 101. Therefore, after processing step 222, the relatively thin (e.g., less than 5 nm) crystal layer 185 will remain within the first segment 110 adjacent to the bottom surface of the dielectric layer 104 (i.e., between the bottom surface of the dielectric layer 104 and the doped region 180).

[0090] The second protective layer 193 can then be selectively removed (if present) (see processing step 224). As described above, the second protective layer can be, for example, a photoresist mask layer or a nitride mask layer. Techniques for selectively removing such materials are well known in the art. Additionally, if the remainder of the mask layer 192 was not selectively removed in processing step 216, it can be removed in the same manner as described above after the doping implantation process and the removal of the second protective layer 193.

[0091] The method may further include recrystallizing the doped region 180 (see processing step 226 and FIG. 11). Specifically, a rapid thermal annealing (RTA) process may then be performed to recrystallize the doped region 180 having a modified crystal structure. That is, the partially completed structure can be heated in a non-oxidizing environment at a relatively high temperature (e.g., above 900°C) for a relatively short time (e.g., 5-180 seconds). During the recrystallization process, a thin crystalline layer 185 at the top surface 103 of the semiconductor substrate 101 in the first segment 110 serves as a seed layer for the recrystallization of the doped region 180 from top to bottom. Additionally, in the first, second, and fourth segments, the lower crystalline portion of the semiconductor substrate 101 serves as a seed layer for the recrystallization of the doped region 180 from bottom to top. As a result, a large single-crystal semiconductor region 112 is formed at the top surface 103 of the semiconductor substrate in the first segment, such that it laterally adjoins the first side of the first STI region 111, and multiple layers of polycrystalline semiconductor regions 150 are also formed, as described in detail above. Figure 1A Or as shown in 1B.

[0092] Specifically, the multilayer polycrystalline semiconductor region 150 will include one or more first layer portions 151 (i.e., one or more buried portions) and one or more second layer portions 152 (i.e., one or more unburied portions).

[0093] Each first layer portion 151 will be located within the semiconductor substrate 101, physically separated from the top surface 103 of the semiconductor substrate 101, and will have a first maximum depth (d1). For example, the first layer portion 151 will be aligned below the single-crystal semiconductor region 112 and the first trench isolation region 111 in the first segment 110. When structures 100A and 100B are formed to include a second segment 120 (e.g., a virtual fill topography segment), the first layer portion 151 will also be aligned below each second STI region 121. When structures 100A and 100B are formed to include a third segment 130 (e.g., an additional active device segment), the first layer portion 151 will also be aligned below the third STI region 131. When structures 100A and 100B are formed to include a fourth segment 140 (e.g., a passive device segment), the first layer portion 151 will also be aligned below the fourth STI region 141. The first maximum depth (d1) refers to the distance from the bottom (i.e., the lowest point) of the first layer portion 151 measured from the top surface 103 of the semiconductor substrate 101. It should be noted that, as shown, the first maximum depth (d1) of different first layer portions 151 is approximately the same; however, some variations may occur across substrate processes. For example, the maximum depth of the first layer portion below the STI region may be slightly different compared to the single-crystal semiconductor region.

[0094] Each second layer portion 152 will be adjacent to the top surface 103 of the semiconductor substrate 101 and will have a second maximum depth (d2) less than the first maximum depth (d1). Specifically, the second layer portion 152 will laterally abut the second side (e.g., the outer side) of the first STI region 111 opposite the first side, such that the first STI region 111 is laterally located between the single-crystal semiconductor region 112 and the second layer portion 152. When structures 100A and 100B are formed to include a second segment 120, the second layer portion 152 will laterally surround and extend between each second STI region 121 within the second segment 120. That is, the second layer portion 152 will constitute the semiconductor filling morphology of the second segment 120. Furthermore, when structures 100A and 100B are formed to include a fourth segment 140, the second layer portion 152 will be located within the fourth segment 140 and laterally abut the fourth STI region 141. It should be noted that the second maximum depth (d2) of the different second layer portions is approximately the same; however, some variations may occur across substrate processes. In any case, the second maximum depth (d2) of all second layer portions 152 is less than the first maximum depth (d1) of all first layer portions 151.

[0095] The configuration of the multilayer polycrystalline semiconductor region 150 (e.g., as a single layer or multiple layers) will vary depending on the type of doping implantation process used in processing step 222. That is, as described above, processing step 222 may include a single doping implantation process or multiple successive doping implantation processes. If a single doping implantation process is used in processing step 222, then processing step 226 may result in the multilayer polycrystalline semiconductor region 150 being a single, relatively thick layer of polycrystalline semiconductor material. For example, as Figure 11A As shown in the partially completed structure, each of the first layer portion 151 and the second layer portion 152 is fully polycrystalline. Alternatively, if multiple successive doping implantation processes are used in processing step 222, processing step 226 can result in the multilayer polycrystalline semiconductor region 150 being multilayered. For example, as Figure 11B As shown in the partially completed structure, each of the first layer portion 151 and the second layer portion 152 includes multiple defined layers of polycrystalline semiconductor material separated by thin layers of crystalline semiconductor material.

[0096] Other characteristics will depend on the process specifications used in processing step 222. For example, the thickness of the single-crystal semiconductor region 112 can be primarily controlled by the energy of the implant (e.g., high energy can result in a thicker single-crystal semiconductor region 112), and secondarily by the RTA time (e.g., a short RTA time can result in a thinner single-crystal semiconductor region 112). Those skilled in the art will recognize that the thickness of the single-crystal semiconductor region 112 (as measured from the top surface of the semiconductor substrate to the top of the first layer portion 151 of the underlying polycrystalline semiconductor region 150) should be sufficient to allow the semiconductor device 113 to be formed thereon (see processing step 232 below) and to function properly.

[0097] In any case, the multilayer polycrystalline semiconductor region 150 does not extend downwards to the bottom surface 102 of the semiconductor substrate 101. Therefore, the resulting semiconductor structures 100A, 100B will also include an additional single-crystal semiconductor region 160. In the first segment 110 (e.g., the active semiconductor device segment), and, if present, the second segment 120 (e.g., the virtual fill topography segment), and / or the fourth segment 140 (e.g., the passive device segment), the additional single-crystal semiconductor region 160 will surround the lower portion of the semiconductor substrate, extending from the bottom of the multilayer polycrystalline semiconductor region 150 (particularly from the bottom of the different layers 151-152 of the multilayer polycrystalline semiconductor region 150) to the bottom surface 102 of the semiconductor substrate 101. In the third segment 130 (e.g., the additional active semiconductor device segment), if present, the additional single-crystal semiconductor region 160 will extend from the top surface 103 of the semiconductor substrate 101 to the bottom surface 102 of the semiconductor substrate 101.

[0098] It should be noted that during the processing steps, after RTA, processing artifacts may also occur in the semiconductor substrate aligned below the multilayer polycrystalline semiconductor region 150, particularly in relatively thin regions 153 of the high-resistivity polycrystalline semiconductor material (e.g., relatively thin regions of high-resistivity polycrystalline silicon). The morphology of this relatively thin region 153 can vary. For example, it can have multilayer portions (similar to the cross-section shown or with some other cross-sections), or it can be substantially planar.

[0099] After recrystallization of the doped region 180, the remaining second portion 191b of the first protective layer 191 can be selectively removed (see processing steps 228 and 229). Figure 12For example, as described above, in processing step 214, if the dielectric layer 104 and the STI region are made of the same first dielectric material (e.g., SiO2), and if the first protective layer 191 is made of a second dielectric material (e.g., SiN), then, as described above, in processing step 214, the first portion 191a of the first protective layer is selectively removed, and then any suitable process can be used to selectively etch the exposed SiN onto the exposed SiO2. Therefore, a thermal phosphoric acid etching process can be used.

[0100] Alternatively, the height of the STI region can be reduced (e.g., using a wet etching process) (see processing step 230 and...). Figure 13 It should be noted that if processing step 230 results in the removal of dielectric layer 104 and exposure of the underlying semiconductor surface, the first dielectric material can be redeposited (e.g., by thermal oxidation) to reconstruct layer 104.

[0101] It should be understood that, despite Figures 12 to 13 The document explains that processing steps 228 and 230 are for... Figure 11A The partially completed structure shown is executed, but for Figure 11B The partially completed structure shown will also undergo the same processing steps.

[0102] To complete semiconductor structures 100A and 100B, additional processes can be subsequently performed (see processing steps 232 and 100B). Figure 1A and 1BAdditional processes may include semiconductor device formation. For example, one or more semiconductor devices 113 may be formed in the first segment 110, and one or more additional semiconductor devices 133 may be formed simultaneously in the third segment 130 (if present). Semiconductor devices 113 may include radio frequency (RF) devices, such as RF switches, and / or any other type of semiconductor device (e.g., bipolar junction transistors, etc.), which will benefit from isolation from additional single-crystal semiconductor regions 160 through a first layer portion 151 (i.e., buried portion) of the high-resistivity multilayer polycrystalline semiconductor region 150. Additional semiconductor devices 133 may be complementary metal-oxide-semiconductor (CMOS) devices, bipolar junction transistors, etc., which may be designed to not require or significantly benefit from such buried isolation. Additional processes may further include middle-of-the-line (MOL) processes (e.g., interlayer dielectric deposition, contact formation, etc.) and back-of-line (BEOL) processes (e.g., metal layer formation). Optionally, the additional process performed may also include forming at least one passive device 143 (e.g., a resistor, capacitor, inductor, etc.) over the top surface 103 of the semiconductor substrate 101 (e.g., at the gate polysilicon layer (as shown), or in the back-end process (BEOL) metal layer (not shown)). Such a passive device 143 may also benefit from the additional isolation provided by the high resistivity multilayer polysilicon region 150 within the substrate, and may exhibit, in particular, reduced parasitic losses due to this region 150. Techniques for forming semiconductor devices and passive devices for semiconductor structures are well known in the art. Therefore, details of these techniques are omitted from this specification to allow the reader to focus on the significant aspects of the disclosed methods.

[0103] It should be understood that in the above structures and methods, semiconductor materials refer to materials whose conductivity can be altered by doping with impurities. Exemplary semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon carbide germanium, silicon carbide, etc.) and gallium nitride-based semiconductor materials. Pure semiconductor materials, more specifically, semiconductor materials that are not doped with impurities to increase conductivity (i.e., undoped semiconductor materials) are referred to in the art as intrinsic semiconductors. Semiconductor materials that are doped with impurities to increase conductivity (i.e., doped semiconductor materials) are referred to in the art as extrinsic semiconductors and will be more conductive than intrinsic semiconductors made from the same substrate material. That is, extrinsic silicon will be more conductive than intrinsic silicon; extrinsic silicon germanium is more conductive than intrinsic silicon germanium, and so on. Furthermore, it should be understood that different types of conductivity (e.g., P-type conductivity and N-type conductivity) can be achieved using different impurities (i.e., different dopants), and the dopants can vary depending on the different semiconductor materials used. For example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, etc.) are typically doped with group III dopants, such as boron (B) or indium (In), to achieve p-type conductivity, while silicon-based semiconductor materials are typically doped with group V dopants, such as arsenic (As), phosphorus (P), or antimony (Sb), to achieve n-type conductivity. Gallium nitride (GaN)-based semiconductor materials are typically doped with magnesium (Mg) to achieve p-type conductivity or silicon (Si) to achieve n-type conductivity. Those skilled in the art will also recognize that different conductivity levels will depend on the relative concentration levels of dopants in a given semiconductor region.

[0104] It should be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not restrictive. For example, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, as used herein, the terms “comprising,” “including,” “containing,” and / or “comprises” specify the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. Additionally, as used herein, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “below,” “above,” “parallel,” and “upright” are used to describe relative positions, as shown in the accompanying drawings (unless otherwise stated), and terms such as “contact,” “direct contact,” “adjacent,” “directly adjacent,” and “directly adjacent” are intended to indicate that at least one element is in physical contact with another element (without any other element separating the elements). The term "lateral" is used herein to describe the relative position of elements, and more specifically, to indicate that an element is positioned above or below another element to the side of that element, as these elements are oriented and shown in the accompanying drawings. For example, an element laterally adjacent to another element will be located next to that element, an element laterally adjacent to another element will be located directly next to that element, and an element laterally surrounding another element will be adjacent to and bordering the outer wall of that element. All corresponding structures, materials, actions, and equivalents of means or steps plus functional elements in the appended claims are intended to include any structure, material, or action used to perform a function in combination with other elements of the specific claims.

[0105] The description of various embodiments of the present invention is provided for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, practical application or improvement of the technology relative to that found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: Semiconductor substrate; as well as The trench isolation region is located within the semiconductor substrate. The semiconductor substrate includes: A single-crystal semiconductor region located on the top surface of the semiconductor substrate on a first side laterally adjacent to the first trench isolation region; and Multilayer polycrystalline semiconductor region, including: The first layer portion is located below the single-crystal semiconductor region, and this first layer portion is a buried portion; and The second layer portion is located on the top surface of the semiconductor substrate that is laterally adjacent to the second side of the first trench isolation region relative to the first side, and the second layer portion is a non-buried portion, wherein the first layer portion has a first maximum depth and the second layer portion has a second maximum depth less than the first maximum depth.

2. The semiconductor structure according to claim 1, wherein, This multilayer polycrystalline semiconductor region contains inert dopants.

3. The semiconductor structure according to claim 1 further includes a semiconductor device on the single-crystal semiconductor region.

4. The semiconductor structure according to claim 1 further includes a radio frequency switch on the single-crystal semiconductor region.

5. The semiconductor structure according to claim 1, further comprising a first segment and a second segment, in, The single-crystal semiconductor region is located in this first segment. The first trench isolation area is located laterally between the first section and the second section. The trench isolation region includes: the first trench isolation region; and the second trench isolation region in the semiconductor substrate within the second segment. The multilayer polycrystalline semiconductor region includes multiple first-layer portions and multiple second-layer portions. The first layer is physically separated from the top surface of the semiconductor substrate, and is located at least below the single-crystal semiconductor region, the first trench isolation region, and each of the second trench isolation regions. The second layer portion is located on the top surface of the semiconductor substrate at least laterally adjacent to the second side of the first trench isolation region and extends between the second trench isolation regions.

6. The semiconductor structure according to claim 5, wherein, The semiconductor substrate also includes an additional single-crystal semiconductor region that extends from the multilayer polycrystalline semiconductor region to the bottom surface of the semiconductor substrate in the first and second sections.

7. The semiconductor structure according to claim 6 further includes a third segment. in, The trench isolation region also includes a third trench isolation region in the semiconductor substrate adjacent to the third segment. Among them, one of the first layer portions of the multilayer polycrystalline semiconductor region is below the third trench isolation region, and The additional single-crystal semiconductor region extends from the top surface of the semiconductor substrate to the bottom surface of the semiconductor substrate in the third segment.

8. The semiconductor structure according to claim 6 further includes a fourth segment. in, The trench isolation region also includes a fourth trench isolation region located in the semiconductor substrate adjacent to the fourth segment. Wherein, one of the first layer portions of the multilayer polycrystalline semiconductor region is located below the fourth trench isolation region, and one of the second layer portions of the multilayer polycrystalline semiconductor region is located in the fourth segment at the top surface of the semiconductor substrate laterally adjacent to the fourth trench isolation region, and The additional single-crystal semiconductor region extends from the multilayer polycrystalline semiconductor region to the bottom surface of the semiconductor substrate in the fourth segment.

9. A method for forming a semiconductor structure, comprising: Forming trench isolation regions in a semiconductor substrate; as well as A multilayer polycrystalline semiconductor region is formed in the semiconductor substrate, such that the multilayer polycrystalline semiconductor region includes: A first layer portion, located below the single-crystal semiconductor region, is a buried portion. The single-crystal semiconductor region is located on the top surface of the semiconductor substrate on a first side laterally adjacent to the first trench isolation region. The first layer portion has a first maximum depth. The second layer portion is located on the top surface of the semiconductor substrate that is laterally adjacent to the second side of the first trench isolation region relative to the first side, and the second layer portion is a non-buried portion, wherein the second layer portion has a second maximum depth less than the first maximum depth.

10. The method according to claim 9, wherein, The formation of this multilayer polycrystalline semiconductor region includes: A doped region is formed within the semiconductor substrate, such that the doped region has a modified crystal structure, wherein, during the formation of the doped region, the semiconductor substrate on the second side of the first trench isolation region is locally protected to limit the depth of the doped region; and The doped region is recrystallized, wherein the recrystallization of the doped region produces the single-crystal semiconductor region and the multilayer polycrystalline semiconductor region.

11. The method of claim 9, further comprising forming a semiconductor device on the single-crystal semiconductor region.

12. The method according to claim 9, in, The formation of the trench isolation region also includes forming the first trench isolation region in the semiconductor substrate between the first segment and the second segment of the semiconductor structure; And a second trench isolation region is formed in the semiconductor substrate in the second section, and The multilayer polycrystalline semiconductor region is formed to include: Multiple first layer portions, physically separated from the top surface of the semiconductor substrate and at least below the single-crystal semiconductor region, the first trench isolation region, and each of the second trench isolation regions; and Multiple second layer portions are located on the top surface of the semiconductor substrate at least laterally adjacent to the second side of the first trench isolation region and extend laterally between the second trench isolation regions.

13. The method according to claim 12, wherein, After the multilayer polycrystalline semiconductor region is formed, an additional single-crystal semiconductor region extends from the multilayer polycrystalline semiconductor region to the bottom surface of the semiconductor substrate in the first segment and the second segment.

14. The method according to claim 13, in, The formation of the trench isolation region also includes forming a third trench isolation region in the semiconductor substrate adjacent to the third segment of the semiconductor structure, and The multilayer polycrystalline semiconductor region is formed such that one of the first layer portions is below the third trench isolation region, and the additional single-crystal semiconductor region extends from the top surface of the semiconductor substrate to the bottom surface of the semiconductor substrate in the third segment.

15. The method according to claim 13, in, The formation of the trench isolation region includes forming a fourth trench isolation region in the semiconductor substrate adjacent to the fourth segment of the semiconductor structure, and The multilayer polycrystalline semiconductor region is formed such that one of the first layer portions is below the fourth trench isolation region, one of the second layer portions is located in the fourth segment at the top surface of the semiconductor substrate laterally adjacent to the fourth trench isolation region, and the additional single-crystal semiconductor region extends from the multilayer polycrystalline semiconductor region to the bottom surface of the semiconductor substrate in the fourth segment.

16. A method for forming a semiconductor structure, comprising: A protective layer is formed on a semiconductor substrate; Forming a trench isolation region that extends through the protective layer to the semiconductor substrate; as well as A multilayer polycrystalline semiconductor region is formed in the semiconductor substrate, wherein the formation of the multilayer polycrystalline semiconductor region includes: An opening is formed in the protective layer above the semiconductor substrate on the first side of the first trench isolation region, such that the protective layer above the semiconductor substrate on the second side of the first trench isolation region opposite to the first side remains intact. A doped region is formed within the semiconductor substrate, such that the doped region has a modified crystal structure, wherein, during the formation of the doped region, the remaining portion of the protective layer locally restricts the depth of the doped region; and The doped region is recrystallized, wherein the recrystallization of the doped region produces a single-crystal semiconductor region at the top surface of the semiconductor substrate laterally adjacent to the first side of the first trench isolation region, and the multilayer polycrystalline semiconductor region includes: The first layer portion is located below the single-crystal semiconductor region, and this first layer portion is a buried portion; and The second layer portion is located on the top surface of the semiconductor substrate on the second side that is laterally adjacent to the first trench isolation region, and the second layer portion is a non-buried portion, wherein the first layer portion has a first maximum depth, and the second layer portion has a second maximum depth that is less than the first maximum depth.

17. The method of claim 16, further comprising forming a semiconductor device on the single-crystal semiconductor region.

18. The method according to claim 16, in, The formation of the trench isolation region includes: forming the first trench isolation region in the semiconductor substrate between the first and second segments of the semiconductor structure; and forming a plurality of second trench isolation regions in the semiconductor substrate in the second segment, such that the protective layer extends laterally between the second trench isolation regions and is further located on a second side laterally adjacent to the first trench isolation region. The formation and recrystallization of the doped region are performed, such that the multilayer polycrystalline semiconductor region includes multiple first-layer portions and multiple second-layer portions. The first layer is physically separated from the top surface of the semiconductor substrate, and is located at least below the single-crystal semiconductor region, the first trench isolation region, and each of the second trench isolation regions. The second layer portion is located on the top surface of the semiconductor substrate and is situated on the second side that is at least laterally adjacent to the first trench isolation region, and extends laterally between the second trench isolation regions.

19. The method according to claim 18, wherein, After the multilayer polycrystalline semiconductor region is formed, an additional single-crystal semiconductor region extends from the multilayer polycrystalline semiconductor region to the bottom surface of the semiconductor substrate in the first segment and the second segment.

20. The method according to claim 19, in, The formation of the trench isolation region also includes forming a third trench isolation region in the semiconductor substrate adjacent to the third segment of the semiconductor structure. The multilayer polycrystalline semiconductor region is further formed such that one of the first layer portions is below the third trench isolation region, and the additional single-crystal semiconductor region extends from the top surface of the semiconductor substrate to the bottom surface of the semiconductor substrate in the third segment.

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