Mask, semiconductor structure and method of forming the same

Abstract

A mask, a semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate; forming a gate structure and a drain in the substrate on one side of the gate structure; forming a dielectric layer covering the gate structure and the drain; etching the dielectric layer to form a first opening exposing the drain; etching the dielectric layer and part of the drain to form a second opening, the second opening intersecting the first opening, and a bottom surface of the second opening being lower than a bottom surface of the first opening; and forming a conductive layer in the first opening and the second opening, the conductive layer in the first opening serving as a drain plug, and the conductive layer in the second opening serving as a cross plug. In the embodiment, a sidewall of the cross plug contacts the drain, the contact area between the drain and the conductive layer is increased, the conduction resistance between the drain and the conductive layer is reduced, and the electrical performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a photomask, a semiconductor structure and a method for forming the same. Background Technology

[0002] In the development of power integrated circuits, single-chip manufacturing processes developed to integrate power switches and control circuits, especially the lateral double diffusion metal-oxide-semiconductor (LDMOS) process currently used for fabricating monolithic integrated circuits, have become a mainstream trend. The LDMOS process involves planar diffusion on the surface of a semiconductor substrate to form the main lateral current path. Because LDMOS is manufactured using typical IC processes, the control circuit and LDMOS can be integrated onto a single monolithic power IC. The LDMOS process employs reduced surface electric field (RESURE) technology and low-thickness epitaxy (BPI) or N-well regions to achieve high voltage and low on-resistance.

[0003] LDMOS devices are field-effect transistors (FETs) similar to traditional FET devices. Both include a pair of source / drain regions separated by a channel region formed in a semiconductor substrate, and a gate electrode formed sequentially above the channel region. However, unlike traditional FET devices, where the source / drain regions are symmetrical to the gate electrode, the drain region in LDMOS devices is formed further away from the gate electrode than the source region. Furthermore, the drain region is formed in a doped well (with the same polarity as the drain region) that separates the channel region and the drain region. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a photomask, a semiconductor structure and a method for forming the same, thereby optimizing the electrical performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a photomask, comprising: a substrate; a gate structure located on the substrate; a drain located in the substrate on one side of the gate structure; a dielectric layer located on the gate structure and the drain; and a first opening penetrating the dielectric layer to expose the drain. The photomask is characterized in that it comprises: a mask pattern, the mask pattern including a first pattern, the first pattern being used to form a second opening in the dielectric layer exposing the drain, the extension direction of the second opening intersecting the extension direction of the first opening, and the bottom surface of the second opening being lower than the bottom surface of the first opening.

[0006] This invention provides a method for forming a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; a drain located in the substrate on one side of the gate structure; a dielectric layer located on the gate structure and the drain; a first opening penetrating the dielectric layer and exposing the drain; and a mask, characterized in that it comprises: a mask pattern, the mask pattern including a first pattern, the first pattern being used to form a second opening in the dielectric layer exposing the drain, the extension direction of the second opening intersecting the extension direction of the first opening, and the bottom surface of the second opening being lower than the bottom surface of the first opening.

[0007] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; a drain located in the substrate on one side of the gate structure; a dielectric layer located on the gate structure and the drain; a drain plug extending through the dielectric layer and connected to the top of the drain; and a cross plug extending through the dielectric layer and connected to the drain, wherein the extending direction of the cross plug intersects the extending direction of the drain plug, and the bottom surface of the cross plug is lower than the bottom surface of the drain plug.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure formation method provided by the embodiments of the present invention, the dielectric layer is etched to form a first opening exposing the drain electrode. The first opening exposes the top surface of the drain electrode. After forming the first opening, the dielectric layer and a portion of the drain electrode are etched to form a second opening. The second opening intersects the first opening, and the bottom surface of the second opening is lower than the bottom surface of the first opening. The second opening exposes the top surface of the drain electrode, and the sidewall of the second opening exposes a portion of the drain electrode. A conductive layer is formed in the first opening and the second opening. The conductive layer in the first opening serves as a drain plug, and the conductive layer in the second opening serves as a cross plug. In this embodiment, the bottom surface of the drain plug formed in the first opening contacts the drain electrode, and the sidewall and bottom surface of the cross plug formed in the second opening contact the drain electrode. This increases the contact area between the drain electrode and the conductive layer, reduces the on-resistance between the drain electrode and the conductive layer, and is beneficial to improving the electrical performance of the semiconductor structure. Attached Figure Description

[0010] Figure 1 and Figure 2 This is a schematic diagram of a key step in a semiconductor structure formation method;

[0011] Figures 3 to 22 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention;

[0012] Figure 23 This is a schematic diagram of the structure of the photomask of the present invention. Detailed Implementation

[0013] As the background technology shows, the semiconductor structures currently formed still suffer from poor electrical performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure formation method.

[0014] refer to Figure 1 and Figure 2 The diagram shows a schematic representation of a key step in a semiconductor structure formation method.

[0015] like Figure 1 As shown, a substrate has adjacent well regions 1 and drift regions 2 formed therein; a gate structure 3 is located on the substrate at the junction of the well regions 1 and drift regions 2; and a drain 4 is located in the drift region 2 on one side of the gate structure 3.

[0016] like Figure 2 As shown, a dielectric layer 5 is formed on the drain 4 and the gate structure 3; the dielectric layer 5 is etched to form an opening (not shown in the figure) exposing the drain 4; a drain plug 6 connected to the drain 4 is formed in the opening.

[0017] The drain plug 6 is used to connect the drain 4 to the downstream metal. The contact resistance between the drain plug 6 and the drain 4 is an important parameter of the electrical performance of the semiconductor structure. As the integration of the semiconductor structure increases, the contact resistance between the drain plug 6 and the drain 4 has an increasingly greater impact on the semiconductor structure. If the contact resistance between the drain plug 6 and the drain 4 is too high, the electrical performance of the semiconductor structure will be poor.

[0018] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a gate structure and a drain located on one side of the gate structure in the substrate; forming a dielectric layer covering the gate structure and the drain; etching the dielectric layer to form a first opening exposing the drain; etching the dielectric layer and a portion of the drain to form a second opening, the second opening intersecting the first opening, and the bottom surface of the second opening being lower than the bottom surface of the first opening; forming conductive layers in the first opening and the second opening, the conductive layer in the first opening serving as a drain plug, and the conductive layer in the second opening serving as a cross plug.

[0019] In the semiconductor structure formation method provided by the embodiments of the present invention, the dielectric layer is etched to form a first opening exposing the drain electrode. The first opening exposes the top surface of the drain electrode. After forming the first opening, the dielectric layer and a portion of the drain electrode are etched to form a second opening. The second opening intersects the first opening, and the bottom surface of the second opening is lower than the bottom surface of the first opening. The second opening exposes the top surface of the drain electrode, and the sidewall of the second opening exposes a portion of the drain electrode. A conductive layer is formed in the first opening and the second opening. The conductive layer in the first opening serves as a drain plug, and the conductive layer in the second opening serves as a cross plug. In this embodiment, the bottom surface of the drain plug formed in the first opening contacts the drain electrode, and the sidewall and bottom surface of the cross plug formed in the second opening contact the drain electrode. This increases the contact area between the drain electrode and the conductive layer, reduces the on-resistance between the drain electrode and the conductive layer, and is beneficial to improving the electrical performance of the semiconductor structure.

[0020] To make the above-mentioned objectives, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] Figures 3 to 22 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0022] refer to Figures 3 to 6 Provides a base.

[0023] The substrate is used to provide a process platform for the subsequent formation of semiconductor structures.

[0024] In this embodiment, an LDMOS fin field-effect transistor is used as an example of a semiconductor structure. Specifically, in the step of providing the substrate, the substrate includes an adjacent first region I and a second region II. The substrate of the first region I includes a substrate 100 and a fin 101 located on the substrate 100, and a well region 103 is formed in the fin 101. The substrate of the second region II includes a substrate 100 and a semiconductor layer 102 located on the substrate, and a drift region 104 is formed in the semiconductor layer 102. In other embodiments, the substrate of the first region includes a substrate and a fin located on the substrate, and a well region is formed in the fin of the first region. The substrate of the second region includes a substrate and a fin located on the substrate, and a drift region is formed in the fin of the second region.

[0025] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be a substrate made of other materials such as germanium substrate, silicon germanide substrate, silicon carbide substrate, gallium arsenide substrate, or indium gallium bismuth substrate, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0026] In this embodiment, the material of the fin 101 is the same as the material of the substrate 100, and the material of the fin 101 is silicon. In other embodiments, the material of the fin can also be a semiconductor material such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ide, and the material of the fin can also be different from the material of the substrate.

[0027] The well region 103 and the drift region 104 are in contact. The well region 103 serves as a lateral diffusion region to form a channel with a concentration gradient, and the drift region 104 is used to withstand a large partial pressure.

[0028] In this embodiment, the drift region 104 contains type I ions, and the trap region 103 contains type II ions. The first type I ions and the second type II ions have different conductivity types.

[0029] Specifically, in this embodiment, when the semiconductor structure is used to form an NLDMOS, the first type ion is an N-type ion, which includes one or more of phosphorus ions, arsenic ions, and antimony ions, and the second type ion is a P-type ion, which includes one or more of boron ions, gallium ions, and indium ions.

[0030] When the semiconductor structure is used to form a PLDMOS, the first type of ion is a P-type ion, which includes one or more of boron ions, gallium ions, and indium ions, and the second type of ion is an N-type ion, which includes one or more of phosphorus ions, arsenic ions, and antimony ions.

[0031] Specifically, the steps for providing the substrate include:

[0032] like Figure 3 As shown, an initial substrate 200 and a hard mask material layer 202 located on the initial substrate 200 are provided. The initial substrate 200 includes a first region I and a second region II. A substrate mask layer 201 is formed on the hard mask material layer 202.

[0033] like Figure 4As shown, a masking layer 204 is formed that covers the second region II and exposes the first region I; with the top of the initial substrate 200 as the etching stop position, the masking layer 204 and the substrate mask layer 201 are etched using a maskless etching process to expose the hard mask material layer 202, forming a hard mask layer 205; after forming the hard mask layer 205, the masking layer 204 and the substrate mask layer 201 are removed.

[0034] like Figure 5 As shown, the initial substrate 200 is etched using the hard mask layer 205 as a mask, forming a substrate 100 and a fin 110 on the substrate in the first region I, and forming a substrate 100 and a semiconductor layer 102 on the substrate 102 in the second region II.

[0035] like Figure 6 As shown, a protective material layer (not shown) is formed covering the substrate 100 and the fin 101; a planarization process is used to remove the protective material layer above the top of the fin 101; after removing the protective material layer above the top of the fin 101, a first implantation mask layer (not shown) is formed, exposing the fin 101 to which a well region 103 is to be formed; the fin 101 exposed by the first implantation mask layer is doped with type II ions to form the well region 103; after forming the well region 103, a second implantation mask layer (not shown) is formed covering the well region 103 and exposing a portion of the fin 101, exposing the semiconductor layer 102 to which a drift region is to be formed; the semiconductor layer 102 exposed by the second implantation mask layer is doped with type I ions to form the drift region 104. In other embodiments, in the step of forming adjacent well regions and drift regions in the substrate, the well region is formed in the fin of the first region, and the drift region is formed in the fin of the second region.

[0036] In this embodiment of the invention, type II ions are doped into the fin 101 exposed by the first implantation mask layer using ion implantation to form a well region 103. Ion implantation has the advantages of simple operation and low process cost.

[0037] In this embodiment of the invention, type I ions are doped into the fin 101 exposed by the second implantation mask layer using ion implantation to form the drift region 104. Ion implantation has the advantages of simple operation and low process cost.

[0038] In this embodiment, the first injection mask layer and the second injection mask layer serve as injection masks for forming the well region 103 and the drift region 104, respectively.

[0039] The first and second injection mask layers are made of materials that can act as masks and are easy to remove, thereby reducing damage to other film structures when removing the first and second injection mask layers.

[0040] In this embodiment, the materials of the first injection mask layer and the second injection mask layer are organic materials, such as: BARC (bottom anti-reflective coating) material, ODL (organic dielectric layer) material, photoresist, DARC (dielectric anti-reflective coating) material, DUO (Deep UV Light Absorbing Oxide) material, or APF (Advanced Patterning Film) material.

[0041] In this embodiment of the invention, the protective material layer covers the sidewall of the fin 101 and the substrate 100. Therefore, during the formation of the well region 103 and the drift region 104 by ion implantation, the protective material layer protects the substrate 100 and the fin 101, reducing the probability of damage to the substrate 100 and the fin 101.

[0042] The method for forming the semiconductor structure further includes: after forming the well region 103 and the drift region 104, removing the hard mask layer 205.

[0043] refer to Figure 7 The method for forming the semiconductor structure further includes: after forming the drift region 104 and the well region 103, etching the fin 101 along the extension direction perpendicular to the fin 101, and forming a fin opening 105 at a location away from the junction of the first region I and the second region II.

[0044] Subsequently, a source electrode is formed in the fin 101 near the junction of the first region I and the second region II at the fin opening 105. The source electrode is doped with type I ions. A body region is formed in the trap region 103 away from the junction of the first region I and the second region II at the fin opening 105. The body region is doped with type II ions. Subsequently, an interlayer dielectric layer is formed in the fin to electrically isolate the body region and the source electrode.

[0045] like Figure 8As shown, the method for forming the semiconductor structure further includes: after forming the fin opening 105, filling the fin opening 105 with an isolation material layer; etching back a portion of the thickness of the isolation material layer to form an isolation layer 106, the isolation layer 106 covering a portion of the sidewall of the fin 101, and the isolation layer 106 covering a portion of the sidewall of the fin opening 105.

[0046] The isolation layer 106 is used to isolate adjacent fins 101.

[0047] refer to Figures 9 to 13 A gate structure 111 and a drain 107 located in the substrate on one side of the gate structure 111 are formed on the substrate.

[0048] The gate structure 111 on the substrate at the junction of the well region 103 and the drift region 104 (e.g.) Figure 12 (as shown) and the drain 107 located in the drift region 104.

[0049] In this embodiment, the gate structure 111 is used to control the turning on and off of the LDMOS channel.

[0050] Specifically, in the step of forming the gate structure 111, the gate structure 111 is formed at the junction of the well region 103 and the drift region 104, with the extension direction perpendicular to the gate structure 111 being lateral. A portion of the laterally sized gate structure 111 spans the fin 101, a portion of the laterally sized gate structure 111 is formed on the semiconductor layer 102, and a portion of the gate structure 111 covers a portion of the top wall and a portion of the sidewall of the fin 101. In other embodiments, in the step of forming the gate structure, the gate structure is formed at the junction of the well region and the drift region, the gate structure spans the fin at the junction of the well region and the drift region, and covers a portion of the top wall and a portion of the sidewall of the fin.

[0051] The gate structure 111 includes: a gate dielectric layer 1111, located on the surface of the fin 101 at the junction of the well region 103 and the drift region 104; and a metal gate layer 1112, located on the gate dielectric layer 1111.

[0052] The gate dielectric layer 1111 is made of HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3.

[0053] In this embodiment, the metal gate layer 1112 is made of a magnesium-tungsten alloy. In other embodiments, the metal gate layer 1112 may also be made of W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0054] In this embodiment, the semiconductor structure further includes a sidewall 108 located on the sidewall of the gate structure 111. During the formation of the semiconductor structure, the sidewall 108 protects the sidewall of the gate structure 111.

[0055] In this embodiment, the material of the sidewall 108 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.

[0056] In the step of forming the drain 107 located in the drift region 104, the source 109 is formed in the substrate on the side of the gate structure away from the drain 107.

[0057] When the semiconductor structure is in operation, the source 109 and drain 107 provide stress to the channel, increasing the migration rate of charge carriers in the channel.

[0058] The drain 107 is located in the drift region 104 on one side of the gate structure 111, and the drain 107 is doped with type I ions; the source 109 is located in the well region 103 on the other side of the gate structure 111, and the source 109 is doped with type I ions.

[0059] Specifically, in the step of forming the drain 107, the drain 107 is formed in the semiconductor layer 102 of the second region II. In other embodiments, in the step of forming the drain, the drain is formed in the fin of the second region.

[0060] It should be noted that the drain 107 is located in the drift region 104, which is formed in the semiconductor layer 102, and the extension direction of the drain 107 is the same as the extension direction of the gate structure 111.

[0061] In this embodiment, the semiconductor structure is an NLDMOS, and the first type ions in the source 109 and drain 107 are N-type ions. In other embodiments, when the semiconductor structure is a PLDMOS, the first type ions in the source and drain regions are P-type ions respectively.

[0062] Specifically, the steps for forming the gate structure 111 and the drain 107 include:

[0063] like Figure 9 As shown, a pseudo-gate structure 110 is located on the substrate at the junction of the well region 103 and the drift region 104. The pseudo-gate structure 110 includes: a gate oxide layer 1101 located on the surface of the fin 101 at the junction of the well region 103 and the drift region 104; and a gate layer 1102 located on the gate oxide layer 1101.

[0064] The pseudo-gate structure 110 occupies space for the subsequent formation of the gate structure.

[0065] In this embodiment, the pseudo-gate structure 110 is a polysilicon gate structure, and correspondingly, the gate oxide layer 1101 is made of silicon oxide; the gate layer 1102 is made of polysilicon.

[0066] After the pseudo-gate structure 110 is formed, a source electrode 109 is formed in the well region 103 near the junction of the first region I and the second region II at the fin opening 105, and a drain electrode 107 is formed in the drift region 104 on the other side of the pseudo-gate structure 110.

[0067] In this embodiment, the source 109 and drain 107 are doped with type I ions.

[0068] It should be noted that the method for forming the semiconductor structure further includes: forming a body region 113 in the well region 103 located at the junction of the fin opening 105 and the first region I and the second region II, wherein the body region 113 is doped with type II ions.

[0069] like Figure 10 As shown, an interlayer dielectric layer 112 is formed on the well region 103 and drift region 104 exposed in the pseudo-gate structure 110, and the interlayer dielectric layer 112 is exposed on the top of the pseudo-gate structure 110.

[0070] The interlayer dielectric layer 112 is used for electrical isolation of adjacent devices.

[0071] In this embodiment, the material of the interlayer dielectric layer 112 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 112.

[0072] In this embodiment, the interlayer dielectric layer 112 is formed using a flowable chemical vapor deposition (FCVD) process. The flowable chemical vapor deposition process has good filling capabilities, which helps reduce the probability of voids and other defects forming within the interlayer dielectric layer 112, thereby improving the film quality of the interlayer dielectric layer 112.

[0073] It should be noted that, in the step of forming the interlayer dielectric layer 112, the interlayer dielectric layer 112 is also formed in the fin opening 105.

[0074] The interlayer dielectric layer 112 is also used for the electrical isolation region 113 and the source electrode 109.

[0075] like Figure 11 As shown, the pseudo-gate structure 110 is removed to form a gate opening 114.

[0076] The gate opening 114 provides process space for the subsequent formation of the metal gate structure.

[0077] like Figure 12 and Figure 13 As shown, Figure 13 The top view shows only the body region 113, source 109, drain 107 and gate structure 111, with the gate structure 111 formed in the gate opening 114.

[0078] The method for forming the semiconductor structure further includes: after forming the gate structure 111, etching back a portion of the thickness of the gate structure 111, forming a gate groove (not shown in the figure) on the top of the gate structure 111; and forming a gate cap layer 118 in the gate groove.

[0079] During the subsequent formation of the semiconductor structure, the gate cap layer 118 is used to protect the gate structure 111 so that it has a good morphology.

[0080] refer to Figure 14 and Figure 15 , Figure 15 for Figure 14 In the cross-sectional view at AA, a dielectric layer 115 is formed covering the gate structure 111 and the drain 107.

[0081] The dielectric layer 115 is used for electrical isolation of the source / drain plugs and gate plugs subsequently formed therein.

[0082] In this embodiment, the dielectric layer 115 is made of silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the dielectric layer 115.

[0083] In this embodiment, the dielectric layer 115 is formed using a fluid chemical vapor deposition process.

[0084] Continue to refer to Figure 14 and Figure 15 The dielectric layer 115 is etched to form a first opening 116 that exposes the drain 107.

[0085] The first opening 116 is in preparation for the subsequent formation of the drain plug.

[0086] In this embodiment, a dry etching process is used to etch the dielectric layer 115 and the interlayer dielectric layer 112 to form a first opening 116 exposing the drain 107. The dry etching process has anisotropic etching characteristics and good control over the etching profile, which helps to ensure that the morphology of the first opening 116 meets process requirements and also improves the removal efficiency of the dielectric layer 115 and the interlayer dielectric layer 112. Furthermore, during the formation of the first opening 116 using the dry etching process, the top of the drain 107 can be used as the etching stop position.

[0087] It should be noted that, in the step of forming the first opening 116 in the dielectric layer 115, the dielectric layer 115 is also etched to form a fourth opening 117 that exposes the source electrode 109.

[0088] The fourth opening 117 is in preparation for the subsequent formation of a source plug that connects to the source 109.

[0089] It should be noted that, in the step of forming the first opening 116 in the dielectric layer 115, the dielectric layer 115 is also etched to form a fifth opening 118 that exposes the body region 113.

[0090] The fifth opening 118 is prepared for the subsequent formation of a body region plug that connects to the body region 113.

[0091] It should be noted that in this embodiment, the extension direction of the first opening 116 is the same as the extension direction of the gate structure 111.

[0092] Because the drain 107 is located in the drift region 104 and extends in the same direction as the gate structure 111, the extension direction of the first opening 116 is the same as the extension direction of the gate structure 111, resulting in a larger contact area between the drain plug subsequently formed in the first opening 116 and the drain 107.

[0093] refer to Figures 16 to 19 The dielectric layer 115 and a portion of the drain 107 are etched to form a second opening 119, which intersects with the first opening 116, and the bottom surface of the second opening 119 is lower than the bottom surface of the first opening 116.

[0094] The dielectric layer 115 is etched to form a first opening 116 exposing the drain 107. The first opening 116 exposes the top surface of the drain 107. After forming the first opening 116, the dielectric layer 115 and a portion of the thickness of the drain 107 are etched to form a second opening 119. The second opening 119 intersects with the first opening 116, and the bottom surface of the second opening 119 is lower than the bottom surface of the first opening 116. The second opening 119 exposes the top surface of the drain 107, and the sidewalls of the second opening 119 expose a portion of the drain 107. Subsequent etching is performed on the... Conductive layers are formed in the first opening 116 and the second opening 119. The conductive layer in the first opening 116 serves as a drain plug, and the conductive layer in the second opening 119 serves as a cross plug. In this embodiment, the bottom surface of the drain plug formed in the first opening 116 contacts the drain 107, and the sidewall and bottom surface of the cross plug formed in the second opening 119 contact the drain 107. This increases the contact area between the drain 107 and the conductive layer, reduces the on-resistance between the drain 107 and the conductive layer, and is beneficial to improving the electrical performance of the semiconductor structure.

[0095] In this embodiment, a dry etching process is used to etch the dielectric layer 115 and a portion of the drain 107 to form the second opening 119. The dry etching process has anisotropic etching characteristics and good control over the etching profile, which helps ensure that the morphology of the second opening 119 meets process requirements and also improves the removal efficiency of the dielectric layer 115 and the interlayer dielectric layer 112. Furthermore, the removal thickness of the drain 107 can be precisely controlled during the formation of the second opening 119 using the dry etching process. Moreover, the dry etching process allows for the etching of the dielectric layer 115, the interlayer dielectric layer 115, and the drain 107 on the same equipment by changing the gas, thus reducing the cost of semiconductor processes.

[0096] It should be noted that in the step of etching the dielectric layer 115 to form the second opening 119, the distance from the bottom surface of the second opening 119 to the bottom surface of the first opening 116 should not be too large or too small. If the distance is too large, the drain 107 will be etched to a greater thickness during the formation of the second opening 119. When the semiconductor structure is working, the drain 107 will not be able to provide sufficient stress to the channel, resulting in a lower carrier migration rate in the channel and poor electrical performance of the semiconductor structure. If the distance is too small, the drain 107 will be etched to a smaller thickness during the formation of the second opening 119, and the area of ​​the drain 107 exposed on the sidewall of the second opening 119 will be too small. The second opening 119 will not significantly increase the exposed area of ​​the drain 107. After the conductive layer is formed in the first opening 116 and the second opening 119, the contact resistance between the conductive layer and the drain 107 will still be relatively large, which will not meet the process requirements. In this embodiment, the distance between the bottom surface of the second opening 119 and the bottom surface of the first opening 116 is 5 nanometers to 30 nanometers.

[0097] Specifically, the steps for forming the second opening 119 include:

[0098] like Figure 16 As shown, an opening mask layer 120 is formed in the first opening 116 and on the dielectric layer 115.

[0099] The opening mask layer 120 serves as a mask for etching the dielectric layer 115 and a portion of the thickness of the drain 107 to form a second opening.

[0100] In this embodiment, the photoresist layer 1202 has a first groove 122 corresponding to the drain 107. In a subsequent process, the dielectric layer 115 and the interlayer dielectric layer 112 exposed by the first groove 122, as well as a portion of the thickness of the drain 107, are etched to form a second opening.

[0101] It should be noted that there are multiple first grooves 122, and the first grooves 122 are arranged along the extension direction of the gate structure. Having multiple first grooves 122 helps to increase the exposed area of ​​the drain 107, reduce the on-resistance between the subsequently formed conductive layer and the drain 107, and improve the electrical performance of the semiconductor structure.

[0102] In this embodiment, the opening mask layer 120 includes an anti-reflective coating 1201 and a photoresist layer 1202 located on the anti-reflective coating 1201.

[0103] It should be noted that the photoresist layer 1202 also has a second groove 123 corresponding to the gate structure 111.

[0104] In the subsequent step of forming the first opening using the opening mask layer 120 as a mask, the dielectric layer 115 and the interlayer dielectric layer 112 exposed by the second groove 123 are also etched to form a third opening exposing the gate structure 111.

[0105] In this embodiment, the extension direction of the second groove 123 is the same as the extension direction of the first groove 122.

[0106] The extension direction of the second groove 123 is the same as that of the first groove 122, so that the optical proximity effect (OPE) is less affected during the formation of the second groove 123 and the first groove 122, which is beneficial to improving the formation quality of the second groove 123 and the first groove 122.

[0107] In other embodiments, the extension directions of the second groove and the first groove intersect.

[0108] like Figures 17 to 19 As shown, Figure 18 for Figure 17 Cross-sectional view at BB. Figure 19 for Figure 17 Top view, Figure 19 The diagram shows only a top view of the first opening 116, the second opening 119, and the third opening 121. The dielectric layer 115 is etched using the opening mask layer 120 as a mask to form the second opening 119, which intersects with the first opening 116.

[0109] In this embodiment, a conductive layer is subsequently formed in the first opening 116 and the second opening 119. The bottom surface of the second opening 119 is lower than the bottom surface of the first opening 116, and the sidewall of the second opening 119 exposes a portion of the drain 107. Therefore, in this embodiment of the invention, compared to the case where only the first opening is formed to expose the top of the drain, the contact area between the subsequently formed conductive layer and the drain 107 is larger, which can reduce the contact resistance between the conductive layer and the drain 107 and is beneficial to improving the electrical performance of the semiconductor structure.

[0110] In this embodiment, the dielectric layer 115 and a portion of the drain electrode 107 are etched using a dry etching process with the opening mask layer 120 as a mask to form a second opening 119.

[0111] Specifically, the process parameters for etching the dielectric layer 115 using a dry etching process with the opening mask layer 120 as a mask to form the second opening 119 include: the etching gas includes one or more of CF4, CH3F, CH2F2, CHF3 and C4F6.

[0112] It should be noted that the flow rate of the etching gas in the step of forming the second opening 119 should not be too high or too low. If the flow rate of the etching gas is too high, it will easily lead to excessive pressure in the reaction chamber, and the etching rate of the dielectric layer 115 will be too fast, which will easily reduce the process controllability and reaction rate uniformity of the etching process, resulting in poor process stability. This will also lead to excessively large rounded corners at the bottom of the second opening 119, meaning that the area of ​​the drain 107 exposed by the second opening 119 will be too small. Consequently, the contact area between the conductive layer subsequently formed in the second opening 119 and the drain 107 will be small. The presence of the second opening 119 will not significantly reduce the on-resistance between the subsequently formed conductive layer and the drain 107, resulting in poor electrical performance of the semiconductor structure. If the flow rate of the etching gas is too low, it will easily lead to excessively low pressure in the reaction chamber, and the etching rate of the dielectric layer 115 will be low, which is not conducive to improving the formation efficiency of the second opening 119. In this embodiment, during the step of forming the second opening 119, the flow rate of the etching gas is 10 sccm to 200 sccm.

[0113] It should be noted that the chamber pressure should not be too high or too low during the step of forming the second opening 119. If the chamber pressure is too high, the decomposition rate of the byproducts generated by etching the dielectric layer 115 will be too slow, and correspondingly, the rate at which the byproducts are discharged from the chamber will be too slow. In addition, if the chamber pressure is too high, the etching gas will also etch the dielectric layer 115 at a faster rate, which will easily reduce the process controllability and reaction rate uniformity of the etching process. This will result in the bottom of the second opening 119 having an excessively large rounded corner, that is, the area of ​​the drain 107 exposed by the second opening 119 will be too small. Consequently, the contact area between the conductive layer subsequently formed in the second opening 119 and the drain 107 will be small. The presence of the second opening 119 will not significantly reduce the conduction resistance between the subsequently formed conductive layer and the drain 107, resulting in poor electrical performance of the semiconductor structure. If the chamber pressure is too low, the plasma density of the etching gas in the chamber will be low, which will easily lead to a lower etching rate of the dielectric layer 115 and will not be conducive to improving the formation efficiency of the second opening 119. In this embodiment, during the step of forming the second opening 119, the chamber pressure is 10 mTorr to 60 mTorr.

[0114] It should be noted that in the step of forming the second opening 119, the extension direction of the second opening 119 is perpendicular to the extension direction of the first opening 116.

[0115] In this embodiment, the second opening 119 is formed by etching the dielectric layer 115 using the opening mask layer 120 as a mask. The process of forming the opening mask layer 120 includes exposure. The extension direction of the second opening 119 is perpendicular to the extension direction of the first opening 116. During the formation of the opening mask layer 120, the interference of the optical proximity effect (OPE) is reduced, which helps to reduce the formation difficulty of the opening mask layer 120. This results in a larger area of ​​the drain electrode 107 exposed by the second opening 119. Consequently, the contact area between the conductive layer subsequently formed in the second opening 119 and the drain electrode 107 is larger, reducing the on-resistance between the subsequently formed conductive layer and the drain electrode 107 and improving the electrical performance of the semiconductor structure.

[0116] The method for forming the semiconductor structure further includes: in the step of forming the second opening 119, the dielectric layer 115 is also etched to form a third opening 121 that exposes the gate structure 111.

[0117] The third opening 121 is in preparation for the subsequent formation of the gate plug.

[0118] Specifically, the third opening 121 and the second opening 119 are both formed by etching using the opening mask layer 120 as a mask.

[0119] It should be noted that before forming the third opening 121, the gate cap layer 118 is also etched.

[0120] In this embodiment, the gate cap layer 118 is etched using the opening mask layer 120 as a mask.

[0121] The method for forming the semiconductor structure further includes: after forming the second opening 119, removing the opening mask layer 120.

[0122] The removal of the opening mask layer 120 prepares for the subsequent formation of conductive layers in the first opening 116, the second opening 119, the third opening 121, the fourth opening 117, and the fifth opening 118.

[0123] In this embodiment, the opening mask layer 120 is removed using an ashing process.

[0124] refer to Figures 20 to 22 , Figure 21 for Figure 20 Cross-sectional view at point CC. Figure 22 for Figure 20 The top view shows conductive layers formed in the first opening 116 and the second opening 119. The conductive layer in the first opening 116 serves as a drain plug 124, and the conductive layer in the second opening serves as a cross plug 125.

[0125] The first opening 116 exposes the top surface of the drain 107, and the second opening 119 exposes the top surface of the drain 107, with a portion of the drain 107 exposed on the sidewall of the second opening 119. A conductive layer is formed in the first opening 116 and the second opening 119. The conductive layer in the first opening 116 serves as a drain plug 124, and the conductive layer in the second opening 119 serves as a cross plug 125. In this embodiment, the bottom surface of the drain plug 124 formed in the first opening 116 contacts the drain 107, and the sidewall and bottom surface of the cross plug 125 formed in the second opening 119 contact the drain 107. This increases the contact area between the drain 107 and the conductive layer, reduces the on-resistance between the drain 107 and the conductive layer, and is beneficial for improving the electrical performance of the semiconductor structure.

[0126] In this embodiment, the conductive layer is made of Cu. Cu has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the contact resistance between the conductive layer and the drain 107, thereby reducing power consumption. In other embodiments, the conductive layer may be made of one or more of Co, W, Ta, TaN, Ti, and TiN.

[0127] It should be noted that, in the step of forming a conductive layer in the first opening 116 and the second opening 119, the conductive layer in the third opening 121 serves as a gate plug 126.

[0128] The gate plug 126 is used to connect the gate structure 111 to the downstream metal.

[0129] It should be noted that, in the step of forming a conductive layer in the first opening 116 and the second opening 119, the conductive layer is also formed in the fourth opening 117, and the conductive layer in the fourth opening 117 serves as the source plug 127.

[0130] The source plug 127 is used to connect the source 109 to the downstream metal.

[0131] It should be noted that, in the step of forming a conductive layer in the first opening 116 and the second opening 119, the conductive layer is also formed in the fifth opening 118, and the conductive layer in the fifth opening 118 serves as a body plug 128.

[0132] The body plug 128 is used to connect the body region 113 to the rear metal section.

[0133] The steps of forming the conductive layer include: filling the first opening 116, the second opening 119, the third opening 121, the fourth opening 117, and the fifth opening 118 with conductive material layers; removing the conductive material layers above the dielectric layer 115 using a planarization process; and using the remaining conductive material layers located in the first opening 116, the second opening 119, the third opening 121, the fourth opening 117, and the fifth opening 118 as the conductive layer.

[0134] In this embodiment, the conductive material layer is formed using an electrochemical electroplating process. Electrochemical electroplating offers advantages such as simple operation, fast deposition rate, and low cost.

[0135] refer to Figures 20 to 22 , Figure 21 for Figure 20 Cross-sectional view at point CC. Figure 22 for Figure 20 The top view of the invention also shows a semiconductor structure.

[0136] The semiconductor structure includes: a substrate; a gate structure 111 located on the substrate; a drain 107 located in the substrate on one side of the gate structure 111; a dielectric layer 115 located on the gate structure 111 and the drain 107; a drain plug 124 penetrating the dielectric layer 115 and connected to the top of the drain 107; and a cross plug 125 penetrating the dielectric layer 115 and connected to the drain 107, wherein the extending direction of the cross plug 125 intersects the extending direction of the drain plug 124, and the bottom surface of the cross plug 125 is lower than the bottom surface of the drain plug 124.

[0137] In the semiconductor structure, both the cross plug 125 and the drain plug 124 are connected to the drain 107. The cross plug 125 and the drain plug 124 intersect, and the bottom surface of the cross plug 125 is lower than the bottom surface of the drain plug 124. Therefore, compared with the case where only the drain plug 124 is connected to the drain 107, in this embodiment of the invention, the sidewall of the cross plug 125 has a larger contact with the drain 107. By using the drain plug 124 and the cross plug 125 as conductive layers, the contact area between the drain 107 and the conductive layer is increased, the on-resistance between the drain 107 and the conductive layer is reduced, and the electrical performance of the semiconductor structure is improved.

[0138] The substrate is used as a process platform for LDMOS.

[0139] In this embodiment, an LDMOS fin field-effect transistor is used as an example of a semiconductor structure. Specifically, in the step of providing the substrate, the substrate includes adjacent first region I and second region II. The substrate in the first region I includes a substrate 100 and a fin located on the substrate 100, wherein a well region 103 is formed in the fin. The substrate in the second region II includes a substrate 100 and a semiconductor layer located on the substrate, wherein a drift region 104 is formed in the semiconductor layer. In other embodiments, the substrate in the first region includes a substrate and a fin located on the substrate, wherein a well region is formed in the fin of the first region. The substrate in the second region includes a substrate and a fin located on the substrate, wherein a drift region is formed in the fin of the second region.

[0140] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be a substrate made of other materials such as germanium substrate, silicon germanide substrate, silicon carbide substrate, gallium arsenide substrate, or indium gallium bismuth substrate, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0141] In this embodiment, the material of the fin is the same as the material of the substrate 100, which is silicon. In other embodiments, the material of the fin can also be a semiconductor material such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the material of the fin can also be different from the material of the substrate.

[0142] The well region 103 and the drift region 104 are in contact. The well region 103 serves as a lateral diffusion region to form a channel with a concentration gradient, and the drift region 104 is used to withstand a large partial pressure.

[0143] In this embodiment, the drift region 104 contains type I ions, and the trap region 103 contains type II ions. The first type I ions and the second type II ions have different conductivity types.

[0144] Specifically, in this embodiment, when the semiconductor structure is NLDMOS, the first type ion is an N-type ion, which includes one or more of phosphorus ions, arsenic ions, and antimony ions, and the second type ion is a P-type ion, which includes one or more of boron ions, gallium ions, and indium ions.

[0145] When the semiconductor structure is PLDMOS, the first type of ion is a P-type ion, which includes one or more of boron ions, gallium ions, and indium ions, and the second type of ion is an N-type ion, which includes one or more of phosphorus ions, arsenic ions, and antimony ions.

[0146] In this embodiment, the well region 103 is located in the fin, and the drift region 104 is located in the semiconductor layer. In other embodiments, the well region is located in the fin of the first region, and the drift region is located in the fin of the second region.

[0147] The semiconductor structure further includes an isolation layer 106 that covers part of the sidewalls of the source 109 and the body region 113.

[0148] The isolation layer 106 is used to isolate adjacent fins 101.

[0149] When the semiconductor structure is in operation, the gate structure 111 is used to control the opening and closing of the channel.

[0150] In this embodiment, the gate structure 111 is located at the junction of the well region 103 and the drift region 104. With its extension direction perpendicular to the lateral direction, a portion of the gate structure 111 spans the fin 101. This portion of the gate structure 111 is formed on the semiconductor layer 102, and a portion of the gate structure 111 covers a portion of the top wall and a portion of the sidewall of the fin 101. In other embodiments, the gate structure spans the fin at the junction of the well region and the drift region, and covers a portion of the top wall and a portion of the sidewall of the fin.

[0151] Therefore, the gate structure 111 includes: a gate dielectric layer 1111 located on the fin surface at the junction of the well region 103 and the drift region 104; and a metal gate layer 1112 located on the gate dielectric layer 1111.

[0152] The gate dielectric layer 1111 is made of HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3.

[0153] In this embodiment, the metal gate layer 1112 is made of a magnesium-tungsten alloy. In other embodiments, the metal gate layer 1112 may also be made of W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0154] The semiconductor structure further includes a sidewall 108 located on the sidewall of the gate structure 111. During the formation of the semiconductor structure, the sidewall 108 protects the sidewall of the gate structure 111.

[0155] In this embodiment, the material of the sidewall 108 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.

[0156] The semiconductor structure further includes a source 109 located in the substrate on the side of the gate structure 111 away from the drain 107. Specifically, the source 109 is located in the well region 103.

[0157] When the semiconductor structure is in operation, the source 109 and drain 107 provide stress to the channel, increasing the migration rate of charge carriers in the channel.

[0158] The drain 107 is located in the drift region 104 on one side of the gate structure 111, and the drain 107 is doped with type I ions; the source 109 is located in the well region 103 on the other side of the gate structure 111, and the source 109 is doped with type I ions.

[0159] Specifically, the drain 107 is formed in the semiconductor layer of the second region II. In other embodiments, in the step of forming the drain, the drain is formed in the fin of the second region.

[0160] It should be noted that the drain 107 is located in the drift region 104, which is formed in the semiconductor layer, and the extension direction of the drain 107 is the same as the extension direction of the gate structure 111.

[0161] In this embodiment, the semiconductor structure is an NLDMOS, and the first type ions in the source 109 and drain 107 are N-type ions. In other embodiments, when the semiconductor structure is a PLDMOS, the first type ions in the source and drain regions are P-type ions respectively.

[0162] The semiconductor structure further includes a body region 113, spaced apart on the side of the source 109 away from the gate structure 111.

[0163] The semiconductor structure further includes an interlayer dielectric layer 112 located on the side of the gate structure 111, exposing the top of the gate structure 111, and the gate structure 111 covering the well region 103 and the drift region 104.

[0164] The dielectric layer 115 is used for electrical isolation of plugs subsequently formed therein.

[0165] In this embodiment, the dielectric layer 115 is made of silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the dielectric layer 115.

[0166] The drain plug 124 and the cross plug 125 are part of the conductive layer, which is connected to the drain 107.

[0167] In this embodiment, the conductive layer is made of Cu. Cu has low resistivity, which helps improve the signal delay in the subsequent RC circuit, increasing the chip's processing speed. It also helps reduce the contact resistance between the conductive layer and the drain 107, thereby reducing power consumption. In other embodiments, the conductive layer may be made of one or more of Co, W, Ta, TaN, Ti, and TiN.

[0168] It should be noted that the distance between the bottom surface of the cross plug 125 and the bottom surface of the drain plug 124 should not be too large or too small. If the distance is too large, that is, the distance between the bottom surface of the cross plug 125 and the bottom surface of the drain plug 124 is too large, the corresponding volume of the drain 107 is small. When the semiconductor structure is working, the drain 107 is not likely to provide sufficient stress to the channel, resulting in a low carrier migration rate in the channel and poor electrical performance of the semiconductor structure. If the distance is too small, the contact area between the sidewall of the cross plug 125 and the drain 107 is too small. The cross plug is not significant in increasing the contact area between the drain 107 and the conductive layer, which easily leads to a still large contact resistance between the conductive layer and the drain 107, failing to meet process requirements. In this embodiment, the distance between the bottom surface of the cross plug 125 and the bottom surface of the drain plug 124 is 5 nanometers to 30 nanometers.

[0169] In this embodiment, the extension direction of the drain plug 124 is the same as the extension direction of the gate structure 111.

[0170] Because the drain 107 is located in the drift region 104 and extends in the same direction as the gate structure 111, the extension direction of the drain plug 124 is the same as the extension direction of the gate structure 111, resulting in a larger contact area between the drain plug 124 and the drain 107.

[0171] In this embodiment, the extension direction of the cross plug 125 is perpendicular to the extension direction of the drain plug 125.

[0172] During the formation of the cross plug 125, the dielectric layer 115 is etched using the opening mask layer as a mask, forming a space in the dielectric layer 115. During the formation of the opening mask layer 120, the interference of the optical proximity effect (OPE) is reduced, which helps to reduce the formation difficulty of the opening mask layer, resulting in a larger contact area between the cross plug 125 and the drain 107, reducing the on-resistance between the conductive layer and the drain 107, and improving the electrical performance of the semiconductor structure.

[0173] The semiconductor structure includes a gate plug 126 that penetrates the dielectric layer 115 and is connected to the gate structure 111.

[0174] The gate plug 126 is used to connect the gate structure 111 to the downstream metal.

[0175] The semiconductor structure further includes a source plug 127 that penetrates the dielectric layer 115 and is connected to the source 109.

[0176] The source plug 127 is used to connect the source 109 to the downstream metal.

[0177] The semiconductor structure further includes a body plug 128 that penetrates the dielectric layer 115 and is connected to the body region 113.

[0178] The body plug 128 is used to connect the body region 113 to the rear metal section.

[0179] The semiconductor structure further includes: an interlayer dielectric layer 112, which is located on the side of the gate structure 111; and a dielectric layer 115, which is located on the interlayer dielectric layer 112.

[0180] The interlayer dielectric layer 112 is used to electrically isolate the source electrode 109 and the body region 113.

[0181] In this embodiment, the material of the interlayer dielectric layer 112 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 112.

[0182] Combination Figure 14 refer to Figure 23 In this embodiment of the invention, a photomask is also provided.

[0183] The mask is used to form a semiconductor structure, the semiconductor structure comprising: a substrate; a gate structure 111 located on the substrate; a drain 107 located in the substrate on one side of the gate structure 111; a dielectric layer 115 located on the gate structure 111 and the drain 107; a first opening penetrating the dielectric layer 115 to expose the drain 107; the mask is characterized in that it comprises: a mask pattern, the mask pattern comprising a first pattern 301, the first pattern 301 being used to form a second opening in the dielectric layer 115 exposing the drain 107, the extension direction of the second opening intersecting the extension direction of the first opening, and the bottom surface of the second opening being lower than the bottom surface of the first opening.

[0184] In this embodiment, the extension direction of the second opening formed by the mask pattern intersects with the extension direction of the first opening, and the bottom surface of the second opening is lower than the bottom surface of the first opening. The first opening exposes the top surface of the drain 107, the second opening exposes the top surface of the drain 107, and the sidewall of the second opening exposes a portion of the drain 107. In this embodiment, the first and second openings expose more of the area of ​​the drain 107. Subsequently, conductive layers are formed in the first and second openings. The conductive layer formed in the first opening serves as a drain plug, and the conductive layer formed in the second opening serves as a cross plug. The sidewall and bottom surface of the cross plug formed in the second opening are in contact with the drain 107, and the bottom surface of the drain plug formed in the first opening is in contact with the drain 107. Compared with the case where only the drain plug is connected to the drain 107, in this embodiment, the sidewall of the cross plug is in contact with the drain 107, which increases the contact area between the drain 107 and the conductive layer, reduces the on-resistance between the drain 107 and the conductive layer, and improves the electrical performance of the semiconductor structure.

[0185] In this embodiment, the extension direction of the first opening is the same as the extension direction of the gate structure 101.

[0186] The drain 107 is formed in the drift region 104 on one side of the gate structure 111, and the drain 107 extends in the same direction as the gate structure 111. The first opening extends in the same direction as the gate structure 101, so that the first opening can expose more of the drain 107, resulting in a larger contact area between the drain plug 124 and the drain 107.

[0187] In this embodiment, the extension direction of the second opening is perpendicular to the extension direction of the first opening.

[0188] In this embodiment, the second opening is formed by exposing and etching the dielectric layer 115 using the first pattern 301. The extension direction of the second opening is perpendicular to the extension direction of the first opening. During the formation of the second opening, the interference of the optical proximity effect (OPE) is reduced, which helps to reduce the difficulty of forming the second opening. This results in a larger area of ​​the drain 107 exposed by the second opening. Consequently, the contact area between the conductive layer subsequently formed in the second opening 119 and the drain 107 is larger, reducing the on-resistance between the subsequently formed conductive layer and the drain 107 and improving the electrical performance of the semiconductor structure.

[0189] It should be noted that the mask also includes a second pattern 302, which is used to form a third opening in the dielectric layer 115 to expose the gate structure 111.

[0190] The third opening is in preparation for the subsequent formation of a gate plug that connects to the gate structure 101.

[0191] In this embodiment, the extension direction of the second graphic 302 is the same as the extension direction of the first graphic 301.

[0192] The extension direction of the second pattern 302 is the same as that of the first pattern 301. Therefore, the influence of the optical proximity effect (OPE) is relatively small during the subsequent formation of the first opening and the second opening based on the first pattern 301 and the second pattern 302, which is beneficial to improving the formation quality of the first opening and the second opening.

[0193] In other embodiments, the extending directions of the second groove and the first groove may also intersect.

[0194] The mask pattern has both a first pattern and a second pattern, which can form a second opening and a third opening in the same etching process, which helps to simplify the semiconductor structure formation process and improve the semiconductor structure formation efficiency.

[0195] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention should be determined by the scope defined in the claims.

Claims

1. A mask for forming a semiconductor structure, the semiconductor structure comprising: a substrate; a gate structure on the substrate; a drain in the substrate on a side of the gate structure; a dielectric layer on the gate structure and the drain; a first opening through the dielectric layer exposing the drain; the mask comprising: a mask pattern, the mask pattern comprising a first pattern for forming a second opening in the dielectric layer exposing the drain, the second opening extending in a direction intersecting a direction of extension of the first opening in a plane parallel to a surface of the substrate, and a bottom surface of the second opening being lower than a bottom surface of the first opening. The second opening extends in a direction perpendicular to the direction of extension of the first opening. The first opening extends in a direction identical to a direction of extension of the gate structure. The mask further comprises a second pattern for forming a third opening in the dielectric layer exposing the gate structure. The method for forming the semiconductor structure comprising: providing a substrate; forming a gate structure on the substrate and a drain in the substrate on a side of the gate structure; forming a dielectric layer covering the gate structure and the drain; etching the dielectric layer to form a first opening exposing the drain; etching the dielectric layer and a portion of the drain to form a second opening intersecting the first opening in a plane parallel to a surface of the substrate, and a bottom surface of the second opening being lower than a bottom surface of the first opening; forming a conductive layer in the first opening as a drain plug and in the second opening as a cross plug. The step of forming the second opening comprises: forming an opening mask layer in the first opening and on the dielectric layer; etching the dielectric layer with the opening mask layer as a mask to form the second opening intersecting the first opening. The method for forming the semiconductor structure further comprises removing the opening mask layer after forming the second opening. The dielectric layer and a portion of the drain are etched to form the second opening using a dry etching process.

2. The mask of claim 1, wherein, The process parameters for etching the dielectric layer with the opening mask layer as a mask to form the second opening comprise: the etching gas comprises one or more of CF4, CH3F, CH2F2, CHF3 and C4F6, the flow rate of the etching gas is 10-200sccm, and the chamber pressure is 10-60mTorr.

3. The mask of claim 1, wherein, In the step of etching the dielectric layer with the opening mask layer as a mask to form the second opening, the distance from the bottom surface of the second opening to the bottom surface of the first opening is 5-30nm.

4. The mask of claim 1, wherein, In the step of forming the second opening, the second opening extends in a direction perpendicular to the direction of extension of the first opening.

5. A method of forming a semiconductor structure, characterized by, In the step of forming the first opening, the first opening extends in a direction identical to a direction of extension of the gate structure. ​ ​ ​ ​ ​ ​ 6. The method of forming a semiconductor structure of claim 5, wherein, ​ ​ ​ ​ 7. The method of forming a semiconductor structure of claim 6, wherein, ​ 8. The method of forming a semiconductor structure of claim 7, wherein, ​ 9. The method of forming a semiconductor structure of claim 6, wherein, ​ 10. The method of forming a semiconductor structure of claim 5, wherein, ​ 11. The method of forming a semiconductor structure of claim 5, wherein, ​ 12. The method of forming a semiconductor structure of claim 5, wherein, In the step of etching the dielectric layer to form the second opening, a third opening is also etched in the dielectric layer to expose the gate structure; In the step of forming the conductive layer in the first and second openings, the conductive layer is also formed in the third opening, and the conductive layer in the third opening serves as a gate plug.

13. The method of forming a semiconductor structure of claim 5, wherein, In the step of forming the drain, a source is formed in the substrate away from the gate structure side of the drain; In the step of forming the first opening in the dielectric layer, a fourth opening is etched in the dielectric layer to expose the source; In the step of forming the conductive layer in the first and second openings, the conductive layer is also formed in the fourth opening, and the conductive layer in the fourth opening serves as a source plug.

14. The method of forming a semiconductor structure of claim 5, wherein, In the step of providing a substrate, the substrate includes adjacent first and second regions, the substrate of the first region includes a substrate and a fin on the substrate, the fin includes a well region formed therein, and the substrate of the second region includes a substrate and a semiconductor layer on the substrate, the semiconductor layer includes a drift region formed therein; In the step of forming the drain, the drain is formed in the drift region; In the step of forming the gate structure, the gate structure is formed at the junction of the well region and the drift region, the gate structure has a lateral dimension perpendicular to the extension direction of the gate structure, a portion of the lateral dimension of the gate structure spans the fin, a portion of the lateral dimension of the gate structure is formed on the semiconductor layer, and a portion of the gate structure covers a portion of the top wall and a portion of the sidewall of the fin.

15. The method of forming a semiconductor structure of claim 5, wherein, In the step of providing a substrate, the substrate includes adjacent first and second regions, the substrate of the first region includes a substrate and a fin on the substrate, the fin of the first region includes a well region formed therein, and the substrate of the second region includes a substrate and a fin on the substrate, the fin of the second region includes a drift region formed therein; In the step of forming the drain, the drain is formed in the fin of the second region; In the step of forming the gate structure, the gate structure is formed at the junction of the well region and the drift region, the gate structure spans the fin at the junction of the well region and the drift region, and covers a portion of the top wall and a portion of the sidewall of the fin.

16. A semiconductor structure, comprising: a substrate; a gate structure on the substrate; a drain in the substrate on a side of the gate structure; a dielectric layer on the gate structure and the drain; a drain plug through the dielectric layer and connected to a top of the drain; a cross plug through the dielectric layer and connected to the drain, the extension direction of the cross plug intersects the extension direction of the drain plug in a plane parallel to the surface of the substrate, and the bottom surface of the cross plug is lower than the bottom surface of the drain plug.

17. The semiconductor structure of claim 16, wherein, The extension direction of the drain plug is the same as the extension direction of the gate structure.

18. The semiconductor structure of claim 16, wherein, The distance from the bottom surface of the cross plug to the bottom surface of the drain plug is 5-30 nm.

19. The semiconductor structure of claim 16, wherein, The extension direction of the cross plug is perpendicular to the extension direction of the drain plug.

20. The semiconductor structure of claim 16, wherein, The semiconductor structure includes a gate plug connected with the gate structure through the dielectric layer.

21. The semiconductor structure of claim 16, wherein, The semiconductor structure includes a source in the substrate away from the drain side of the gate structure.

22. The semiconductor structure of claim 16, wherein, The substrate includes adjacent first and second regions, the substrate of the first region includes a substrate and a fin on the substrate, a well region is formed in the fin, the substrate of the second region includes a substrate and a semiconductor layer on the substrate, a drift region is formed in the semiconductor layer; The drain is located in the drift region; The gate structure is located at the junction of the well region and the drift region, and the gate structure has a partial lateral dimension across the fin, and a partial lateral dimension formed on the semiconductor layer, and a partial lateral dimension covering part of the top wall and part of the side wall of the fin.

23. The semiconductor structure of claim 16, wherein, The substrate includes adjacent first and second regions, the substrate of the first region includes a substrate and a fin on the substrate, a well region is formed in the fin of the first region, the substrate of the second region includes a substrate and a fin on the substrate, a drift region is formed in the fin of the second region; The drain is located in the drift region; The gate structure is located at the junction of the well region and the drift region, and the gate structure has a partial lateral dimension across the fin, and a partial lateral dimension formed on the semiconductor layer, and a partial lateral dimension covering part of the top wall and part of the side wall of the fin.

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