Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, the substrate including a first region and a second region, the substrate including a substrate, a gate structure located on the substrate, source and drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer covering the source and drain doped layers, with the extension direction of the gate structure being lateral; forming a sacrificial layer on the interlayer dielectric layer, the sacrificial layer having a first sidewall located at the interface between the first region and the second region; forming a sidewall layer on the first sidewall of the sacrificial layer, the lateral dimension of the sidewall layer being smaller than the lateral dimension of the sacrificial layer. The smaller lateral dimension of the sidewall layer results in a smaller lateral dimension of the blocking structure formed using the sidewall layer as a mask, making it easier to completely expose the source and drain doped layers in the first region and the second region. This results in a larger contact area between the source and drain plugs formed in the groove and the source and drain doped layers, which is beneficial for improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to reduce the impact of short-channel effects, semiconductor processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. Furthermore, FinFETs have better compatibility with existing integrated circuit manufacturing processes compared to other devices. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby optimizing the electrical performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region, the substrate including a substrate, a gate structure located on the substrate, source / drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer covering the source / drain doped layers, wherein the extension direction of the gate structure is perpendicular to the interface between the first region and the second region, and the extension direction of the gate structure is lateral; forming a sacrificial layer on the interlayer dielectric layer, the sacrificial layer having a first sidewall located at the interface between the first region and the second region; forming a sidewall layer on the first sidewall of the sacrificial layer, the lateral dimension of the sidewall layer being smaller than the lateral dimension of the sacrificial layer; removing the sacrificial layer; etching the interlayer dielectric layer using the sidewall layer as a mask to form a blocking structure and grooves located on both sides of the blocking structure, the grooves exposing the source / drain doped layers; and forming source / drain plugs in the grooves.

[0006] Optionally, the sidewall layer may be made of one or more of amorphous silicon, amorphous carbon, amorphous germanium, silicon oxide, and silicon nitride.

[0007] Optionally, in the step of forming the sidewall layer, the lateral dimension of the sidewall layer is 3 nanometers to 10 nanometers.

[0008] Optionally, in the step of forming the sacrificial layer, in the lateral direction, the sidewall in the sacrificial layer corresponding to the first sidewall serves as the second sidewall; the step of forming a sidewall layer on the first sidewall of the sacrificial layer includes: conformally covering the sacrificial layer and the interlayer medium layer exposed by the sacrificial layer with a sidewall material layer; removing the sidewall material layer on the interlayer medium layer, the top of the sacrificial layer, and the second sidewall, and the remaining sidewall material layer located on the first sidewall of the sacrificial layer serves as the sidewall layer.

[0009] Optionally, the step of removing the sidewall material layer on the interlayer dielectric layer, the top of the sacrificial layer, and the second sidewall includes: removing the sidewall material layer on the interlayer dielectric layer, the top of the sacrificial layer, and the second sidewall using an ion beam etching process, with the remaining sidewall material layer on the first sidewall serving as the sidewall layer.

[0010] Optionally, the process parameters of the ion beam etching process include: the etching ions include one or more of He, Ar, Ne, Kr and Xe, the bias voltage is 50V to 1000V, the chamber pressure is 5mTorr to 1000mTorr, and the angle between the incident direction of the etching ions and the normal of the substrate surface is greater than 5° and less than 30°.

[0011] Optionally, the step of removing the sidewall material layer on the interlayer dielectric layer, the top of the sacrificial layer, and the second sidewall includes: ion-doping the sidewall material layer on the interlayer dielectric layer, the top of the sacrificial layer, and the second sidewall to form a pseudo sidewall layer; removing the pseudo sidewall layer, and the remaining sidewall material layer located on the first sidewall serving as the sidewall layer.

[0012] Optionally, the pseudo sidewall layer is formed by ion implantation to ion-dope the interlayer dielectric layer, the top of the sacrificial layer, and the sidewall material layer of the second sidewall.

[0013] Optionally, the process parameters for ion doping of the interlayer dielectric layer, the top of the sacrificial layer, and the sidewall material layer of the second sidewall using ion implantation include: ion implantation energy of 0.5 keV to 5 keV, implanted ions including O, N, or Ge, and the angle between the ion implantation direction and the normal to the substrate surface being greater than 5° and less than 30°.

[0014] Optionally, the pseudo sidewall layer can be removed using a maskless dry etching process.

[0015] Optionally, the sidewall material layer may be formed using atomic layer deposition or chemical vapor deposition.

[0016] Optionally, in the step of forming the sacrificial layer, the thickness of the sacrificial layer is 10 nanometers to 40 nanometers.

[0017] Optionally, the material of the sacrificial layer includes one or more of silicon nitride, aluminum oxide, titanium nitride, titanium oxide, and tantalum oxide.

[0018] Optionally, in the step of providing a substrate, the substrate further includes: a dielectric layer located on the interlayer dielectric layer and the gate structure; in the step of forming a sacrificial layer on the interlayer dielectric layer, the sacrificial layer is formed on the dielectric layer; during the process of etching the interlayer dielectric layer using the sidewall layer as a mask, the dielectric layer is also etched.

[0019] Optionally, in the step of providing the substrate, a fin is formed on the substrate, the gate structure spans the fin and covers a portion of the top wall and a portion of the sidewall of the fin; in the step of providing the substrate, the source / drain doped layer is located in the fin on both sides of the gate structure.

[0020] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate, the substrate including a first region and a second region; a gate structure located on the substrate, the extension direction of the gate structure being perpendicular to the interface between the first region and the second region, with the extension direction of the gate structure being lateral; source / drain doped layers located on both sides of the gate structure; an interlayer dielectric layer located on the substrate, the interlayer dielectric layer covering the source / drain doped layers and exposing the top of the gate structure; a sacrificial layer located on the interlayer dielectric layer, the sacrificial layer having a first sidewall located at the interface between the first region and the second region; and a sidewall layer located on the first sidewall of the sacrificial layer, wherein, in the extension direction of the gate structure, the lateral dimension of the sidewall layer is smaller than the lateral dimension of the sacrificial layer.

[0021] Optionally, the lateral dimension of the sidewall layer is 3 nanometers to 10 nanometers.

[0022] Optionally, the height of the sidewall layer is 10 nanometers to 40 nanometers.

[0023] Optionally, the sidewall layer may be made of one or more of amorphous silicon, amorphous carbon, amorphous germanium, silicon oxide, and silicon nitride.

[0024] Optionally, the material of the sacrificial layer includes one or more of aluminum oxide, titanium nitride, titanium oxide, and tantalum oxide.

[0025] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0026] In the semiconductor structure formation method provided by the embodiments of the present invention, a sacrificial layer is formed on the interlayer dielectric layer. The sacrificial layer has a first sidewall located at the interface between the first region and the second region. A sidewall layer is formed on the first sidewall of the sacrificial layer. The lateral dimension of the sidewall layer is smaller than that of the sacrificial layer. After removing the sacrificial layer, the interlayer dielectric layer is etched using the sidewall layer as a mask to form the blocking structure. Because the lateral dimension of the sidewall layer is small, the lateral dimension of the blocking structure formed using the sidewall layer as a mask is also small. The blocking structure can easily completely expose the source and drain doped layers in the first and second regions, resulting in a larger contact area between the source and drain plugs formed in the groove and the source and drain doped layers, which is beneficial to improving the electrical performance of the semiconductor structure. Attached Figure Description

[0027] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0028] Figures 5 to 14This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0029] As the background technology shows, the devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0030] refer to Figures 1 to 4 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0031] like Figure 1 and Figure 2 As shown, Figure 1 Only the source / drain doped layer 5, gate structure 4, and mask layer 7 are shown. Figure 2 for Figure 1 In the schematic diagram of cross section aa, a substrate is provided, the substrate including a first region I and a second region II, the substrate including a substrate 1, a plurality of fins 2 discrete on the substrate 1, a gate structure 4 spanning the fins 2, and source / drain doped layers 5 located on both sides of the gate structure 4 in the fins 2, the gate structure 4 covering part of the top wall and part of the side wall of the fins 2; a dielectric layer 6 is formed covering the substrate; a mask layer 7 is formed on the dielectric layer 6 at the junction of the first region and the second region.

[0032] like Figure 3 As shown, the dielectric layer 6 is etched using the mask layer 7 as a mask to form a blocking structure 8 and a groove 9 located between the blocking structure 8, and the groove 9 exposes the source / drain doped layer 5.

[0033] like Figure 4 As shown, a source / drain plug 10 connected to the source / drain doped layer 5 is formed in the groove 9.

[0034] The blocking structure 8 is used to isolate the source / drain plugs 10 of the first region I and the second region II. In advanced nanotechnology, the source / drain doped layers 5 in the first region I and the second region II are getting closer and closer. If the size of the blocking structure 8 is large, the blocking structure 8 is likely to cover part of the source / drain doped layer 5. That is to say, the groove 9 is not easy to completely expose the source / drain doped layer 5 at the junction of the first region I and the second region II. Correspondingly, the contact area between the source / drain plug 10 formed in the groove 9 and the source / drain doped layer 5 at the junction of the first region I and the second region II is small, and the contact resistance between the source / drain plug 10 and the source / drain doped layer 5 is large, resulting in poor electrical performance of the semiconductor structure.

[0035] To address the technical problem, embodiments of the present invention provide a substrate comprising a first region and a second region. The substrate includes a substrate, a gate structure on the substrate, source / drain doped layers on both sides of the gate structure, and an interlayer dielectric layer covering the source / drain doped layers. The extension direction of the gate structure is perpendicular to the interface between the first and second regions, with the extension direction of the gate structure being lateral. A sacrificial layer is formed on the interlayer dielectric layer, the sacrificial layer having a first sidewall located at the interface between the first and second regions. A sidewall layer is formed on the first sidewall of the sacrificial layer, the lateral dimension of the sidewall layer being smaller than the lateral dimension of the sacrificial layer. The sacrificial layer is removed. The interlayer dielectric layer is etched using the sidewall layer as a mask to form a blocking structure and grooves on both sides of the blocking structure, the grooves exposing the source / drain doped layers. Source / drain plugs are formed in the grooves.

[0036] In the semiconductor structure formation method provided by the embodiments of the present invention, a sacrificial layer is formed on the interlayer dielectric layer. The sacrificial layer has a first sidewall located at the interface between the first region and the second region. A sidewall layer is formed on the first sidewall of the sacrificial layer. The lateral dimension of the sidewall layer is smaller than that of the sacrificial layer. After removing the sacrificial layer, the interlayer dielectric layer is etched using the sidewall layer as a mask to form the blocking structure. Because the lateral dimension of the sidewall layer is small, the lateral dimension of the blocking structure formed using the sidewall layer as a mask is also small. The blocking structure can easily completely expose the source and drain doped layers in the first and second regions, resulting in a larger contact area between the source and drain plugs formed in the groove and the source and drain doped layers, which is beneficial to improving the electrical performance of the semiconductor structure.

[0037] To make the above-mentioned objectives, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 5 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0039] refer to Figure 5 and Figure 6 , Figure 6 for Figure 5 Cross-sectional view at point AA Figure 5The diagram illustrates a gate structure 101 and source / drain doped layers 102. A substrate is provided, comprising a first region I and a second region II. The substrate includes a substrate 100, a gate structure 101 located on the substrate 100, source / drain doped layers 102 located on both sides of the gate structure 101, and an interlayer dielectric layer 103 covering the source / drain doped layers 102. The extension direction of the gate structure 101 is perpendicular to the interface between the first region I and the second region II, and is lateral to the extension direction of the gate structure 101.

[0040] The substrate includes a first region I and a second region II. In this embodiment, the first region I and the second region II are used to form different types of transistors. In this embodiment, the first region I is used to form an NMOS (Negative Channel Metal Oxide Semiconductor), and the second region II is used to form a PMOS (Positive Channel Metal Oxide Semiconductor). In other embodiments, the first region I and the second region II can also be used to form the same type of transistor, for example, both can form NMOS or both can form PMOS.

[0041] The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.

[0042] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium nitride. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. An interface layer may also be formed on the surface of the substrate 100, and the interface layer may be made of silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0043] When the semiconductor structure is in operation, the gate structure 101 is used to control the opening and closing of the channel.

[0044] In this embodiment, the gate structure 101 is made of magnesium-tungsten alloy. In other embodiments, the gate structure may also be made of W, Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0045] When the semiconductor structure is in operation, the source and drain doped layers 102 provide stress to the channel, thereby increasing the carrier migration rate.

[0046] In this embodiment, the transistor in the first region I is an NMOS, and the source and drain doped layers 102 are used as the source and drain of the NMOS. When the semiconductor structure is working, the source and drain doped layers 102 apply tensile stress to the channel below the gate structure 101, and stretching the channel can improve the electron migration rate.

[0047] The transistor in the second region II is a PMOS, and the source and drain doping layers 102 are used as the source and drain of the PMOS. When the semiconductor structure is working, the source and drain doping layers 102 apply compressive stress to the channel below the gate structure 101, and compressing the channel can improve the hole mobility.

[0048] The semiconductor structure further includes an interlayer dielectric layer 103 located on the side of the gate structure 101, wherein the top surface of the interlayer dielectric layer 103 is lower than or flush with the top surface of the gate structure 101.

[0049] Interlayer dielectric layer 103 is used for electrical isolation of adjacent devices.

[0050] In this embodiment, the material of the interlayer dielectric layer 103 is an insulating material. Specifically, the material of the interlayer dielectric layer 103 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 103.

[0051] It should be noted that, in the step of providing the substrate, fins 104 are formed on the substrate 100.

[0052] In this embodiment, the material of the fin 104 is the same as the material of the substrate 100, which is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0053] The gate structure 101 spans the fin 104 and covers part of the top wall and part of the side wall of the fin 104.

[0054] Correspondingly, the source and drain doped layers 102 are located in the fins 104 on both sides of the gate structure 101.

[0055] It should be noted that the semiconductor structure further includes a dielectric layer 105, located on the gate structure 101 and the interlayer dielectric layer 103.

[0056] The dielectric layer 105 and the interlayer dielectric layer 103 are electrically isolated together to form the source and drain plugs.

[0057] In this embodiment, the dielectric layer 105 is made of an insulating material. Specifically, the dielectric layer 105 is made of silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the dielectric layer 105.

[0058] refer to Figure 7 and Figure 8A sacrificial layer 106 is formed on the interlayer dielectric layer 103. The sacrificial layer 106 has a first sidewall 107 located at the interface between the first region I and the second region II.

[0059] The sacrificial layer 106 provides a process basis for the subsequent formation of the sidewall layer. The sacrificial layer 106 has a first sidewall 107, which is located at the interface between the first region I and the second region II. The sidewall layer formed on the first sidewall 107 is located at the interface between the first region I and the second region II.

[0060] Specifically, the material of the sacrificial layer 106 includes one or more of silicon nitride, aluminum oxide, titanium nitride, titanium oxide, and tantalum oxide. In this embodiment, the material of the sacrificial layer 106 includes silicon nitride.

[0061] Specifically, in the step of forming a sacrificial layer 106 on the interlayer dielectric layer 103, the sacrificial layer 106 is formed on the dielectric layer 105.

[0062] The step of forming a sacrificial layer 106 on the interlayer dielectric layer 103 includes: forming a sacrificial material layer (not shown in the figure) on the dielectric layer 105; forming a mask layer (not shown in the figure) on the sacrificial material layer, wherein one sidewall of the mask layer is located at the interface between the first region I and the second region II; etching the sacrificial material layer using the mask layer as a mask, and the remaining sacrificial material layer serves as the sacrificial layer 106.

[0063] In this embodiment, the sacrificial material layer is formed using atomic layer deposition (ALD). ALD is a deposition process in which a vapor precursor is alternately pulsed into a reaction chamber, causing chemical adsorption and surface reaction on the substrate. Through ALD, the sacrificial material layer is formed on the surface of the dielectric layer 105 in the form of atomic layers, which improves the uniformity of the deposition rate, the thickness uniformity of the sacrificial material layer, and the structural uniformity of the sacrificial material layer. Furthermore, the process temperature of ALD is typically low, which also helps to reduce the thermal budget and lower the probability of semiconductor structural performance deviations.

[0064] In this embodiment, the sacrificial material layer is etched using the mask layer as a mask, and the remaining sacrificial material layer serves as the sacrificial layer 106. Dry etching has anisotropic etching characteristics, providing good control over the etching profile, which helps ensure the morphology of the sacrificial layer 106 meets process requirements and also improves the removal efficiency of the sacrificial material layer.

[0065] It should be noted that the sacrificial layer 106 should not be too thin or too thick. If the sacrificial layer 106 is too thick, forming it will require excessive processing time, resulting in low formation efficiency. Furthermore, if the sacrificial layer 106 is too thick, the sidewall layer subsequently formed on its sidewalls will also be too thick. To minimize the lateral dimension of the blocking structure formed using the sidewall layer as a mask, the lateral dimension of the sidewall layer will also be small. If the sidewall layer is too thick and has a small lateral dimension, it will result in an excessively large aspect ratio. During the semiconductor structure formation process, this can easily lead to bending or even collapse of the sidewall layer, resulting in poor formation quality of the blocking structure. If the sacrificial layer 106 is too thin, it can lead to a smaller thickness of the subsequently formed sidewall layer. In the subsequent etching of the interlayer dielectric layer 103 using the sidewall layer as a mask to form a blocking structure and grooves on both sides of the blocking structure, the sidewall layer is easily consumed too quickly during the etching process. This prevents the sidewall layer from effectively functioning as an etching mask, resulting in an insufficient height of the blocking structure. In other words, the grooves on both sides of the blocking structure are too shallow. Subsequently, source / drain plugs are formed in these grooves, contacting the source / drain doped layers. The contact resistance between these plugs and the source / drain doped layers 102 is high, leading to poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the sacrificial layer 106 is 10 nanometers to 40 nanometers.

[0066] It should be noted that, in the step of forming the sacrificial layer 106, in the lateral direction, the sidewall of the sacrificial layer 106 corresponding to the first sidewall 107 serves as the second sidewall.

[0067] refer to Figures 9 to 11 A sidewall layer 108 is formed on the first sidewall 107 of the sacrificial layer 106 (e.g., Figure 11 As shown), the lateral dimension of the sidewall layer 108 is smaller than the lateral dimension of the sacrificial layer 106.

[0068] A sacrificial layer 106 is formed on the interlayer dielectric layer 103. The sacrificial layer 106 has a first sidewall 107 located at the interface between the first region I and the second region II. A sidewall layer 108 is formed on the first sidewall 107 of the sacrificial layer 106. The lateral dimension of the sidewall layer 108 is smaller than that of the sacrificial layer 106. After removing the sacrificial layer 106, the interlayer dielectric layer 103 is etched using the sidewall layer 108 as a mask to form the blocking structure. Because the lateral dimension of the sidewall layer 108 is small, the lateral dimension of the blocking structure formed using the sidewall layer 108 as a mask is also small. The blocking structure can easily expose the source / drain doped layers 102 in the first region I and the second region II, resulting in a larger contact area between the source / drain plugs formed in the groove and the source / drain doped layers 102, which is beneficial to improving the electrical performance of the semiconductor structure.

[0069] In this embodiment, the lateral dimension of the sidewall layer 108 is smaller than that of the sacrificial layer 106. Subsequently, the sacrificial layer 106 is removed, and the interlayer dielectric layer 103 is etched using the sidewall layer 108 as a mask. This results in a smaller lateral dimension of the formed blocking structure, making it easier to expose the source / drain doped layers 102 in the first region I and the second region II in the grooves formed on both sides of the blocking structure. Source / drain plugs are then formed in these grooves, resulting in a lower contact resistance between the source / drain plugs and the source / drain doped layers 102, which is beneficial for improving the electrical performance of the semiconductor structure.

[0070] Specifically, the material of the sidewall layer 108 includes one or more of amorphous silicon, amorphous carbon, amorphous germanium, silicon oxide, and silicon nitride. In this embodiment, the material of the sidewall layer 108 includes amorphous silicon.

[0071] It should be noted that during the step of forming the sidewall layer 108, the lateral dimension of the sidewall layer 108 should not be too large or too small. If the lateral dimension of the sidewall layer 108 is too large, during the subsequent etching of the interlayer dielectric layer 103 and dielectric layer 105 using the sidewall layer 108 as a mask, the formed blocking structure is likely to cover part of the source / drain doped layer 102 at the junction of the first region I and the second region II. Consequently, the contact area between the source / drain plug subsequently formed in the groove and the source / drain doped layer 102 at the junction of the first region I and the second region II is small, and the contact resistance between the source / drain plug and the source / drain doped layer 102 at the junction of the first region I and the second region II is large, resulting in poor electrical performance of the semiconductor structure. If the lateral dimension of the sidewall layer 108 is too small, the lateral dimension of the formed blocking structure will be small during the subsequent etching of the interlayer dielectric layer 103 using the sidewall layer 108 as a mask. This results in source / drain plugs being formed in the grooves on both sides of the blocking structure, which are prone to bridging. Consequently, the blocking structure cannot effectively electrically isolate the source / drain plugs located on both sides, leading to poor electrical properties in the semiconductor structure. In this embodiment, the lateral dimension of the sidewall layer is 3 nanometers to 10 nanometers.

[0072] In this embodiment, the step of forming a sidewall layer 108 on one sidewall of the sacrificial layer 106 includes: as follows Figure 9 As shown, a conformal cover layer 109 of sidewall material 109 is applied to the sacrificial layer 106 and the interlayer medium layer 103 exposed on the sacrificial layer 106.

[0073] The sidewall material layer 109 is prepared for the subsequent formation of the sidewall layer.

[0074] In this embodiment, the sidewall material layer 109 is formed using atomic layer deposition (ALD). ALD involves multiple ALD cycles, which improves the thickness uniformity of the sidewall material layer 109, enabling it to conformally cover the top and sidewalls of the sacrificial layer 106 and the surface of the dielectric layer 105. Furthermore, ALD offers good gap-filling performance and step coverage, thereby enhancing the conformal coverage capability of the sidewall material layer 109. In other embodiments, the sidewall material layer can also be formed using chemical vapor deposition (CVD).

[0075] Specifically, in this embodiment, the dielectric layer 105 is formed on the gate structure 101 and the interlayer dielectric layer 103, and correspondingly, the sidewall material layer 109 conformally covers the sacrificial layer 106 and the dielectric layer 105 exposed by the sacrificial layer 106.

[0076] like Figure 10 and Figure 11 As shown, the sidewall material layer 109 on the interlayer medium layer 103, the top of the sacrificial layer 106, and the second sidewall is removed, and the remaining sidewall material layer 109 on the first sidewall 107 of the sacrificial layer 106 is used as the sidewall layer 108.

[0077] In this embodiment, the step of removing the sidewall material layer 109 on the interlayer dielectric layer 103, the top of the sacrificial layer 106, and the second sidewall includes: ion doping the sidewall material layer 109 on the interlayer dielectric layer 103, the top of the sacrificial layer 106, and the second sidewall to form a pseudo sidewall layer 110; removing the pseudo sidewall layer 110, and the remaining sidewall material layer 109 located on the first sidewall 107 serves as the sidewall layer 108.

[0078] In this embodiment, ion implantation is used to dope the sidewall material layer 109 on the interlayer dielectric layer 103, the top of the sacrificial layer 106, and the second sidewall to form the sidewall layer 108. Ion implantation has the advantages of simple operation and low process cost.

[0079] Specifically, the implanted ions include O, N, or Ge. In this embodiment, the implanted ions include O, and the sidewall material layer 108 is made of amorphous silicon, with O forming silicon oxide with the amorphous silicon. In other embodiments, the implanted ions include N, and the sidewall material layer is made of amorphous silicon, with N forming silicon nitride with the amorphous silicon; or, the implanted ions include Ge, and the sidewall material layer is made of amorphous silicon, with Ge forming silicon germanide with the amorphous silicon.

[0080] It should be noted that during the ion doping process on the interlayer dielectric layer 103, the top of the sacrificial layer 106, and the sidewall material layer 109 on the second sidewall, the ion doping of the sidewall material layer is performed from one side of the second sidewall. Due to the shading effect, the doped ions are less likely to be incorporated into the sidewall material layer 109 on the first sidewall 107. This improves the etching selectivity ratio between the pseudo sidewall layer 110 and the sidewall material layer 109 on the first sidewall 107 during the subsequent removal of the pseudo sidewall layer 110, thereby improving the formation quality of the sidewall layer 108.

[0081] It should be noted that the angle between the ion implantation direction and the surface normal of the substrate 100 should not be too large or too small. If the angle is too large, the ion concentration in the pseudo sidewall layer 110 on the top of the sacrificial layer 106 and the surface of the dielectric layer 105 will be low. During the subsequent removal of the pseudo sidewall layer 110 using a maskless etching process, the etching selectivity between the pseudo sidewall layer 110 and the sidewall material layer 109 on the first sidewall 107 will be relatively small. During the removal of the pseudo sidewall layer 110, the sidewall material layer 109 on the first sidewall 107 will be significantly damaged. Consequently, the formation quality of the blocking structure and the grooves on both sides of the blocking structure formed using the sidewall layer as a mask will be poor. When the semiconductor structure is working, the blocking structure cannot effectively electrically isolate the source and drain plugs formed in the grooves, resulting in poor electrical performance of the semiconductor structure. If the included angle is too small, the ion concentration of the pseudo sidewall layer 110 on the second sidewall is relatively small. Consequently, during the subsequent removal of the pseudo sidewall layer 110, the etching selectivity between the pseudo sidewall layer 110 on the second sidewall and the sidewall material layer 109 on the first sidewall 107 is relatively small. After completely removing the pseudo sidewall layer 110 on the second sidewall, the damage to the sidewall material layer 109 on the first sidewall 107 is relatively small, meaning that the damage to the sidewall layer is relatively large. In this embodiment, during the ion implantation step, the angle between the ion implantation direction and the normal to the surface of the substrate 100 is greater than 5° and less than 30°.

[0082] It should be noted that the ion implantation energy should not be too high or too low. If the ion implantation energy is too high, the ions can easily penetrate the sidewall material layer 109 and enter the sacrificial layer 106 or dielectric layer 105. The ion dose in the pseudo sidewall layer 110 will be low, resulting in poor formation quality of the pseudo sidewall layer 110. During the subsequent removal of the pseudo sidewall layer 110 using a maskless etching process, the etching selectivity between the pseudo sidewall layer 110 and the sidewall material layer 109 on the first sidewall 107 is relatively small. After the pseudo sidewall layer 110 is completely removed, the damage to the sidewall material layer 109 on the first sidewall 107 is small. In other words, the damage to the sidewall layer is large. Consequently, the formation quality of the blocking structure and the grooves on both sides of the blocking structure formed using the sidewall layer as a mask is poor. When the semiconductor structure is working, the blocking structure cannot effectively electrically isolate the source and drain plugs formed in the grooves, resulting in poor electrical performance of the semiconductor structure. If the ion implantation energy is too low, the implanted ions are easily doped onto the surface of the sidewall material layer 109. During the subsequent maskless etching process to remove the pseudo-sidewall layer 110, the etching selectivity between the pseudo-sidewall layer 110 and the sidewall material layer 109 on the first sidewall 107 is relatively small, easily leading to significant damage to the sidewall layer. Consequently, the formation quality of the blocking structure and the grooves on both sides of the blocking structure formed using the sidewall layer as a mask is poor. When the semiconductor structure is working, the blocking structure cannot effectively electrically isolate the source / drain plugs formed in the grooves, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the ion implantation energy is 0.5 keV to 5 keV.

[0083] It should be noted that during the ion doping process on the interlayer dielectric layer 103, the top of the sacrificial layer 106, and the sidewall material layer 109 on the second sidewall, due to the influence of the shielding effect, the sidewall material layer 109 on the surface of the dielectric layer 105 near the first sidewall 107 is not easily doped with ions.

[0084] In this embodiment, a maskless dry etching process is used to remove the dummy sidewall layer 110. The maskless dry etching process has anisotropic etching characteristics, completely removing the dummy sidewall 110 on the top of the sacrificial layer 106 and the surface of the dielectric layer 105 while minimizing damage to the sidewall material layer 109 on the first sidewall 107. Furthermore, it can also remove the sidewall material layer 109 on the surface of the dielectric layer 105, resulting in a better formation quality of the sidewall layer 108. In addition, the maskless dry etching process eliminates the need for a photomask, reducing the process cost of forming the sidewall layer 108.

[0085] In this embodiment, during the removal of the pseudo sidewall layer 110 using a maskless dry etching process, the etching gas used includes hydrogen fluoride gas. In other embodiments, when the implanted ion is N, the etching gas used includes CHF3 and CH2F2; when the implanted ion is Ge, the etching gas used includes hydrogen chloride.

[0086] It should be noted that during the process of removing the pseudo sidewall layer 110 using a maskless dry etching process, the undoped sidewall material layer 109 on the surface of the dielectric layer 105 near the first sidewall 107 is also removed.

[0087] In other embodiments, ion beam etching (IBE) can be used to remove the sidewall material layers on the interlayer dielectric layer, the top of the sacrificial layer, and the second sidewall, leaving the remaining sidewall material layer on the first sidewall as the sidewall layer. IBE is an anisotropic physical etching process that provides energetic etching ions, which are inert ions. Inert ion bombardment can physically remove the sidewall material layers on the interlayer dielectric layer and the second sidewall, and due to the shielding effect, it is unlikely to damage the sidewall material layer on the first sidewall.

[0088] Specifically, in the step of etching the sidewall material layer using an anisotropic plasma etching process to form the sidewall layer, the angle between the incident direction of the etching ions and the normal of the substrate surface is greater than 5° and less than 30°, the etching ions include one or more of He, Ar, Ne, Kr and Xe, the bias voltage is 50V to 1000V, and the chamber pressure is 5mTorr to 1000mTorr.

[0089] refer to Figure 12 Remove the sacrificial layer 106.

[0090] The sacrificial layer 106 is removed in preparation for subsequent etching of the interlayer dielectric layer 105 using the sidewall layer 108 as a mask.

[0091] In this embodiment, the sacrificial layer 106 is removed using a wet etching process. Wet etching is an isotropic etching process, which has a high etching rate, is simple to operate, and has low processing costs.

[0092] In this embodiment, the sacrificial layer 106 is made of silicon nitride, and the wet etching solution includes a phosphoric acid solution.

[0093] refer to Figure 13Using the sidewall layer 108 as a mask, the interlayer dielectric layer 105 is etched to form a blocking structure 112 and grooves 111 located on both sides of the blocking structure 112, with the grooves 111 exposing the source / drain doped layer 102.

[0094] The groove 111 provides process space for the subsequent formation of source and drain plugs, and the blocking structure 112 is used to electrically isolate the source and drain plugs of the first region I and the second region II.

[0095] In this embodiment, the interlayer dielectric layer 103 is etched using an anisotropic dry etching process with the sidewall layer as a mask to form the blocking structure 112 and the grooves 111 located on both sides of the blocking structure 112. The dry etching process has anisotropic etching characteristics and good control over the etching profile, which helps to ensure that the morphology of the grooves 111 meets the process requirements. Furthermore, during the etching of the interlayer dielectric layer 103 using the dry etching process, the top of the source / drain doped layer 102 can be used as the etching stop position, simplifying the process steps.

[0096] It should be noted that during the process of etching the interlayer dielectric layer 103 using the sidewall layer 108 as a mask, the dielectric layer 105 is also etched.

[0097] Accordingly, the blocking structure 112 includes a first blocking layer 1122 formed by etching the dielectric layer 105 and a second blocking layer 1121 formed by etching the interlayer dielectric layer 103.

[0098] The method for forming the semiconductor structure further includes: after forming the blocking structure 112, removing the sidewall layer 108.

[0099] In this embodiment, a wet etching process is used to remove the sidewall layer 108. The wet etching process has the advantages of high etching rate, simple operation, and low cost.

[0100] In this embodiment, the sidewall layer 108 is made of amorphous silicon, and the wet etching solution includes tetramethylammonium hydroxide solution (TMAH).

[0101] refer to Figure 14 A source / drain plug 113 is formed in the groove 111.

[0102] The source / drain plug 113 is used to connect the source / drain doped layers 102 in the same region.

[0103] The source / drain plug 113 is made of a conductive material. Specifically, the conductive material includes one or more of W, Co, Cu, and Al. In this embodiment, the source / drain plug 113 is made of W. W has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure.

[0104] Accordingly, embodiments of the present invention also provide a semiconductor structure. (See reference...) Figure 11 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0105] The semiconductor structure includes: a substrate 100, which includes a first region I and a second region II; a gate structure (not shown) located on the substrate 100, the extension direction of the gate structure being perpendicular to the interface between the first region I and the second region II, with the extension direction of the gate structure being lateral; source / drain doped layers 102 located on both sides of the gate structure; an interlayer dielectric layer 103 located on the substrate 100, the interlayer dielectric layer 103 covering the source / drain doped layers 102 and exposing the top of the gate structure; a sacrificial layer 106 located on the interlayer dielectric layer 103, the sacrificial layer 106 having a first sidewall 107 located at the interface between the first region I and the second region II; and a sidewall layer 108 located on the first sidewall 107 of the sacrificial layer 106, wherein the lateral dimension of the sidewall layer 108 is smaller than the lateral dimension of the sacrificial layer 106 in the extension direction of the gate structure.

[0106] In the semiconductor structure provided in this embodiment of the invention, a sacrificial layer 106 is located on the interlayer dielectric layer 103. The sacrificial layer 106 has a first sidewall 107 located at the interface between the first region I and the second region II. A sidewall layer 108 is formed on the first sidewall 107 of the sacrificial layer 106. The lateral dimension of the sidewall layer 108 is smaller than that of the sacrificial layer 106. After the sacrificial layer 106 is removed, the interlayer dielectric layer 103 is etched using the sidewall layer 108 as a mask to form the blocking structure. Because the lateral dimension of the sidewall layer 108 is small, the lateral dimension of the blocking structure formed using the sidewall layer 108 as a mask is also small. The blocking structure can easily expose the source / drain doped layers 102 in the first region I and the second region II, resulting in a larger contact area between the source / drain plugs formed in the groove and the source / drain doped layers 102, which is beneficial to improving the electrical performance of the semiconductor structure.

[0107] The substrate includes a first region I and a second region II. In this embodiment, the first region I and the second region II are used to form different types of transistors. In this embodiment, the first region I is used to form an NMOS (Negative Channel Metal Oxide Semiconductor), and the second region II is used to form a PMOS (Positive Channel Metal Oxide Semiconductor). In other embodiments, the first region I and the second region II can also be used to form the same type of transistor, for example, both can form NMOS or both can form PMOS.

[0108] The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.

[0109] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium nitride. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. An interface layer may also be formed on the surface of the substrate 100, and the interface layer may be made of silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0110] When the semiconductor structure is in operation, the gate structure 101 is used to control the opening and closing of the channel.

[0111] In this embodiment, the gate structure 101 is made of magnesium-tungsten alloy. In other embodiments, the gate structure may also be made of W, Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0112] When the semiconductor structure is in operation, the source and drain doped layers 102 provide stress to the channel, thereby increasing the carrier migration rate.

[0113] In this embodiment, the transistor in the first region I is an NMOS, and the source and drain doped layers 102 are used as the source and drain of the NMOS. When the semiconductor structure is working, the source and drain doped layers 102 apply tensile stress to the channel below the gate structure 101, and stretching the channel can improve the electron migration rate.

[0114] The transistor in the second region II is a PMOS, and the source and drain doping layers 102 are used as the source and drain of the PMOS. When the semiconductor structure is working, the source and drain doping layers 102 apply compressive stress to the channel below the gate structure 101, and compressing the channel can improve the hole mobility.

[0115] The semiconductor structure further includes an interlayer dielectric layer 103 located on the side of the gate structure 101, wherein the top surface of the interlayer dielectric layer 103 is lower than or flush with the top surface of the gate structure 101.

[0116] Interlayer dielectric layer 103 is used for electrical isolation of adjacent devices.

[0117] In this embodiment, the material of the interlayer dielectric layer 103 is an insulating material. Specifically, the material of the interlayer dielectric layer 103 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 103.

[0118] It should be noted that, in the step of providing the substrate, a fin 104 is formed on the substrate 100, and the gate structure 101 spans the fin 104 and covers part of the top wall and part of the side wall of the fin 104.

[0119] In this embodiment, the material of the fin 104 is the same as the material of the substrate 100, which is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0120] The gate structure 101 spans the fin 104 and covers part of the top wall and part of the side wall of the fin 104.

[0121] Correspondingly, the source and drain doped layers 102 are located in the fins 104 on both sides of the gate structure 101.

[0122] It should be noted that the semiconductor structure further includes a dielectric layer 105, located on the gate structure 101 and the interlayer dielectric layer 103.

[0123] The dielectric layer 105 and the interlayer dielectric layer 103 are electrically isolated together to form the source and drain plugs.

[0124] In this embodiment, the dielectric layer 105 is made of an insulating material. Specifically, the dielectric layer 105 is made of silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the dielectric layer 105.

[0125] A sacrificial layer 106 is located on the interlayer dielectric layer 105. The sacrificial layer 106 has a first sidewall 107 located at the interface between the first region I and the second region II.

[0126] During the formation of the semiconductor structure, the sidewall layer 108 is formed after the sacrificial layer 106, which provides the process basis for the formation of the sidewall layer 108.

[0127] Specifically, the material of the sacrificial layer 106 includes one or more of silicon nitride, aluminum oxide, titanium nitride, titanium oxide, and tantalum oxide. In this embodiment, the material of the sacrificial layer 106 includes silicon nitride.

[0128] In the subsequent process, the sacrificial layer 106 is removed, and the interlayer dielectric layer 103 and dielectric layer 105 are etched using the sidewall layer 108 as a mask to form a blocking structure and the grooves located on both sides of the blocking structure.

[0129] Specifically, the material of the sidewall layer 108 includes one or more of amorphous silicon, amorphous carbon, amorphous germanium, silicon oxide, and silicon nitride. In this embodiment, the material of the sidewall layer 108 includes amorphous silicon.

[0130] It should be noted that the sidewall layer 108 should not be too high or too low. If the sidewall layer 108 is too high, forming the sidewall layer 108 will require excessive processing time. In order to make the lateral dimension of the blocking structure formed using the sidewall layer 108 as a mask smaller, the lateral dimension of the sidewall layer 108 should also be smaller. If the sidewall layer 108 is too thick and has a small lateral dimension, it will result in an excessively large aspect ratio. After the sacrificial layer 106 is removed, the sidewall layer 108 will be prone to bending or even collapse, resulting in poor formation quality of the blocking structure. If the sidewall layer 108 is too short, in the subsequent step of etching the interlayer dielectric layer 103 and dielectric layer 105 using the sidewall layer 108 as a mask, the sidewall layer 108 will be consumed too quickly, and it will not be able to effectively serve as an etching mask. This results in an insufficient height of the blocking structure, meaning the grooves on both sides of the blocking structure are too shallow. Subsequently, source / drain plugs that contact the source / drain doped layers are formed in these grooves. The contact resistance between the source / drain plugs and the source / drain doped layers 102 is relatively high, leading to poor electrical performance of the corresponding semiconductor structure. In this embodiment, the thickness of the sidewall layer 108 is 10 nanometers to 40 nanometers.

[0131] It should be noted that the lateral dimension of the sidewall layer 108 should not be too large or too small. If the lateral dimension of the sidewall layer 108 is too large, during the subsequent etching of the interlayer dielectric layer 103 and dielectric layer 105 using the sidewall layer 108 as a mask, the formed blocking structure will easily cover part of the source / drain doped layer 102 at the junction of the first region I and the second region II. Consequently, the contact area between the source / drain plug subsequently formed in the groove and the source / drain doped layer 102 at the junction of the first region I and the second region II will be small, and the contact resistance between the source / drain plug and the source / drain doped layer 102 at the junction of the first region I and the second region II will be large, resulting in poor electrical performance of the semiconductor structure. If the lateral dimension of the sidewall layer 108 is too small, the lateral dimension of the formed blocking structure will be small during the subsequent etching of the interlayer dielectric layer 103 using the sidewall layer 108 as a mask. This results in source / drain plugs being formed in the grooves on both sides of the blocking structure, which are prone to bridging. Consequently, the blocking structure cannot effectively electrically isolate the source / drain plugs located on both sides, leading to poor electrical properties in the semiconductor structure. In this embodiment, the lateral dimension of the sidewall layer is 3 nanometers to 10 nanometers.

[0132] It should be noted that, in the step of forming the sacrificial layer 106, in the lateral direction, the sidewall of the sacrificial layer 106 corresponding to the first sidewall 107 serves as the second sidewall.

[0133] The semiconductor structure can be formed using the formation method of the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0134] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate, the substrate comprising a first region and a second region, the substrate comprising a substrate, a gate structure on the substrate, source-drain doped layers on both sides of the gate structure, and an interlayer dielectric layer covering the source-drain doped layers, the extension direction of the gate structure being perpendicular to the interface between the first region and the second region, the extension direction being the lateral direction; forming a sacrificial layer on the interlayer dielectric layer, the sacrificial layer having a first sidewall, the first sidewall being located at the interface between the first region and the second region; forming a sidewall layer on the first sidewall of the sacrificial layer, the lateral dimension of the sidewall layer being smaller than the lateral dimension of the sacrificial layer; removing the sacrificial layer; etching the interlayer dielectric layer with the sidewall layer as a mask to form a blocking structure and a groove on both sides of the blocking structure, the blocking structure completely exposing the source-drain doped layers in the first region and the second region, and the groove exposing the source-drain doped layers; forming a source-drain plug in the groove.

2. The method of forming a semiconductor structure of claim 1, wherein, The material of the sidewall layer comprises one or more of amorphous silicon, amorphous carbon, amorphous germanium, silicon oxide, and silicon nitride.

3. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming the sidewall layer, the lateral dimension of the sidewall layer is 3-10 nm.

4. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming the sacrificial layer, in the lateral direction, the sidewall of the sacrificial layer corresponding to the first sidewall is a second sidewall. The step of forming a sidewall layer on the first sidewall of the sacrificial layer comprises conformally covering a sidewall material layer on the sacrificial layer and the interlayer dielectric layer exposed by the sacrificial layer. The step of removing the sidewall material layer on the interlayer dielectric layer, the top of the sacrificial layer, and the second sidewall comprises:

5. The method of forming a semiconductor structure of claim 4, wherein, The step of removing the sidewall material layer on the interlayer dielectric layer, the top of the sacrificial layer, and the second sidewall comprises: The process parameters of the ion beam etching process include: the etching ions include one or more of He, Ar, Ne, Kr, and Xe, the bias voltage is 50-1000 V, the chamber pressure is 5-1000 mTorr, and the angle between the incident direction of the etching ions and the surface normal of the substrate is greater than 5° and less than 30°.

6. The method of forming a semiconductor structure of claim 5, wherein, The step of removing the sidewall material layer on the interlayer dielectric layer, the top of the sacrificial layer, and the second sidewall comprises:

7. The method of forming a semiconductor structure of claim 4, wherein, The step of removing the sidewall material layer on the interlayer dielectric layer, the top of the sacrificial layer, and the second sidewall comprises: The ion implantation process is used to ion dope the sidewall material layer on the interlayer dielectric layer, the top of the sacrificial layer, and the second sidewall to form the pseudo-sidewall layer. ​ 8. The method of forming a semiconductor structure of claim 7, wherein, ​ 9. The method of forming a semiconductor structure of claim 8, wherein, The process parameters of ion implantation process for ion doping the sidewall material layer on the interlayer dielectric layer, the top of the sacrificial layer and the second sidewall include: ion implantation energy is 0.5 KeV to 5 KeV, the implantation ions include O, N or Ge, the angle between the direction of ion implantation and the normal of the substrate surface is greater than 5° and less than 30°.

10. The method of forming a semiconductor structure of claim 7, wherein, The pseudo-sidewall layer is removed by using a maskless dry etching process.

11. The method of forming a semiconductor structure of claim 4, wherein, The sidewall material layer is formed by using an atomic layer deposition process or a chemical vapor deposition process.

12. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming the sacrificial layer, the thickness of the sacrificial layer is 10 nm to 40 nm.

13. The method of forming a semiconductor structure of claim 1, wherein, The material of the sacrificial layer includes one or more of silicon nitride, aluminum oxide, titanium nitride, titanium oxide and tantalum oxide.

14. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, the substrate further includes a dielectric layer on the interlayer dielectric layer and the gate structure. In the step of forming the sacrificial layer on the interlayer dielectric layer, the sacrificial layer is formed on the dielectric layer. In the process of etching the interlayer dielectric layer with the sidewall layer as a mask, the dielectric layer is also etched.

15. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, a fin is formed on the substrate, and the gate structure spans the fin and covers part of the top wall and part of the sidewall of the fin. In the step of providing the substrate, the source / drain doping layer is in the fin on both sides of the gate structure.

16. A semiconductor structure, characterized by Comprising: A substrate, the substrate includes a first region and a second region; A gate structure on the substrate, the extension direction of the gate structure is perpendicular to the interface between the first region and the second region, and the extension direction of the gate structure is transverse; A source / drain doping layer on both sides of the gate structure; An interlayer dielectric layer on the substrate, the interlayer dielectric layer covers the source / drain doping layer and exposes the top of the gate structure; A sacrificial layer on the interlayer dielectric layer, the sacrificial layer has a first sidewall, and the first sidewall is located at the interface between the first region and the second region; A sidewall layer on the first sidewall of the sacrificial layer, in the extension direction of the gate structure, the lateral size of the sidewall layer is smaller than the lateral size of the sacrificial layer, and after the sacrificial layer is removed, the interlayer dielectric layer is etched with the sidewall layer as a mask to form a blocking structure, and the blocking structure completely exposes the source / drain doping layer in the first region and the second region.

17. The semiconductor structure of claim 16, wherein, The lateral size of the sidewall layer is 3 nm to 10 nm.

18. The semiconductor structure of claim 16, wherein, The height of the sidewall layer is 10 nm to 40 nm.

19. The semiconductor structure of claim 16, wherein, The material of the sidewall layer includes one or more of amorphous silicon, amorphous carbon, amorphous germanium, silicon oxide and silicon nitride.

20. The semiconductor structure of claim 16, wherein, The material of the sacrificial layer includes one or more of aluminum oxide, titanium nitride, titanium oxide and tantalum oxide.

Images