Semiconductor structure and method of forming the same

Abstract

A semiconductor structure includes a first transistor having a first source / drain (S / D) component and a first gate; a second transistor having a second S / D component and a second gate; a multilayer interconnect disposed above the first transistor and the second transistor; a signal interconnect located below the first transistor and the second transistor; and a power rail located below and electrically isolated from the signal interconnect, wherein the signal interconnect electrically connects one of the first S / D component and the first gate to one of the second S / D component and the second gate. Embodiments of the present application also relate to methods of forming a semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. BACKGROUND

[0002] The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices that can support a greater number of increasingly complex and sophisticated functions simultaneously. To meet these demands, there has been a consistent trend in the integrated circuit (IC) industry to produce low-cost, high-performance, and low-power ICs. To date, these goals have been largely achieved by reducing the size of ICs (e.g., the minimum IC feature size), which improves production efficiency and reduces associated costs. However, this scaling has also increased the complexity of the IC fabrication process. Thus, to realize consistent improvements in IC devices and their performance, similar improvements in IC fabrication processes and techniques are needed.

[0003] For example, in standard cell designs, as IC feature sizes are reduced, the size (or footprint) of standard cells (e.g., inverters, AND, OR, and NOR cells) are also scaled down in order to increase circuit density. As a result, the area available for signal interconnects for each standard cell (such as in the M0, M1, M2 layers, etc.) has been reduced. This has created several adverse effects, such as crowded wiring, increased parasitic capacitance, and so on. Thus, while existing methods in semiconductor fabrication have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects. SUMMARY

[0004] Some embodiments of the present application provide a semiconductor structure, comprising: a first transistor having a first source / drain (S / D) feature and a first gate; a second transistor having a second S / D feature and a second gate; a multilayer interconnect disposed above the first transistor and the second transistor; a signal interconnect located below the first transistor and the second transistor; and a power rail located below and electrically isolated from the signal interconnect, wherein the signal interconnect electrically connects one of the first S / D feature and the first gate to one of the second S / D feature and the second gate.

[0005] Some embodiments of the present application provide a method of forming a semiconductor structure, comprising: providing a structure having a first transistor and a second transistor located above a substrate and a first isolation structure located between the first transistor and the second transistor, wherein the first transistor includes a first source / drain (S / D) component and the second transistor includes a second S / D component, the structure further having a first via and a second via connected to the first S / D component and the second S / D component, respectively, and extending to a backside of the structure; partially removing the first isolation structure, thereby exposing a first sidewall surface of the first via and a second sidewall surface of the second via, wherein a first portion of the first isolation structure remains in the structure; depositing a metal interconnect on the first portion of the first isolation structure that electrically contacts the first sidewall surface and the second sidewall surface; and forming an isolation component on the metal interconnect, the first via, and the second via.

[0006] Some embodiments of the present application provide a method of forming a semiconductor structure, comprising: providing a structure having a first transistor and a second transistor, wherein the first transistor includes a first source / drain (S / D) component and the second transistor includes a second S / D component, the structure further having a multilayer interconnect located above a frontside of the first transistor and the second transistor, a first via disposed on a backside of the first S / D component, a second via disposed on a backside of the second S / D component, and a first isolation component disposed on a backside of the structure and adjacent to the first via and the second via; partially removing the first isolation component, thereby forming a trench at the backside of the structure, wherein the trench exposes a first sidewall surface of the first via and a second sidewall surface of the second via; depositing a dielectric spacer on a surface of the trench; patterning the dielectric spacer to expose the first sidewall surface and the second sidewall surface; depositing one or more metal materials on the remaining portion of the dielectric spacer and filling the trench; and etching back the one or more metal materials, the first via, and the second via, wherein a remaining portion of the one or more metal materials becomes a signal interconnect that electrically connects the first via and the second via. BRIEF DESCRIPTION OF DRAWINGS

[0007] The application can best be understood by reference to the following detailed description when considered in connection with the accompanying drawings. It should be noted that various components have not been drawn to scale and certain components have been arbitrarily enlarged or reduced in order to more clearly discuss the present application. In fact, the dimensions can be arbitrarily increased or decreased for the clarity of discussion and discussion.

[0008] Figure 1A and Figure 1B A flow diagram of a method of forming a semiconductor device having backside signal interconnects and backside power rails is shown in accordance with various aspects of the present application.

[0009] Figure 2A A perspective view of a portion of a semiconductor device is shown in accordance with some embodiments, and Figure 2B A cross-sectional view of a semiconductor device in Figure 2A is shown.

[0010] Figure 2C A top view of a portion of a semiconductor device in Figure 2A is shown, and Figure 2D and Figure 2E show a cross-sectional view of a portion of a semiconductor device in Figure 2A along lines D-D and E-E in Figure 2C in accordance with some embodiments, respectively.

[0011] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 9 , Figure 10 , Figure 11A , Figure 12 , Figure 13 , Figure 14 and Figure 15 show a perspective view of a portion of a semiconductor device in Figure 2A in accordance with some embodiments.

[0012] Figure 8B and Figure 11B show a plan view of a portion of a semiconductor device in Figure 2A in accordance with some embodiments.

[0013] Figure 16A , Figure 16B , Figure 16C , Figure 16D and Figure 16E show a schematic layout view of a portion of a semiconductor device in Figure 2A in accordance with some embodiments.

[0014] Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F , Figure 17G , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E , Figure 18F , Figure 18G and Figure 18H shows a perspective view of a portion of a semiconductor device in Figure 2A in accordance with some embodiments.

[0015] Figure 19A shows a schematic view of a portion of a semiconductor device in Figure 2A in accordance with some embodiments. Figure 19B and Figure 19C shows a layout view of a portion of a semiconductor device in Figure 19A in accordance with some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides numerous different embodiments or examples of implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first component over or on a second component can include embodiments in which one or more additional components are formed between the first and second components such that the first component can not be in direct contact with the second component. Additionally, the present disclosure can refer to reference numerals that are the same but denote different aspects, embodiments or features of the present disclosure. This repetition is for the purpose of simplicity and clarity and does not itself serve as a limitation of the disclosure. Therefore, as used herein, the expression "for example" and the like indicates an example and does not indicate an exhaustive list of possible implementations or embodiments.

[0017] Further, for ease of description, spatial relative terms, such as "under", "below", "lower", "on", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. The spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relative descriptors used herein interpreted accordingly. Still further, when describing numerical values or numerical ranges, the term "about" or "approximately" is used to encompass a value within a certain variation (such as + / - 10% or other variation) of the stated value. Unless otherwise specified, the present disclosure is described in terms of specific techniques, in light of the specific technical field, based on knowledge of those skilled in the art. For example, the term "about 5 nm" can encompass a range of sizes from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

[0018] This application relates generally to semiconductor structures and fabrication processes, and more particularly to semiconductor devices having backside signal interconnects and backside power rails. As noted above, signal interconnects (or signal wiring) have become increasingly crowded as devices continue to scale down in size. In addition to interconnect structures on the front side (or front side) of the structure, the inventive subject matter includes providing signal interconnects on the back side (or back side) of the structure containing transistors. The transistors can include gate-all-around (GAA) transistors, FinFET transistors, and / or other types of transistors. Backside signal interconnects can be made between source / drain components and another source / drain component, between source / drain components and gates, and between gates and another gate. In addition to power rails in the front side interconnect structures, the structure is also provided with backside power rails (or power wiring) under the backside signal interconnects. Thus, the structure is provided with an increased number of signal wiring traces and power wiring traces for direct connection to the source / drain components and gates of the transistors. Using the present invention, IC building blocks such as standard cells can be made smaller and circuit density of the IC can be made higher. Details of the structure and fabrication method of the present invention are described below in conjunction with the accompanying drawings, which show processes for fabricating a GAA device according to some embodiments. GAA devices refer to devices having vertically stacked horizontally oriented multi-channel transistors such as nanowire transistors and nanosheet transistors. GAA devices are promising candidates to take CMOS to the next stage of the development roadmap due to their better gate control capability, lower leakage current, and full FinFET device layout compatibility. FinFET devices with backside signal interconnects and backside power rails can also be fabricated using the present invention. For simplicity, the present invention uses GAA devices as an example. Those of ordinary skill in the art will appreciate that they can readily design or modify other processes and structures such as FinFET devices using the present invention as a basis to implement the same purpose and / or achieve the same advantages as the embodiments introduced herein.

[0019] Figure 1A and Figure 1B is a flowchart of a method 100 for fabricating a semiconductor device according to various aspects of the present invention. Additional processes are contemplated by the present invention. Additional operations can be provided before, during, and after method 100, and some operations described can be removed, modified, or combined for additional embodiments of the method 100.

[0020] Method 100 is described below in conjunction with Figures 2A to 15 Figures 2A to 15 ​Various top views, cross-sectional views, and perspective views of a semiconductor device (or semiconductor structure) 200 at various manufacturing steps according to method 100 of some embodiments are shown. In some embodiments, device 200 is part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, memory devices, other suitable components, or combinations thereof. For clarity, simplified representations have been provided. Figures 2A to 15 To better understand the inventive concept of the present invention. Additional components may be added to device 200, and some components described below may be replaced, modified, or eliminated in other embodiments of device 200.

[0021] At operation 102, method 100 ( Figure 1A A semiconductor structure (or semiconductor device) 200 is provided, the semiconductor structure 200 having a substrate 201, a device layer 500 located above the front side of the substrate 201, and an interconnect structure (or multilayer interconnect) 600 located above the device layer 500. The device layer 500 includes transistors. Figure 2A A perspective view of device 200 is shown, and Figure 2B A partial cross-sectional view of device 200 is shown. Device 200 may be included in... Figure 2A Other layers or components not shown include, for example, a passivation layer located above the interconnect structure 600. The substrate 201 is located on the back side of the device 200, and the interconnect structure 600 is located on the front side of the device 200. In other words, the substrate 201, the device layer 500, and the interconnect structure 600 are disposed stacked on top of each other from the back side to the front side of the device 200.

[0022] In this embodiment, substrate 201 is a bulk silicon (Si) substrate, such as a silicon wafer. In alternative embodiments, substrate 201 includes other semiconductors, such as germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP); or alloy semiconductors, such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), and indium gallium phosphide (GaInP). In some embodiments, substrate 201 may include a silicon-on-insulator (SOI) substrate, may be stretched and / or compressed for performance enhancement, may include epitaxial regions, doped regions, and / or include other suitable components and layers.

[0023] Device layer 500 includes semiconductor active regions, such as semiconductor fins, and individual active devices (e.g., transistors) created in or on the semiconductor active regions. Device layer 500 can also include passive devices, such as capacitors, resistors, and inductors. Device layer 500 also includes local interconnects, isolation structures, and other structures.

[0024] Interconnect structure 600 is located above device layer 500 and includes conductors 666, such as metal lines and vias, embedded in one or more dielectric layers 664. Conductors 666 provide connections to devices in device layer 500. Conductors 666 can also provide power rails and ground planes for device 200. Conductors 666 can include copper, aluminum, or other suitable materials and can be formed using a single damascene process, a dual damascene process, or other suitable processes. Dielectric layers 664 can include silicon nitride, silicon oxynitride, silicon nitride with oxygen (O) or carbon (C) elements, oxides formed of tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxides such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials.

[0025] Figure 2C A top view of portions of device 200 is shown, and Figure 2D and Figure 2E Cross-sectional views of portions of device 200 are shown along D-D line and E-E line, respectively, in Figure 2C Device 200 includes gate stacks 240 oriented longitudinally along the “y” direction and active regions, such as semiconductor fins 204, oriented longitudinally along the “x” direction. Figure 2C The illustrated example includes 4 transistors 202, each located at an intersection of a gate stack 240 and a semiconductor fin 204. As will be discussed, each transistor 202 includes two source / drain (S / D) components 260 located on opposite sides of a respective gate stack 240 and one or more channel layers 215 connected the two S / D components and junctioned by the respective gate stack 240. Figure 2C , Figure 2D and Figure 2E Further details of device layer 500 are shown. In particular, D-D line is taken along the longitudinal direction of semiconductor fin 204 (“x” direction) and E-E line is taken into the source / drain region of a transistor and parallel to the longitudinal direction of gate stack 240 (“y” direction).

[0026] Reference is made to Figures 2C to 2EThe semiconductor device 200 includes an isolation component 230 (or isolation structure 230) located above a substrate 201, a semiconductor fin 204 extending from the substrate 201 and adjacent to the isolation component 230, and a source / drain (S / D) component 260 located above the semiconductor fin 204 in the S / D region. The semiconductor device 200 also includes one or more channel semiconductor layers (or channel layers) 215 suspended above the semiconductor fin 204 and connected to the S / D component 260 along the "x" direction; and gate stacks 240 located between the S / D components 260 and surrounding each channel layer 215. Semiconductor device 200 also includes an internal isolation layer 255 located between S / D component 260 and gate stack 240, an external gate spacer 247 located above the sidewall of gate stack 240 and above the topmost channel layer 215, a contact etch stop layer (CESL) 269 adjacent to the gate spacer 247 and located above S / D component 260 and isolation component 230, an interlayer dielectric (ILD) layer 270 located above CESL 269, another CESL 269' located above ILD 270, and another ILD 270' located above CESL 269'. Above gate stack 240, semiconductor device 200 also includes a self-aligned capping layer 352. In some embodiments (e.g.) Figure 2D As depicted, an adhesive layer 357 can be deposited over the gate stack 240 to improve adhesion between the gate stack 240 and the gate via 359 and reduce their contact resistance. Above the S / D components 260, the semiconductor device 200 also includes a silicide component 273, an S / D contact 275, a dielectric S / D capping layer 356, and an S / D contact via 358. In the depicted embodiment, the dielectric S / D capping layer 356 is disposed over some of the source / drain components 260, and the S / D contact via 358 is disposed over other source / drain components 260. The device 200 also includes a semiconductor layer 239 beneath some of the S / D components 260. In an embodiment, the semiconductor layer 239 comprises a semiconductor material different from that of the semiconductor fins 204 and acts as a placeholder for forming back-side vias. In embodiments where device 200 is a FinFET device, channel layer 215 is merged into a single channel layer (semiconductor fin channel), and internal spacers 255 are omitted. Furthermore, in such a FinFET embodiment, gate stack 240 joins the top and sidewalls of the semiconductor fin channel, and... Figure 2D In the cross-sectional view, the gate stack 240 will be located only on top of the semiconductor fin channel. The various elements of the semiconductor device 200 are further described below.

[0027] In various embodiments, the semiconductor fins 204 can comprise silicon, silicon germanium, germanium, or other suitable semiconductor, and can be un-doped, unintentionally doped, or lightly doped with n-type or p-type dopants. The fins 204 can be patterned by any suitable method. For example, the fins 204 can be patterned using one or more photolithography processes including a bi-patterned process or a multi-patterned process. In general, bi- or multi-patterned processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, a pitch that is less than obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used as mask elements for patterning the fins 204. For example, the mask elements can be used to etch a recess into a semiconductor layer in or over the substrate 201, leaving the fins 204 on the substrate 201. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, a dry etching process can implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gas, and / or a plasma, and / or combinations thereof. For example, a wet etching process can include etching in dilute hydrofluoric acid (DHF); a potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchant. Many other embodiments of methods of forming the fins 204 can be suitable.

[0028] The isolation components 230 can comprise silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material (e.g., comprising silicon, oxygen, nitrogen, carbon, or other suitable isolation component), or combinations thereof. The isolation components 230 can comprise different structures, such as shallow trench isolation (STI) structures and / or deep trench isolation (DTI) structures. In embodiments, the isolation components 230 can be formed by filling trenches between the fins 204 with an insulator material (e.g., by using a CVD process or a spin-on glass process), performing a chemical mechanical polishing (CMP) process to remove excess insulator material and / or to planarize a top surface of the insulator material layer, and etching back the insulator material layer to form the isolation components 230. In some embodiments, the isolation components 230 comprise a multi-layer structure, such as a silicon nitride layer disposed over a thermal oxide liner layer.

[0029] The semiconductor layer 239 can be deposited using an epitaxial growth process or by other suitable processes. In some embodiments, epitaxial growth of the semiconductor layer 239 is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metal-organic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth processes, or a combination thereof. The semiconductor layer 239 includes a semiconductor material that is different from the semiconductor material included in the semiconductor fins 204 to achieve etch selectivity during subsequent processing. For example, the semiconductor layer 239 and the semiconductor fins 204 can include different materials, different atomic percentage of components, different weight percentage of components, and / or other characteristics to achieve a desired etch selectivity during an etch process. In an embodiment, the semiconductor fins 204 include silicon and the semiconductor layer 239 includes silicon germanium. In another embodiment, the semiconductor layer 239 and the semiconductor fins 204 can both include silicon germanium but have different silicon atomic percentages. The present disclosure encompasses any combination of semiconductor materials included in the semiconductor layer 239 and the semiconductor fins 204 that can provide a desired etch selectivity, including any of the semiconductor materials disclosed herein. The semiconductor layer 239 serves as a placeholder for backside vias and / or backside isolation.

[0030] The S / D components 260 include epitaxially grown semiconductor material, such as epitaxially grown silicon, germanium, or silicon germanium. The S / D components 260 can be formed by any epitaxial process including chemical vapor deposition (CVD) techniques, molecular beam epitaxy, other suitable epitaxial growth processes, or a combination thereof. The S / D components 260 can be doped with n-type dopants and / or p-type dopants. In some embodiments, for n-type transistors 202, the S / D components 260 include silicon and can be doped with carbon, phosphorous, arsenic, other n-type dopants, or a combination thereof (e.g., forming Si:C epitaxial S / D components, Si:P epitaxial S / D components, or Si:C:P epitaxial S / D components). In some embodiments, for p-type transistors 202, the S / D components 260 include silicon germanium or germanium and can be doped with boron, other p-type dopants, or a combination thereof (e.g., forming Si:Ge:B epitaxial S / D components). The S / D components 260 can include multiple epitaxial semiconductor layers having different levels of dopant density. In some embodiments, an anneal process (e.g., rapid thermal anneal (RTA) and / or laser anneal) is performed to activate the dopants in the epitaxial S / D components 260.

[0031] In embodiments, the channel layers 215 include a semiconductor material suitable for a transistor channel, such as silicon, silicon germanium, or other semiconductor material. In various embodiments, the channel layers 215 can be rod-shaped, strip-shaped, sheet-shaped, or other shape. In one embodiment, the channel layers 215 are initially part of a stack of semiconductor layers that includes channel layers 215 and other (sacrificial) semiconductor layers that are alternately stacked layer-by-layer. The sacrificial semiconductor layers and the channel layers 215 include different material compositions (such as different semiconductor materials, different atomic percentage of components, and / or different weight percentage of components) to achieve etch selectivity. During a gate replacement process to form the gate stack 240, the sacrificial semiconductor layers are removed, leaving the channel layers 215 that will overhang the semiconductor fin 204.

[0032] In some embodiments, the inner spacer layers 255 include a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbide nitride). In some embodiments, the inner spacer layers 255 include a low-k dielectric material, such as those described herein. The inner spacer layers 255 can be formed by deposition and etching processes. For example, after etching the S / D trenches and before epitaxially growing the S / D features 260 from the S / D trenches, an etching process can be used to recess the sacrificial semiconductor layers located between adjacent channel layers 215 to form gaps vertically between adjacent channel layers 215. One or more dielectric materials are then deposited (e.g., using CVD or ALD) to fill the gaps. Another etching process is performed to remove the dielectric material outside the gaps, thereby forming the inner spacer layers 255.

[0033] In the depicted embodiment, each gate stack 240 includes a gate dielectric layer 349 and a gate electrode 350. Gate dielectric layer 349 can include a high-k dielectric material, such as Hf02, HfSiO, HfSi04, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, Zr02, ZrSi02, A10, AlSiO, AI2O3, TiO, Ti02, LaO, LaSiO, Ta203, Ta205, Y203, SrTi03, BaZrO, BaTi03(BTO), (Ba,Sr)Ti03(BST), Si3N4, hafnium dioxide-aluminum dioxide (Hf02-AI2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric material generally refers to a dielectric material having a high dielectric constant, e.g., a dielectric constant greater than that of silicon dioxide (k ~ 3.9). Gate dielectric layer 349 can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. In some embodiments, gate stack 240 further includes an interface layer between gate dielectric layer 349 and channel layer 215. The interface layer can include silicon dioxide, silicon oxynitride, or other suitable materials. In some embodiments, gate electrode layer 350 includes an n-type or p-type work function layer and a metal fill layer. For example, an n-type work function layer can include a metal having a sufficiently low effective work function, such as titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or combinations thereof. For example, a p-type work function layer can include a metal having a sufficiently large effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. For example, a metal fill layer can include aluminum, tungsten, cobalt, copper, and / or other suitable materials. Gate electrode layer 350 can be formed by CVD, PVD, plating, and / or other suitable processes. Because gate stack 240 includes a high-k dielectric layer and a metal layer, it is also referred to as a high-k metal gate.

[0034] In an embodiment, the gate spacers 247 include a dielectric material, such as a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN)). In embodiments, the gate spacers 247 can include La2O3, Al2O3, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Y2O3, AlON, TaCN, ZrSi, or other suitable materials. For example, a dielectric layer including silicon and nitrogen, such as a silicon nitride layer, can be deposited over a dummy gate stack (which is later replaced by the high-k metal gate stack 240), and the dielectric layer is subsequently etched (e.g., anisotropically etched) to form the gate spacers 247. In some embodiments, the gate spacers 247 include a multi-layer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, are formed adjacent to the gate stack 240. In embodiments, the gate spacers 247 can have a thickness of, for example, about 1 nm to about 40 nm.

[0035] In some embodiments, the SAC layer 352 includes La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable materials. The SAC layer 352 protects the gate stack 240 from etching and CMP processes used to etch the S / D contact holes. The SAC layer 352 can be formed by recessing the gate stack 240 and optionally the gate spacers 247, depositing one or more dielectric materials over the recessed gate stack 240 and optionally over the recessed gate spacers 247, and performing a CMP process on the one or more dielectric materials.

[0036] In embodiments, the CESLs 269 and 269' can each include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable materials; and can be formed by CVD, PVD, ALD, or other suitable methods. The ILD layers 270 and 270' can each include an oxide formed from tetraethyl orthosilicate (TEOS), an undoped silicate glass, or a doped silicon oxide such as borophosphosilicate glass (BPSG), fluorine-doped silicon dioxide glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), a low-k dielectric material, other suitable dielectric material, or combinations thereof. The ILD layers 270 and 270' can each be formed by PECVD (plasma-enhanced CVD), FCVD (flowable CVD), or other suitable methods.

[0037] In some embodiments, the silicide component 273 can include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds.

[0038] In embodiments, the S / D contacts 275 can include a conductive barrier layer and a metal fill layer over the conductive barrier layer. The conductive barrier layer can include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and can be formed by CVD, PVD, ALD, and / or other suitable processes. The metal fill layer can include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals, and can be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted in the S / D contacts 275.

[0039] In some embodiments, the capping layer 356 includes La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable material. The capping layer 356 protects the S / D contacts 275 from etching and CMP processes, and isolates the S / D contacts 275 from interconnect structures formed thereon. In some embodiments, the SAC layer 352 and the capping layer 356 include different materials to achieve etch selectivity, e.g., during formation of the capping layer 356.

[0040] In one embodiment, the S / D contact via 358 and the gate via 359 can each include a conductive barrier layer and a metal fill layer positioned above the conductive barrier layer. The conductive barrier layer can include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and can be formed by CVD, PVD, ALD, and / or other suitable processes. The metal fill layer can include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals, and can be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted in the S / D contact via 358 and / or the gate via 359. In some embodiments, the adhesion layer 357 can include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and can be formed by CVD, PVD, ALD.

[0041] At operation 104, the method 100 Figure 1A thins the device 200 down from the backside of the device 200 until the semiconductor fins 204, the semiconductor layer 239, and the isolation component 230 are exposed from the backside of the device 200. The resulting structure is shown in Figure 3 for simplicity. It should be noted that the device 200 is upside down in Figure 3 and in Figure 3 and in Figures 4 to 15 and Figures 17A to 18H , the “-z” axis of the figures represents pointing upwards. Furthermore, in Figure 3In the described embodiment, some of the S / D components 260 are n-type (labeled 260(N)) and are used in n-type transistors 202, and some of the S / D components 260 are p-type (labeled 260(P)) and are used in p-type transistors 202. In embodiments, operation 104 first flips the device 200 upside down and attaches the front side of the device 200 to a carrier, and then applies a thinning process to the back side of the device 200. The thinning process can include a mechanical grinding process and / or a chemical thinning process. During the mechanical grinding process, a large amount of substrate material can first be removed from the substrate 201. Thereafter, the chemical thinning process can apply an etching chemical to the back side of the substrate 201 to further thin the substrate 201.

[0042] At operation 106, the method 100 Figure 1A forms backside vias 282 electrically connected to some of the S / D components 260. In embodiments, the backside vias 282 are formed by a lithography process that includes a photoresist layer, a mask, and a lithography exposure. The backside vias 282 can be formed by a lithography process that is the same as the lithography process used to form the front side vias 280. In embodiments, the backside vias 282 are formed by a lithography process that is different than the lithography process used to form the front side vias 280. Figure 4An embodiment of the generated structure is illustrated. Operation 106 includes various processes. In an embodiment, operation 106 selectively etches the semiconductor layer 239 to form a hole exposing the S / D component 260. For example, operation 106 may apply a wet etching process, a dry etching process, a reactive ion etching process, or another suitable etching process, wherein the etching process is tuned to selectively remove the semiconductor layer 239 and minimally etch the semiconductor fins 204 and the isolation structure 230. Once the S / D component 260 is exposed in the hole, operation 106 may further partially recess the S / D component 260. Subsequently, operation 106 deposits one or more metals over the S / D component 260 and in the hole to form a back-side via 282. The back-side via 282 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the back-side via 282 may include more than one layer of material. For example, the back-side via 282 may include a barrier layer and one or more low-resistance metals located on the barrier layer. The barrier layer may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), cobalt (Co), ruthenium (Ru), or other suitable materials, and the low-resistance metal may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), aluminum (Al), or other metals. In some embodiments, operation 106 forms a silicide component (not shown) above the exposed surface of the S / D component 260, and then forms the back-side via 282 on the silicide component. The silicide components may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. After depositing one or more metals for the back-side via 282, operation 106 may perform a CMP process to planarize the back-side surface of device 200.

[0043] At operation 108, method 100 ( Figure 1A The isolation structure 230 is partially recessed, thereby forming a trench 400 above the back side of the device 200. Figure 5 An example of the generated structure is shown below. (See reference...) Figure 5From the backside of the device 200, the isolation structure 230 is etched back until a thin layer of the isolation structure 230 remains. In some embodiments, the thickness Tl of the remaining layer of the isolation structure 230 is in the range of about 4 nm to about 20 nm. This layer of the isolation structure 230 provides isolation between the subsequently formed signal interconnects 406 Figure 11A and Figure 11B ) and the gate stack 240 (see Figure 18E ). If this layer is too thin, such as less than 4 nm, the isolation can be insufficient and there is a risk of shorting the signal interconnects 406 and the gate stack 240. If this layer is too thick, such as greater than 20 nm, the backside structure can be too thick and some of the backside vias 282, such as the backside via 282 at the right back corner of the device 200 in Figure 14 , can be too tall and have an excessive resistance for certain applications.

[0044] In embodiments, the operation 108 can apply a wet etch process, a dry etch process, a reactive ion etch process, or another suitable etch process, where the etch process is adjusted to selectively etch the isolation structure 230 and to etch the semiconductor fins 204 and the backside vias 282 almost entirely. A timer can be used to control the etch process to obtain the desired thin layer of the isolation structure 230. In embodiments, the etching is self-aligned to the isolation structure 230 without the need to use an etch mask. In another embodiment, the operation 108 forms an etch mask to cover the areas of the device 200, including the areas of the isolation structure 230, that will not form the signal interconnects, and the isolation structure 230 is etched through the etch mask. After the etching is completed, the etch mask is removed. The etching creates the trench 400 on the backside of the device 200. Referring to Figure 5 , the floor of the trench 400 is the surface of the isolation structure 230 and the sidewalls of the trench 400 include the sidewalls of the semiconductor fins 204 and the sidewalls of the backside vias 282.

[0045] At operation 110, the method 100 Figure 1A forms a dielectric spacer 402 on the surface of the trench 400 and over the backside of the device 200. An embodiment of the resulting structure is shown in Figure 6 . Referring to Figure 6A dielectric spacer 402 is deposited on surfaces of the isolation structure 230, the semiconductor fin 204, and the backside via 282 exposed in the trench 400. The dielectric spacer 402 is also deposited on the backside surface of the device 200. In embodiments, the dielectric spacer 402 includes a dielectric material having silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN)). In embodiments, the dielectric spacer 402 is deposited to have a uniform or substantially uniform thickness on the various surfaces described above. For example, the dielectric spacer 402 can be deposited using ALD or other suitable processes to achieve a uniform or substantially uniform thickness. In some embodiments, the dielectric spacer 402 has a thickness T2 in a range from about 3 nm to about 8 nm. As will be discussed, the dielectric spacer 402 provides isolation between the signal interconnect 406 and some of the backside vias 282 that are subsequently formed (see Figure 11B , an example where the dielectric spacer 402 isolates the signal interconnect 406 from the via 282 at the right back corner). If the dielectric spacer 402 is too thin (such as less than 3 nm), the isolation can be insufficient and the risk of shorting of the signal interconnect 406 and some of the backside vias 282 can be high. As will be further discussed, the dielectric spacer 402 and the signal interconnect 406 collectively fill the trench 400 (see Figure 11A , an example). Thus, if the dielectric spacer 402 is too thick (such as greater than 8 nm), then in some cases depending on the spacing between adjacent backside vias 282 along the “y” direction, the signal interconnect can be too thin (and its electrical resistance can be too large). In various embodiments, the dielectric spacer 402 can include a single layer of material or multiple layers of different materials.

[0046] At operation 112, the method 100 Figure 1A ) patterns the dielectric spacer 402 to expose surfaces of some of the backside vias 282 that are to be connected by the backside signal interconnect. This can involve a variety of processes including photolithography and etching processes. Embodiments of operation 112 are shown in Figure 7 、 Figure 8A and Figure 8B , where after patterning the dielectric spacer 402, the backside vias 282 in the left back corner and the right front corner of the device 200 shown in Figures 7 to 8B are exposed.

[0047] Reference is made to Figure 7A patterned etch mask 404 is formed over the backside of the device 200. The patterned etch mask 404 covers unetched portions of the dielectric spacer 402. The patterned etch mask 404 includes a material that is different than the material of the dielectric spacer 402 to enable etch selectivity. In some embodiments, the patterned etch mask 404 includes a patterned photoresist (or resist). In some embodiments, the patterned etch mask 404 also includes an anti-reflective coating (ARC) layer or other layer under the patterned resist. Other materials for the patterned etch mask 404 are contemplated by the present subject matter so long as etch selectivity is achieved during etching of the dielectric spacer 402. In some embodiments, the patterned etch mask 404 is formed by a photolithography process that includes a resist layer, performing a pre-exposure bake process, performing an exposure process using a mask, performing a post-exposure bake process, and performing a development process. After development, the resist layer is patterned into the etch mask 404 corresponding to the mask. Optionally, the exposure process can be implemented or replaced by other methods, such as maskless lithography, e-beam writing, ion beam writing, or combinations thereof. It is noted that in the illustrated embodiment, the patterned etch mask 404 is present in the top surface of the dielectric spacer 402 in the selected region, and can or can not be present on the sidewalls of the dielectric spacer 402 inside the trench 400. Figure 7 In the illustrated embodiment, the patterned etch mask 404 is present in the top surface of the dielectric spacer 402 in the selected region, and can or can not be present on the sidewalls of the dielectric spacer 402 inside the trench 400.

[0048] Reference is made to Figure 8A Operation 112 etches the dielectric spacer 402 through the patterned etch mask 404, thereby exposing the top and sidewall surfaces of the backside via 282 that will be connected by the backside signal interconnect (406 in Figure 11A and Figure 11B It also exposes portions of the semiconductor fin 204 and the isolation structure 230. In the present embodiment, the etch process is a dry etch process and is anisotropic (vertical etch). As a result, the portion of the dielectric spacer 402 that is located on the sidewalls of the trench 400 and directly underneath the patterned etch mask 404 is not etched. The etch is tuned to selectively etch the material of the dielectric spacer 402 and to etch the semiconductor fin 204, the isolation structure 230, and the backside via 282 very little. After the etch is completed, the patterned etch mask 404 is removed, for example by resist stripping, ashing, or other suitable process.

[0049] Figure 8B A plan view of the device 200 from the backside of the device 200 is shown after completion of operation 112. As Figure 8B shown, the shape of the exposed surfaces of the isolation structure 230 can be defined by the photolithography in operation 112 as described above. As shown, the distance between the two backside vias 282 along the "y" direction is PI, which is approximately S / D components 260(N) and 260(P) ( Figure 3 The exposed surface of the isolation structure 230 has a central portion that is parallel to the "x" direction in the longitudinal direction and two protrusions extending from both ends of the central portion toward opposite directions ("y" and "-y"). The central portion has a width W1 in the "y" direction, and both protrusions have a width W2 in the "y" direction. P1 = W1 + 2W2 holds. In some embodiments, the dimension P1 is in the range of about 20 nm to about 60 nm. In one embodiment, the width W1 is about half of the dimension P1 and varies in the range of about 3 nm to about 5 nm. In other words, W1 = (1 / 2)P1 ± Δ, where Δ is in the range of about 3 nm to about 5 nm. The variation Δ accounts for misalignment and other inaccuracies during photolithography. As will be discussed, the shape of the exposed surface of the isolation structure 230 is the same as the shape of the bottom surface of the signal interconnect 406 (when viewed from the backside of the device 200). Figure 8B Figure 11A The shape of the exposed surface of the isolation structure 230 is the same as the shape of the bottom surface of the signal interconnect 406 (when viewed from the backside of the device 200).

[0050] At operation 114, the method 100 Figure 1B fills the trench 400 with one or more metals 406. Referring to Figure 9 , the one or more metals 406 are deposited on the isolation structure 230 and are in direct contact with the sidewall surface of the backside via 282 exposed in the trench 400. The one or more metals 406 are also in direct contact with the sidewall surface of the semiconductor fin 204 exposed in the trench 400. As will be discussed, the semiconductor fin 204 will be replaced by an insulating material 408 in a later step Figure 13 . Thus, there is no concern of shorting through the one or more metals 406 and the semiconductor fin 204. The one or more metals 406 can include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), aluminum (Al), or other metals, and can be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the one or more metals 406 can include a barrier layer and one or more low-resistance metals on the barrier layer. The barrier layer can include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), cobalt (Co), ruthenium (Ru), or other suitable materials, and the low-resistance metals can include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), aluminum (Al), or other metals.

[0051] At operation 116, the method 100 Figure 1B etches back the one or more metals 406 and the backside via 282. The resulting structure is as shown in Figure 10 ​As shown. Operation 116 can apply one or more etching processes, which can be adjusted to selectively etch one or more metals 406 and the material of the back-side via 282, and barely etch the dielectric spacer 402 and the semiconductor fin 204. The etching process can include dry etching, wet etching, reactive ion etching, or other suitable processes. A portion of one or more metals 406 remains in the trench 400 and becomes the signal interconnect 406 (or metal interconnect 406). A timer can be used to control the etching process so that the metal interconnect 406 achieves a desired thickness T3 (along the "z" or "-z" direction), such as in the range of about 5 nm to about 20 nm. If the signal interconnect 406 is too thin (e.g., less than 5 nm), its resistance may be undesirably high for some applications. If the signal interconnect 406 is too thick (e.g., greater than 20 nm), the back side of device 200 may be undesirably high. Furthermore, this will undesirably increase the resistance of the connection to the back-side power rail (such as...). Figure 14 The length and resistance of some back-side vias 282 (via 282 at the right rear corner of device 200). The area of ​​the contact interface between the signal interconnect 406 and the back-side via 282 is T3*W3, where W3 is the width of the via 282 along the "x" direction. In some embodiments, W3 is in the range of about 10 nm to about 30 nm.

[0052] At operation 118, method 100 ( Figure 1B The patterned dielectric spacer 402 is etched back. The resulting structure is as follows: Figure 11A As shown. Operation 118 may apply one or more etching processes, which may be adjusted to selectively etch the material of the patterned dielectric spacer 402 and barely etch the signal interconnect 406, back-side via 282, and semiconductor fin 204. The etching process may include dry etching, wet etching, reactive ion etching, or other suitable processes. A portion of the dielectric spacer 402 remains in the trench 400 and has an "L" shape in the front view. The vertical portion of the "L"-shaped spacer 402 is disposed between the signal interconnect 406 and the semiconductor fin 204. The horizontal portion of the "L"-shaped spacer 402 is disposed between the signal interconnect 406 and the isolation structure 230. Figure 11B A plan view of device 200 as viewed from the rear side is shown. (As shown) Figure 11A and Figure 11B As shown, the dielectric spacer 402 has a thickness T2 along the "y" direction. In one embodiment, the thickness T2 is in the range of about 3 nm to about 8 nm, and its importance has been referenced. Figure 6 A discussion was held.

[0053] like Figure 11AAs shown, the top surface of the signal interconnect 406 is substantially flat, and the bottom surface of the signal interconnect 406 has a stepped profile. The portion of the bottom surface of the signal interconnect 406 is disposed on the isolation structure 230, and another portion of the bottom surface of the signal interconnect 406 is disposed on the horizontal portion of the dielectric spacer 402. Thus, from the front view, the signal interconnect 406 has an inverted "L" shape that is complementary to the "L" shaped spacer 402. The vertical portion of the inverted "L" shape is disposed directly above the isolation structure 230, and the horizontal portion of the inverted "L" shape is disposed directly above the dielectric spacer. The portion of the signal interconnect 406 disposed directly above the isolation structure 230 has the same shape and dimensions as the exposed surface of the isolation structure 230, with a central portion having a width W1 and being longitudinally parallel to the "x" direction, and two protrusions extending from both ends of the central portion toward opposite directions ("y" and "-y") and each having a width W2. The top surface of the signal interconnect 406 is also shown in Figure 8B the isolation structure 230, with a central portion having a width W1 and being longitudinally parallel to the "x" direction, and two protrusions extending from both ends of the central portion toward opposite directions ("y" and "-y") and each having a width W2. The top surface of the signal interconnect 406 is also shown in Figure 11B the isolation structure 230, with a central portion having a width W1 and being longitudinally parallel to the "x" direction, and two protrusions extending from both ends of the central portion toward opposite directions ("y" and "-y") and each having a width W2. The top surface of the signal interconnect 406 is also shown in Figure 11A and Figure 11B As shown, the first sidewall surface of the signal interconnect 406 directly contacts the backside via 282 at the left rear corner, and the second sidewall surface of the signal interconnect 406 directly contacts the backside via 282 at the right front corner, thereby connecting the two backside vias 282. It is noted that in Figure 11A the device 200 is upside down. Thus, when the device 200 is viewed from the front side, the top surface and the bottom surface of the signal interconnect 406 discussed above are the bottom surface and the top surface of the signal interconnect 406, respectively.

[0054] At operation 120, the method 100 Figure 1B forms the isolation component 408 over the signal interconnect 406 and fills the trench 400. The resulting structure is shown in Figure 12As shown. In one embodiment, operation 120 includes depositing one or more dielectric materials over signal interconnects 406 and filling trenches 400, and then performing a CMP process to planarize the backside surface of device 200 and to expose backside vias 282 and semiconductor fins 204. Portions of the one or more dielectric materials remain in trenches 400 and become isolation features 408. Isolation features 408 can include one layer of dielectric material or multiple layers of dielectric material, such as a dielectric liner layer and a dielectric fill layer over the dielectric liner layer. In one embodiment, isolation features 408 include a dielectric material having silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN)). In some embodiments, isolation features 408 can include La2O3, Al2O3, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Y2O3, AlON, TaCN, ZrSi, or other suitable materials. Isolation features 408 can be deposited using ALD, CVD, or other suitable methods.

[0055] At operation 122, method 100 Figure 1B replaces semiconductor fins 204 with one or more dielectric materials. In an embodiment, the one or more dielectric materials are the same materials as those in isolation features 408, such as Figure 13 As shown. In another embodiment, the one or more dielectric materials are different materials than those in isolation features 408. Operation 122 can involve multiple processes including etching and deposition processes. For example, operation 122 can first perform one or more etches to remove semiconductor fins 204 and semiconductor layer 239 thereunder. The etching processes can include dry etching, wet etching, reactive ion etching, or other suitable processes. The etching processes are selected to etch the materials of semiconductor fins 204 and semiconductor layer 239 selectively and to etch isolation features 408, signal interconnects 406, dielectric spacers 402, isolation structures 230, and backside vias 282 very little. After etching semiconductor fins 204 and semiconductor layer 239 thereunder, trenches are formed at the backside of device 200 and portions of some S / D features 260, internal isolation 255, and gate stack 240 are exposed. Subsequently, operation 122 deposits one or more dielectric materials into the trenches and performs a CMP process to planarize the backside of device 200 and to expose some backside vias 282 that will be connected to backside power rails, such as backside via 282 at the right back corner in Figure 13

[0056] At operation 124, method 100 Figure 1B ​) forming one or more backside power rails 284. According to embodiments, the resulting structure is as shown in Figure 14 As shown in Figure 14 Some of the backside vias 282, such as the backside via 282 at the right back corner in Figure 14 , are electrically connected to the backside power rails 284. In embodiments, the backside power rails 284 can be formed using a damascene process, a dual damascene process, a metal patterning process, or other suitable process. The backside power rails 284 can include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metal, and can be deposited by CVD, PVD, ALD, plating, or other suitable process. Although not shown in Figure 14 The backside power rails 284 are embedded in one or more dielectric layers. Having the backside power rails 284 advantageously increases the number of available metal traces in the device 200 for direct connection to source / drain contacts and vias. It also increases gate density for greater device integration compared to other structures without the backside power rails 284. The backside power rails 284 can have a width that is wider than the size of the first level metal (M0) traces on the front side of the device 200, which advantageously reduces backside power rail resistance. The isolation components 408 disposed between the backside power rails 284 and the signal interconnects 406 have a thickness T4. In some embodiments, the thickness T4 is in a range from about 4 nm to about 20 nm. If the thickness T4 is too small, such as less than 4 nm, the coupling capacitance between the signal interconnects 406 and the backside power rails 284 can be undesirably high for certain applications, and the isolation effect can be insufficient. If the thickness T4 is too large, such as greater than 20 nm, the length and resistance of some of the backside vias 282, such as the backside via 282 at the right back corner in Figure 14 , can be undesirably large for certain applications.

[0057] At operation 126, the method 100 Figure 1B performs further fabrication processes on the device 200. For example, it can form one or more interconnect layers on the backside of the device 200, form a passivation layer on the backside of the device 200, and perform other back end of line (BEOL) processes.

[0058] Figure 15 shows a perspective view of the device 200 according to embodiments. As shown in Figure 15As shown, the device 200 includes a backside power rail 284 and backside vias 282. Some of the backside vias 282 connect some of the S / D components 260 vertically to the backside power rail 284. Some of the backside vias 282 are connected to some of the S / D components 260, but some of the backside vias 282 are isolated from the backside power rail 284 by isolation components 408. Signal interconnects 406 connect multiple backside vias 282. In this embodiment (as well as in the embodiments shown in Figure 14 , the signal interconnects 406 are isolated from the gate stacks 240. The channel layers 215 are vertically stacked on top of one another and connected between pairs of S / D components 260. The gate stacks 240 are engaged with and wrapped around each channel layer 215. Some of the S / D components 260 are provided with both frontside contacts 275 and backside vias 282.

[0059] Figures 16A to 16E Various non-limiting examples of signal interconnects 406 that can be implemented in the device 200 are shown. Figure 16A Examples of signal interconnects 406 establishing connections between a transistor’s S / D and another S / D of an adjacent transistor are shown. Figure 16B Examples of signal interconnects 406 establishing connections between a transistor’s S / D and another S / D of a non-adjacent transistor (i.e., there is an intervening transistor between the two transistors) are shown. Figure 16A and Figure 16B may be formed by the operations discussed above with reference to Figures 1A to 15 . Figure 16C Examples of signal interconnects 406 establishing connections between a transistor’s S / D and a gate of an adjacent transistor are shown. Figure 16D Examples of signal interconnects 406 establishing connections between a transistor’s gate and another gate of an adjacent transistor are shown. Figure 16E Examples of signal interconnects 406 establishing connections between a transistor’s gate and another gate of a non-adjacent transistor (i.e., there is an intervening transistor between the two transistors) are shown.

[0060] Figures 17A to 17G Perspective views of the device 200 during various operations in embodiments of the method 100 in which signal interconnects 406 establish connections between two gates (such as in the examples in Figure 16D and Figure 16E are shown. Figures 17A to 17G Certain aspects of the device 200 are similar to the above-discussed Figures 3 to 15 . The device 200 is provided upside-down in each of Figures 17A to 17G . Furthermore, a side view of the device 200 (exposing the gate stacks 240) can be provided as a cross-sectional view taken along the F-F line in Figure 2C . Thus, in Figures 17A to 17G Channel layer 215 is not shown in the diagram. A brief discussion follows. Figures 17A to 17G and its related methods.

[0061] like Figure 17A As shown, device 200 is provided with the various components 260, 356, 269, 270, 240, 230, 204 and 282 discussed above. Figure 17A The device 200 shown operates via 102, 104, and 106 ( Figure 1A To form this structure. Specifically, an isolation structure 230 is provided on the back side of the gate stack 240, and a back-side via 282 is formed and connected to some S / D components 260.

[0062] like Figure 17B As shown, the isolation structure 230 is etched back from the back side of device 200 until a thin layer of the isolation structure 230 is retained. In some embodiments, the retained layer of the isolation structure 230 has a thickness T1 in the range of about 4 nm to about 20 nm, as referenced. Figure 5 Its importance has been discussed. Any suitable etching process can be used to etch the isolation structure 230. The etching process selectively etches the material of the isolation structure 230 and barely etches the semiconductor fins 204 and the back-side via 282. A timer can be used to control the etching process to obtain the desired thin layer of the isolation structure 230. In the embodiment, an etching mask is formed to cover areas of the device 200 where signal interconnects will not be formed, and then the isolation structure 230 is etched through the etching mask. After etching is complete, the etching mask is removed. The etch-back of the isolation structure 230 creates trenches 400 on the back side of the device 200.

[0063] like Figure 17C As shown, similar to operation 110 described above, dielectric spacers 402 are formed to cover various surfaces on the back side of device 200, including various surfaces of trench 400. For example, dielectric spacers 402 may be formed to have a uniform or substantially uniform thickness. Then, similar to operation 112 described above, photolithography and etching processes are used to pattern the dielectric spacers 402 and the isolation structure 230 to form holes 401 therein, which expose the gate stack 240 for fabricating signal interconnects connected to the gate stack 240.

[0064] like Figure 17DAs shown, similar to operation 114 described above, one or more metals 406 are deposited to fill trenches 400 and holes 401. Then, one or more metals 406 are etched back, similar to operation 116 described above. The retained portions of the one or more metals 406 become signal interconnects (or metal interconnects) 406 connecting the two gates 240 of the two transistors. In this embodiment, the top surface of the signal interconnect 406 is flat or substantially flat, and the bottom surface of the signal interconnect 406 has two protrusions whose bottom surfaces directly contact the gate stack 240. It should be noted that... Figure 17D The device 200 is upside down. Therefore, when viewing the device 200 from the front, the top and bottom surfaces of the signal interconnect 406 discussed above are the bottom and top surfaces of the signal interconnect 406, respectively.

[0065] like Figure 17E As shown, similar to operation 118 described above, the dielectric spacer 402 is partially etched back. (As...) Figure 17F As shown, similar to operation 120 described above, an isolation component 408 is formed above the signal interconnect 406. Figure 17G As shown, similar to operation 122 above, the semiconductor fin 204 is replaced with an insulating material.

[0066] Figures 18A to 18H A perspective view of device 200 during various operations in an embodiment of method 100 is shown, wherein signal interconnects 406 are located at the S / D component and the gate (such as... Figure 16C Establish connections between instances in the dataset. Figures 18A to 18H Some aspects are similar to those discussed above. Figures 3 to 15 Place device 200 in Figures 18A to 18H Each of them is provided upside down. Additionally, a side view of device 200 (exposing the gate stack 240) can be provided along... Figure 2C The cross-sectional view taken from the FF line in the diagram. Therefore, in Figures 18A to 18H Channel layer 215 is not shown in the diagram. A brief discussion follows. Figures 18A to 18H and its related methods.

[0067] Figure 18A and Figure 18B respectively with Figure 17A and Figure 17B Same. Therefore, the comparison is omitted here. Figure 18A and Figure 18B The discussion. For example... Figure 18CAs shown, similar to operation 110 described above, dielectric spacers 402 are formed to cover the various surfaces of the back side of device 200, including the various surfaces of trench 400. For example, dielectric spacers 402 may be formed to have a uniform or substantially uniform thickness. Then, similar to operation 112 described above, photolithography and etching processes are used to pattern the dielectric spacers 402 and the isolation structure 230 to form holes 401 therein, which expose the gate stack 240 for fabricating signal interconnects connected to the gate stack 240.

[0068] like Figure 18D As shown, similar to operation 112 above, the dielectric spacer 402 is patterned again using photolithography and etching processes to expose the back-side via 282 for fabricating signal interconnects connected to the back-side via 282. Adjustment for... Figure 18D The etching process selectively etches the material of the dielectric spacer 402 and hardly etches the back-side via 282, semiconductor fin 204 and isolation structure 230.

[0069] like Figure 18E As shown, similar to operation 114 described above, one or more metals 406 are deposited to fill trench 400 and via 401. Then, similar to operation 116 described above, one or more metals 406 and back-side via 282 are etched back. The retained portions of one or more metals 406 become signal interconnects (or metal interconnects) 406 connecting the gate 240 to the S / D component 260. In this embodiment, the top surface of the signal interconnect 406 is flat or substantially flat, and the bottom surface of the signal interconnect 406 has two protrusions. The bottom surface of one protrusion directly contacts the gate stack 240, and the sidewall surface of the other protrusion directly contacts the back-side via 282. It should be noted that, in Figure 18E In this context, device 200 is upside down. Therefore, when viewing device 200 from the front, the top and bottom surfaces of the signal interconnect 406 discussed above are the bottom and top surfaces of the signal interconnect 406, respectively.

[0070] like Figure 18F As shown, similar to operation 118 described above, the dielectric spacer 402 is partially etched back. (As...) Figure 18G As shown, similar to operation 120 described above, an isolation component 408 is formed above the signal interconnect 406. Figure 18H As shown, similar to operation 122 above, the semiconductor fin 204 is replaced with an insulating material.

[0071] Figure 19AA schematic diagram of an exemplary logic cell 300 that can benefit from aspects of the present invention is shown. The logic cell 300 can be included in the device 200. The logic cell 300 implements an AOI (AND-OR-INVERTER) function and includes 4 PMOSFETs and 4 NMOSFETs. The logic cell 300 includes input terminals A1, A2, B1, and B2, an output terminal ZN, and an internal network n01.

[0072] Figure 19B A layout implementation of the logic cell 300 according to the present embodiment is shown. In particular, portions of the input terminals A1, A2, B1, B2, the internal network n01, and the output terminal ZN are implemented as signal interconnects at the front side of the logic cell 300, while another portion of the output terminal ZN is implemented as a signal interconnect at the back side of the logic cell 300, such as the signal interconnect 406 shown. Figure 14 Figure 15 Because portions of the output terminal ZN are implemented as back side signal interconnects, the routing at the front side of the logic cell 300 is less congested. In particular, the front side signal interconnects for ZN do not directly face any of the signal interconnects for the input terminals A1, A2, B1, and B2, thereby reducing their parasitic resistance. In the layout of Figure 19B the gates are oriented vertically, while the active regions (such as channel regions and S / D regions) are oriented horizontally. The gates and active regions are implemented at the front side of the logic cell 300. The logic cell 300 occupies an area that spans 5 gate-to-gate pitches. The front side signal interconnects are implemented using 4 metal traces.

[0073] Figure 19C Another layout implementation of the logic cell 300 according to the present embodiment is shown. In particular, portions of the input terminals A1, A2, B1, B2, the internal network n01, and the output terminal ZN are implemented as signal interconnects at the front side of the logic cell 300, while another portion of the output terminal ZN is implemented as a signal interconnect at the back side of the logic cell 300, such as the signal interconnect 406 shown. Figure 14 Figure 15 In the layout of Figure 19C the gates are oriented vertically, while the active regions (such as channel regions and S / D regions) are oriented horizontally. The gates and active regions are implemented at the front side of the logic cell 300. The logic cell 300 occupies an area that spans 5 gate-to-gate pitches. The front side signal interconnects are implemented using 3 metal traces. Compared to the implementation in Figure 19B Figure 19C the implementation in uses less area of the silicon wafer. However, the parasitic resistance of the output terminal ZN at the front side can be higher than the parasitic resistance in Figure 19B the implementation in.​​​

[0074] While not intended to be limiting, embodiments of the present application provide one or more benefits to semiconductor structures and fabrication. For example, embodiments of the present application provide signal interconnects at the backside of a device and under transistors. Backside signal interconnects can be used to make connections between S / D and another S / D, S / D and gate, and gate and another gate. With backside signal interconnects, the wiring at the frontside of a device becomes less congested and higher circuit density can be achieved. Embodiments of the present application can be easily integrated into existing semiconductor fabrication processes.

[0075] In one exemplary aspect, the present application is directed to a semiconductor structure. The semiconductor structure includes a first transistor having a first source / drain (S / D) component and a first gate; a second transistor having a second S / D component and a second gate; a multilayer interconnect disposed above the first transistor and the second transistor; a signal interconnect located below the first transistor and the second transistor; and a power rail located below the signal interconnect and electrically isolated from the signal interconnect, wherein the signal interconnect electrically connects one of the first S / D component and the first gate to one of the second S / D component and the second gate.

[0076] In one embodiment, the semiconductor structure further includes a first via located below the first transistor and electrically connected to the first S / D component; and a second via located below the second transistor and electrically connected to the second S / D component, wherein the first via and the second via are isolated from the power rail and the signal interconnect directly contacts the first via and the second via. In yet another embodiment, a bottom surface of the signal interconnect is substantially planar and a top surface of the signal interconnect has a stepped profile. In another embodiment, a first sidewall surface of the signal interconnect directly contacts the first via and a second sidewall surface of the signal interconnect directly contacts the second via.

[0077] In an embodiment of the semiconductor structure, the signal interconnect electrically connects the first gate to the second gate. In yet another embodiment, a bottom surface of the signal interconnect is substantially planar and a top surface of the signal interconnect has two protrusions that directly contact the first gate and the second gate.

[0078] In an embodiment, the semiconductor structure further includes a first via located below the first transistor and electrically connected to the first S / D component, wherein the signal interconnect directly contacts the first via and the second gate. In yet another embodiment, a bottom surface of the signal interconnect is substantially planar, a sidewall surface of the signal interconnect directly contacts the first via, and a top surface of the signal interconnect directly contacts the gate.

[0079] In an embodiment of the semiconductor structure, the signal interconnect is part of a standard logic cell and the signal interconnect is routed within a boundary of the standard logic cell. In another embodiment where the first transistor further includes a third S / D component, the semiconductor structure further includes a third via located below the first transistor and electrically connecting the third S / D component to a power rail.

[0080] In another exemplary aspect, the invention is directed to a method, the method including providing a structure having a first transistor and a second transistor located above a substrate and a first isolation structure located between the first transistor and the second transistor, where the first transistor includes a first source / drain (S / D) component and the second transistor includes a second S / D component, the structure further having a first via and a second via connected to the first S / D component and the second S / D component, respectively, and extending to a backside of the structure. The method further includes partially removing the first isolation structure, thereby exposing a first sidewall surface of the first via and a second sidewall surface of the second via, where a first portion of the first isolation structure remains in the structure. The method further includes depositing a metal interconnect on the first portion of the first isolation structure and electrically contacting the first sidewall surface and the second sidewall surface; and forming an isolation component on the metal interconnect, the first via, and the second via.

[0081] In an embodiment, the method further includes etching back the metal interconnect, the first via, and the second via prior to forming the isolation component. In another embodiment, the method further includes forming a power rail on the isolation component.

[0082] In an embodiment of the method, the partial removal of the first isolation structure creates a trench, and the first sidewall surface and the second sidewall surface are portions of sidewalls of the trench. In yet another embodiment, the method further includes depositing a dielectric spacer on surfaces of the trench prior to depositing the metal interconnect, and patterning the dielectric spacer to expose the first sidewall surface and the second sidewall surface, where the metal interconnect is partially deposited on the dielectric spacer. In yet another embodiment, the method further includes partially removing the dielectric spacer prior to forming the isolation component after depositing the metal interconnect.

[0083] In yet another exemplary aspect, the application is directed to a method, the method comprising providing a structure having a first transistor and a second transistor, wherein the first transistor includes a first source / drain (S / D) component and the second transistor includes a second S / D component, the structure further having a multilayer interconnect above a front side of the first and second transistors, a first via disposed on a backside of the first S / D component, a second via disposed on a backside of the second S / D component, and a first isolation component disposed on a backside of the structure and adjacent to the first and second vias. The method further comprises partially removing the first isolation component, thereby forming a trench at the backside of the structure, wherein the trench exposes a first sidewall surface of the first via and a second sidewall surface of the second via. The method further comprises depositing a dielectric spacer on a surface of the trench; patterning the dielectric spacer to expose the first and second sidewall surfaces; depositing one or more metallic materials over the remaining portion of the dielectric spacer and filling the trench; and etching back the one or more metallic materials, the first via, and the second via, wherein a remaining portion of the one or more metallic materials becomes a signal interconnect electrically connecting the first via and the second via.

[0084] In an embodiment, after the etching back, the method further comprises partially removing the remaining portion of the dielectric spacer. In another embodiment, after the etching back, the method further comprises forming a second isolation component on the signal interconnect, the first via, and the second via. In yet another embodiment, the method comprises forming a power rail on the second isolation component and at the backside of the structure.

[0085] The features outlined above briefly summarize a number of embodiments so that those skilled in the art will better understand the aspects of the present application. Those skilled in the art should appreciate that they can readily use the present application as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present application, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present application.

Claims

1. A semiconductor structure, comprising: The first transistor has a first source / drain component and a first gate; The second transistor has a second source / drain component and a second gate; A multilayer interconnect is disposed above the first transistor and the second transistor; A signal interconnect is located below the first transistor and the second transistor; A power rail is located below and electrically isolated from the signal interconnect, wherein the signal interconnect electrically connects one of the first source / drain components and one of the first gate to one of the second source / drain components and one of the second gate; A first via is located below the first transistor and electrically connected to the first source / drain component; and The second via is located below the second transistor and electrically connected to the second source / drain component, wherein the first via and the second via are isolated from the power rail, and the signal interconnect directly contacts the first via and the second via.

2. The semiconductor structure according to claim 1, further comprising: A substrate, with the first transistor and the second transistor located above the substrate.

3. The semiconductor structure according to claim 1, wherein, The bottom surface of the signal interconnect is substantially flat, and the top surface of the signal interconnect has a stepped profile.

4. The semiconductor structure according to claim 1, wherein, The first sidewall surface of the signal interconnect directly contacts the first through hole, and the second sidewall surface of the signal interconnect directly contacts the second through hole.

5. The semiconductor structure according to claim 1, wherein, The signal interconnect connects the first gate to the second gate.

6. The semiconductor structure according to claim 5, wherein, The bottom surface of the signal interconnect is substantially flat, and the top surface of the signal interconnect has two protrusions that directly contact the first gate and the second gate.

7. The semiconductor structure according to claim 1, wherein, The signal interconnect directly contacts the first via and the second gate.

8. The semiconductor structure according to claim 7, wherein, The bottom surface of the signal interconnect is substantially flat, the sidewall surface of the signal interconnect directly contacts the first through hole, and the top surface of the signal interconnect directly contacts the second gate.

9. The semiconductor structure according to claim 1, wherein, The signal interconnects are part of a standard logic cell and are wired within the boundaries of the standard logic cell.

10. The semiconductor structure according to claim 1, wherein, The first transistor further includes a third source / drain component, and also includes: A third via is located below the first transistor and electrically connects the third source / drain component to the power rail.

11. A method for forming a semiconductor structure, comprising: A structure is provided having a first transistor and a second transistor located above a substrate and a first isolation structure located between the first transistor and the second transistor, wherein the first transistor includes a first source / drain component and the second transistor includes a second source / drain component, and the structure further has a first via and a second via respectively connected to the first source / drain component and the second source / drain component and extending to the back side of the structure; The first isolation structure is partially removed, thereby exposing the first sidewall surface of the first through hole and the second sidewall surface of the second through hole, wherein a first portion of the first isolation structure remains in the structure; Depositing metal interconnects that electrically contact the first sidewall surface and the second sidewall surface on the first portion of the first isolation structure; and Isolation components are formed on the metal interconnect, the first through hole, and the second through hole.

12. The method of claim 11, further comprising, before forming the isolation component: The metal interconnects, the first via, and the second via are etched back.

13. The method of claim 11, further comprising: A power rail is formed on the isolation component.

14. The method according to claim 11, wherein, The partial removal of the first isolation structure creates a trench, and the first sidewall surface and the second sidewall surface are parts of the sidewall of the trench.

15. The method of claim 14, further comprising, before depositing the metal interconnect: Dielectric spacers are deposited on the surface of the trench; as well as The dielectric spacer is patterned to expose the first sidewall surface and the second sidewall surface, wherein the metal interconnect is partially deposited on the dielectric spacer.

16. The method of claim 15, further comprising, after depositing the metal interconnect: The dielectric spacer is partially removed before the isolation component is formed.

17. A method for forming a semiconductor structure, comprising: A structure is provided having a first transistor and a second transistor, wherein the first transistor includes a first source / drain component and the second transistor includes a second source / drain component, the structure further having a multilayer interconnect located above the front side of the first transistor and the second transistor, a first via disposed on the back side of the first source / drain component, a second via disposed on the back side of the second source / drain component, and a first isolation component disposed on the back side of the structure and adjacent to the first via and the second via; The first isolation member is partially removed to form a groove on the back side of the structure, wherein the groove exposes the first sidewall surface of the first through hole and the second sidewall surface of the second through hole; Dielectric spacers are deposited on the surface of the trench; The dielectric spacer is patterned to expose the first sidewall surface and the second sidewall surface; One or more metallic materials are deposited over the retained portion of the dielectric spacer and the trench is filled; and The one or more metal materials, the first through-hole, and the second through-hole are etched back, wherein the retained portions of the one or more metal materials become signal interconnects that electrically connect the first through-hole and the second through-hole.

18. The method of claim 17, further comprising: After the back etching, the retained portion of the dielectric spacer is partially removed.

19. The method of claim 17, further comprising: After the back etching, a second isolation component is formed on the signal interconnect, the first via, and the second via.

20. The method of claim 19, further comprising: A power rail is formed on the second isolation component and on the back side of the structure.

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