Method for forming a microelectronic device and related microelectronic device, memory device, and electronic system

Abstract

This application relates to a method of forming a microelectronic device and related microelectronic devices, memory devices, and electronic systems. The method of forming a microelectronic device includes forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent to the conductive shielding structure. A second dielectric structure is formed on the first dielectric structure and horizontally adjacent to the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending parallel in a first horizontal direction. Each of the fin structures includes: two dielectric end structures integral with the remainder of the second dielectric structure; and an additional conductive shielding structure inserted between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend parallel in the first horizontal direction and horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction.

Description

[0001] Priority Statement

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 16 / 999,817, "METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS," filed on August 21, 2020. TECHNICAL FIELD

[0003] In various embodiments, the present disclosure generally relates to the field of microelectronic device design and manufacturing. More specifically, the present disclosure relates to methods of forming microelectronic devices and to related microelectronic devices, memory devices, and electronic systems. BACKGROUND ART

[0004] Microelectronic device designers generally desire to increase the integration or density of features within a microelectronic device by reducing the size of individual features and by reducing the separation distance between adjacent features. In addition, microelectronic device designers generally desire to design architectures that are not only compact but also provide performance advantages, as well as designs that are simplified, easier, and less expensive to manufacture.

[0005] A relatively common microelectronic device is a memory device. A memory device may include a memory array having a plurality of memory cells arranged in a grid pattern. One type of memory cell is a dynamic random access memory (DRAM). In the simplest design configuration, a DRAM cell includes an access device (e.g., a transistor) and a storage device (e.g., a capacitor). Modern applications of memory devices may utilize a large number of DRAM unit cells arranged in arrays of rows and columns. DRAM cells may be electrically accessed via digital lines and word lines arranged along the rows and columns of the array.

[0006] DRAM device manufacturers face significant challenges in reducing the area of DRAM cells to accommodate increased feature density as feature pitch decreases. The number, size, arrangement, and formation methods of different features employed within a DRAM device may undesirably impede the reduction of the DRAM device size, the increase in the storage density of the DRAM device, and / or the reduction of manufacturing costs. For example, the configurations and methods for forming a conventional shielding structure to protect the digital lines of a DRAM device from unwanted electrical interference (e.g., electromagnetic interference, crosstalk) may impede or prevent the desired reduction in the spacing of the digital lines and / or may limit the location of the conductive contact structures (e.g., digital line contacts) of the digital lines due to the risk of short circuits. SUMMARY OF THE INVENTION

[0007] In some embodiments, a method of forming a microelectronic device includes forming a conductive shielding material over each of a conductive shielding structure and a first dielectric structure horizontally adjacent to the conductive shielding structure. A second dielectric structure is formed over the first dielectric structure and horizontally adjacent to the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending parallel to each other in a first horizontal direction. Each of the fin structures includes: two dielectric end structures integral with the remainder of the second dielectric structure; and an additional conductive shielding structure inserted between the two dielectric end structures in the first horizontal direction. First conductive lines are formed to extend parallel to each other in the first horizontal direction and horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction.

[0008] In additional embodiments, a microelectronic device includes a lower conductive shielding structure, a dielectric structure, conductive lines, fin structures, dielectric spacer structures, and an additional dielectric structure. The dielectric structure substantially surrounds an outer horizontal boundary of the lower conductive shielding structure. The conductive lines are disposed over the lower conductive shielding structure and extend parallel to each other in a first horizontal direction. The fin structures are disposed over the lower conductive shielding structure and extend parallel to each other in the first horizontal direction. The fin structures are inserted between the conductive lines in a second horizontal direction orthogonal to the first horizontal direction. Each of the fin structures includes opposing dielectric end structures and an additional conductive shielding structure inserted between the opposing dielectric end structures. The dielectric spacer structures are inserted between each of the fin structures and the lower conductive shielding structure and the conductive lines. The additional dielectric structure is disposed over the dielectric structure and substantially horizontally surrounds the region occupied by the conductive lines, the fin structures, and the dielectric spacer structures.

[0009] In another embodiment, a memory device includes a conductive shielding structure, a first peripheral dielectric structure, a second peripheral dielectric structure, and a memory array region. The conductive shielding structure overlies a substrate structure. The first peripheral dielectric structure overlies the substrate structure and is horizontally adjacent to the conductive shielding structure outwardly. The second peripheral dielectric structure is on the first peripheral dielectric structure. The memory array region is horizontally adjacent to the second peripheral dielectric structure inwardly. The memory array region includes fin structures, digit lines, dielectric spacer structures, access lines, and memory cells. The fin structures overlie the conductive shielding structure and extend in a first horizontal direction. Each of the fin structures includes: two dielectric end structures that protrude from the second peripheral dielectric structure and are integral with the second peripheral dielectric structure; and an additional conductive shielding structure that is horizontally inserted between the two dielectric end structures. The digit lines overlie the conductive shielding structure and extend in the first horizontal direction. The digit lines are alternating with the fin structures in a second horizontal direction perpendicular to the first horizontal direction. The dielectric spacer structures are horizontally inserted between the digit lines and the fin structures, and vertically inserted between the digit lines and the conductive shielding structure. The access lines overlie the digit lines and extend parallel in the second horizontal direction. The memory cells overlie the digit lines and are electrically connected to the digit lines and the access lines.

[0010] In yet other embodiments, an electronic system includes: an input device; an output device; a processor device operably connected to the input device and the output device; and a memory device operably connected to the processor device. The memory device includes a shielding plate, a peripheral dielectric structure, an additional peripheral dielectric structure, fin structures, digit lines, access lines, and memory cells. The shielding plate includes a conductive material. The peripheral dielectric structure horizontally surrounds the shielding plate. The additional peripheral dielectric structure is vertically on the peripheral dielectric structure and has an inner horizontal boundary that is offset outwardly from an inner horizontal boundary of the peripheral dielectric structure. The fin structures vertically overlie the shielding plate and extend parallel in a first horizontal direction. Each of the fin structures includes: two dielectric end structures that horizontally protrude from the additional peripheral dielectric structure; and an additional shielding structure that includes additional conductive material extending from and between the two dielectric end structures. The digit lines are horizontally alternating with the fin structures. An upper surface of the digit lines is substantially coplanar with an upper surface of the fin structures. The access lines vertically overlie the digit lines and extend parallel in a second horizontal direction orthogonal to the first horizontal direction. The memory cells vertically overlie the digit lines and are coupled to the digit lines and the access lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1A to 9B A simplified partial cross-sectional view for illustrating a method of forming a microelectronic device in accordance with an embodiment of the present disclosure ( Figure 1A , 2A , 3A, 4A, 5A, 6A, 7A, 8A, 8C, and 9A), a simplified partial top view (Figure 1B , 2B , 3B, 4B, 5B, 6B, 7B, 8B, and 9B).

[0012] Figure 10 is a functional block diagram of a memory device according to an embodiment of the present disclosure.

[0013] Figure 11 is a schematic block diagram of an electronic system according to an embodiment of the present disclosure. Detailed Description

[0014] The following description provides specific details, such as material compositions, shapes, and sizes, in order to provide a full description of embodiments of the present disclosure. However, those of ordinary skill in the art will understand that embodiments of the present disclosure may be practiced without these specific details. In fact, embodiments of the present disclosure may be practiced in conjunction with conventional microelectronic device manufacturing techniques employed in the industry. Additionally, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices, such as DRAM devices). The structures described below do not form complete microelectronic devices. Only those process actions and structures necessary for understanding embodiments of the present disclosure are described in detail below. Additional actions for forming a complete microelectronic device according to the described structures may be performed by conventional manufacturing techniques.

[0015] The drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Due to, for example, manufacturing techniques and / or tolerances, variations from the shapes depicted in the figures will be expected. Thus, embodiments described herein should not be construed as limited to the specific shapes or regions as illustrated, but rather include, for example, shape deviations caused by manufacturing. For example, regions illustrated or described as box-shaped may have rough and / or non-linear features, and regions illustrated or described as circular may include some rough and / or linear features. Additionally, the illustrated acute angles may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the exact shape of the regions and do not limit the scope of the claims of the present invention. The drawings are not necessarily drawn to scale. Additionally, common elements between the figures may retain the same numerical designations.

[0016] As used herein, "memory device" means and includes a microelectronic device that presents memory functionality but is not necessarily limited to memory functionality. In other words and by way of non-limiting example only, the term "memory device" includes not only conventional memories (e.g., conventional volatile memories such as conventional DRAM; conventional non-volatile memories such as conventional NAND memories), but also application specific integrated circuits (ASICs) (e.g., system-on-chip (SoC)), microelectronic device combinational logic and memory, and graphics processing units (GPUs) incorporating memory.

[0017] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device that contribute in a predetermined manner to the operation of one or more of the structure and the device.

[0018] As used herein, the terms "vertical", "longitudinal", "horizontal", and "lateral" are with respect to the principal plane of a structure and are not necessarily defined by the earth's gravitational field. A "horizontal" or "lateral" direction is a direction that is substantially parallel to the principal plane of the structure, while a "vertical" or "longitudinal" direction is a direction that is substantially perpendicular to the principal plane of the structure. The principal plane of a structure is defined by the surface of the structure that has a relatively larger area compared to the other surfaces of the structure. Referring to the various figures, a "horizontal" or "lateral" direction may be perpendicular to the indicated "Z" axis and may be parallel to the indicated "X" axis and / or parallel to the indicated "Y" axis; and a "vertical" or "longitudinal" direction may be parallel to the indicated "Z" axis, perpendicular to the indicated "X" axis, and perpendicular to the indicated "Y" axis.

[0019] As used herein, features (e.g., regions, structures, devices) described as being "adjacent" to each other mean and include features having the disclosed identification(s) that are positioned closest (e.g., nearest) to each other. Additional features that do not match the disclosed identification(s) of the "adjacent" features (e.g., additional regions, additional structures, additional devices) may be disposed between the "adjacent" features. In other words, "adjacent" features may be positioned directly adjacent to each other such that no other features intervene between the "adjacent" features; or "adjacent" features may be positioned indirectly adjacent to each other such that at least one feature having an identification other than the identification associated with at least one "adjacent" feature is positioned between the "adjacent" features. Thus, features described as being "vertically adjacent" to each other mean and include features having the disclosed identification(s) that are vertically closest (e.g., vertically nearest) to each other. Additionally, features described as being "horizontally adjacent" to each other mean and include features having the disclosed identification(s) that are horizontally closest (e.g., horizontally nearest) to each other.

[0020] As used herein, spatial relative terms, such as "beneath", "below", "lower", "bottom", "above", "upper", "top", "front", "rear", "left", "right", etc., may be used for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Unless otherwise specified, the spatial relative terms are intended to cover different orientations of the material in addition to the orientation depicted in the figures. For example, if the material in the figures is inverted, an element described as "beneath", "below", "under" or "on the bottom" of another element or feature will be oriented "above" or "on the top" of the other element or feature. Thus, the term "beneath" can cover both an upper and a lower orientation depending on the context in which the term is used, which will be apparent to those of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptors used herein may be interpreted accordingly.

[0021] Unless the context clearly dictates otherwise, as used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms.

[0022] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] As used herein, the phrase "coupled to" refers to structures that are operatively connected to each other (e.g., electrically connected by direct Ohmic connection or by an indirect connection (e.g., via another structure)).

[0024] As used herein, the term "substantially" with respect to a given parameter, characteristic or condition means and includes the degree to which the given parameter, characteristic or condition is understood by one of ordinary skill in the art to conform to a variance (e.g., within an acceptable tolerance). By way of example, depending on the particular parameter, characteristic or condition that is substantially met, the parameter, characteristic or condition may be met at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0025] As used herein, "about" or "substantially" with respect to a value of a particular parameter encompasses that value and a degree of variance from that value that will be understood by one of ordinary skill in the art within the acceptable tolerance of the particular parameter. For example, "about" or "substantially" with respect to a value may encompass additional values that are within the range of 90.0% to 110.0% of that value, such as within the range of 95.0% to 105.0% of that value, within the range of 97.5% to 102.5% of that value, within the range of 99.0% to 101.0% of that value, within the range of 99.5% to 100.5% of that value, or within the range of 99.9% to 100.1% of that value.

[0026] As used herein, "conductive material" means and includes conductive materials such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe- and Ni-based alloys, Co- and Ni-based alloys, Fe- and Co-based alloys, Co- and Ni- and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steels, low-carbon steels, stainless steels); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon-germanium (SiGe)). In addition, "conductive structure" means and includes a structure formed of and including a conductive material.

[0027] As used herein, "insulating material" means and includes electrical insulating materials such as one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x ), zirconium oxide (ZrO x ), tantalum oxide (TaO x ), and magnesium oxide (MgO x )) of one or more); at least one dielectric nitride material (e.g., silicon nitride (SiNy )); at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )); at least one dielectric oxycarbide material (e.g., silicon oxycarbide (SiO x C y )); at least one hydrogenated dielectric oxycarbide material (e.g., hydrogenated silicon oxycarbide (SiC x O y H z )); and at least one dielectric oxynitride carbide material (e.g., silicon oxynitride carbide (SiO x C z N y )); Chemical formulas containing one or more of "x", "y", and "z" herein (e.g., SiO x , AlO x , HfO x , NbO x , TiO x , SiN y , SiO x N y , SiO x C y , SiC x O y H z , SiO x C z N y ) represent materials having an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) for each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Since chemical formulas represent relative atomic ratios and an inexact chemical structure, the insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values of "x", "y", and "z" (if present) may be integers or may be non-integers. As used herein, the term "non-stoichiometric compound" means and includes a compound having a composition of an element that cannot be represented by a ratio of well-defined natural numbers and that violates the law of definite proportions. In addition, "insulating structure" means and includes a structure formed of and containing an insulating material.

[0028] Unless otherwise indicated by the context, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique for depositing or growing the material can be selected by one of ordinary skill in the art. Additionally, unless otherwise indicated by the context, the removal of materials described herein can be achieved by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor etching), ion milling, planarization by grinding (e.g., chemical mechanical planarization (CMP)), or other known methods.

[0029] Figures 1A to 9B A simplified partial cross-sectional view ([ Figure 1A , 2A , 3A, 4A, 5A, 6A, 7A, 8A, 8C, and 9A) and a simplified partial top view ([ Figure 1B , 2B , 3B, 4B, 5B, 6B, 7B, 8B, and 9B) for illustrating embodiments of a method of forming a microelectronic device structure (e.g., a memory structure) for a microelectronic device (e.g., a memory device, such as a DRAM device). In conjunction with the description provided below, it will be apparent to one of ordinary skill in the art that the methods described herein can be used to form various devices. In other words, the methods of the present disclosure can be used whenever it is desired to form a microelectronic device.

[0030] Referring simultaneously to Figure 1A and Figure 1B (which depict Figure 1AA simplified partial top view of the microelectronic device structure 100 shown in [reference], the microelectronic device structure 100 can be formed to include: a substrate structure 102; a control logic region 104, which is on, above, and / or within the substrate structure 102; a lower shielding structure 106, which is on or above a part of the control logic region 104 that is within the horizontal boundaries (e.g., in the X and Y directions) of the memory array region 103 of the microelectronic device structure 100; a peripheral dielectric structure 108, which is on or above another part of the control logic region 104 that is at least partially outside the horizontal boundaries of the memory array region 103 and is horizontally adjacent to the lower shielding structure 106 outwardly (e.g., in the X and Y directions); a shielding material 112, which is on or above the lower shielding structure 106 and the peripheral dielectric structure 108; an optional etch stop structure 110, which is vertically inserted between the shielding material 112 and each of the lower shielding structure 106 and the peripheral dielectric structure 108; a capping material 114, which is on or above the shielding material 112; and an array masking structure 116, which is on or above a part of the capping material 114. The foregoing features of the microelectronic device structure 100 and Figure 1A and 1B additional features (e.g., additional structures, additional materials, additional regions) of the microelectronic device structure 100 at the processing stages depicted in [reference] are described in further detail below.

[0031] The substrate structure 102 includes a substrate material or construction on which additional features (e.g., materials, structures, devices) of the microelectronic device structure 100 are formed. The substrate structure 102 can include a semiconductor structure (e.g., a semiconductor wafer) on a support structure or a substrate semiconductor material. In some embodiments, the substrate structure 102 includes a semiconductor wafer. For example, the substrate structure 102 can be formed of and include one or more of the following: silicon materials such as single-crystalline silicon and / or polycrystalline silicon (also referred to herein as "polysilicon"); silicon germanium; germanium; gallium arsenide; gallium nitride; gallium phosphide; indium phosphide; indium gallium nitride; and aluminum gallium nitride. In some embodiments, the substrate structure 102 is formed of single-crystalline silicon and includes single-crystalline silicon. The semiconductor substrate structure can include, for example, a single-crystalline silicon wafer. The substrate structure 102 can include one or more layers, structures, and / or regions formed therein and / or thereon.

[0032] The control logic region 104 may include various transistors and conductive wiring structures (e.g., wire conductor structures, conductive contact structures) that together form control logic circuitry for various control logic devices of the microelectronic device structure 100. In some embodiments, the control logic devices of the control logic region 104 include complementary metal oxide semiconductor (CMOS) circuits. The control logic devices of the control logic region 104 may be configured to control various operations of additional features (e.g., memory cell arrays) subsequently formed within the memory array region 103 of the microelectronic device structure 100, as described in further detail below. As a non-limiting example, the control logic devices of the control logic region 104 may include charge pumps (e.g., V CCP charge pump, V NEGWL charge pump, DVC2 charge pump), delay locked loop (DLL) circuits (e.g., ring oscillators), V dd regulators, string drivers, page buffers, and one or more (e.g., each) of various chip / stack control circuits. As another non-limiting example, the control logic devices of the control logic region 104 may include devices configured to control column operations of arrays (e.g., storage node structure arrays, access device arrays) to be formed within the memory array region 103 of the microelectronic device structure 100, such as decoders (e.g., local stack decoders, column decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSAs), PMOS sense amplifiers (PSAs)), repair circuits (e.g., column repair circuits), I / O devices (e.g., local I / O devices), memory test devices, array multiplexers (MUXs), and error checking and correction (ECC) devices. As another non-limiting example, the control logic devices of the control logic region 104 may include devices configured to control row operations of arrays (e.g., storage node structure arrays, access device arrays) to be formed within the memory array region 103 of the microelectronic device structure 100, such as decoders (e.g., local stack decoders, row decoders), drivers (e.g., access line drivers, word line (WL) drivers), repair circuits (e.g., row repair circuits), memory test devices, MUXs, ECC devices, and self-refresh / wear leveling devices. Portions of the control logic devices of the control logic region 104 (e.g., portions of transistors, such as source regions, drain regions, and channel regions of transistors) may extend at least partially into the substrate structure 102.

[0033] The lower shielding structure 106 (e.g., lower shielding plate, bottom shielding plate) can be configured and positioned to shield (e.g., protect) features (e.g., structures, materials, devices) to be formed within the memory array region 103 of the microelectronic device structure 100 from unwanted electrical interference (e.g., electromagnetic interference (EMI)). The lower shielding structure 106 can be formed of and include a conductive material. In some embodiments, the lower shielding structure 106 is formed of and includes a metallic material, such as one or more of at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). By way of non-limiting example, the lower shielding structure 106 can be formed of and include tungsten (W). The lower shielding structure 106 can be substantially uniform, or the lower shielding structure 106 can be non-uniform. As used herein, the term "uniform" means that the relative amounts of the elements contained within a feature (e.g., material, structure) do not vary throughout the different portions (e.g., different horizontal portions, different vertical portions) of the feature. Conversely, as used herein, the term "non-uniform" means that the relative amounts of the elements contained within a feature (e.g., material, structure) vary throughout the different portions of the feature. If the lower shielding structure 106 is non-uniform, then the amount of one or more of the elements contained within the lower shielding structure 106 can vary stepwise (e.g., change abruptly), or can vary continuously (e.g., change gradually, such as linearly, parabolically) throughout the different portions of the lower shielding structure 106. The lower shielding structure 106 can be formed of and include, for example, a stack of at least two different conductive materials.

[0034] The peripheral dielectric structure 108 can be horizontally positioned adjacent (e.g., close to, near, directly adjacent) to the outer horizontal boundary (e.g., peripheral horizontal boundary) of the substrate structure 102. The peripheral dielectric structure 108 can horizontally surround the lower shielding structure 106. The peripheral dielectric structure 108 can also horizontally surround the memory array region 103 of the microelectronic device structure 100. As Figure 1A and 1B shown, a portion (e.g., horizontal inner portion) of the peripheral dielectric structure 108 can horizontally extend into the memory array region 103 of the microelectronic device structure 100. The peripheral dielectric structure 108 can be positioned directly horizontally adjacent to the lower shielding structure 106. Additionally, the upper vertical boundary (e.g., upper surface) of the peripheral dielectric structure 108 can be substantially coplanar with the upper vertical boundary (e.g., upper surface) of the lower shielding structure 106.

[0035] The peripheral dielectric structure 108 can be formed of and include at least one dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiOx , phosphorus silicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x , TiO x , ZrO x , TaO x and MgO x ), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), at least one dielectric oxycarbide material (e.g., SiO x C y ), at least one hydrogenated dielectric oxycarbide material (e.g., SiC x O y H z ), and at least one dielectric carbon oxynitride material (e.g., SiO x C z N y ). In some embodiments, the peripheral dielectric structure 108 is formed of at least one dielectric oxide material (e.g., SiO x , such as silicon dioxide (SiO2)) and includes the at least one dielectric oxide material. The peripheral dielectric structure 108 may be substantially uniform, or the peripheral dielectric structure 108 may be non-uniform. If the peripheral dielectric structure 108 is non-uniform, then the amount of one or more elements included in the peripheral dielectric structure 108 may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change gradually, such as linearly, parabolically) throughout different portions of the peripheral dielectric structure 108. The peripheral dielectric structure 108 may be formed, for example, of a stack of at least two different dielectric materials and includes a stack of at least two different dielectric materials.

[0036] The shielding material 112 may overlie (e.g., in the Z direction) the lower shielding structure 106 and the upper vertical boundary (e.g., upper surface) of the peripheral dielectric structure 108. The shielding material 112 may be used to form a shielding structure for a subsequently formed fin structure, as described in further detail below. The shielding material 112 may be formed to extend substantially continuously horizontally over the lower shielding structure 106 and the peripheral dielectric structure 108. The upper vertical boundary and the lower vertical boundary of the shielding material 112 may each be substantially planar individually.

[0037] The shielding material 112 may be formed of and include a conductive material. In some embodiments, the lower shielding structure 106 is formed of and includes a metal material, such as one or more of at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). The material composition of the shielding material 112 may be substantially the same as the material composition of the lower shielding structure 106, or the material composition of the shielding material 112 may be different from the material composition of the lower shielding structure 106. In some embodiments, the shielding material 112 is formed of and includes W. The shielding material 112 may be substantially uniform, or the shielding material 112 may be non-uniform. If the shielding material 112 is non-uniform, then the amount of one or more elements included in the shielding material 112 may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change gradually, such as linearly, parabolically) across different portions of the shielding material 112. The shielding material 112 may be formed of and include a stack of at least two different conductive materials, for example.

[0038] Optionally, the etch stop structure 110 may be formed vertically above the lower shielding structure 106 and the peripheral dielectric structure 108 and vertically below the shielding material 112. The etch stop structure 110 may be used, for example, to mitigate over-etching into the lower shielding structure 106 and the peripheral dielectric structure 108 during subsequent patterning of the shielding material 112, as described in further detail below. If formed, the etch stop structure 110 may extend horizontally continuously substantially over the lower shielding structure 106 and the peripheral dielectric structure 108. Additionally, the upper vertical boundary and the lower vertical boundary of the etch stop structure 110 (if formed) may each be substantially planar individually.

[0039] If formed, the etch stop structure 110 may include a conductive material. In some embodiments, the lower shielding structure 106 is formed of and includes a metal material, such as one or more of at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). The material composition of the etch stop structure 110 may be different from the material composition of the shielding material 112 and the lower shielding structure 106. In some embodiments, the etch stop structure 110 is formed of and includes a conductive metal nitride, such as titanium nitride (TiN x ) and tungsten nitride (WN x) one or more of those in. The etch stop structure 110 may be substantially uniform, or the lower shielding structure 106 may be non-uniform. If the etch stop structure 110 is formed and non-uniform, the amount of one or more elements included in the etch stop structure 110 may change stepwise (e.g., change suddenly), or may change continuously (e.g., change gradually, such as linearly, parabolically) in different parts of the etch stop structure 110. The etch stop structure 110 may be formed, for example, by a stack of at least two different conductive materials and include a stack of at least two different conductive materials.

[0040] The capping material 114 may vertically overlie the upper vertical boundary (e.g., upper surface) of the shielding material 112. The capping material 114 may be used to subsequently form a capping structure for a subsequently formed fin structure, as described in further detail below. The capping material 114 may be formed to extend substantially continuously horizontally over the shielding material 112. The upper vertical boundary and the lower vertical boundary of the capping material 114 may each be substantially planar individually.

[0041] The capping material 114 may be formed of an insulating material and include an insulating material. By way of non-limiting example, the capping material 114 may be formed of and include one or more of the following: at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x , TiO x , ZrO x , TaO x and MgO x one or more of those), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), at least one dielectric oxycarbide material (e.g., SiO x C y ), at least one hydrogenated dielectric oxycarbide material (e.g., SiC x O y H z ), and at least one dielectric carbon oxynitride material (e.g., SiO x C z N y ). In some embodiments, the capping material 114 is formed of at least one dielectric nitride material (e.g., SiN y, for example, Si3N4) and includes the at least one dielectric nitride material. The capping material 114 can be substantially uniform, or the capping material 114 can be non-uniform. If the capping material 114 is non-uniform, the amount of one or more elements included in the peripheral dielectric structure 108 can vary stepwise (e.g., change abruptly), or can vary continuously (e.g., change gradually, such as linearly, parabolically) throughout different portions of the capping material 114. The capping material 114 can be formed, for example, by a stack of at least two different dielectric materials and includes a stack of at least two different dielectric materials.

[0042] The array masking structure 116 can cover a portion of the capping material 114 within the horizontal boundaries (e.g., in the X and Y directions) of the memory array region 103 of the microelectronic device structure 100. The array masking structure 116 can also extend horizontally into an additional portion of the capping material 114 outside the horizontal boundaries of the memory array region 103 (e.g., the portion of the capping material 114 within the horizontal boundaries of the peripheral dielectric structure 108), but only partially cover the additional portion. As Figure 1A shown, other portions of the capping material 114 can remain exposed (e.g., uncovered) under the openings 118 (e.g., trenches), which are positioned horizontally adjacent to the horizontal boundaries (e.g., in the X and Y directions) of the array masking structure 116. The horizontal dimensions (e.g., in the X and Y directions) of the openings 118 (and thus, the exposed portion of the capping material 114) can correspond to the required horizontal dimensions of one or more additional structures (e.g., additional peripheral dielectric structures) that are subsequently formed to extend vertically through at least the capping material 114 and the shielding material 112, as described in further detail below.

[0043] The array masking structure 116 can act as a mask that is used to protect portions of the capping material 114 and the shielding material 112 that are vertically beneath the array masking structure 116 and within the horizontal boundaries of the array masking structure 116 from removal during subsequent processing, as described in further detail below. The array masking structure 116 can include, for example, one or more of a hard mask structure and a photoresist structure. By way of non-limiting example, the array masking structure 116 can be formed by one or more of (e.g., a stack) and include one or more of: amorphous carbon (e.g., spin-on carbon (SOC)), silicon (e.g., polysilicon), dielectric materials (e.g., one or more of dielectric oxide materials, dielectric nitride materials, dielectric oxycarbide materials, hydrogenated dielectric oxycarbide materials, and dielectric carbon oxynitride materials), and photoresist materials (e.g., positive photoresist materials, negative tone photoresist materials).

[0044] Next, with reference to Figure 2A and Figure 2B (which depictsFigure 2A A simplified partial top view of the microelectronic device structure 100 at the processing stage shown in Figure 1A and 1B ), the microelectronic device structure 100 may undergo at least one material removal process to remove at least the portions of the capping material 114 and the shielding material 112 that are not protected by the array shielding structure 116 ( Figure 2A as shown in Figure 1A and 1B ), and form a groove 120 that extends completely vertically (e.g., in the Z direction) through the capping material 114 and the shielding material 112. As Figure 2A and 2B shown in Figure 1A and 1B ), in an embodiment where the etch stop structure 110 is formed, the material removal process may also remove the portions of the etch stop structure 110 that are not protected by the array shielding structure 116 (

[0045] While referring to Figure 3A and Figure 3B which depict Figure 3A a simplified partial top view of the microelectronic device structure 100 at the processing stage shown in Figure 2A ), an additional peripheral dielectric structure 122 may be formed within the groove 120 that extends vertically through at least the capping material 114 and the shielding material 112 ( Figure 2A ). The additional peripheral dielectric structure 122 may be substantially confined within the boundaries (e.g., horizontal boundaries, vertical boundaries) of the groove 120 ( Figure 2A ), and may substantially fill the groove 120 ( Figure 3AAs shown, the additional peripheral dielectric structure 122 may physically contact the upper surface of the peripheral dielectric structure 108. The additional peripheral dielectric structure 122 may also physically contact the side surfaces of the remaining portions of the capping material 114 and the shielding material 112. In embodiments where the etch stop structure 110 is formed, the additional peripheral dielectric structure 122 may also physically contact the side surfaces of the remaining portions of the etch stop structure 110. The upper boundary (e.g., upper surface) of the additional peripheral dielectric structure 122 may be formed to be substantially coplanar with the upper boundary (e.g., upper surface) of the remaining portion of the capping material 114.

[0046] The additional peripheral dielectric structure 122 may be formed of and include at least one dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x , TiO x , ZrO x , TaO x , and MgO x ), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), at least one dielectric oxycarbide material (e.g., SiO x C y ), at least one hydrogenated dielectric oxycarbide material (e.g., SiC x O y H z ), and at least one dielectric carbon oxynitride material (e.g., SiO x C z N y ). The material composition of the additional peripheral dielectric structure 122 may be substantially the same as the material composition of the peripheral dielectric structure 108, or the material composition of the additional peripheral dielectric structure 122 may be different from the material composition of the peripheral dielectric structure 108. In some embodiments, the additional peripheral dielectric structure 122 is formed of at least one dielectric oxide material (e.g., SiO x, e.g., SiO2) and includes the at least one dielectric oxide material. The additional peripheral dielectric structure 122 may be substantially uniform, or the additional peripheral dielectric structure 122 may be non-uniform. If the additional peripheral dielectric structure 122 is non-uniform, the amount of one or more elements included in the additional peripheral dielectric structure 122 may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change gradually, such as linearly, parabolically) throughout different portions of the additional peripheral dielectric structure 122. The additional peripheral dielectric structure 122 may be formed, for example, of a stack of at least two different dielectric materials and includes a stack of at least two different dielectric materials.

[0047] Next, with reference simultaneously to Figure 4A and Figure 4B (which depicts Figure 4A a simplified partial top view of the microelectronic device structure 100 at the processing stage shown in Figure 4A ), an additional masking structure 124 may be formed on or above the additional peripheral dielectric structure 122 and the capping material 114; a spacer structure 132 may be formed on or above a portion of the additional masking structure 124 that is within the horizontal boundaries of the memory array region 103; and a peripheral masking structure 130 may be formed on or above an additional portion of the additional masking structure 124 that is outside the horizontal boundaries of the memory array region 103. As shown in Figure 4A , trenches 133 (e.g., openings, apertures) may be formed horizontally between horizontally adjacent spacer structures 132 (e.g., in the X direction) and separate the horizontally adjacent spacer structures 132.

[0048] As described in further detail below, an additional masking structure 124 can be used to transfer a pattern formed by a spacer structure 132 and a peripheral masking structure 130 into a capping material 114, a shielding material 112, and an additional peripheral dielectric structure 122 to form a fin structure. The additional masking structure 124 can be formed of and include at least one material that facilitates the aforementioned transfer of the pattern formed by the spacer structure 132 and the peripheral masking structure 130 and that can be easily removed relative to the capping material 114, the shielding material 112, and the additional peripheral dielectric structure 122. By way of non-limiting example, the additional masking structure 124 can be formed of and include one or more of the following: amorphous carbon, silicon (e.g., polysilicon), dielectric materials (e.g., one or more of a dielectric oxide material, a dielectric nitride material, a dielectric oxycarbide material, a hydrogenated dielectric oxycarbide material, and a dielectric carbon oxynitride material), and photoresist materials (e.g., a positive photoresist material, a negative tone photoresist material). The additional masking structure 124 can be substantially uniform, or the additional masking structure 124 can be non-uniform. If the additional masking structure 124 is non-uniform, then the amount of one or more elements included in the additional masking structure 124 can vary stepwise (e.g., change abruptly), or can vary continuously (e.g., change gradually, e.g., linearly, parabolically) throughout different portions of the additional masking structure 124. The additional masking structure 124 can, for example, be formed of and include a stack of at least two different materials.

[0049] As Figure 4A shown, in some embodiments, the additional masking structure 124 includes a stack structure that includes a first masking material 126 and a second masking material 128 on or above the first masking material 126. The first masking material 126 can, for example, include amorphous carbon (e.g., SOC); and the second masking material 128 can, for example, include at least one different material, such as one or more of silicon (e.g., polysilicon) and dielectric materials (e.g., one or more of a dielectric oxide material, a dielectric nitride material, a dielectric oxycarbide material, a hydrogenated dielectric oxycarbide material, and a dielectric carbon oxynitride material).

[0050] The spacer structure 132 can be formed to have horizontal dimensions (e.g., in the X direction and in the Y direction) and a horizontal pitch (e.g., in the X direction) corresponding to (e.g., substantially the same as) the desired horizontal dimensions and horizontal pitch of the fin structure to be formed from the capping material 114, the shielding material 112, and the additional peripheral dielectric structure 122 by subsequent processing actions, as described in further detail below. The spacer structure 132 can be formed to have a horizontally elongated shape extending parallel in the Y direction and be separated from one or more other horizontally adjacent spacer structures 132 (e.g., spaced apart) by a distance D1 in the X direction. The trench 133 can extend completely vertically in the Z direction through the spacer structure 132 to expose a portion of the upper surface of the additional shielding structure 124. The spacer structure 132 can be positioned horizontally outside the horizontal boundaries of the additional peripheral dielectric structure 122 in the X direction and can extend horizontally into the horizontal boundaries of the additional peripheral dielectric structure 122 in the Y direction.

[0051] As Figure 4A shown, the spacer structure 132 can individually exhibit a width W1 in the X direction and can be separated (e.g., spaced apart) from one or more other horizontally adjacent spacer structures 132 by a distance D1 in the X direction. In some embodiments, the width W1 of an individual spacer structure 132 ranges from about 6 nanometers (nm) to about 10 nm; and the distance D1 between horizontally adjacent spacer structures 132 (and thus, the width of an individual trench 133 in the X direction) ranges from about 30 nm to about 50 nm. The spacer structures 132 can each be formed to have a width W1 and a distance D1 that are substantially the same as those of other horizontally adjacent spacer structures 132; or at least one of the spacer structures 132 can be formed to have a width W1 and / or a distance D1 that are different from those of at least one other of the spacer structures 132 compared to other horizontally adjacent spacer structures 132.

[0052] Still referring simultaneously to Figure 4A and Figure 4B , in the Y direction, a portion (e.g., the central portion) of each individual spacer structure 132 can be located within the horizontal boundaries ( Figure 4A ) of the shielding material 112 ( Figure 4B ) under the additional shielding structure 124, as depicted by the dashed lines in Figure 4A . In addition, other portions (e.g., the opposite end portions) of each individual spacer structure 132 can extend beyond the horizontal boundaries of the shielding material 112 ( Figure 4A ) and into the horizontal boundaries in the Y direction of the additional peripheral dielectric structure 122 ( Figure 4B ), also depicted by the dashed lines in Figure 4B . As Figure 4B shown, the other portions of each individual spacer structure 132 can extend horizontally into the horizontal boundaries in the Y direction of the peripheral shielding structure 130.

[0053] The peripheral shielding structure 130 can be configured and positioned to protect portions of the additional shielding structure 124 and the spacer structure 132 from being removed during subsequent processing operations to form fin structures, as described in further detail below. As Figure 4B shown, in the Y direction, the peripheral shielding structure 130 can only partially (e.g., not completely) cover the additional peripheral dielectric structure 122. For example, portions of the additional peripheral dielectric structure 122 that are close to the shielding material 112 in the Y direction can remain uncovered by the peripheral shielding structure 130, while other portions of the additional peripheral dielectric structure 122 that are relatively further away from the shielding material 112 in the Y direction can be covered by the peripheral shielding structure 130. Additionally, other portions of the additional peripheral dielectric structure 122 that are adjacent to the shielding material 112 in the X direction can be substantially covered by the peripheral shielding structure 130.

[0054] The peripheral shielding structure 130 can be formed of and include at least one material that facilitates the desired patterning of the additional shielding structure 124 using the spacer structure 132 and the peripheral shielding structure 130 (and thus, the desired patterning of the shielding material 112, the capping material 114, and the additional peripheral dielectric structure 122). By way of non-limiting example, the peripheral shielding structure 130 can be formed of and include a photoresist material (e.g., a positive photoresist material, a negative tone photoresist material). The peripheral shielding structure 130 can be substantially uniform, or the peripheral shielding structure 130 can be non-uniform. If the peripheral shielding structure 130 is non-uniform, the amount of one or more elements included in the peripheral shielding structure 130 can vary stepwise (e.g., change abruptly), or can vary continuously (e.g., change gradually, such as linearly, parabolically) throughout different portions of the peripheral shielding structure 130. The peripheral shielding structure 130 can be formed of and include a stack of at least two different materials (e.g., at least two different photoresist materials), for example.

[0055] Next, with reference to both Figure 5A and Figure 5B (which depict a simplified partial top view of the microelectronic device structure 100 at the processing stage shown in Figure 4A ), a pattern defined by regions of the microelectronic device structure 100 that are protected by at least one of the peripheral shielding structure 130 ( Figure 4A and 4B ) and the spacer structure 132 ( Figure 4A and 4B ) can be transferred into portions of the shielding material 112, the capping material 114, and the additional peripheral dielectric structure 122 to form fin structures 134 that are separated from each other by additional trenches 136. As Figure 4BAs shown, each individual fin structure 134 includes a central region 134A and (e.g., in the Y direction) relatively end regions 134B that are horizontally adjacent to the central region 134A. The central region 134A of each fin structure 134 can be horizontally inserted (e.g., in the Y direction) between the relatively end regions 134B of the fin structure 134. The central region 134A of the fin structure 134 can include: an additional shielding structure 138 ( Figure 5A ), which is formed of a shielding material 112 ( Figure 4A ); and a capping structure 140 ( Figure 5A and 5B ), which overlies the additional shielding structure 138 and is formed of a capping material 114 ( Figure 4A ). The relatively end regions 134B of the fin structure 134 can include a dielectric end structure 137 ( Figure 5B ), which includes the remaining (e.g., uncovered) portion of the additional peripheral dielectric structure 122, and the remaining portion horizontally protrudes (e.g., in the Y direction) from the other remaining portions of the additional peripheral dielectric structure 122 and is integral with the other remaining portions. The dielectric end structure 137 of an individual fin structure 134 can be positioned to be directly horizontally adjacent to (e.g., in the Y direction) the additional shielding structure 138 and the capping structure 140 of the fin structure 134.

[0056] The additional shielding structure 138 of the fin structure 134 can be used to protect (e.g., shield) conductive lines (e.g., digital lines, bit lines, data line structures) sequentially formed in the additional trenches 136 from electrical interference (e.g., crosstalk, other generated noise) from each other and / or other features (e.g., structures, materials, devices) of the microelectronic device structure 100. The additional shielding structure 138 can be formed to have a horizontally elongated shape that extends parallel in the Y direction and can be separated from each other in the X direction by the additional trenches 136. As Figure 5A shown, the additional shielding structure 138 can individually exhibit a width W1 in the X direction that is substantially the same as that of the spacer structure 132 ( Figure 4A ); and can be separated (e.g., spaced apart) in the X direction from one or more other horizontal additional shielding structures 138 by a distance D1 that is substantially the same as that of the spacer structure 132 ( Figure 4A ) that separates them. In addition, the additional shielding structure 138 can individually exhibit a length in the Y direction that is less than the length of the spacer structure 132 ( Figure 4A ) used to form the additional shielding structure 138.

[0057] The capping structure 140 of the fin structure 134 can act as an insulating capping structure for the additional shielding structure 138 of the fin structure 134. The capping structure 140 can be formed to have a horizontally elongated shape that extends parallel in the Y direction and can be separated from each other in the X direction by the additional trenches 136. AsFigure 5A As shown, the capping structure 140 can individually exhibit a width W1 in the X direction that is substantially the same as that of the spacer structure 132 ( Figure 4A ), and can be separated (e.g., spaced apart) from one or more other horizontally adjacent capping structures 140 in the X direction by a distance D1 that is substantially the same as that of the spacer structure 132 ( Figure 4A ) that separates them. Additionally, the capping structure 140 can individually exhibit a length in the Y direction that is less than the length of the spacer structure 132 ( Figure 4A ) used to form the capping structure 140.

[0058] The dielectric end structure 137 of the fin structure 134 can reduce the risk of short circuits that might otherwise be associated with extending an additional shielding structure 138 of the fin structure 134 into the opposite end region 134B of the fin structure 134. For example, compared to a configuration where the additional shielding structure 138 of the fin structure 134 extends horizontally into the opposite end region 134B of the fin structure 134, the dielectric end structure 137 of the fin structure 134 can permit a subsequently formed conductive contact (e.g., a digital line contact) to extend (e.g., vertically in the Z direction) into a portion of a subsequently formed conductive line structure (e.g., a digital line) that is horizontally close to the opposite end region 134B of the fin structure 134, and reduce the risk of the conductive contact shorting out the additional shielding structure 138 of a horizontally adjacent fin structure 134. Even if the subsequently formed conductive contact horizontally overlaps (e.g., in the X direction) the opposite end region 134B of a horizontally adjacent fin structure 134, since the dielectric end structure 137 occupies the opposite end region 134B (compared to the additional shielding structure 138), the subsequently formed conductive contact will not effect a short circuit between the additional shielding structures 138 of horizontally adjacent fin structures 134. The dielectric end structure 137 of the fin structure 134 can individually exhibit a width W1 in the X direction that is substantially the same as that of the spacer structure 132 ( Figure 4A ), and can be separated (e.g., spaced apart) from one or more other horizontally adjacent dielectric end structures 137 in the X direction by a distance D1 that is substantially the same as that of the spacer structure 132 ( Figure 4A ) that separates them.

[0059] Next, referring simultaneously to Figure 6A and Figure 6B (which depict a simplified partial top view of the microelectronic device structure 100 at the processing stage shown in Figure 6A ), the dielectric spacer material 142 can be formed on or above the surface of the microelectronic device structure 100 both inside and outside the boundaries (e.g., horizontal boundaries, vertical boundaries) of the additional trench 136. In Figure 6BIn [reference], the horizontal boundaries of some features (e.g., fin structures 134, additional peripheral dielectric structures 122) of the microelectronic device structure 100 that are vertically below the dielectric spacer material 142 are depicted by dashed lines. As Figure 6A shown, the dielectric spacer material 142 can be formed to extend (e.g., continuously) over the exposed surfaces (e.g., exposed upper surfaces, exposed side surfaces) of the fin structures 134, including their dielectric end structures 137 ( Figure 6B ), additional shielding structures 138, and exposed surfaces of the capping structures 140, the exposed surfaces of the additional peripheral dielectric structures 122, and the exposed surfaces of the etch stop structures 110 (if present, or if the etch stop structures 110 are absent, then the exposed surfaces of the peripheral dielectric structures 108 and the lower shielding structures 106). The dielectric spacer material 142 can be formed to partially (e.g., not completely) fill the additional trenches 136. Additionally, as Figure 6A shown, the dielectric spacer material 142 can also be formed to substantially fill other trenches (if present) that are horizontally inserted (e.g., in the X direction) between the additional peripheral dielectric structures 122 and the fin structures 134 that are most horizontally proximate (e.g., in the X direction) to them. In additional embodiments, for example, in embodiments where some of the fin structures 134 are formed to be directly horizontally adjacent (e.g., in the X direction) to the additional peripheral dielectric structures 122, the dielectric spacer material 142 does not horizontally intervene between the additional peripheral dielectric structures 122 and the fin structures 134 that are most horizontally proximate (e.g., in the X direction) to them.

[0060] As Figure 6AAs depicted, the dielectric spacer material 142 can be formed to have a variable (e.g., non-constant, changing) thickness above different surfaces (e.g., side surfaces, upper surfaces) of the microelectronic device structure 100. For example, the portion of the dielectric spacer material 142 that forms the lower vertical boundary (e.g., bottom surface, bottom) of the additional trench 136 on or above the surface (e.g., upper surface) of the microelectronic device structure 100 can be formed to be relatively thicker than other portions of the dielectric spacer material 142 that form the horizontal boundary (e.g., side surfaces) of the additional trench 136 on or above other surfaces (e.g., side surfaces) of the microelectronic device structure 100. In some embodiments, the height H1 (e.g., vertical thickness) of the portion of the dielectric spacer material 142 formed on the surface defining the lower vertical boundary of the additional trench 136 is about 2 times (2×) to about 3 times (3×) (e.g., about 2.25 times (2.25×) to about 2.5 times (2.5×), about 2.5×) the width W2 (e.g., horizontal thickness) of the other portions of the dielectric spacer material 142 formed on the other surfaces defining the horizontal boundary of the additional trench 136. By way of non-limiting example, the height H1 of the foregoing portion of the dielectric spacer material 142 can be in the range of about 24 nm to about 30 nm, and the width W2 of the foregoing other portions of the dielectric spacer material 142 can be in the range of about 10 nm to about 12 nm.

[0061] The dielectric spacer material 142 can be formed of and include at least one dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x , TiO x , ZrO x , TaO x and MgO x ), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), at least one dielectric oxycarbide material (e.g., SiO x C y ), at least one hydrogenated dielectric oxycarbide material (e.g., SiC x O y H z ), and at least one dielectric carbon oxynitride material (e.g., SiO x C z N y)。In some embodiments, the dielectric spacer material 142 is formed of and comprises at least one low-k dielectric material, such as SiO x C y 、SiO x N y 、SiC x O y H z and SiO x C z N y or more of these. The dielectric spacer material 142 can be substantially uniform, or the dielectric spacer material 142 can be non-uniform. If the dielectric spacer material 142 is non-uniform, the amount of one or more elements included in the dielectric spacer material 142 can vary stepwise (e.g., change abruptly), or can vary continuously (e.g., change gradually, such as linearly, parabolically) across different portions of the dielectric spacer material 142. The dielectric spacer material 142 can be formed, for example, of and comprise a stack of at least two different dielectric materials.

[0062] To facilitate a variable thickness of the dielectric spacer material 142, one or more deposition inhibition actions can be employed during the formation of the dielectric spacer material 142. By way of non-limiting example, the upper portion of the side surface of the fin structure 134 can be treated with a plasma that includes one or more inhibitor materials (e.g., fluorine) that impede the deposition of the dielectric spacer material 142 on the upper portion of the side surface of the fin structure 134. The inhibitor material can be formed on the upper portion of the side surface of the fin structure 134, while substantially not being formed on the lower portion of the side surface of the fin structure 134 and on the surface defining the lower boundary of the additional trench 136. Thereafter, at least one material deposition process (e.g., at least one ALD process, at least one CVD process) can be used to form the dielectric spacer material 142 over the exposed surfaces of the microelectronic device structure 100. The inhibitor material can temporarily impede the formation of the dielectric spacer material 142 thereon relative to other portions of the microelectronic device structure 100 that do not have the inhibitor material, such that the dielectric spacer material 142 is formed to exhibit the variable thickness described previously herein. Optionally, the deposition inhibition action (e.g., plasma treatment action) can be cycled with the material deposition action (e.g., ALD action, CVD action) to form the dielectric spacer material 142.

[0063] Next, with reference to both Figure 7A and Figure 7B (which depict Figure 7A(simplified partial top view of the microelectronic device structure 100 at the processing stage shown in FIG. ), digital line material 144 may be formed on or above the dielectric spacer material 142. The digital line material 144 may be formed on or above the surface of the dielectric spacer material 142 inside and outside the boundaries (e.g., horizontal boundary, vertical boundary) of the additional trench 136( Figure 6A ). In Figure 7B , the horizontal boundaries of some features (e.g., fin structures 134, additional peripheral dielectric structures 122, dielectric spacer material 142) vertically below the digital line material 144 of the microelectronic device structure 100 are depicted by dashed lines. The digital line material 144 may be formed to substantially (e.g., completely) fill the portion of the additional trench 136( Figure 6A ) that remains unfilled by the dielectric spacer material 142.

[0064] The digital line material 144 may be formed of a conductive material and contain a conductive material. In some embodiments, the digital line material 144 is formed of a metal material and contains a metal material, such as one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). By way of non-limiting example, the digital line material 144 may be formed of W and contain W. The digital line material 144 may be substantially uniform, or the digital line material 144 may be non-uniform. If the digital line material 144 is non-uniform, the amount of one or more elements contained in the digital line material 144 may vary stepwise (e.g., change suddenly), or may vary continuously (e.g., change gradually, such as linearly, parabolically) throughout different portions of the digital line material 144. The digital line material 144 may be formed, for example, of a stack of at least two different conductive materials and contain a stack of at least two different conductive materials.

[0065] Next, referring simultaneously to Figure 8A , Figure 8B and Figure 8C , the dielectric spacer material 142( Figure 7A ) and the portion of the digital line material 144( Figure 7A ) vertically overlying (e.g., in the Z direction) the fin structure 134 may be removed to form a dielectric spacer structure 146 from the dielectric spacer material 142( Figure 7A ) and form a digital line 148 (e.g., data line, bit line) from the digital line material 144( Figure 7A ). Figure 8A The view depicted in Figure 8B is a simplified partial cross-sectional view of the microelectronic device structure 100 with respect to the dashed line B1-B1 illustrated in Figure 8C The view depicted in Figure 8BA simplified partial cross-sectional view of the microelectronic device structure 100 of the dashed line C1-C1 as described therein. Thus, and as described in further detail below, Figure 8A The view depicted therein illustrates the central region 134A of some of the fin structures 134 of the microelectronic device structure 100; and Figure 8C The view depicted therein illustrates one of the opposite end regions 134B of some of the fin structures 134 of the microelectronic device structure 100.

[0066] As Figure 8A shown therein, portions of the capping structure 140 that vertically overlie the fin structure 134 and that are of the removable dielectric spacer material 142 ( Figure 7A ) and the digital line material 144 ( Figure 7A ) can be removed to form the dielectric spacer structure 146 and the digital line 148. In such embodiments, the upper boundaries (e.g., upper surfaces) of the dielectric spacer structure 146 and the digital line 148 can be formed to be substantially coplanar with the upper boundary of the capping structure 140. In additional embodiments, portions of the capping structure 140 and the additional peripheral dielectric structures 122 and dielectric end structures 137 ( Figure 8B and 8C ) that are at substantially the same vertical position as the capping structure 140 can also be removed during the formation of the dielectric spacer structure 146 and the digital line 148. In some such embodiments, the upper boundaries of the dielectric spacer structure 146 and the digital line 148 are substantially coplanar with the upper boundary of the additional shielding structure 138 of the fin structure 134, as depicted by the dashed line A1-A1 shown in Figure 8A therein.

[0067] The digital line 148 can be formed to have a horizontally elongated shape that extends parallel in the Y direction and is separated from each other in the X direction by the fin structure 134. As Figure 8A shown therein, within the central region 134A of the fin structure 134, the additional shielding structure 138 is horizontally interposed in the X direction between horizontally adjacent digital lines 148. Thus, the additional shielding structure 138 can mitigate (e.g., reduce, impede, prevent) unwanted electrical interference (e.g., crosstalk) between horizontally adjacent digital lines 148.

[0068] The dielectric spacer structure 146 can be formed to substantially cover and surround the horizontal boundaries in the X direction and the lower vertical boundaries in the Z direction of the digital line 148. The dielectric spacer structure 146 can be formed to have a horizontally elongated geometry that extends parallel in the Y direction and has a U-shaped transverse cross-sectional shape. The upper portion of the dielectric spacer structure 146 can be horizontally interposed between the digital line 148 and the fin structure 134, and the lower portion of the dielectric spacer structure 146 can be vertically interposed between the digital line 148 of the microelectronic device structure 100 and the lower shielding structure 106 (and the etch stop structure 110, if present).

[0069] As Figure 8C shown, within the opposing end regions 134B of the fin structure 134, the dielectric end structure 137 is horizontally interposed in the X direction between horizontally adjacent digital lines 148. The upper boundary of the dielectric end structure 137 can be substantially coplanar with the upper boundaries of the dielectric spacer structure 146 and the digital line 148. As previously discussed, horizontally interposing the dielectric end structure 137 of the fin structure 134 between the digital lines 148 can relax the constraints (e.g., affected by the risk of short circuit) on forming conductive contacts (e.g., digital line contacts) within the horizontal boundaries in the Y direction of the opposing end regions 134B of the fin structure 134. If additional shielding structures 138 of the fin structure 134 are used in the positions of the dielectric end structure 137 in the opposing end regions 134B of the fin structure 134 ( Figure 8A ), then the conductive contacts can be additionally employed.

[0070] Next, referring simultaneously to Figure 9A and Figure 9B (which depict a simplified partial top view of the microelectronic device structure 100 at the processing stage shown in Figure 9A ), an isolation material 150, an access line 152 (e.g., word line), a vertical access device 154 (e.g., vertical transistor), and a storage node structure 156 (e.g., capacitor) can be formed above the upper vertical boundary of the digital line 148. The vertical access device 154 and the storage node structure 156 can together form a memory cell 158, each individually comprising one of the vertical access devices 154 and one of the storage node structures 156. The foregoing features of the microelectronic device structure 100 at the processing stages depicted in Figure 9A and Figure 9B are further described in detail below. Figure 9A The view depicted in Figure 9B is a simplified partial cross-sectional view of the microelectronic device structure 100 with respect to the dashed line B1 - B1 illustrated in Figure 9A and Figure 9B . For clarity and ease of understanding the drawings and the associated description, not all of the features depicted in one of Figure 9Aand Figure 9B depicted in another of Figure 9B omitted Figure 9A the isolation material 150 shown in, to more clearly illustrate the features of the microelectronic device structure 100 that are vertically below the isolation material 150. In addition, the storage node structure 156 has been depicted as transparent to more clearly illustrate the features of the microelectronic device structure 100 (e.g., the vertical access device 154).

[0071] The access line 152 can be formed to have a horizontally elongated shape extending parallel in the X direction. The access line 152 can extend horizontally orthogonally to the digital line 148. The vertical access device 154 can be formed to be horizontally between horizontally adjacent access lines 152 in the Y direction, as described in further detail below. The access line 152 can be used as the conductive gate structure of the vertical access device 154, also as described in further detail below. In Figure 9A , the individual access lines 152 are depicted using dashed lines to indicate that the access lines 152 are horizontally adjacent in the Y direction to Figure 9A the vertical access device 154 depicted in, although the access line 152 is not located in the plane of the cross-section of the microelectronic device structure 100 indicated by the dashed line B1 - B1 in Figure 9B .

[0072] The access line 152 can be formed of and comprise a conductive material. In some embodiments, the access lines 152 are individually formed of and comprise a metal material, such as one or more of at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). By way of non-limiting example, the access line 152 can be individually formed of W and comprise W. The access lines 152 can be individually substantially uniform, or the access lines 152 can be individually non-uniform. If the individual access lines 152 are non-uniform, then the amount of one or more elements contained in the access line 152 can vary stepwise (e.g., change suddenly), or can vary continuously (e.g., change gradually, such as linearly, parabolically) throughout different portions of the access line 152. The access line 152 can be formed of and comprise a stack of at least two different conductive materials, for example.

[0073] The vertical access device 154 can be formed vertically on or above the digital line 148 and be in electrical communication with the digital line 148. As Figure 9AAs shown, in some embodiments, a vertical access device 154 is formed on a digital line 148. Each vertical access device 154 may include a conductive doped region 154A (serving as source and drain regions) and a channel region 154B vertically inserted between the conductive doped regions 154A. Additionally, each vertical access device 154 may individually include a portion that is horizontally adjacent (e.g., in the Y direction) to at least one of the access lines 152 and is at least partially within the vertical boundaries (e.g., in the Z direction) of its channel region 154B. The portion of the access line 152 may serve as the gate of the vertical access device 154. Further, at least one gate dielectric material may be formed to be horizontally interposed between the channel region 154B of each vertical access device 154 and the portion of the access line 152 that is horizontally adjacent to the channel region 154B.

[0074] For each of the vertical access devices 154, its conductive doped region 154A and channel region 154B may be formed of and include a semiconducting material, such as one or more of a silicon material (e.g., polysilicon), a silicon germanium material, a germanium material, a gallium arsenide material, a gallium nitride material, and an indium phosphide material. In some embodiments, the conductive doped region 154A and the channel region 154B each include polysilicon. Additionally, the conductive doped region 154A of each vertical access device 154 may be doped with one or more desired dopants. In some embodiments, the conductive doped region 154A of at least one vertical access device 154 is formed of and includes a semiconducting material (e.g., polysilicon) doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). In some such embodiments, the channel region 154B of the vertical access device 154 is formed of and includes a semiconducting material doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In some other such embodiments, the channel region 154B of the vertical access device 154 is formed of and includes a substantially undoped semiconducting material. In additional embodiments, the conductive doped region 154A of at least one vertical access device 154 is formed of and includes a semiconducting material (e.g., polysilicon) doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In some of such additional embodiments, the channel region 154B of the vertical access device 154 is formed of and includes a semiconducting material doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). In some other such additional embodiments, the channel region 154B of the vertical access device 154 is formed of and includes a substantially undoped semiconducting material.

[0075] As Figure 9AAs shown, the storage node structure 156 (e.g., a capacitor) can be formed vertically above the vertical access device 154 and is in electrical communication with the vertical access device 154. The storage node structure 156 can be configured to store charge representing a programmable logic state. For example, the charged state of the storage node structure 156 can represent a first logic state (e.g., logic 1), and the uncharged state of the storage node structure 156 can represent a second logic state (e.g., logic 0). In some embodiments, the storage node structure 156 includes a dielectric material configured to store charge associated with a logic state. The dielectric material can include, for example, one or more of the following: including silicon dioxide, silicon nitride, polyimide, titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), oxide-nitride-oxide materials (e.g., silicon dioxide-silicon nitride-silicon dioxide), strontium titanate (SrTiO3) (STO), barium titanate (BaTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), ferroelectric materials (e.g., ferroelectric hafnium oxide, ferroelectric zirconium oxide, lead zirconate titanate (PZT), etc.), and high-k dielectric materials. In some embodiments, the storage node structure 156 is formed of zirconium oxide and includes zirconium oxide.

[0076] As Figure 9A illustrated, the isolation material 150 can be formed on or above the additional peripheral dielectric structure 122, the dielectric spacer structure 146, and the fin structure 134. The isolation material 150 can be formed to cover and surround at least portions of the access line 152 and the vertical access device 154. The isolation material 150 can also be formed to at least partially cover and surround the storage node structure 156. The isolation material 150 can be formed of at least one insulating material and includes at least one insulating material. By way of non-limiting example, the isolation material 150 can be formed of and include one or more of the following: at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x and TiO x ), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), at least one dielectric oxycarbide material (e.g., SiO x C y ), at least one hydrogenated dielectric oxycarbide material (e.g., SiC x O y H z ), at least one dielectric carbon oxynitride material (e.g., SiOx C z N y ) and amorphous carbon. In some embodiments, the isolation material 150 is formed of SiO x (e.g., SiO2) and includes SiO x . The isolation material 150 may be substantially uniform, or the isolation material 150 may be non-uniform. If the isolation material 150 is non-uniform, then the amount of one or more elements included in the isolation material 150 may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change gradually, such as linearly, parabolically) throughout different portions of the isolation material 150. The isolation material 150 may be formed, for example, of a stack of at least two different insulating materials and include a stack of at least two different insulating materials.

[0077] After forming the memory cell 158 (including its vertical access device 154 and storage node structure 156), the microelectronic device structure 100 may undergo additional processing to form a microelectronic device including the microelectronic device structure 100. By way of non-limiting example, conductive contact structures may be formed to electrically connect (e.g., couple) the memory cell 158 to control logic circuitry of control logic devices within the control logic region 104. At least some of such conductive contact structures may be formed, for example, to vertically extend through the peripheral dielectric structure 108 and additional peripheral dielectric structure 122 of the microelectronic device structure 100.

[0078] Thus, according to an embodiment of the present disclosure, a method of forming a microelectronic device includes forming a conductive shielding material over each of a conductive shielding structure and a first dielectric structure horizontally adjacent to the conductive shielding structure. A second dielectric structure is formed on the first dielectric structure and horizontally adjacent to the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending parallel to each other in a first horizontal direction. Each of the fin structures includes: two dielectric end structures integral with the remainder of the second dielectric structure; and an additional conductive shielding structure inserted between the two dielectric end structures in the first horizontal direction. A first set of conductive lines is formed to extend parallel to each other in the first horizontal direction and horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction.

[0079] In addition, according to an embodiment of the present disclosure, a microelectronic device includes a lower conductive shielding structure, a dielectric structure, conductive lines, fin structures, dielectric spacer structures, and an additional dielectric structure. The dielectric structure substantially surrounds the outer horizontal boundaries of the lower conductive shielding structure. The conductive lines are disposed over the lower conductive shielding structure and extend parallel in a first horizontal direction. The fin structures are disposed over the lower conductive shielding structure and extend parallel in the first horizontal direction. The fin structures are inserted between the conductive lines in a second horizontal direction orthogonal to the first horizontal direction. Each of the fin structures includes opposing dielectric end structures and an additional conductive shielding structure inserted between the opposing dielectric end structures. The dielectric spacer structures are inserted between each of the fin structures and the lower conductive shielding structure and the conductive lines. The additional dielectric structure is disposed over the dielectric structure and substantially horizontally surrounds the region occupied by the conductive lines, the fin structures, and the dielectric spacer structures.

[0080] Figure 10 A functional block diagram of a microelectronic device 200 (e.g., a memory device, such as a DRAM device) according to an embodiment of the present disclosure is illustrated. The microelectronic device 200 may include, for example, an embodiment of the microelectronic device structure 100 after the processing stages previously referenced Figure 9A and 9B described. As Figure 10 shown, the microelectronic device 200 may include memory cells 202 (e.g., corresponding to the memory cells 158 previously referenced Figure 9A and 9B described), digital lines 204 (e.g., corresponding to the digital lines 148 previously referenced Figures 8A to 9B described), access lines 206 (e.g., corresponding to the access lines 152 previously referenced Figure 9A and 9B described), a row decoder 208, a column decoder 210, a memory controller 212, a sensing device 214, and an input / output device 216. One or more (e.g., each) of the row decoder 208, the column decoder 210, the memory controller 212, the sensing device 214, and the input / output device 216 may be located, for example, within the control logic region 104 previously referenced for the microelectronic device structure 100 Figure 1A and 1B described. The microelectronic device 200 also includes other features of the microelectronic device structure 100 after the processing stages previously referenced Figure 9A and 9B described, such as the lower shielding structure 106, the peripheral dielectric structure 108, the additional peripheral dielectric structure 122, the fin structures 134 (including at least its additional shielding structure 138 and dielectric end structure 137), and the dielectric spacer structure 146.

[0081] The memory cells 202 of the microelectronic device 200 can be programmed to at least two different logic states (e.g., logic 0 and logic 1). Each memory cell 202 can individually include a storage node structure (e.g., corresponding to one of the storage node structures 156 previously referenced Figure 9A and 9B described) a capacitor and a vertical access device (e.g., corresponding to one of the vertical access devices 154 previously referenced Figure 9A and 9B described). The storage node structure stores a charge representing the programmable logic state of the memory cell 202 (e.g., a charged capacitor can represent a first logic state, e.g., logic 1; and an uncharged capacitor can represent a second logic state, e.g., logic 0). When a minimum threshold voltage is applied (e.g., by means of one of the access lines 206) to its channel region (e.g., corresponding to the channel region 154B previously referenced Figure 9A and 9B described) to operate on the storage node structure (e.g., read, write, rewrite), the vertical access device permits access to the storage node structure.

[0082] Operations on the memory cells 202 can be performed by activating appropriate digital lines 204 and access lines 206. Activating the digital line structure 204 or the access line structure 206 can include applying a voltage potential to the digital line structure 204 or the access line structure 206. Each column of the memory cells 202 can be individually connected to one of the digital lines 204, and each row of the memory cells 202 can be individually connected to one of the access lines 206. Individual memory cells 202 can be addressed and accessed by the intersection of the digital lines 204 and the access lines 206.

[0083] The memory controller 212 can control the operation of the memory cells 202 through various components, the various components including a row decoder 208, a column decoder 210, and a sensing device 214. The memory controller 212 can generate a row address signal directed to the row decoder 208 to activate (e.g., apply a voltage potential to) a predetermined access line 206, and can generate a column address signal directed to the column decoder 210 to activate (e.g., apply a voltage potential to) a predetermined digital line 204. The memory controller 212 can also generate and control the various voltage potentials employed during the operation of the microelectronic device 200. Generally, the amplitude, shape, and / or duration of the applied voltage can be adjusted (e.g., varied) and can be different for the various operations of the microelectronic device 200.

[0084] During the use and operation of the microelectronic device 200, after access, the memory cell 202 can be read (e.g., sensed) by the sensing device 214. The sensing device 214 can compare the signal (e.g., voltage) of the appropriate digital line structure 204 with a reference signal to determine the logical state of the memory cell 202. If, for example, the digital line structure 204 has a voltage higher than the reference voltage, then the sensing device 214 can determine that the stored logical state of the memory cell 202 is logic 1, and vice versa. The sensing device 214 can include transistors and amplifiers to detect and amplify the difference in the signals (commonly referred to as "latching" in the art). The detected logical state of the memory cell 202 can be output to the input / output device 216 through the column decoder 210. In addition, the memory cell 202 can be set (e.g., written) by similarly activating the appropriate access line structure 206 and the appropriate digital line structure 204 of the microelectronic device 200. By controlling the digital line structure 204 when the access line structure 206 is activated, the memory cell 202 can be set (e.g., a logical value can be stored in the memory cell 202). The column decoder 210 can accept data from the input / output device 216 to be written to the memory cell 202. In addition, the memory cell 202 can also be updated (e.g., recharged) by reading the memory cell 202. The read operation places the content of the memory cell 202 on the appropriate digital line structure 204, which is then pulled up to a full level (e.g., fully charged or discharged) by the sensing device 214. When the access line structure 206 associated with the memory cell 202 is deactivated, all the memory cells 202 in the row associated with the access line structure 206 return to being fully charged or discharged.

[0085] Thus, according to an embodiment of the present disclosure, a memory device includes a conductive shielding structure, a first peripheral dielectric structure, a second peripheral dielectric structure, and a memory array region. The conductive shielding structure is disposed over a substrate structure. The first peripheral dielectric structure is disposed over the substrate structure and is horizontally adjacent to the conductive shielding structure outwardly. The second peripheral dielectric structure is disposed on the first peripheral dielectric structure. The memory array region is horizontally adjacent to the second peripheral dielectric structure inwardly. The memory array region includes fin structures, digital lines, dielectric spacer structures, access lines, and memory cells. The fin structures are disposed over the conductive shielding structure and extend in a first horizontal direction. Each of the fin structures includes: two dielectric end structures that protrude from the second peripheral dielectric structure and are integral with the second peripheral dielectric structure; and an additional conductive shielding structure that is horizontally inserted between the two dielectric end structures. The digital lines are disposed over the conductive shielding structure and extend in the first horizontal direction. The digital lines are alternated with the fin structures in a second horizontal direction perpendicular to the first horizontal direction. The dielectric spacer structures are horizontally inserted between the digital lines and the fin structures, and vertically inserted between the digital lines and the conductive shielding structure. The access lines are disposed over the digital lines and extend parallel in the second horizontal direction. The memory cells are disposed over the digital lines and are electrically connected to the digital lines and the access lines.

[0086] A microelectronic device structure (e.g., the microelectronic device structure 100 after the processing stages previously referred to Figure 9A and 9B described) and a microelectronic device (e.g., the microelectronic device 200 previously referred to Figure 10 described) according to an embodiment of the present disclosure can be used in an embodiment of the electronic system of the present disclosure. For example, Figure 11 is a block diagram of an illustrative electronic system 300 according to an embodiment of the present disclosure. The electronic system 300 may include, for example, a computer or computer hardware components, a server or other network-connected hardware components, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g., or tablet computer), an e-book, a navigation device, etc. The electronic system 300 includes at least one memory device 302. The memory device 302 may include, for example, the microelectronic device structures previously described herein (e.g., the microelectronic device structure 100 after the processing stages previously referred to Figure 9A and 9B described) and one or more of the microelectronic devices (e.g., the microelectronic device 200 previously referred to Figure 10 described). The electronic system 300 may further include at least one electronic signal processor device 304 (commonly referred to as a “microprocessor”). The electronic signal processor device 304 may optionally include the microelectronic device structures previously described herein (e.g., previously referred toFigure 9A and 9B one or more of the microelectronic device structures 100) and microelectronic devices (e.g., the microelectronic device 200 previously referenced Figure 10 after the processing stages described. Although the memory device 302 and the electronic signal processor device 304 are depicted as Figure 10 two (2) separate devices in, in additional embodiments, a single (e.g., only one) memory / processor device having the functionality of the memory device 302 and the electronic signal processor device 304 is included in the electronic system 300. In such embodiments, the memory / processor device may include the microelectronic device structures previously described herein (e.g., the microelectronic device structure 100 after the processing stages previously referenced Figure 9A and 9B one or more of the microelectronic devices (e.g., the microelectronic device 200 previously referenced Figure 10 after the processing stages described. The electronic system 300 may further include one or more input devices 306 for a user to input information into the electronic system 300, such as a mouse or other pointing device, a keyboard, a touchpad, buttons, or a control panel. The electronic system 300 may further include one or more output devices 308 for outputting (e.g., visual or audio output) information to the user, such as a monitor, a display, a printer, an audio output jack, speakers, etc. In some embodiments, the input device 306 and the output device 308 may include a single touchscreen device that can be used to input information into the electronic system 300 and output visual information to the user. The input device 306 and the output device 308 may be in electrical communication with one or more of the memory device 302 and the electronic signal processor device 304.

[0087] Accordingly, in accordance with an embodiment of the present disclosure, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device. The memory device includes a shielding plate, a peripheral dielectric structure, an additional peripheral dielectric structure, a fin structure, digital lines, access lines, and memory cells. The shielding plate includes a conductive material. The peripheral dielectric structure horizontally surrounds the shielding plate. The additional peripheral dielectric structure is vertically disposed on the peripheral dielectric structure and has an inner horizontal boundary that is offset outward from an inner horizontal boundary of the peripheral dielectric structure. The fin structure vertically overlies the shielding plate and extends parallel in a first horizontal direction. Each fin structure includes: two dielectric end structures that horizontally project from the additional peripheral dielectric structure; and an additional shielding structure that includes additional conductive material extending from and between the two dielectric end structures. The digital lines are horizontally alternating with the fin structures. An upper surface of the digital lines is substantially coplanar with an upper surface of the fin structures. The access lines vertically overlie the digital lines and extend parallel in a second horizontal direction orthogonal to the first horizontal direction. The memory cells vertically overlie the digital lines and are coupled to the digital lines and the access lines.

[0088] Compared to conventional structures, conventional devices, and conventional methods, the methods, structures, and devices of the present disclosure advantageously facilitate one or more of improved performance of microelectronic devices, reduced cost (e.g., manufacturing cost, material cost), increased miniaturization of components, and increased packaging density. Compared to conventional methods, conventional structures, and conventional devices, the methods, structures, and devices of the present disclosure can also improve scalability, efficiency, and simplicity. The methods and structures of the present disclosure can reduce problems associated with the formation and processing of conventional microelectronic devices that include shielding structures for their conductive lines (e.g., digital lines). For example, the methods and structures of the present disclosure are not affected by the relatively small size and spacing error tolerances conventionally associated with properly forming shielding structures for digital lines. Additionally, compared to conventional methods and structures, the methods and structures of the present disclosure can reduce the risk of unwanted short circuits.

[0089] Additional non-limiting example embodiments of the present disclosure are set forth below.

[0090] Example 1: A method of forming a microelectronic device, comprising: forming a conductive shielding material over each of a conductive shielding structure and a first dielectric structure horizontally adjacent to the conductive shielding structure; forming a second dielectric structure on the first dielectric structure and horizontally adjacent to the conductive shielding material; patterning the conductive shielding material and the second dielectric structure to form fin structures extending parallel to each other in a first horizontal direction, each of the fin structures including: two dielectric end structures integral with the remainder of the second dielectric structure; and an additional conductive shielding structure inserted between the two dielectric end structures in the first horizontal direction; and forming first conductive lines extending parallel to each other in the first horizontal direction and horizontally alternating with the fin structures in a second horizontal direction orthogonal to the first horizontal direction.

[0091] Example 2: The method according to Example 1, further comprising forming a dielectric spacer structure including an upper portion horizontally inserted between the first conductive lines and the fin structures and a lower portion vertically inserted between the first conductive lines and the conductive shielding structure.

[0092] Example 3: The method according to Example 2, further comprising making the vertical height of the lower portion of the dielectric spacer structure at least twice the horizontal width in the second horizontal direction of each of the upper portions of the dielectric spacer structure.

[0093] Example 4: The method according to one of Examples 2 and 3, wherein forming the dielectric spacer structure and forming the first conductive lines includes: forming a dielectric spacer material over and between the fin structures, the dielectric spacer material partially filling a trench inserted between the fin structures in the second horizontal direction; forming a conductive material over the dielectric spacer material, the conductive material substantially filling the portion of the trench not occupied by the dielectric spacer material; and removing the vertically overlying portions of the dielectric spacer material and the conductive material over the fin structures to form the dielectric spacer structure from the dielectric spacer material and form the first conductive lines from the conductive material.

[0094] Example 5: The method according to any one of Examples 1 to 4, further comprising: forming a dielectric capping material over the conductive shielding material; and patterning the dielectric capping material while patterning the conductive shielding material and the second dielectric structure to form the fin structures, each of the fin structures being formed to further include a dielectric capping structure formed from the dielectric capping material over its additional conductive shielding structure.

[0095] Example 6: The method according to any one of Examples 1 to 5, wherein forming a second dielectric structure on the first dielectric structure and horizontally adjacent to the conductive shielding material includes: removing a portion of the conductive shielding material close to the outer horizontal boundary of the conductive shielding material to form a groove vertically extending through the conductive shielding material to the first dielectric structure; and forming the second dielectric structure in the groove vertically extending through the conductive shielding material.

[0096] Example 7: The method according to any one of Examples 1 to 6, further comprising forming a conductive etch stop structure vertically between the conductive shielding material and each of the conductive shielding structure and the first dielectric structure before forming the second dielectric structure.

[0097] Example 8: The method according to any one of Examples 1 to 7, wherein patterning the conductive shielding material and the second dielectric structure includes: forming a masking structure above the second dielectric structure and the conductive shielding material; forming a spacer structure above the masking structure, the spacer structure being separated from each other by trenches and having a width in a second horizontal direction corresponding to the width of the fin structure to be formed in the second horizontal direction; forming an additional masking structure above the masking structure and at least partially horizontally overlapping the second dielectric structure; and transferring the pattern at least partially defined by the spacer structure and the additional masking structure into the second dielectric structure and the conductive shielding material.

[0098] Example 9: The method according to any one of Examples 1 to 8, further comprising: forming a second conductive wire above the first conductive wire, the second conductive wires extending parallel to each other in a second horizontal direction; forming an access device above the first conductive wire, the access device being coupled to the first conductive wire and the second conductive wire; and forming a storage node structure above the access device and coupled to the access device.

[0099] Example 10: A microelectronic device, comprising: a lower conductive shielding structure; a dielectric structure substantially surrounding the outer horizontal boundary of the lower conductive shielding structure; conductive wires overlying the lower conductive shielding structure and extending parallel to each other in a first horizontal direction; fin structures overlying the lower conductive shielding structure and extending parallel to each other in the first horizontal direction, the fin structures being inserted between the conductive wires in a second horizontal direction orthogonal to the first horizontal direction, and each including opposing dielectric end structures and additional conductive shielding structures inserted between the opposing dielectric end structures; dielectric spacer structures inserted between each of the fin structures and the lower conductive shielding structure and the conductive wires; and additional dielectric structures on the dielectric structure and substantially horizontally surrounding the region occupied by the conductive wires, the fin structures, and the dielectric spacer structures.

[0100] Example 11: The microelectronic device according to Example 10, wherein the relative dielectric end structure of the fin structure is integral and continuous with the additional dielectric structure.

[0101] Example 12: The microelectronic device according to one of Examples 10 and 11, wherein the upper boundary of the fin structure is substantially coplanar with the upper boundaries of the conductive line, the dielectric spacer structure, and the additional dielectric structure.

[0102] Example 13: The microelectronic device according to any one of Examples 10 to 12, further comprising a conductive structure on the upper surface of the lower conductive shielding structure, and the dielectric structure, the fin structure, and the dielectric spacer structure are positioned on the upper surface of the conductive structure.

[0103] Example 14: The microelectronic device according to any one of Examples 10 to 13, wherein the fin structure individually further comprises a dielectric capping structure on the additional conductive shielding structure.

[0104] Example 15: The microelectronic device according to any one of Examples 10 to 14, further comprising: a substrate structure underlying each of the lower conductive shielding structure and the dielectric structure; and a control logic region including control logic circuitry at least partially vertically inserted between the substrate structure and each of the lower conductive shielding structure and the dielectric structure.

[0105] Example 16: The microelectronic device according to Example 15, wherein the control logic circuitry comprises complementary metal oxide semiconductor (CMOS) circuitry.

[0106] Example 17: The microelectronic device according to any one of Examples 10 to 16, further comprising: a memory cell overlying the conductive line and in electrical communication with the conductive line; and an additional conductive line overlying the conductive line and extending parallel in a second horizontal direction, the additional conductive line being horizontally adjacent to and in electrical communication with the memory cell.

[0107] Example 18: The microelectronic device according to Example 17, wherein each memory cell comprises: a vertical access device on one of the conductive lines; and a storage node structure on the vertical access device.

[0108] Embodiment 19: A memory device includes: a conductive shielding structure overlying a substrate structure; a first peripheral dielectric structure overlying the substrate structure and horizontally adjacent to the conductive shielding structure outwardly; a second peripheral dielectric structure on the first peripheral dielectric structure; and a memory array region horizontally adjacent to the second peripheral dielectric structure inwardly and including: fin structures overlying the conductive shielding structure and extending in a first horizontal direction, each of the fin structures including: two dielectric end structures protruding from the second peripheral dielectric structure and integral with the second peripheral dielectric structure; an additional conductive shielding structure horizontally inserted between the two dielectric end structures; digital lines overlying the conductive shielding structure and extending in the first horizontal direction, the digital lines alternating with the fin structures in a second horizontal direction perpendicular to the first horizontal direction; dielectric spacer structures horizontally inserted between the digital lines and the fin structures and vertically inserted between the digital lines and the conductive shielding structure; access lines overlying the digital lines and extending parallel in the second horizontal direction; and memory cells overlying the digital lines and electrically connected to the digital lines and the access lines.

[0109] Embodiment 20: The memory device according to Embodiment 19 further includes a control logic region at least partially vertically inserted between the substrate structure and the conductive shielding structure, the control logic region including control logic devices electrically connected to the memory cells of the memory array region.

[0110] Embodiment 21: In the memory device according to one of Embodiments 19 and 20, each of the dielectric spacer structures individually includes: two upper portions horizontally adjacent to opposite side surfaces of one of the digital lines; and a lower portion under the two upper portions and integral with the two upper portions, the lower portion vertically adjacent to the bottom surface of one of the digital lines.

[0111] Embodiment 22: In the memory device according to any one of Embodiments 19 to 21, the fin structure further includes a dielectric capping structure on the additional conductive shielding structure, an upper surface of the dielectric capping structure being substantially coplanar with upper surfaces of the two dielectric end structures.

[0112] Embodiment 23: In the memory device according to any one of Embodiments 19 to 22, an internal horizontal boundary of the second peripheral dielectric structure horizontally deviates outwardly from an internal horizontal boundary of the first peripheral dielectric structure.

[0113] Embodiment 24: In the memory device according to any one of Embodiments 19 to 23, each of the memory cells is positioned between two of the access lines in the first horizontal direction and between two of the fin structures in the second horizontal direction.

[0114] Example 25: The memory device according to any one of Examples 19 to 24, wherein each of the memory cells includes: a vertical transistor on an upper surface of one of the digital lines, the vertical transistor including a source region, a drain region, a channel region vertically between the source region and the drain region, and a gate horizontally adjacent to the channel region including a part of one access line; and a storage node structure on the vertical transistor.

[0115] Example 26: An electronic system, comprising: an input device; an output device; a processor device operatively connected to the input device and the output device; and a memory device operatively connected to the processor device and including: a shielding plate including a conductive material; a peripheral dielectric structure horizontally surrounding the shielding plate; an additional peripheral dielectric structure vertically on the peripheral dielectric structure and having an inner horizontal boundary offset outward from an inner horizontal boundary of the peripheral dielectric structure; a fin structure vertically overlying the shielding plate and extending parallel in a first horizontal direction, each of the fin structures including two dielectric end structures horizontally protruding from the additional peripheral dielectric structure and an additional shielding structure including additional conductive material extending between and extending from the two dielectric end structures; digital lines horizontally alternating with the fin structures, an upper surface of the digital lines being substantially coplanar with an upper surface of the fin structures; access lines vertically overlying the digital lines and extending parallel in a second horizontal direction orthogonal to the first horizontal direction; and memory cells vertically overlying the digital lines and coupled to the digital lines and the access lines.

[0116] Example 27: The electronic system according to Example 26, wherein the memory device includes a dynamic random access memory (DRAM) device.

[0117] Example 28: The electronic system according to one of Examples 26 and 27, further including control logic circuitry vertically under the shielding plate and the peripheral dielectric structure, the control logic circuitry being coupled to the memory cells.

[0118] Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the present disclosure is not limited to the specific forms disclosed. Indeed, the present disclosure will cover all modifications, equivalents, and alternatives falling within the scope of the following appended claims and their legal equivalents. For example, elements and features disclosed with respect to one embodiment may be combined with elements and features disclosed with respect to other embodiments of the present disclosure.

Claims

1. A method of forming a microelectronic device, comprising: forming a conductive shielding material over each of a conductive shielding structure and a first dielectric structure horizontally adjacent to the conductive shielding structure; forming a second dielectric structure over the first dielectric structure and horizontally adjacent to the conductive shielding material; patterning the conductive shielding material and the second dielectric structure to form fin structures extending parallel to each other in a first horizontal direction, each of the fin structures comprising: two dielectric end structures integral with the remainder of the second dielectric structure; and an additional conductive shielding structure inserted between the two dielectric end structures in the first horizontal direction; and forming first conductive lines extending parallel to each other in the first horizontal direction and horizontally alternating with the fin structures in a second horizontal direction orthogonal to the first horizontal direction.

2. The method according to claim 1, further comprising forming a dielectric spacer structure comprising an upper portion horizontally inserted between the first conductive lines and the fin structures and a lower portion vertically inserted between the first conductive lines and the conductive shielding structure.

3. The method according to claim 2, further comprising making the vertical height of the lower portion of the dielectric spacer structure at least twice the horizontal width in the second horizontal direction of each of the upper portions of the dielectric spacer structure.

4. The method according to claim 2, wherein forming the dielectric spacer structure and forming the first conductive lines comprise: forming a dielectric spacer material over and between the fin structures, the dielectric spacer material partially filling a trench inserted between the fin structures in the second horizontal direction; forming a conductive material over the dielectric spacer material, the conductive material substantially filling the portion of the trench not occupied by the dielectric spacer material; and removing the portions of the dielectric spacer material and the conductive material vertically overlying the fin structures to form the dielectric spacer structure from the dielectric spacer material and the first conductive lines from the conductive material.

5. The method according to any one of claims 1 to 4, further comprising: forming a dielectric capping material over the conductive shielding material; and patterning the dielectric capping material while patterning the conductive shielding material and the second dielectric structure to form the fin structures, each of the fin structures being formed to further comprise a dielectric capping structure formed from the dielectric capping material over the additional conductive shielding structure.

6. The method according to any one of claims 1 to 4, wherein forming the second dielectric structure over the first dielectric structure and horizontally adjacent to the conductive shielding material comprises: removing a portion of the conductive shielding material close to the outer horizontal boundary of the conductive shielding material to form a groove vertically extending through the conductive shielding material to the first dielectric structure; and The second dielectric structure is formed within the groove extending vertically through the conductive shielding material.

7. The method according to any one of claims 1 to 4, further comprising forming a conductive etch stop structure vertically between the conductive shielding material and each of the conductive shielding structure and the first dielectric structure before forming the second dielectric structure.

8. The method according to any one of claims 1 to 4, wherein patterning the conductive shielding material and the second dielectric structure comprises: forming a masking structure over the second dielectric structure and the conductive shielding material; forming a spacer structure over the masking structure, the spacer structure being separated from each other by trenches and having a width in the second horizontal direction corresponding to the width of the fin structure to be formed in the second horizontal direction; forming an additional masking structure over the masking structure and at least partially horizontally overlapping the second dielectric structure; and transferring a pattern at least partially defined by the spacer structure and the additional masking structure into the second dielectric structure and the conductive shielding material.

9. The method according to any one of claims 1 to 4, further comprising: forming a second conductive wire over the first conductive wire, the second conductive wires extending parallel to each other in the second horizontal direction; forming an access device over the first conductive wire, the access device being coupled to the first conductive wire and the second conductive wire; and forming a storage node structure over the access device and coupled to the access device.

10. A microelectronic device, comprising: a lower conductive shielding structure; a dielectric structure substantially surrounding an outer horizontal boundary of the lower conductive shielding structure; conductive wires overlying the lower conductive shielding structure and extending parallel to each other in a first horizontal direction; fin structures overlying the lower conductive shielding structure and extending parallel to each other in the first horizontal direction, the fin structures being inserted between the conductive wires in a second horizontal direction orthogonal to the first horizontal direction and each comprising: opposite dielectric end structures; and an additional conductive shielding structure inserted between the opposite dielectric end structures; dielectric spacer structures inserted between each of the fin structures and the lower conductive shielding structure and the conductive wires; and an additional dielectric structure over the dielectric structure and substantially horizontally surrounding an area occupied by the conductive wires, the fin structures and the dielectric spacer structures.

11. The microelectronic device according to claim 10, wherein the opposite dielectric end structures of the fin structures are integral and continuous with the additional dielectric structure.

12. The microelectronic device according to claim 10, wherein upper boundaries of the fin structures are substantially coplanar with upper boundaries of the conductive wires, the dielectric spacer structures and the additional dielectric structure.

13. The microelectronic device according to claim 10, further comprising a conductive structure on an upper surface of the lower conductive shielding structure, and the dielectric structure, the fin structure, and the dielectric spacer structure are positioned on an upper surface of the conductive structure.

14. The microelectronic device according to claim 10, wherein each of the fin structures further individually comprises a dielectric capping structure on the additional conductive shielding structure.

15. The microelectronic device according to any one of claims 10 to 14, further comprising: a substrate structure that is beneath each of the lower conductive shielding structure and the dielectric structure; and a control logic region that includes control logic circuitry at least partially vertically inserted between the substrate structure and each of the lower conductive shielding structure and the dielectric structure.

16. The microelectronic device according to claim 15, wherein the control logic circuitry comprises a complementary metal oxide semiconductor (CMOS) circuit.

17. The microelectronic device according to any one of claims 10 to 14, further comprising: memory cells that are overlying and electrically connected to the conductive lines; and additional conductive lines that are overlying and extending parallel in the second horizontal direction to the conductive lines, the additional conductive lines being horizontally adjacent and electrically connected to the memory cells.

18. The microelectronic device according to claim 17, wherein each of the memory cells comprises: a vertical access device that is on one of the conductive lines; and a storage node structure that is on the vertical access device.

19. A memory device, comprising: a conductive shielding structure that is overlying a substrate structure; a first peripheral dielectric structure that is overlying the substrate structure and horizontally adjacent outwardly to the conductive shielding structure; a second peripheral dielectric structure that is on the first peripheral dielectric structure; and a memory array region that is horizontally adjacent inwardly to the second peripheral dielectric structure and includes: fin structures that are overlying the conductive shielding structure and extending in a first horizontal direction, each of the fin structures comprising: two dielectric end structures that protrude from the second peripheral dielectric structure and are integral with the second peripheral dielectric structure; an additional conductive shielding structure that is horizontally inserted between the two dielectric end structures; digital lines that are overlying the conductive shielding structure and extending in the first horizontal direction, the digital lines alternating with the fin structures in a second horizontal direction perpendicular to the first horizontal direction; dielectric spacer structures that are horizontally inserted between the digital lines and the fin structures, and vertically inserted between the digital lines and the conductive shielding structure; access lines that are overlying the digital lines and extending parallel in the second horizontal direction; and memory cells that are overlying the digital lines and electrically connected to the digital lines and the access lines.

20. The memory device according to claim 19, further comprising a control logic region at least partially vertically inserted between the substrate structure and the conductive shielding structure, the control logic region including control logic means electrically connected to the memory cells of the memory array region.

21. The memory device according to claim 19, wherein each of the dielectric spacer structures individually comprises: two upper portions horizontally adjacent to opposite side surfaces of one of the digital lines; and a lower portion below the two upper portions and integral with the two upper portions, the lower portion vertically adjacent to a bottom surface of the one of the digital lines.

22. The memory device according to any one of claims 19 to 21, wherein the fin structure further comprises a dielectric capping structure on the additional conductive shielding structure, an upper surface of the dielectric capping structure being substantially coplanar with upper surfaces of the two dielectric end structures.

23. The memory device according to any one of claims 19 to 21, wherein an internal horizontal boundary of the second peripheral dielectric structure is horizontally offset outward from an internal horizontal boundary of the first peripheral dielectric structure.

24. The memory device according to any one of claims 19 to 21, wherein each of the memory cells is positioned between two of the access lines in the first horizontal direction and between two of the fin structures in the second horizontal direction.

25. The memory device according to any one of claims 19 to 21, wherein each of the memory cells comprises: a vertical transistor on an upper surface of one of the digital lines, the vertical transistor comprising: a source region; a drain region; a channel region vertically between the source region and the drain region; and a gate horizontally adjacent to the channel region including a portion of one of the access lines; and a storage node structure on the vertical transistor.

26. An electronic system, comprising: an input device; an output device; a processor device operably connected to the input device and the output device; and a memory device operably connected to the processor device and comprising: a shielding plate including a conductive material; a peripheral dielectric structure horizontally surrounding the shielding plate; an additional peripheral dielectric structure vertically on the peripheral dielectric structure and having an internal horizontal boundary offset outward from an internal horizontal boundary of the peripheral dielectric structure; a fin structure vertically overlying the shielding plate and extending parallel in a first horizontal direction, each of the fin structures comprising: two dielectric end structures horizontally protruding from the additional peripheral dielectric structure; and an additional shielding structure including additional conductive material extending from and between the two dielectric end structures; digital lines horizontally alternating with the fin structures, an upper surface of the digital lines being substantially coplanar with upper surfaces of the fin structures. An access line, which vertically overlies the digital line and extends parallel in a second horizontal direction orthogonal to the first horizontal direction; and A memory cell, which vertically overlies the digital line and is coupled to the digital line and the access line.

27. The electronic system according to claim 26, wherein the memory device includes a dynamic random access memory (DRAM) device.

28. The electronic system according to any one of claims 26 and 27, further comprising control logic circuitry vertically beneath the shielding plate and the peripheral dielectric structure, the control logic circuitry being coupled to the memory cell.

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