Improved bump coplanarity of semiconductor device assemblies and methods of making the same

Abstract

Improved bump coplanarity for semiconductor device assemblies and associated methods and systems are disclosed. In one embodiment, when forming an opening in a passivation layer of a semiconductor device to expose a surface of a bond pad, an additional opening can also be formed in the passivation layer. The additional opening can have a shallower depth than the opening that extends to the surface of the bond pad by partially exposing the passivation layer using a chrome leak process. Subsequently, when forming an active bump (pillar) on the exposed surface of the bond pad, a dummy bump (pillar) can be formed on the recessed surface of the additional opening such that the difference in height above the passivation surface between the active bump and the dummy bump is reduced to improve coplanarity.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor device assemblies, and more particularly to improved bump coplanarity for semiconductor device assemblies. BACKGROUND

[0002] Semiconductor packages generally include a semiconductor die (e.g., a memory chip, a microprocessor chip, an imager chip) mounted on a substrate and enclosed in a protective covering. The semiconductor die can include functional features, such as memory cells, processor circuitry, or imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to corresponding conductive structures of the substrate, which can be coupled to terminals external to the protective covering such that the semiconductor die can be connected to higher-level circuitry.

[0003] In some semiconductor packages, a direct die attach method (e.g., flip-chip bonding between the semiconductor die and the substrate) can be used to reduce the footprint of the semiconductor package. Such direct die attach methods can include directly connecting a plurality of conductive pillars (or bumps) of the semiconductor die to corresponding conductive structures of the substrate. Moreover, a solder structure can be formed over individual conductive pillars (or bumps) to facilitate bonding between the conductive pillars and the corresponding conductive structures - e.g., to form joints. If the conductive pillars have different heights, too short conductive pillars can fail to connect to the corresponding conductive structures, resulting in an“open circuit” (which can be referred to as a no-joint), while too tall conductive pillars can be crushed against the corresponding conductive structures to result in a“broken” joint. SUMMARY

[0004] In one aspect, the present application provides a semiconductor die comprising: a passivation layer including a dielectric layer over a bond pad and a polyimide layer over the dielectric layer; a first opening in the passivation layer, the first opening extending from a surface of the passivation layer to a surface of the bond pad; a first conductive pillar disposed within the first opening, the first conductive pillar connected to the bond pad and having a first height above the surface of the passivation layer; a second opening in the passivation layer, the second opening extending from the surface of the passivation layer past the polyimide layer; and a second conductive pillar disposed within the second opening, the second conductive pillar having a second height above the surface of the passivation layer, wherein a difference between the first and second heights is less than or equal to a predetermined value.

[0005] In another aspect, the present application provides a semiconductor die comprising: a passivation layer including a dielectric layer over a bond pad and a polyimide layer over the dielectric layer; an opening in the passivation layer, the opening extending from a surface of the passivation layer to a surface of the bond pad, wherein the opening has a first width at the surface of the passivation layer, a second width at a break portion through the polyimide layer that is less than the first width, and a third width at the surface of the bond pad that is less than the second width; a first conductive pillar disposed within the opening, the first conductive pillar connected to the bond pad and having a first height above the surface of the passivation layer; and a second conductive pillar disposed on the surface of the passivation layer, the second conductive pillar having a second height, wherein a difference between the first and second heights is less than or equal to a predetermined value.

[0006] In another aspect, the present application provides a method comprising: forming a dielectric layer over a bond pad of a semiconductor die; forming a polyimide layer over the dielectric layer; exposing the polyimide layer using a mask including a first region configured for full exposure and a second region configured for partial exposure; developing the exposed polyimide layer, wherein the polyimide layer includes a first opening corresponding to the first region and a second opening corresponding to the second region, and wherein the first opening extends from a surface of the polyimide layer to a surface of the bond pad and the second opening extends partially from the surface of the polyimide layer into the dielectric layer; and simultaneously forming a first conductive pillar within the first opening and a second conductive pillar within the second opening, wherein the first and second conductive pillars have first and second heights above the surface of the polyimide layer, respectively, and wherein a difference between the first and second heights is less than or equal to a predetermined value. BRIEF DESCRIPTION OF DRAWINGS

[0007] Many aspects of the technology can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on clearly illustrating the principles of the technology.

[0008] Figure 1A and 1B is a cross-sectional view of a semiconductor die illustrating bump coplanarity of the semiconductor die.

[0009] Figure 2A and 2B is a cross-sectional view of a semiconductor die according to an embodiment of the technology.

[0010] Figures 3A to 3D illustrates a stage of a process for forming bumps according to an embodiment of the technology.

[0011] Figure 4is a cross-sectional view of a semiconductor die according to embodiments of the present technology.

[0012] Figure 5 is a block diagram schematically illustrating a system including a semiconductor device assembly configured according to embodiments of the present technology.

[0013] Figure 6 is a flowchart of a method of forming bumps with improved coplanarity of semiconductor dies according to embodiments of the present technology. DETAILED DESCRIPTION

[0014] The following description relates to certain details of several embodiments of a bump (or pillar) with improved coplanarity for semiconductor device assemblies and related systems and methods. A semiconductor device or die (e.g., a memory device) can include conductive bumps attached to active components (e.g., various functional features and / or circuitry) of the semiconductor device to pass signals into and / or out of the semiconductor device. Such bumps (pillars) can be referred to as active bumps (active pillars). The semiconductor device can also include dummy bumps to provide structural support for the semiconductor device during assembly process steps (e.g., a flip-chip bonding process). The dummy bumps can be electrically floating (e.g., isolated from the active components of the semiconductor device), or can be connected to a ground node of the semiconductor device.

[0015] As described in greater detail below, active bumps coupled to the bond pads can be recessed relative to dummy bumps that are typically disposed on a surface of a passivation layer that is disposed above the bond pads. Thus, during a flip-chip bonding process, when the active bumps form joints (e.g., interconnects) with corresponding conductive structures of another semiconductor device (or a package substrate), the dummy bumps can cause broken joints and their structural integrity can be compromised. Moreover, the broken joints can contact one or more adjacent joints (e.g., joints that include active bumps), resulting in unwanted electrical shorts. If the goal of the flip-chip bonding process is to have the dummy bumps form joints without causing broken joints, the active bumps can suffer from open joints (e.g., open circuits).

[0016] Several embodiments of the present technology relate to a process that utilizes creating a recessed region in a passivation layer of a semiconductor device such that a dummy bump can be formed on the recessed region. In this manner, the dummy bump and the active bumps can have a height above the passivation layer that is within a predetermined range that is acceptable for direct chip attachment methods (e.g., a flip-chip bonding process). The predetermined range can be designed to allow for certain height variations among the bumps that can not cause yield and / or reliability issues after a flip-chip bonding process - e.g., due to broken joints and / or open joints.

[0017] The process can utilize a mask comprising one or more regions configured to allow portions of the underlying layer to be exposed to electromagnetic energy of light used during a photolithography process step, which can be referred to as a chrome leak process. The partially exposed underlying layer can exhibit intermediate behavior (e.g., intermediate etch rate) when compared to regions that are not exposed or that have full exposure. In this manner, the process (e.g., chrome leak process) can produce recessed regions without causing additional processing steps (e.g., additional photolithography steps and associated etching and / or cleaning steps to separately produce the recessed regions), and thereby reduce the height difference between active bumps and dummy bumps to improve coplanarity.

[0018] The term "semiconductor device or die" generally refers to a solid state device that includes one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, microprocessors, or diodes, among others. Such semiconductor devices can include integrated circuits or components, data storage elements, processing components, and / or other features fabricated on a semiconductor substrate. Furthermore, the term "semiconductor device or die" can refer to a finished device or an assembly or other structure at various stages of processing before becoming a finished device. Depending on its context of use, the term "substrate" can refer to a wafer-level substrate or a singulated, die-level substrate. Also, a substrate can include a semiconductor wafer, a package support substrate, an interposer, a semiconductor device or die, etc. Persons of ordinary skill in the relevant art will recognize that suitable steps of the methods described herein can be performed at the wafer level or at the die level.

[0019] Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor manufacturing techniques. For example, materials can be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating, and / or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques. Some techniques can be combined with photolithography processes. Persons of ordinary skill in the relevant art will also appreciate that the techniques can have additional embodiments, and can be practiced without the specific details set forth herein Figures 2A to 5 Several details of the described embodiments can be varied, especially as to

[0020] As used herein, the terms "vertical," "lateral," "down," "up," "upper," and "lower" can refer to the relative orientation or position of features in a semiconductor device assembly in view of the orientation shown in the figures. For example, "upper" or "uppermost" can refer to a feature that is closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices having other orientations.

[0021] Figure 1A is a cross-sectional view of a semiconductor die 101 illustrating coplanarity between active bumps and dummy bumps. Figure 1AThe semiconductor die 101 includes a substrate 105 (e.g., a silicon substrate) having various active components (e.g., functional features) such as memory arrays, peripheral circuit systems, integrated circuit components, etc. The semiconductor die 101 may include a plurality of bonding pads (one of which is described as bonding pad 110) coupled to the active components of the semiconductor die 101. Furthermore, the semiconductor die 101 may include a passivation layer 115 for protecting the active components and bonding pads. In some embodiments, the passivation layer 115 may include a dielectric layer 120 and a polyimide layer 125 formed over the dielectric layer 120. Figure 1A The diagram illustrates the removal of a portion of the passivation layer 115 to form an opening that exposes the surface of the bonding pad 110. The opening is depicted as having a depth D1 below the surface of the passivation layer 115.

[0022] Furthermore, bumps 130 (which may be referred to as pillars) may be formed on the exposed surface of the bonding pad 110. Bumps 130 may comprise a conductive metal (e.g., copper (Cu)), and given that the bonding pad 110 is coupled to an active component of the semiconductor die 101, bumps 130 may be referred to as active bumps 130. Bumps 130 are depicted having a total height H. A and the height h of the surface above the passivation layer 115 A Furthermore, the semiconductor die 101 may include dummy bumps 135 formed on the surface of the passivation layer 115. Thus, the dummy bumps 135 are isolated from the active components of the semiconductor die 100 and electrically float. The dummy bumps 135 are depicted having a total height H. D and the height h of the surface above the passivation layer 115 D The h D With H D same.

[0023] In some embodiments, the total height of active and dummy bumps (e.g., H) A and H D The dummy bumps can be scaled differently – for example, by designing the areal density of the dummy bumps to be different from that of the active bumps and / or by designing the cross-sectional area of ​​the dummy bumps to be different from that of the active bumps. However, unless otherwise noted, the active bumps 130 and dummy bumps 135 can be considered to have approximately the same structural dimensions (e.g., height and / or width) within statistical variations of the process technology – for example, within a 5% variation, within a 10% variation, etc. – to clearly illustrate the principles of this technology.

[0024] Figure 1A h A with h D The difference between them is denoted as ΔH, which can be referred to as the coplanarity between the active bump 130 and the dummy bump 135 - for example, h A with hD The smaller the difference AH between the active bump 130 and the dummy bump 135, the better (improved, enhanced) the co-planarity for forming a semiconductor device assembly - e.g., reducing the probability of having broken joints and / or no joints during a flip-chip bonding process. In general, AH can be designed to be less than or equal to a predetermined value or within a certain range (e.g., co-planarity requirements) such that the flip-chip bonding process can form interconnects (joints) without yield or reliability issues - e.g., due to broken joints and / or no joints. For example, AH can be less than five (5) micrometers (pm). In other examples, AH can be between five (5) to seven (7) pm. In yet another example, AH can be less than ten (10) pm.

[0025] Figure 1B is a cross-sectional view of a semiconductor die 102 illustrating co-planarity between an active bump and a dummy bump. The semiconductor die 102 can include aspects of the semiconductor die 101. For example, the semiconductor die 102 includes a substrate 105 having various active components of the semiconductor die 102 and a plurality of bond pads (one of which is depicted as bond pad 110) coupled to the active components of the semiconductor die 102. Further, the semiconductor die 100 includes a passivation layer 115 having a dielectric layer 120 and a polyimide layer 125. Figure 1B illustrates removing a portion of the passivation layer 115 to form an opening exposing a surface of the bond pad 110. When compared to the semiconductor die 101 described with reference to Figure 1A When compared to the semiconductor die 101 described with reference to

[0026] As described in greater detail with reference to Figure 3C In greater detail, the bumps of the semiconductor dies 101 and 102 can be formed utilizing an electroplating process that forms a conductive material on a surface that is not covered by photoresist. For example, the active bump 130 can correspond to a photoresist pattern (e.g., an opening in the photoresist) that is smaller than the opening in the passivation layer 115 in which the active bump 130 is formed. As such, the active bump 130 is formed (grown) from a bottom of the photoresist pattern during the electroplating process.

[0027] In contrast, the active bump 140 can correspond to a photoresist pattern (e.g., an opening in the photoresist) that is larger than the opening in the passivation layer 115. As such, the active bump 140 can be formed (grown) not only from a bottom of the photoresist pattern, but also from a sidewall (and / or surface) of the passivation layer 115. In such cases, the active bump 140 can be grown taller than the dummy bump 135 that is grown from the bottom of the resist pattern - e.g., the height h AGreater than (higher than) the height h of the dummy bump 135 D However, h A with h D The difference ΔH can be referred to as the coplanarity between the active bump 140 and the dummy bump 135, and the smaller the difference ΔH, the better (improved, enhanced) coplanarity the semiconductor die 102 is considered to have for forming semiconductor device assemblies - for example, reducing the probability of having broken connectors and / or no connectors during flip chip bonding processes.

[0028] Figure 2A This is a cross-sectional view of a semiconductor die according to an embodiment of the present technology. Figure 2A The semiconductor die in the reference may contain a reference Figure 1A The semiconductor die 101 is described in several aspects. For example, the semiconductor die includes a bonding pad 110 and an active bump 130 coupled to the bonding pad 110. The semiconductor die also includes a passivation layer 115 having a dielectric layer 120 and a polyimide layer 125. Furthermore, the semiconductor die is illustrated to include another bonding pad 210. The bonding pad 210 may be coupled to a ground plane (or ground node) of the semiconductor die. Additionally, Figure 2A The semiconductor die may include first, second, and third dummy bumps 235, 240, and 245. Unless otherwise noted, all bumps (e.g., active bump 130, dummy bumps 235, 240, and 245) are considered to have the same total height and width.

[0029] In some embodiments, dielectric layer 120 may comprise a composite layer of dielectric materials (e.g., oxides, nitrides, oxynitrides, etc.). In some cases, dielectric layer 120 may comprise only an inorganic dielectric layer (e.g., oxides, nitrides, etc.). In some embodiments, prior to forming polyimide layer 125, dielectric layer 120 may be planarized (e.g., polished) to remove (or otherwise reduce) the surface topography of dielectric layer 120, which may be caused by the underlying bonding pads 110 and 210.

[0030] like Figure 2A As shown, the active bump 130 is disposed in a first opening extending from the surface of the passivation layer 115 to the surface of the bonding pad 110. The first opening may have a depth D1 from the surface of the passivation layer 115. Furthermore, the active bump 130 may have a height h above the surface of the passivation layer 115. A .

[0031] Figure 2AA first dummy bump 235 is illustrated disposed in a second opening extending from a surface of the passivation layer 115 through the polyimide layer 125. The second opening can have a depth D2 from the surface of the passivation layer 115. In addition, the first dummy bump 235 is depicted as having a height hi above the surface of the passivation layer 115 that is less than a full height of the first dummy bump 235. As depicted in Figure 2A , the depth D2 can be less than the depth Dl, and thus the height hi can be greater than the height h A . As compared to the dummy bump 135 depicted in Figure 1A , the first dummy bump 235 is located at a surface of the second opening that is recessed from the surface of the passivation layer 115. In this manner, the difference between h A and hi (AH1) is less than the AH described with reference to Figure 1A , and the first dummy bump 235 provides improved coplanarity with respect to the active bump 130 - e.g., to reduce the probability of having a broken joint and / or no joint during a flip-chip bonding process. In some embodiments, the difference between h A and hi (AH1) can be greater than or equal to five (5) microns and less than or equal to seven (7) microns.

[0032] Although the depth D2 of the second opening is described and illustrated as being less than the depth Dl in Figure 2A , the present technology is not limited as such. For example, the depth D2 can be scaled to be approximately the same as the depth Dl within statistical process variations. In another example, the depth D2 can be scaled to be greater than the depth Dl, so long as the difference between h A and hi (AH1) is less than a predetermined value (e.g., a coplanarity criterion).

[0033] Further, Figure 2A A second dummy bump 240 is illustrated disposed in a third opening extending from a surface of the passivation layer 115 toward the dielectric layer 120 without extending through the polyimide layer 125. The second opening can have a depth D3 from the surface of the passivation layer 115. In addition, the second dummy bump 240 is depicted as having a height h2 above the surface of the passivation layer 115 that is less than a full height of the second dummy bump 240. As depicted in Figure 2A , the depth D3 can be less than the depths Dl and / or D2, and thus the height h2 can be greater than the heights h A and / or hi. As compared to the dummy bump 135 depicted in Figure 1A , the second dummy bump 240 is located at a surface of the third opening that is recessed from the surface of the passivation layer 115. In this manner, the difference between h A and h2 (AH2) is less than the AH described with reference to Figure 1AThe described ΔH, and the second dummy bump 240 disposed in a third opening having a recess from the surface of the passivation layer 115, provides improved coplanarity relative to the active bump 130 - for example, reducing the probability of having broken connectors and / or no connectors during flip chip bonding processes.

[0034] If h A If the difference (ΔH2) between h2 and h2 is insufficient—for example, greater than a predetermined value (e.g., coplanarity criterion)—then the design parameters of the second dummy bump 240 can be changed to reduce the total height of the second dummy bump 240 to reduce h2, i.e., the height above the surface of the passivation layer 115. For example, the cross-sectional area of ​​the second dummy bump 240 can be increased (e.g., greater than the cross-sectional area of ​​the active bump 130 and / or the first dummy bump 235) so that in reference Figure 3C During the described electroplating process, the second dummy bump 240 may grow shorter than the active bump 130 and / or the first dummy bump 235—for example, the second dummy bump 240 may have a shorter total height than the active bump 130 and / or the first dummy bump 235. Alternatively, if the second dummy bump 240 is included in a plurality of second dummy bumps 240 having areal density, then the areal density of the plurality of second dummy bumps 240 can be increased such that individual second dummy bumps 240 can grow shorter than the active bump 130 and / or the first dummy bump 235. In this way, h can be reduced. A The difference (ΔH2) between h2 and h2 makes ΔH2 less than or equal to a predetermined value - for example, satisfying the coplanarity criterion.

[0035] also, Figure 2A A third dummy bump 245 is described, positioned within a fourth opening extending from the surface of the passivation layer 115 to the surface of the bonding pad 210. The fourth opening may have a depth D4 from the surface of the passivation layer 115. Furthermore, the third dummy bump 245 is depicted as having a height h3 above the surface of the passivation layer 115. In some embodiments, the depth D4 of the fourth opening may be the same as the depth D1 (e.g., within statistical process variations). Therefore, h... A The difference between h3 and h3 is negligible (e.g., within statistical process variations), thus providing near-ideal coplanarity. Since the third dummy bump 245 is coupled to the bonding pad 210, the third dummy bump 245 is connected to the ground plane (or ground node) of the semiconductor die, as the bonding pad 210 can be coupled to the ground plane as described above.

[0036] In some embodiments, the surface of the mating pad 210 may be as referenced. Figure 3BA stop surface is provided during the described process of removing the dielectric layer 120 (e.g., when compared to a second opening that terminates within the dielectric layer 120). This stop surface can provide improved process control (e.g., the depth of an opening with a stop surface can be more uniform when compared to the depth of an opening without a stop surface). However, the semiconductor die can have limitations on placing a certain number of pads (e.g., ground bond pads 210) in various locations, such as through substrate vias (TSVs) that can not be compatible with ground bond pads, industry standard specifications (e.g., Joint Electron Device Engineering Council (JEDEC)) that prohibit placing ground bond pads at certain locations, etc.

[0037] Figure 2B is a cross-sectional view of a semiconductor die according to embodiments of the technology. Figure 2B The semiconductor die in can include the semiconductor die 101 described with reference to Figure 1A The semiconductor die 101 described and / or the semiconductor die in can include aspects of the semiconductor die described with reference to Figure 2A The semiconductor die described can include, for example, Figure 2B The semiconductor die includes bond pads 110 and active bumps 130 coupled to the bond pads 110. The semiconductor die also includes a passivation layer 115 that includes a polyimide layer 125. Further, the semiconductor die is illustrated as including bond pads 210 coupled to ground nodes of the semiconductor die. Further, Figure 2B The semiconductor die in includes first, second, and third dummy bumps 235, 240, and 245.

[0038] The passivation layer 115 includes a dielectric layer 121 that is conformal to the bond pads 110 and 210 when compared to the semiconductor die described with reference to Figure 2A The dielectric layer 121 has a uniform thickness (denoted as "T" in Figure 2B in some embodiments, the dielectric layer 121 includes a single dielectric layer. As described with reference to Figure 2A The dummy bumps 235, 240, and 245 provide improved coplanarity with respect to the active bumps 130 - e.g., to reduce the probability of having broken joints and / or no joints during a flip-chip bonding process. As such, the technology can be applied to semiconductor dies with a planarized dielectric layer (e.g., the dielectric layer 120) and / or semiconductor dies with a conformal dielectric layer (e.g., the dielectric layer 121) to improve the coplanarity of the bumps.

[0039] Figures 3A to 3D Stages of a process for forming bumps with improved coplanarity according to embodiments of the technology are illustrated. Figures 3A to 3D The semiconductor die depicted in can include the semiconductor die 101 described with reference to Figure 1A The semiconductor die 101 described and / or the semiconductor die in can include aspects of the semiconductor die described with reference toFigure 2A The described aspects of the semiconductor die. For example, Figure 3A This describes a semiconductor die comprising bonding pads 110 and 210 and a passivation layer 115 having a dielectric layer 120 and a polyimide layer 125. As described above, the dielectric layer 120 formed over the bonding pads 110 and 210 may be planarized prior to the formation of the polyimide layer 125.

[0040] Figure 3B This illustration shows a cross-sectional view of a semiconductor die including the first to fourth openings formed in the passivation layer 115. In this respect, Figure 3A The semiconductor die depicted may have been exposed using a photomask 305 comprising first to fourth regions R1 to R4 corresponding to the first to fourth openings, respectively. The first region of the photomask may be configured for full exposure—e.g., 100% exposure. The second region of the photomask may be configured for a first partial exposure—e.g., 80% exposure. Similarly, the third region of the photomask may be configured for a second partial exposure less than the first partial exposure—e.g., 50% exposure. The fourth region of the photomask may be configured for full exposure—e.g., 100% exposure.

[0041] In this way, the first partial exposure associated with the second region R2 allows a first degree of electromagnetic energy penetration through the photomask 305 during the exposure process (indicated by the down arrow below the second region R2). Similarly, the second partial exposure associated with the third region R3 allows a second degree of electromagnetic energy penetration through the photomask 305 during the exposure process (indicated by the down arrow below the third region R3), the second degree of electromagnetic energy penetration being less than the first degree of electromagnetic energy penetration. Furthermore, the second region R2 of the photomask 305 may contain a first partially opaque material configured for the first degree of electromagnetic energy penetration, and the third region R3 of the photomask 305 may contain a second partially opaque material configured for the second degree of electromagnetic energy penetration. In some cases, given the partially opaque material (e.g., chromium) configured for partial exposure of the underlying layer, the photomask 305 may be referred to as containing chromium leakage. Therefore, a photolithography process utilizing a photomask 305 containing chromium leakage may be referred to as a chromium leakage process.

[0042] Subsequently, the exposed polyimide layer 125 can be developed such that the passivation layer 115 can have a first opening corresponding to the first region Rl, a second opening corresponding to the second region R2, a third opening corresponding to the third region R3, and a fourth opening corresponding to the fourth region R4. Moreover, developing the exposed polyimide layer can include removing at least a portion of the dielectric layer 120 underlying the exposed polyimide layer 125 - e.g., utilizing a dry etch process. In some embodiments, forming the openings in the passivation layer 115 can be accomplished through at least two separate process steps - e.g., developing the exposed polyimide layer (e.g., in an aqueous organic developer), followed by a dry etch process. In this regard, the varying degrees of electromagnetic energy received at the polyimide layer 125 using the chromeless-giap process can result in varying thicknesses of the remaining polyimide layer in the different regions after the exposed polyimide layer has been developed. The remaining polyimide layer can at least partially block the subsequent dry etch process (until it is completely consumed by the dry etch) such that the depth of the openings can vary. As such, the amount of dielectric layer 120 removed can be related to (e.g., proportional to) the electromagnetic energy that penetrates the photomask 305 during the exposure process.

[0043] The first (and fourth) openings corresponding to the first region Rl (and the fourth region R4) configured for full exposure can extend from the surface of the polyimide layer 115 to the surface of the bond pad (e.g., bond pad 110, bond pad 210) - e.g., the first region Rl has no remaining polyimide layer and the dry etch process is designed to remove the dielectric layer 120 over the bond pad 110. The second region R2 (e.g., configured for 80% of a first partial exposure) can extend partially from the surface of the polyimide layer 115 into the dielectric layer 120 - e.g., the second region R2 has 20% of the polyimide layer remaining and the dry etch process is partially blocked until the 20% of the polyimide layer is consumed by the dry etch process. Similarly, the third opening corresponding to the third region R3 (e.g., configured for 50% of a second partial exposure) can extend from the surface of the polyimide layer 115 toward the dielectric layer 120 without extending through the polyimide layer 125 - e.g., the third region R3 has 50% of the polyimide layer remaining and the dry etch process is completely blocked without completely consuming the remaining 50% of the polyimide layer. Thus, the first opening is depicted as having a depth Dl, which can be the same as the depth D4 of the fourth opening (e.g., within statistical process variations). The second opening is depicted as having a depth D2 that is less than Dl (and / or D4). Similarly, the third opening has a depth D3 that is less than D2.

[0044] Figure 3C A cross-sectional view of a semiconductor die including the first through fourth patterns 315, 320, 325, and 330 formed in the photoresist 310 is illustrated. In this regard, the photoresist 310 can have been dispensed over the passivation layer 115, which can have been formed over the dielectric layer 120, which can have been formed over the bond pad 110. Figure 3BThe semiconductor die depicted in FIG. 1 can include a plurality of active bumps 130 formed in first to fourth openings 305, 310, 315, and 320, respectively. In this regard, a plating process can have been performed on the semiconductor die depicted in FIG. 1. Subsequently, first to fourth patterns 315, 320, 325, and 330 can be formed on photoresist 310 using photolithography processes known to those skilled in the art.

[0045] Figure 3D A cross-sectional view of a semiconductor die including active bumps 130 formed in first to fourth openings 305, 310, 315, and 320, respectively, and first to third dummy bumps 235, 240, and 245 is illustrated. In this regard, a plating process can have been performed on the semiconductor die depicted in FIG. 1. Figure 3C For example, a plating process (e.g., a Cu plating process) can be performed using a plating solution to deposit a metallic material (e.g., copper) over surfaces exposed to the plating solution (e.g., surfaces not covered by photoresist 310) - e.g., while forming active bumps 130 and first to third dummy bumps 235, 240, and 245. In some embodiments, the total height of the individual bumps is approximately equal (e.g., within statistical process variations).

[0046] In some embodiments, the total height of the bumps can be modified by varying the areal density of the individual bumps (or other structural dimension of the bumps, e.g., the cross-sectional area of the bumps). Areal density can correspond to the percentage of area within a unit area that is occupied by a bump, which can affect the rate of metal deposition during a plating process. For example, Figure 3D The semiconductor die of FIG. 1 can include a plurality of first dummy bumps, one of which is depicted as first dummy bump 235. In addition, Figure 3D The semiconductor die of FIG. 1 can also include a plurality of second dummy bumps, one of which is depicted as second dummy bump 240. In some embodiments, the areal density of the second dummy bumps can be designed to be greater than the areal density of the first dummy bumps. Thus, the height of the second dummy bumps (e.g., second dummy bump 240) can be less than the height of the first dummy bumps (e.g., first dummy bump 235). In this way, if the coplanarity between active bump 130 and second dummy bump 240 is insufficient (e.g., greater than a coplanarity criterion) as shown in FIG. 1, the total height of second dummy bump 240 can be reduced to improve coplanarity. Figure 3D

[0047] Figure 4 A cross-sectional view of a semiconductor die according to embodiments of the present technology. Figure 4 The semiconductor die of FIG. 1 can include aspects of the semiconductor die 102 described with reference to Figure 1B For example, the semiconductor die includes bond pads 110 and a passivation layer 115 having a dielectric layer 120 and a polyimide layer 125. When compared to the semiconductor die 102 of FIG. 1, Figure 1B Figure 4 ​​The semiconductor die described includes an active bump 410 disposed in an opening extending from a surface of the passivation layer 115 to a surface of the bond pad 110. In this manner, the active bump 410 is disposed on a recessed surface of the opening such that when compared to the reference Figure 1B The coplanarity described - e.g., the delta H between the active bump 140 and the dummy bump 135 - is improved (e.g., the height h of the active bump 410 above the surface of the passivation layer 115 A is improved compared to the height h of the dummy bump 135. D

[0048] Figure 4 The opening in which the active bump 410 is disposed can be formed by a process similar to the process described and illustrated with reference to Figures 3A to 3D In this regard, the opening has a first width (denoted as Wl) at the surface of the passivation layer, a second width (denoted as W2) that is less than the first width at the break portion through the polyimide layer 125 (e.g., the break portion of the opening is within the dielectric layer 120), and a third width (denoted as W3) that is less than the second width at the surface of the bond pad. Further, the active bump 410 can include a first portion 411 having a fourth width (denoted as W4) that is less than the second width (W2) of the opening, where the first portion 411 is over the break portion of the opening. The active bump 410 can also include a second portion 412 that fills the opening under the break portion.

[0049] The semiconductor die described with reference to Figures 2A to 4 may be included in a semiconductor device assembly 500 that can be incorporated into any of a myriad of larger and / or more complex systems, representative examples of which are Figure 5 ​The system 570 is schematically shown. The system 570 can include the semiconductor device assembly 500, a power supply 572, a driver 574, a processor 576, and / or other subsystems or components 578. The semiconductor device assembly 500 can include features generally similar to features having active bumps and dummy bumps (e.g., dummy bumps disposed at recessed surfaces of a passivation layer) within tolerance limits (e.g., predetermined values, coplanarity criteria) as described herein, and thus can mitigate various issues that can limit yield and / or reliability performance of the semiconductor device assembly 500 - e.g., due to open and / or broken joints. The resulting system 570 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative systems 570 can include, but are not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, and appliances. The components of the system 570 can be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system 570 can also include remote devices and any of a wide variety of computer readable media.

[0050] Figure 6 is a flowchart 600 illustrating a method of forming bumps with improved coplanarity of semiconductor dies in accordance with embodiments of the present technology. The flowchart 600 can include aspects of the method as described with reference to Figures 2A to 4

[0051] The method includes forming a dielectric layer over a bond pad of a semiconductor die (block 610). The method further includes forming a polyimide layer over the dielectric layer (block 615). The method further includes exposing the polyimide layer using a photomask including a first region configured for full exposure and a second region configured for partial exposure (block 620). The method further includes developing the exposed polyimide layer, wherein the polyimide layer includes a first opening corresponding to the first region and a second opening corresponding to the second region, and wherein the first opening extends from a surface of the polyimide layer to a surface of the bond pad and the second opening extends partially from the surface of the polyimide layer into the dielectric layer (block 625). The method further includes simultaneously forming a first conductive pillar within the first opening and a second conductive pillar within the second opening, wherein the first and second conductive pillars have first and second heights above the surface of the polyimide layer, respectively, and wherein a difference between the first and second heights is less than or equal to a predetermined value (block 630).

[0052] ​In some embodiments, developing the exposed polyimide layer includes removing at least a portion of the dielectric layer beneath the exposed polyimide layer. In some embodiments, simultaneously forming the first and second conductive pillars includes: applying a photoresist to the polyimide layer having the first and second openings; forming a first pattern corresponding to the first conductive pillar and a second pattern corresponding to the second conductive pillar on the photoresist; and electroplating a conductive material in the first and second patterns.

[0053] In some embodiments, the partial exposure associated with the second region corresponds to a first partial exposure through a first degree of electromagnetic energy penetration through the photomask, wherein the photomask includes a third region configured for a second partial exposure, the second partial exposure corresponding to a second degree of electromagnetic energy penetration less than the first degree of electromagnetic energy penetration; as a result of exposing and developing the polyimide layer, a third opening is formed on the polyimide layer, the third opening corresponding to the third region; and the third opening extends from the surface of the polyimide layer toward the dielectric layer without extending through the polyimide layer.

[0054] In some embodiments, the method may further include forming a third conductive pillar simultaneously with the first and second conductive pillars, wherein the third conductive pillar has a third height above the surface of the polyimide layer, and wherein the difference between the first and third heights is less than or equal to a predetermined value. In some embodiments, a second region of the photomask includes a first portion of opaque material configured for electromagnetic energy penetration of a first degree, and a third region of the photomask includes a second portion of opaque material configured for electromagnetic energy penetration of a second degree. In some embodiments, the method may further include planarizing the dielectric layer prior to forming the polyimide layer.

[0055] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more methods can be combined.

[0056] As will be clear from the foregoing, specific embodiments of the present technology have been described herein for illustrative purposes, but various modifications may be made without departing from this disclosure. For example, although the recessed openings formed in the passivation layer have been described as follows... Figures 2A to 4 The cross-sectional view shows a single discrete opening, but various embodiments are possible that can configure the opening. For example, a recessed opening may include an area that is a rectangle, a circle, or an ellipse. Furthermore, certain aspects of the technology described in the context of a particular embodiment may be combined or eliminated in other embodiments.

[0057] The devices discussed herein, including semiconductor devices, can be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping using various chemicals, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate by ion implantation or by any other doping means.

[0058] As used in this document, including in the claims, “or” as used in a list of items (for example, as in “A, B, or C”) means an inclusive list such that, for example, A or B or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used in this document, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used in this document, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0059] From the foregoing, it will be appreciated that specific embodiments of the application have been described herein for purposes of illustration, but well realize that various modifications are possible without departing from the scope of the application. Accordingly, the disclosure is not limited except as by the appended claims. In the description provided herein, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the technology. However, it will be recognized by one skilled in the relevant art that embodiments of the technology can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures or operations are not shown or described in detail in order to avoid obscuring aspects of the technology. Generally, it will be understood that various other devices, systems, and methods in accordance with embodiments of the technology can be practiced without the specific details set forth above.

Claims

1. A semiconductor die, comprising: A passivation layer comprising a dielectric layer above a bonding pad and a polyimide layer above the dielectric layer; A first opening is formed in the passivation layer and extends from the surface of the passivation layer to the surface of the bonding pad. A first conductive pillar is disposed within the first opening, the first conductive pillar is connected to the bonding pad and has a first height above the surface of the passivation layer; A second opening is located in the passivation layer and extends from the surface of the passivation layer through the polyimide layer. and A second conductive pillar is disposed within the second opening, the second conductive pillar having a second height above the surface of the passivation layer, wherein the difference between the first and second heights is less than or equal to a predetermined value.

2. The semiconductor die according to claim 1, wherein the predetermined value is greater than or equal to five (5) micrometers and less than or equal to seven (7) micrometers.

3. The semiconductor die according to claim 1, wherein: The first opening has a first depth; and The second opening has a second depth that is less than the first depth.

4. The semiconductor die according to claim 1, wherein the first opening and the second opening are formed simultaneously.

5. The semiconductor die according to claim 1, further comprising: A third opening is provided in the passivation layer, the third opening extending from the surface of the passivation layer toward the dielectric layer without extending through the polyimide layer; and A third conductive pillar is disposed within the third opening, the third conductive pillar having a third height above the surface of the passivation layer, wherein the difference between the first and third heights is less than or equal to the predetermined value.

6. The semiconductor die according to claim 5, wherein: The second conductive pillar is contained within a plurality of second conductive pillars, each having a second total height; The third conductive post is contained within a plurality of third conductive posts, each having a third total height less than the second total height; and The areal density of the plurality of second conductive pillars is less than the areal density of the plurality of third conductive pillars.

7. The semiconductor die of claim 1, wherein the bonding pad is a first bonding pad of an active component coupled to the semiconductor die, and the semiconductor die further comprises: A second bonding pad is coupled to the ground plane of the semiconductor die, wherein the second conductive pillar is connected to the second bonding pad.

8. The semiconductor die of claim 1, wherein the dielectric layer comprises two or more dielectric materials and is planarized, and then the polyimide layer is deposited over the planarized dielectric layer.

9. The semiconductor die of claim 1, wherein the dielectric layer comprises a single dielectric material having a uniform thickness on the surface and sidewalls of the bonding pad.

10. The semiconductor die of claim 1, wherein the second opening comprises an occupied area that is one of a rectangle, a circle, or an ellipse.

11. A semiconductor die, comprising: A passivation layer comprising a dielectric layer above a bonding pad and a polyimide layer above the dielectric layer; A first opening is provided in the passivation layer, extending from the surface of the passivation layer to the surface of the bonding pad, wherein the first opening has a first width at the surface of the passivation layer, a second width less than the first width at a notch portion through the polyimide layer, and a third width less than the second width at the surface of the bonding pad. A second opening is provided in the passivation layer, extending from the surface of the passivation layer toward the dielectric layer without extending through the polyimide layer. A first conductive pillar is disposed within the first opening, the first conductive pillar is connected to the bonding pad and has a first height above the surface of the passivation layer; and A second conductive post is disposed within the second opening, the second conductive post having a second height, wherein the difference between the first and second heights is less than or equal to a predetermined value.

12. The semiconductor die of claim 11, wherein the first conductive pillar includes a first portion having a fourth width less than the second width, the first portion being above the notch portion.

13. The semiconductor die of claim 12, wherein the first conductive pillar comprises a second portion filling the opening beneath the notch portion.

14. A method of manufacturing a semiconductor device assembly, the method comprising: A dielectric layer is formed above the bonding pads of the semiconductor die; A polyimide layer is formed over the dielectric layer; The polyimide layer is exposed using a photomask comprising a first region configured for full exposure and a second region configured for partial exposure; The exposed polyimide layer is developed, wherein the polyimide layer includes a first opening corresponding to the first region and a second opening corresponding to the second region, and wherein the first opening extends from the surface of the polyimide layer to the surface of the bonding pad and the second opening extends from the surface of the polyimide layer to the dielectric layer in part; and Simultaneously, a first conductive pillar is formed in the first opening and a second conductive pillar is formed in the second opening, wherein the first and second conductive pillars have a first and a second height respectively above the surface of the polyimide layer, and wherein the difference between the first and second heights is less than or equal to a predetermined value.

15. The method of claim 14, wherein developing the exposed polyimide layer comprises removing at least a portion of the dielectric layer beneath the exposed polyimide layer.

16. The method of claim 14, wherein simultaneously forming the first and second conductive pillars comprises: A photoresist is applied to the polyimide layer having the first and second openings; A first pattern corresponding to the first conductive pillar and a second pattern corresponding to the second conductive pillar are formed on the photoresist; and Conductive material is electroplated in the first and second patterns.

17. The method of claim 14, wherein the partial exposure associated with the second region is a first partial exposure corresponding to a first degree of electromagnetic energy penetration through the photomask, and wherein: The photomask includes a third region configured for a second partial exposure, the second partial exposure corresponding to a second level of electromagnetic energy penetration that is less than the first level of electromagnetic energy penetration; As a result of exposing and developing the polyimide layer, a third opening is formed on the polyimide layer, the third opening corresponding to the third region; and The third opening extends from the surface of the polyimide layer toward the dielectric layer, but does not extend through the polyimide layer.

18. The method of claim 17, further comprising: A third conductive pillar is formed simultaneously with the first and second conductive pillars, wherein the third conductive pillar has a third height above the surface of the polyimide layer, and wherein the difference between the first and third heights is less than or equal to the predetermined value.

19. The method of claim 17, wherein the second region of the photomask comprises a first portion of opaque material configured for electromagnetic energy penetration of the first degree and the third region of the photomask comprises a second portion of opaque material configured for electromagnetic energy penetration of the second degree.

20. The method of claim 17, further comprising: The dielectric layer is planarized before the polyimide layer is formed.

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