Semiconductor structure and method of manufacturing the same

Abstract

A semiconductor structure includes a trench capacitor, a stacked capacitor, a first electrode plate and a second electrode plate. The trench capacitor is disposed in a substrate, wherein the trench capacitor includes a first conductive structure and a first dielectric structure, wherein the first conductive structure contacts the first dielectric structure. The stacked capacitor includes a second conductive structure and a second dielectric structure, the second conductive structure contacts the second dielectric structure, wherein the stacked capacitor is aligned with the trench capacitor along an axis perpendicular to an upper surface of the substrate, and the first conductive structure is electrically connected to the second conductive structure. The first electrode plate is electrically connected to the first dielectric structure and the second dielectric structure. The second electrode plate is electrically connected to the first conductive structure and the second conductive structure. The trench capacitor and the stacked capacitor are connected in parallel to produce a relatively large capacitance value, and the trench capacitor and the stacked capacitor are aligned perpendicular to each other, thus occupying a very small space.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor structure and a method of fabricating a semiconductor structure. BACKGROUND

[0002] A decoupling capacitor is a capacitor installed at a power supply terminal of a component, which can provide a more stable power supply and reduce noise (decoupling) of the component coupled to the power supply terminal, thereby indirectly reducing the influence of the noise of the component on other components.

[0003] With the development of technology, the capacitance value and size of a decoupling capacitor become very important in order to avoid the shutdown or loss of function of an electronic device. When the capacitance value of a decoupling capacitor is insufficient, some functions of the electronic device will be difficult to operate.

[0004] From the above description, it is necessary to develop a manufacturing method of a decoupling capacitor to increase the capacitance value of the decoupling capacitor and solve the above problems. SUMMARY

[0005] To solve the above problems, one embodiment of the present disclosure relates to a semiconductor structure, which includes a trench capacitor, a stacked capacitor, a first electrode plate, and a second electrode plate. The trench capacitor is disposed in a substrate, wherein the trench capacitor includes a first conductive structure and a first dielectric structure, and the first conductive structure contacts the first dielectric structure. The stacked capacitor includes a second conductive structure and a second dielectric structure, and the second conductive structure contacts the second dielectric structure, wherein the stacked capacitor is aligned with the trench capacitor along an axis perpendicular to an upper surface of the substrate, and the first conductive structure is electrically connected to the second conductive structure. The first electrode plate is electrically connected to the first dielectric structure and the second dielectric structure. The second electrode plate is electrically connected to the first conductive structure and the second conductive structure, thereby the trench capacitor and the stacked capacitor are connected in parallel between the first electrode plate and the second electrode plate.

[0006] In one or more embodiments of the present disclosure, an upper surface of the first conductive structure is aligned with an upper surface of the first conductive structure.

[0007] In one or more embodiments of the present disclosure, the first conductive structure is located within the substrate and surrounds a portion of the first dielectric structure.

[0008] In one or more embodiments of the present disclosure, the first dielectric structure has another portion extending to the substrate.

[0009] In one or more embodiments of the present disclosure, the second conductive structure surrounds a portion of the second dielectric structure.

[0010] In one or more embodiments of the present disclosure, the second conductive structure is cup-shaped.

[0011] In one or more embodiments of the application, the semiconductor structure further includes a via and a third electrode plate. The via extends through the substrate, wherein the via contacts the first conductive structure. The third electrode plate is disposed under the substrate, wherein the third electrode plate contacts the via.

[0012] In one or more embodiments of the application, the second electrode plate is axially aligned with the third electrode plate.

[0013] In one or more embodiments of the application, a thickness of the substrate is less than or equal to 6 micrometers (pm).

[0014] In one or more embodiments of the application, a first portion of the first dielectric structure is axially aligned with a first portion of the second dielectric structure, and a second portion of the first dielectric structure and a second portion of the second dielectric structure extend in opposite directions, respectively.

[0015] Another aspect of the application provides a method of fabricating a semiconductor structure, including: forming a trench capacitor in a substrate, wherein the trench capacitor includes a first conductive structure and a first dielectric structure, the first conductive structure contacting the first dielectric structure; forming a stacked capacitor, the stacked capacitor including a second conductive structure and a second dielectric structure, wherein the second conductive structure contacts the second dielectric structure, the stacked capacitor being axially aligned with the trench capacitor along an axis perpendicular to an upper surface of the substrate, wherein the first conductive structure is electrically connected to the second conductive structure; forming a first electrode plate, wherein the first electrode plate is electrically connected to the first dielectric structure and the second dielectric structure; and forming a second electrode plate, wherein the second electrode plate is electrically connected to the first conductive structure and the second conductive structure, whereby the trench capacitor and the stacked capacitor are connected in parallel between the first electrode plate and the second electrode plate.

[0016] In one or more embodiments of the application, forming the trench capacitor in the substrate includes: forming a first trench in the substrate; forming a first conductive layer on the first trench and the substrate; partially removing the first conductive layer to form the first conductive structure; and forming the first dielectric structure on the first conductive structure.

[0017] In one or more embodiments of the application, a portion of the first conductive structure surrounds a portion of the first dielectric structure located in the substrate.

[0018] In one or more embodiments of the application, an upper surface of the dielectric structure is aligned with an upper surface of the first conductive structure.

[0019] In one or more embodiments of the application, forming the stacked capacitor includes forming a first metal structure extending through the first intermetallic dielectric layer over the trench capacitor, forming a second intermetallic dielectric layer over the first intermetallic dielectric layer, forming a second trench within the second intermetallic dielectric layer, the second trench aligned with the first trench and exposing a portion of the first metal structure, and forming a second dielectric structure over the second conductive structure.

[0020] In one or more embodiments of the application, an upper surface of the second conductive structure is aligned with an upper surface of the second intermetallic dielectric layer.

[0021] In one or more embodiments of the application, the second conductive structure is cup-shaped.

[0022] In one or more embodiments of the application, a method of fabricating a semiconductor structure includes forming an intermetallic dielectric layer between a second electrode plate and a substrate, and forming a fourth metal structure within the intermetallic dielectric layer, the fourth metal structure contacting the first electrode plate and the first metal structure.

[0023] In one or more embodiments of the application, a method of fabricating a semiconductor structure includes forming an intermetallic dielectric layer between a first electrode plate and a substrate, and forming a second metal structure and a third metal structure, wherein the second metal structure contacts the first electrode plate and a second dielectric structure, and the third metal structure contacts the first electrode plate and a first dielectric structure.

[0024] In one or more embodiments of the application, a method of fabricating a semiconductor structure includes forming a via extending through the substrate, wherein the via contacts the first conductive structure, and forming a third electrode plate below the substrate, wherein the third electrode plate contacts the via.

[0025] In embodiments of the application, the decoupling capacitor includes a trench capacitor and a stacked capacitor connected in parallel, and the decoupling capacitor has a relatively large capacitance value because the trench capacitor and the stacked capacitor are connected in parallel. In addition, because the trench capacitor and the stacked capacitor are aligned with each other, the decoupling capacitor occupies a very small amount of space. BRIEF DESCRIPTION OF DRAWINGS

[0026] To describe the above-mentioned and other advantages and features of the application, a more particular description will be rendered by reference to specific embodiments thereof, which are illustrated in the appended drawings. These drawings are not intended to limit the scope of the application, and are included merely to describe a particular embodiment of the application. The principles and application of the present application will be better understood by reference to the drawings, where:

[0027] Figure 1 A flowchart of a method of fabricating a semiconductor structure in accordance with one or more embodiments of the application is depicted;

[0028] Figures 2 to 9 According to one or more embodiments of the present application, various steps of a method of fabricating a semiconductor structure are illustrated; and

[0029] Figure 10 According to one or more embodiments of the present application, various steps of a method of fabricating a semiconductor structure are illustrated; and Figure 9 A cross-sectional view of a semiconductor structure is illustrated, wherein the semiconductor structure is a die wafer. DETAILED DESCRIPTION

[0030] Several embodiments of the present application will be described with reference to the drawings. Details of the embodiments of the present application will be described with reference to the drawings in order to fully disclose the present application to those skilled in the art. However, it should be understood that these details are not intended to limit the present application. That is, these details are non-essential to the present application in some embodiments of the present application. In addition, for the sake of brevity, some conventional structures and elements are not described in detail in order to not obscure the present application in unnecessary detail.

[0031] Figure 1 A flowchart of a method 100 of fabricating a semiconductor structure is illustrated according to some embodiments of the present application. The method 100 of fabricating a semiconductor structure begins at step 101, which includes forming a trench capacitor in a substrate, wherein the trench capacitor includes a first conductive structure and a first dielectric structure, and wherein the first conductive structure contacts the first dielectric structure. Next, the method 100 proceeds to step 103, which includes forming a stacked capacitor including a second conductive structure and a second dielectric structure, wherein the second conductive structure contacts the second dielectric structure, and wherein the stacked capacitor is aligned with the trench capacitor along an axis perpendicular to an upper surface of the substrate, and wherein the first conductive structure is electrically connected to the second conductive structure. The method 100 then proceeds to step 105, which includes forming a first electrode plate, wherein the first electrode plate is electrically connected to the first dielectric structure and the second dielectric structure. The method 100 also includes step 107, which includes forming a second electrode plate, wherein the second electrode plate is electrically connected to the first conductive structure and the second conductive structure, whereby the trench capacitor and the stacked capacitor are connected in parallel between the first electrode plate and the second electrode plate. Some of the steps described above can be performed in a different order or simultaneously with other steps described herein. In addition, not all of the steps described above need to be completed in order to implement one or more embodiments described herein, and one or more steps shown herein can be performed by one or more separate actions and / or stages.

[0032] Figures 2 to 9 Cross-sectional views of various steps of a method 100 of fabricating a semiconductor structure 200 are illustrated according to some embodiments of the present application. Figure 2 and Figure 3 Step 101 can be graphically represented, wherein step 101 includes forming a trench capacitor 220 in a substrate 210. Referring to FIG. 2, a cross-sectional view of a substrate 210 is illustrated, wherein the substrate 210 includes a trench capacitor 220.Figure 2 and Figure 3 A first trench R1 is formed in the substrate 210, and then a first conductive layer L1 is conformally formed on the first trench R1 and the upper surface S1 of the substrate 210. Then, the first conductive layer L1 is partially removed, thereby forming a first conductive structure 221 and a third conductive structure 222, wherein the first conductive structure 221 and the third conductive structure 222 are separated from each other. Then, a first dielectric structure 223 is formed on the first conductive structure 221, and the third conductive structure 222 is spaced apart from the first dielectric structure 223.

[0033] In particular, the substrate 210 can be made of any suitable semiconductor material, including bulk semiconductor material (e.g., a semiconductor wafer alone or including other materials) and a semiconductor material region (e.g., a semiconductor material region alone or including other semiconductor materials). The first conductive structure 221 and the first dielectric structure 223 can be formed using a deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or any other suitable deposition process. In addition, the first conductive layer L1 can be partially removed by any suitable etching process, such as a non-isotropic etching process, although the present disclosure is not limited thereto.

[0034] In some embodiments of the present disclosure, the first conductive structure 221 has a first portion 221a that surrounds a first portion 223a of the first dielectric structure 223 in the substrate 210, and the first portion 221a is cup-shaped. The first portion 221a of the first conductive structure 221 and the first portion 223a of the first dielectric structure 223 are in the substrate 210, so the trench capacitor 220 occupies a relatively small space. In addition, an upper surface S2 of the first dielectric structure 223 is aligned with an upper surface S3 of the first conductive structure 221. A second portion 221b of the first conductive structure 221 extends onto the substrate 210, and a second portion 223b of the first dielectric structure 223 extends onto the substrate 210 and contacts the substrate 210.

[0035] Figures 4 to 7 Step 103, which includes forming a stacked capacitor 240 including a second conductive structure 241 and a second dielectric structure 243, wherein the second conductive structure 241 contacts the second dielectric structure 243, can be graphically represented as Figure 4A first metal interlayer I1 is formed on the substrate 210 and the trench capacitor 220. Then, a first metal structure 231 is formed, wherein the first metal structure 231 extends through the first metal interlayer I1, and the first metal structure 231 can be made by a suitable deposition process or an electroplating process, wherein the first conductive structure 221 contacts the first metal structure 231. In addition, a first portion 233a of a second metal structure 233 (refer to Figure 9 ) is formed, wherein the first portion 233a has two metal pillars extending through the first metal interlayer I1, and the two metal pillars respectively contact the third conductive structure 222 and the first dielectric structure 223.

[0036] Referring to Figure 5 and Figure 6 , a second metal interlayer I2 is formed on the first metal interlayer I1 and the first metal structure 231. Then, a second trench R2 is formed in the second metal interlayer I2, wherein the second trench R2 is aligned with the first trench R1 along an axial direction A1 perpendicular to the upper surface S1 of the substrate 210, and wherein the second trench R2 exposes the first metal structure 231. Then, a second conductive layer L2 is conformally formed on the second trench R2 and the second metal interlayer I2 by a suitable deposition process, and then a chemical-mechanical planarization process is performed on the second conductive layer L2 to partially remove the second conductive layer L2 on the second metal interlayer I2, thereby forming a cup-shaped second conductive structure 241 on the second trench R2. In addition, the first metal structure 231 contacts the second conductive structure 241. Specifically, the second conductive structure 241 has an upper surface S4 aligned with an upper surface S5 of the second metal interlayer I2, but the present application is not limited thereto. The first portion 221a of the first conductive structure 221 is aligned with the second conductive structure 241 along the axial direction A1 perpendicular to the upper surface S1 of the substrate 210.

[0037] Referring to Figure 7 , a second dielectric structure 243 can be formed on the second conductive structure 241 by any suitable deposition process and a suitable etching process. Specifically, a first portion 243a of the second dielectric structure 243 is cup-shaped and surrounded by the second conductive structure 241 located in the second metal interlayer I2, and a second portion 243b of the second dielectric structure 243 contacts and extends onto the second metal interlayer I2. The first portion 243a of the second dielectric structure 243 is aligned with the first portion 223a of the first dielectric structure 223 along the axial direction A1 perpendicular to the upper surface S1 of the substrate 210.

[0038] Figure 8 and Figure 9The steps 105 and 107 can be represented graphically, the step 105 includes forming the first electrode plate 251, and the step 107 includes forming the second electrode plate 253. The first electrode plate 251 and the second electrode plate 253 can be fabricated by any suitable deposition and etching processes, and the present application is not limited thereto. The first electrode plate 251 is electrically connected to the first dielectric structure 223 and the second dielectric structure 243, and the first dielectric structure 223 and the second dielectric structure 243 are polarized by the first electrode plate 251. The second electrode plate 253 is electrically connected to the first conductive structure 221 and the second conductive structure 241, and thereby the trench capacitor 220 and the stacked capacitor 240 are connected in parallel between the first electrode plate 251 and the second electrode plate 253. After the steps 105 and 107 are performed, the semiconductor structure 200 (i.e., the decoupling capacitor) is formed, and the semiconductor structure 200 includes the trench capacitor 220 and the stacked capacitor 240 connected in parallel.

[0039] In some embodiments of the present application, the step 105 includes forming a third intermetal dielectric layer I3 on the second intermetal dielectric layer I2. Specifically, the first intermetal dielectric layer I1, the second intermetal dielectric layer I2, and the third intermetal dielectric layer I3 are disposed between the first electrode plate 251 and the substrate 210. Then, the second portion 233b of the second metal structure 233 extends through the second intermetal dielectric layer I2 and the third intermetal dielectric layer I3, and the second portion 233b of the second metal structure 233 is formed on the first portion 233a of the second metal structure 233. In addition, the second portion 233b of the second metal structure 233 contacts the first electrode plate 251, and the first electrode plate 251 is electrically connected to the first dielectric structure 223, i.e., the first dielectric structure 223 is polarized by the first electrode plate 251. In addition, the third metal structure 235 is formed on the second portion 243b of the second dielectric structure 243, the third metal structure 235 extends through the third intermetal dielectric layer I3, and the third metal structure 235 contacts the first electrode plate 251 and the second dielectric structure 243.

[0040] In some embodiments of the present application, step 107 includes forming a third intermetal dielectric layer I3 on the second intermetal dielectric layer I2. Specifically, the first intermetal dielectric layer I1, the second intermetal dielectric layer I2, and the third intermetal dielectric layer I3 are disposed between the second electrode plate 253 and the substrate 210. Step 107 also includes forming a fourth metal structure 237 extending through the second intermetal dielectric layer I2 and the third intermetal dielectric layer I3, wherein the fourth metal structure 237 contacts the first metal structure 231 and the second electrode plate 253. Thus, the second electrode plate 253 is electrically connected to the first conductive structure 221 and the second conductive structure 241. In addition, a protective layer 281 can be formed on the first electrode plate 251 and the second electrode plate 253, and the material of the protective layer 281 can include silicon dioxide (SiO2), but the present application is not limited thereto.

[0041] In some embodiments of the present application, the method 100 further includes forming a via 271 extending through the substrate 210, wherein the via 271 contacts the second portion 221b of the first conductive structure 221, and forming a third electrode plate 255 under the substrate 210, wherein the third electrode plate 255 contacts the via 271. The via 271 can be formed by a suitable deposition process and etching process. In addition, a chemical mechanical polishing process can be performed on the substrate 210 to reduce the thickness of the substrate 210, and the thickness of the substrate 210 can be less than or equal to 6 micrometers (μm) to facilitate the formation of the via 271. In addition, the third electrode plate 255 can be electrically connected to a power terminal or a ground terminal, but the present application is not limited thereto.

[0042] Please refer to Figure 9Another aspect of the present disclosure provides a semiconductor structure 200 (may also be referred to as a decoupling capacitor), which includes a trench capacitor 220, a stacked capacitor 240, a first electrode plate 251 and a second electrode plate 253. The trench capacitor 220 is disposed in a substrate 210, wherein the trench capacitor 220 includes a first conductive structure 221 and a first dielectric structure 223, and the first conductive structure 221 contacts the first dielectric structure 223. The stacked capacitor 240 includes a second conductive structure 241 and a second dielectric structure 243, wherein the second conductive structure 241 contacts the second dielectric structure 243, and the stacked capacitor 240 is aligned with the trench capacitor 220 along an axis A1 perpendicular to an upper surface S1 of the substrate 210, and the first conductive structure 221 and the second conductive structure 241 are electrically connected to each other. The first electrode plate 251 is electrically connected to the first dielectric structure 223 and the second dielectric structure 243, and the first dielectric structure 223 and the second dielectric structure 243 are polarized by the first electrode plate 251. The second electrode plate 253 is electrically connected to the first conductive structure 221 and the second conductive structure 241, so that the trench capacitor 220 and the stacked capacitor 240 are connected in parallel between the first electrode plate 251 and the second electrode plate 253.

[0043] In some embodiments of the present disclosure, an upper surface S2 of the first conductive structure 221 is aligned with an upper surface S3 of the first dielectric structure 223. A first portion 223a of the first dielectric structure 223 is surrounded by a first portion 221a of the first conductive structure 221 in the substrate 210, and a second portion 223b of the first dielectric structure 223 extends onto the substrate 210.

[0044] In some embodiments of the present disclosure, a first intermetal dielectric layer I1 is located between the trench capacitor 220 and the stacked capacitor 240, the first metal structure 231 extends through the first intermetal dielectric layer I1, and opposite sides of the first intermetal dielectric layer I1 are provided with the first conductive structure 221 and the second conductive structure 241, respectively.

[0045] In some embodiments of the present disclosure, a second intermetal dielectric layer I2 is located on the first intermetal dielectric layer I1, and the second intermetal dielectric layer I2 surrounds the second conductive structure 241 located inside it. In addition, the second conductive structure 241 is cup-shaped, and the second conductive structure 241 is aligned with the first conductive structure 221, and the second conductive structure 241 surrounds a first portion 243a of the second dielectric structure 243 in the second intermetal dielectric layer I2. A second portion 243b of the second dielectric structure 243 contacts and extends above the second intermetal dielectric layer I2. In addition, the second portion 223b of the first dielectric structure 223 and the second portion 243b of the second dielectric structure 243 extend in opposite directions, respectively.

[0046] In some embodiments of the present application, a third intermetal dielectric layer I3 is disposed on the stacked capacitor 240 and the second intermetal dielectric layer I2. The first electrode plate 251 and the second electrode plate 253 are disposed on the third intermetal dielectric layer I3. The second metal structure 233 extends through the first intermetal dielectric layer I1, the second intermetal dielectric layer I2 and the third intermetal dielectric layer I3, and the second metal structure 233 contacts the first electrode plate 251 and the second portion 223b of the first dielectric structure 223. On the other hand, the third metal structure 235 is formed on the second dielectric structure 243, and the third metal structure 235 (e.g., a metal pillar) extends through the third intermetal dielectric layer I3, and thus the third metal structure 235 contacts the second dielectric structure 243 and the first electrode plate 251. Therefore, the first electrode plate 251 electrically connects the first dielectric structure 223 and the second dielectric structure 243, which are polarized by the first electrode plate 251.

[0047] In some embodiments of the present application, the fourth metal structure 237 (e.g., a metal pillar) extends through the second intermetal dielectric layer I2 and the third intermetal dielectric layer I3, and the fourth metal structure 237 contacts the second electrode plate 253 and the first metal structure 231. Therefore, the second electrode plate 253 electrically connects the first conductive structure 221 and the second conductive structure 241, and thus the trench capacitor 220 and the stacked capacitor 240 are connected in parallel to the first electrode plate 251 and the second electrode plate 253. In addition, a protective layer 281 is formed on the third intermetal dielectric layer I3, and the protective layer 281 covers the first electrode plate 251 and the second electrode plate 253, but the present application is not limited thereto.

[0048] In some embodiments of the present application, the first dielectric structure 223 and the second dielectric structure 243 comprise a high-k material, which can be titanium dioxide (TiO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), lanthanum oxide (La2O3), hafnium oxide (HfO2) or other suitable materials. Generally, the first electrode plate 251 and the second electrode plate 253 comprise a conductive material, which can be a metal, a specific metal nitride or a siliconized metal nitride, but the present application is not limited thereto. The first electrode plate 251 and the second electrode plate 253 can comprise platinum (Pt), aluminum (Al), copper (Cu), titanium nitride (TiN), silver (Au), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN) and copper (Cu), but the present application is not limited thereto.

[0049] In some embodiments of the present application, the semiconductor structure 200 further comprises a via 271 extending through the substrate 210, wherein the via 271 contacts the first metal structure 231. A third electrode plate 255 is located under the substrate 210, and the third electrode plate 255 contacts the via 271. The second electrode plate 253 is aligned with the third electrode plate 255 along the axial direction Al, and the via 271 is aligned with the fourth metal structure 237 along the axial direction Al. The thickness of the substrate 210 is less than or equal to 6 micrometers (μm) to facilitate the formation of the via 271 in the substrate 210. The third electrode plate 255 can be electrically connected to a power supply terminal or a ground terminal, and the third electrode plate 255 can comprise the same or different material as the first electrode plate 251 and the second electrode plate 253, but the present application is not limited thereto.

[0050] Please refer to Figure 10 In some embodiments of the present application, a device wafer 300 with a protective layer 310 is disposed on the semiconductor structure 200. In addition, the protective layer 310 is fixed to the protective layer 281 via a fusion bonding process. The device wafer 300 further comprises a signal line 320, wherein the signal line 320 is electrically connected to the first electrode plate 251, but the present application is not limited thereto.

[0051] In embodiments of the present application, the decoupling capacitor comprises a trench capacitor and a stacked capacitor connected in parallel, and the decoupling capacitor has a relatively large capacitance value. In addition, since the trench capacitor and the stacked capacitor are aligned with each other, the decoupling capacitor occupies a very small space.

[0052] Having described different embodiments of the present application as above, it should be understood that the different embodiments are presented only as examples, and not as limitations. Many modifications can be made to the embodiments of the present application according to the disclosure herein without departing from the spirit and scope of the present application. Therefore, the breadth and scope of the present application should not be limited by the above-described examples.

[0053]

List of Symbols

[0054] 100: method

[0055] 101, 103, 105, 107: step

[0056] 200: semiconductor structure

[0057] 210: substrate

[0058] 220: trench capacitor

[0059] 221: first conductive structure

[0060] 221a: first portion

[0061] 221b: second portion

[0062] 222: third conductive structure

[0063] 223: first dielectric structure

[0064] 223a: first portion

[0065] 223b: second portion

[0066] 231: first metal structure

[0067] 233: second metal structure

[0068] 233a: first portion

[0069] 233b: second portion

[0070] 235: third metal structure

[0071] 237: fourth metal structure

[0072] 240: stacked capacitor

[0073] 241: second conductive structure

[0074] 243: second dielectric structure

[0075] 243a: first portion

[0076] 243b: second portion

[0077] 251: first electrode plate

[0078] 253: second electrode plate

[0079] 255: third electrode plate

[0080] 271: communication post

[0081] 281: protective layer

[0082] 300: device wafer

[0083] 310: protective layer

[0084] 320: signal line

[0085] A1: axial direction

[0086] I1: first intermetal dielectric layer

[0087] I2: second intermetal dielectric layer

[0088] I3: third intermetal dielectric layer

[0089] L1: first conductive layer

[0090] L2: second conductive layer

[0091] R1: first trench

[0092] R2: second trench

[0093] S1, S2, S3, S4, S5: upper surface.

Claims

1. A semiconductor structure, characterized in that, include: A trench capacitor is disposed in a substrate, wherein the trench capacitor includes a first conductive structure and a first dielectric structure, wherein the first conductive structure contacts the first dielectric structure. A stacked capacitor includes a second conductive structure and a second dielectric structure, the second conductive structure contacting the second dielectric structure, wherein the stacked capacitor is aligned with the trench capacitor along an axial direction perpendicular to the upper surface of the substrate, and the first conductive structure is electrically connected to the second conductive structure. First electrode plate; The second metal structure contacts the first electrode plate and the first dielectric structure; The second electrode plate is electrically connected to the first conductive structure and the second conductive structure; as well as A third metal structure contacts the first electrode plate and the second dielectric structure, thereby connecting the trench capacitor and the stacked capacitor in parallel between the first electrode plate and the second electrode plate.

2. The semiconductor structure according to claim 1, characterized in that, The upper surface of the first dielectric structure is aligned with the upper surface of the first conductive structure.

3. The semiconductor structure according to claim 1, characterized in that, The first conductive structure is located within the substrate and surrounds a portion of the first dielectric structure.

4. The semiconductor structure according to claim 3, characterized in that, The first dielectric structure has another portion extending onto the substrate.

5. The semiconductor structure according to claim 1, characterized in that, The second conductive structure surrounds a portion of the second dielectric structure.

6. The semiconductor structure according to claim 1, characterized in that, The second conductive structure is cup-shaped.

7. The semiconductor structure according to claim 1, characterized in that, Also includes: A connecting post extends through the substrate, wherein the connecting post contacts a first conductive structure; as well as A third electrode plate is disposed under the substrate, wherein the third electrode plate contacts the connecting post.

8. The semiconductor structure according to claim 7, characterized in that, The second electrode plate is aligned with the third electrode plate along the axial direction.

9. The semiconductor structure according to claim 7, characterized in that, The thickness of the substrate is less than or equal to 6 micrometers.

10. The semiconductor structure according to claim 1, characterized in that, The first portion of the first dielectric structure is aligned with the first portion of the second dielectric structure along the axial direction, and the second portions of the first dielectric structure and the second dielectric structure extend in opposite directions.

11. A method for manufacturing a semiconductor structure, characterized in that, include: A trench capacitor is formed in the substrate, wherein the trench capacitor includes a first conductive structure and a first dielectric structure, and the first conductive structure contacts the first dielectric structure. A stacked capacitor is formed, the stacked capacitor including a second conductive structure and a second dielectric structure, wherein the second conductive structure contacts the second dielectric structure, the stacked capacitor is aligned with the trench capacitor along an axial direction perpendicular to the upper surface of the substrate, and wherein the first conductive structure is electrically connected to the second conductive structure. Forming a second metal structure and a third metal structure; A first electrode plate is formed, wherein the second metal structure contacts the first electrode plate and the first dielectric structure, and the third metal structure contacts the first electrode plate and the second dielectric structure; A second electrode plate is formed, wherein the second electrode plate is electrically connected to the first conductive structure and the second conductive structure, thereby the trench capacitor and the stacked capacitor are connected in parallel between the first electrode plate and the second electrode plate.

12. The method according to claim 11, characterized in that, The trench capacitor is formed within the substrate by: A first trench is formed within the substrate; A first conductive layer is formed on the first trench and the substrate; Partially removing the first conductive layer to form the first conductive structure; and The first dielectric structure is formed on the first conductive structure.

13. The method according to claim 11, characterized in that, A portion of the first conductive structure surrounds a portion of the first dielectric structure located within the substrate.

14. The method according to claim 11, characterized in that, The upper surface of the first dielectric structure is aligned with the upper surface of the first conductive structure.

15. The method according to claim 12, characterized in that, The stacked capacitors consist of: A first metal structure is formed, which extends through a first intermetallic dielectric layer on the trench capacitor. A second intermetallic dielectric layer is formed on the first intermetallic dielectric layer; A second trench is formed within the second intermetallic dielectric layer, the second trench being aligned with the first trench and exposing a portion of the first metal structure; and A second dielectric structure is formed on the second conductive structure.

16. The method according to claim 15, characterized in that, The upper surface of the second conductive structure is aligned with the upper surface of the second intermetallic dielectric layer.

17. The method according to claim 15, characterized in that, The second conductive structure is cup-shaped.

18. The method according to claim 15, characterized in that, include: An intermetallic dielectric layer is formed between the second electrode plate and the substrate; as well as A fourth metal structure is formed within the intermetallic dielectric layer, and the fourth metal structure contacts the first electrode plate and the first metal structure.

19. The method according to claim 11, characterized in that, include: An intermetallic dielectric layer is formed between the first electrode plate and the substrate.

20. The method according to claim 11, characterized in that, include: A connecting post is formed extending through the substrate, wherein the connecting post contacts the first conductive structure; as well as A third electrode plate is formed under the substrate, wherein the third electrode plate contacts the connecting post.

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