Semiconductor structure

Abstract

A semiconductor structure with a test structure is disclosed. The semiconductor structure includes a semiconductor substrate, a memory element, and a test structure. The memory element is disposed on the semiconductor substrate and has an element region and an edge region. The edge region surrounds the element region. The test structure is disposed on the semiconductor substrate and includes a dummy region, a test edge region, and a plurality of cells. The test edge region surrounds the dummy region. The plurality of cells has a first set of cells disposed in the dummy region and a second set of cells disposed in the test edge region. The second set of cells includes outermost cells of the plurality of cells. An edge region shape that the edge region surrounds in a top view is different from a test edge region shape that the test edge region surrounds in the top view.

Description

[0001] This invention claims priority and benefits to U.S. Patent Application No. 16 / 990,654, filed August 11, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a semiconductor structure. More particularly, it relates to a semiconductor structure having a test structure. Background Technology

[0003] In the manufacturing process of memory components, multiple manufacturing steps are required to form the desired component. For example, in the manufacturing process of a DRAM, forming capacitors and transistors requires many steps. To ensure that the component structure is completely formed on the wafer through multiple manufacturing steps, a test structure is usually formed on the wafer to test the component's functionality during the manufacturing process.

[0004] The above description of "prior art" is merely a background description and does not acknowledge that the subject matter of this disclosure is disclosed. It does not constitute prior art in this disclosure, and no description of the above "prior art" should be considered part of this invention. Summary of the Invention

[0005] This disclosure provides a semiconductor structure having a semiconductor substrate, a memory element, and a test structure. The memory element is disposed on the semiconductor substrate and has a component region and an edge region. The edge region surrounds the component region. The test structure is disposed on the semiconductor substrate and includes a dummy region, a test edge region, and a plurality of cell units. The test edge region surrounds the dummy region. The plurality of cell units includes a first group of cell units disposed in the dummy region and a second group of cell units disposed in the test edge region. The second group of cell units includes the outermost cell unit. The shape of the edge region surrounded by the edge region in a top view differs from the shape of the test edge region surrounded by the test edge region in the top view.

[0006] In some embodiments, one edge line of the test edge region in the top view is parallel to another edge line of the edge region in the top view. The dimension of one edge line of the test edge region is larger than the dimension of another edge line of the edge region.

[0007] In some embodiments, the edge line of the test edge region includes a portion of the second set of unit cells.

[0008] In some embodiments, one edge line of the test edge region in the top view is parallel to another edge line of the edge region in the top view. The dimension of one edge line of the test edge region is smaller than the dimension of another edge line of the edge region.

[0009] In some embodiments, the edge line of the test edge region includes a portion of the second set of unit cells.

[0010] In some embodiments, the size of the test structure in a top view is different from the size of the memory element in the top view.

[0011] In some embodiments, the size of the memory element in the top view is larger than the size of the test structure in the top view.

[0012] In some embodiments, the size of the memory element in the top view is smaller than the size of the test structure in the top view.

[0013] This disclosure also provides a semiconductor structure having a semiconductor substrate, a memory element, and a test structure. The memory element is disposed on the semiconductor substrate and has a component region and an edge region. The edge region surrounds the component region. The test structure is disposed on the semiconductor substrate and includes a dummy region, a test edge region, and a plurality of cell units. The test edge region surrounds the dummy region. The plurality of cell units are disposed in the test edge region, and no cell units are disposed in the dummy region. The size of the edge region surrounded by the edge region in a top view is different from the size of the test edge region surrounded by the test edge region in a top view.

[0014] In some embodiments, one edge line of the test edge region in the top view is parallel to another edge line of the edge region in the top view. The dimension of one edge line of the test edge region is larger than the dimension of another edge line of the edge region.

[0015] In some embodiments, the test edge region boundary line includes a portion of the plurality of unit cells.

[0016] In some embodiments, one edge line of the test edge region in the top view is parallel to another edge line of the edge region in the top view. The dimension of one edge line of the test edge region is smaller than the dimension of another edge line of the edge region.

[0017] In some embodiments, the test edge region boundary line includes a portion of the plurality of unit cells.

[0018] In some embodiments, the edge region in a top view has a size larger than the test edge region in the top view.

[0019] In some embodiments, the size of the edge region in the top view is smaller than the size of the test edge region in the top view.

[0020] This disclosure further provides a semiconductor structure having a semiconductor substrate, a memory element, and a test structure. The memory element is disposed on the semiconductor substrate and has a plurality of first cell units. The test structure is disposed on the semiconductor substrate and has a plurality of second cell units. The arrangement of the first cell units in a top view is different from the arrangement of the second cell units in the top view.

[0021] In some embodiments, a first cell arrangement edge of the first unit cell in the top view is parallel to a second cell arrangement edge of the second unit cell in the top view. The size of the first cell arrangement edge of the first unit cell is larger than the size of the second cell arrangement edge of the second unit cell.

[0022] In some embodiments, a first cell arrangement edge of the first cell in the top view is parallel to a second cell arrangement edge of the second cell in the top view. The size of the first cell arrangement edge of the first cell is smaller than the size of the second cell arrangement edge of the second cell.

[0023] In some embodiments, the size of the first cell arrangement edge in the top view is larger than the size of the second cell arrangement edge in the top view.

[0024] In some embodiments, the size of the first cell arrangement edge in the top view is smaller than the size of the second cell arrangement edge in the top view.

[0025] The technical features and advantages of this disclosure have been summarized quite extensively above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0026] The disclosure of the present invention can be more fully understood by referring to the accompanying drawings in conjunction with the embodiments and claims, wherein the same element symbols in the drawings refer to the same elements.

[0027] Figure 1 A top view schematic diagram illustrating a semiconductor structure according to an embodiment of the present disclosure.

[0028] Figure 2 For along Figure 1 The diagram shows a cross-sectional view of the semiconductor structure along line AA.

[0029] Figure 3 A top view schematic diagram illustrating a semiconductor structure according to an embodiment of the present disclosure.

[0030] Figure 4 A top view schematic diagram illustrating a semiconductor structure according to an embodiment of the present disclosure.

[0031] Figure 5 A top view schematic diagram illustrating a semiconductor structure according to an embodiment of the present disclosure.

[0032] Figure 6 A top view schematic diagram illustrating a semiconductor structure according to an embodiment of the present disclosure.

[0033] Figure 7 A top view schematic diagram illustrating a semiconductor structure according to an embodiment of the present disclosure.

[0034] Figure 8 A top view schematic diagram illustrating a semiconductor structure according to an embodiment of the present disclosure.

[0035] The attached figures are labeled as follows:

[0036] 10: Semiconductor Structure

[0037] 12: Semiconductor substrate

[0038] 14: Memory elements

[0039] 16: Test Structure

[0040] 30: Semiconductor Structure

[0041] 32: Semiconductor substrate

[0042] 34: Memory elements

[0043] 36: Test Structure

[0044] 40: Semiconductor Structure

[0045] 42: Semiconductor substrate

[0046] 44: Memory elements

[0047] 46: Test Structure

[0048] 50: Semiconductor Structure

[0049] 52: Semiconductor substrate

[0050] 54: Memory elements

[0051] 56: Test Structure

[0052] 60: Semiconductor Structure

[0053] 62: Semiconductor substrate

[0054] 64: Memory elements

[0055] 66: Test Structure

[0056] 70: Semiconductor Structure

[0057] 72: Semiconductor substrate

[0058] 74: Memory elements

[0059] 76: Test Structure

[0060] 80: Semiconductor Structure

[0061] 82: Semiconductor substrate

[0062] 84: Memory Elements

[0063] 86: Test Structure

[0064] 121: Lined area

[0065] 141: Component Area

[0066] 142: Unit cell

[0067] 143: Edge region

[0068] 161: Virtual Area

[0069] 162: Test edge region

[0070] 163: unit cell

[0071] 341: Component Area

[0072] 342: Unit cell

[0073] 343: Edge region

[0074] 361: Virtual Area

[0075] 362: Test edge region

[0076] 363: unit cell

[0077] 441: Component Area

[0078] 442: Unit cell

[0079] 443: Edge region

[0080] 461: Virtual Area

[0081] 462: Test edge region

[0082] 463: Unit cell

[0083] 541: Component Area

[0084] 542: Unit cell

[0085] 543: Edge region

[0086] 561: Virtual Area

[0087] 562: Test edge region

[0088] 563: Unit cell

[0089] 641: Component Area

[0090] 642: Unit cell

[0091] 643: Edge region

[0092] 661: Virtual Area

[0093] 662: Test edge region

[0094] 663: Unit cell

[0095] 741: Component Area

[0096] 742: Unit cell

[0097] 743: Edge Region

[0098] 761: Virtual Area

[0099] 762: Test edge region

[0100] 763: Unit cell

[0101] 841: Component Area

[0102] 842: Unit cell

[0103] 843: Edge region

[0104] 861: Virtual Area

[0105] 862: Test edge region

[0106] 863: Unit cell

[0107] 142a: Capacitor

[0108] 142b: Metal layer

[0109] 142c: Metal layer

[0110] 143a: Edge line

[0111] 143b: Edge

[0112] 162a: Edge line

[0113] 162b: Edge Line

[0114] 162c: Capacitor

[0115] 163a: Group 1

[0116] 163b: Group 2

[0117] 342a: Capacitor

[0118] 343a: Edge line

[0119] 343b: Edge

[0120] 362a: Edge line

[0121] 362b: Edge

[0122] 362c: Capacitor

[0123] 363a: Group 1

[0124] 363b: Group 2

[0125] 442a: Capacitor

[0126] 443a: Edge line

[0127] 443b: Edge

[0128] 462a: Edge line

[0129] 462b: Edge

[0130] 462c: Capacitor

[0131] 463a: Group 1

[0132] 463b: Group 2

[0133] 542a: Capacitor

[0134] 543a: Edge line

[0135] 543b: Edge Line

[0136] 562a: Edge line

[0137] 562b: Edge line

[0138] 562c: Capacitor

[0139] 563a: Group 1

[0140] 563b: Group 2

[0141] 642a: Capacitor

[0142] 643a: Edge line

[0143] 643b: Edge

[0144] 662a: Edge line

[0145] 662b: Edge line

[0146] 662c: Capacitor

[0147] 663a: Group 1

[0148] 663b: Group 2

[0149] 742a: Capacitor

[0150] 743a: Edge line

[0151] 743b: Edge Line

[0152] 762a: Edge line

[0153] 762b: Edge Line

[0154] 762c: Capacitor

[0155] 763a: Group 1

[0156] 763b: Group 2

[0157] 842a: Capacitor

[0158] 843a: Edge line

[0159] 843b: Edge Line

[0160] 862a: Edge line

[0161] 862b: Edge Line

[0162] 862c: Capacitor

[0163] 863a: Group 1

[0164] 863b: Group 2

[0165] AA: Line

[0166] X: Direction

[0167] Y: direction Detailed Implementation

[0168] The following description of this disclosure, accompanied by the accompanying drawings which are incorporated in and form a part of this specification, illustrates embodiments of this disclosure; however, this disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0169] Terms such as “an embodiment,” “an embodiment,” “an exemplary embodiment,” “another embodiment,” and “another embodiment” indicate that the embodiments described in this disclosure may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase “in an embodiment” does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0170] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0171] It should be understood that the following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or the desired nature of the apparatus. Furthermore, the description below of a first feature being formed "on" or "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. For simplicity and clarity, various features may be drawn at any scale. In the drawings, some layers / features may be omitted for simplicity.

[0172] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used in this invention to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the element in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used in this invention can be interpreted accordingly.

[0173] It should be understood that, for the sake of clarity and simplicity, Figures 3 to 8 Similar features in [the text] are represented by the same symbols. Furthermore, in [the text]... Figures 3 to 8 Similar components may also include similar materials, so for the sake of brevity, descriptions of these details have been omitted.

[0174] Figure 1 A top view schematic diagram illustrating a semiconductor structure 10 according to an embodiment of the present disclosure is shown. Figure 2 For along Figure 1 A cross-sectional schematic diagram of the semiconductor structure shown by line AA in the diagram. (Reference) Figure 1 and Figure 2 In some embodiments, a semiconductor structure 10 includes a semiconductor substrate 12, a memory element 14, and a test structure 16.

[0175] In some embodiments, the semiconductor substrate 12 may be made of semiconductor materials such as, but not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon-germanium substrate. The semiconductor substrate 12 may also be formed of other semiconductor materials including group III, group IV, and group V elements.

[0176] In some embodiments, the memory element 14 is disposed on the semiconductor substrate 12. In some embodiments, the memory element 14 is a dynamic random access memory (DRAM). The memory element 14 includes a plurality of cell cells 142. In some embodiments, each cell cell 142 includes a transistor and a capacitor 142. The plurality of cell cells 142 each have a bit line and a word line. For clarity, the transistor, the bit line, and the word line are not shown in the figures. In some embodiments, the capacitor 142a is disposed between two metal layers 142b and 142c (e.g., in...). Figure 2 (as shown in the image).

[0177] In some embodiments, the cell 142 is arranged in an array. The gap between any two memory elements 142 may be the same. The size of the gap is not limited. The memory element 14 may include a element region 141 and an edge region 143. The edge region 143 surrounds the element region 141. The element region 141 and the edge region 143 are defined by the function of the memory element 142. In other words, the memory elements 142 in the element region 141 are memory cells of the memory element 14, and the memory elements 142 in the edge region 143 are dummy cells of the memory element 14. In some embodiments, the edge region 143 includes the outermost cell 142 of the memory element 14.

[0178] Test structure 16 is disposed on semiconductor substrate 12. In some embodiments, test structure 16 is disposed in a scribing region 121 of semiconductor substrate 12. Test structure 16 includes a dummy region 161, a test edge region 162, and a plurality of memory elements 163. Test edge region 162 surrounds dummy region 161. In some embodiments, each memory element 163 includes a transistor and a capacitor 162c. For clarity, the transistor is not shown in the figures. In some embodiments, the memory elements 163 in dummy region 161 are arranged in an array. In some embodiments, the arrangement of memory elements 142 of memory element 14 in the top view is different from the arrangement of memory elements 163 in the top view.

[0179] In some embodiments, cell 163 has a first set of cells 163a and a second set of cells 163b. The first set of cells 163a of memory element 163 is disposed in dummy region 161. The second set of cells 163b of cell 163 is disposed in test edge region 162. The first set of cells 163a and the second set of cells 163b may have the same structure or different structures. The first set of cells 163a of cell 163 in dummy region 161 may serve as cells 142 in element region 141 of analog memory element 14. The second set of cells 163b of cell 163 may serve as cells 142 in edge region 143 of analog memory element 14. In some embodiments, cells 163 in the second set of cells 163b include the outermost cells 163 of test structure 16.

[0180] In some embodiments, the shape enclosed by edge region 143 in a top view is different from the shape enclosed by test edge region 162 in a top view. The shape enclosed by edge region 143 in the top view is the same as the shape of element region 141 in the top view. The shape enclosed by test edge region 162 in the top view is the same as the shape of dummy region 161 in the top view. In some embodiments, the shape enclosed by edge region 143 in the top view or the shape of element region 141 is a shape formed collectively by unit cells 142. In some embodiments, the shape enclosed by test edge region 162 in the top view or the shape of dummy region 161 is a shape formed collectively by unit cells 163. In some embodiments, the size of test structure 16 in the top view is different from the size of memory element 14 in the top view. In some embodiments, the size of memory element 14 in the top view is larger than the size of test structure 16 in the top view. It should be understood that the size of memory element 14 or test structure 16 is the size occupied by memory element 14 or test structure 16.

[0181] In some embodiments, the shape surrounded by edge region 143 may be a square, a rectangle, or other suitable shape. The shape surrounded by test edge region 142 may be a square, a rectangle, or other suitable shape. In this disclosure, the shape surrounded by edge region 143 is a different rectangle from the shape surrounded by test edge region 162; these are merely examples and are not intended to be limiting.

[0182] The edge lines 162a and 162b of the test edge region 162 are parallel to the edge lines 143a and 143b of the edge region 143, respectively. The edge lines 143a and 143b of the edge region 143 are formed by a portion of unit cell 142. The edge lines 162a and 162b of the test edge region 162 are formed by a portion of a second set of unit cells 163a of unit cell 163. In some embodiments, the size of the edge line 162a of the test edge region 162 (extending in the Y direction) is greater than the size of the edge line 143a of the edge region 143 (extending in the Y direction). In some embodiments, the size of the edge line 162b of the test edge region 162 (extending in the X direction) is smaller than the size of the edge line 143b of the edge region 143 (extending in the X direction). In other words, the length of edge line 162a is greater than the length of edge line 143a, and the length of edge line 162b is less than the length of edge line 143b.

[0183] Typically, the capacitor 142a in the edge region 143 cannot function as a capacitor in the element region 141. In other words, the capacitor 142a in the edge region 143 of the memory element 14 is inactive and is therefore treated as a dummy capacitor. In some embodiments of this disclosure, the capability of the capacitor 142a in the edge region 143 of the memory element 14 can be tested using the test structure 16.

[0184] In summary, the test edge region 162 of the test structure 16 can be designed as a test sample of the edge region 143 of the memory element 14. For example, the dimensions of the edges 162a and 162b of the test edge region 162 can be larger or smaller than the dimensions of the edges 143a and 143b of the edge region 143. When the dimension of the edge 162a of the test edge region 162 is larger than the dimension of the edge 143a of the edge region 143, the test results of the test edge region 162 (e.g., the quality of the capacitor 162c) can be better or worse than the test results of the edge region 143 of the memory element 14. Therefore, the structure of the edge region 143 of the memory element 14 can be redesigned based on the test edge region 162. The same result can also be obtained when the dimension of the edge 162b of the test edge region 162 is larger than the dimension of the edge 143b of the edge region 143.

[0185] Furthermore, based on the test results of the test edge region 162, the capacitor 142a in the edge region 143 of the memory element 14 can be redesigned for other purposes (e.g., as a decoupling capacitor). In other words, when the capacitance of the capacitor 162c in the test edge region 162 is greater than a predetermined parameter, the capacitor 142a in the edge region 143 of the memory element 14 can have different functional capabilities.

[0186] Figure 3 A top view schematic diagram illustrating a semiconductor structure 30 according to an embodiment of the present disclosure. (See also...) Figure 3 In some embodiments, the semiconductor structure 30 includes a semiconductor substrate 32, a memory element 34, and a test structure 36. In some embodiments, the memory element 34 includes a plurality of unit cells 342. Each memory element 342 includes a transistor and a capacitor 342a. In some embodiments, the memory element 34 may include a device region 341 and an edge region 343. The memory element 34 is similar to Figure 1 and Figure 2 For the sake of brevity, repeated details of memory element 14 are omitted.

[0187] Test structure 36 includes a dummy region 361, a test edge region 362, and a plurality of memory elements 363. In some embodiments, the unit cell 363 has a first group 363a and a second group 363b. Test structure 36 and Figure 1 The difference between the test structures 16 is that the dimensions of the two side lines 362a and 362b of the test edge region 362 are larger than the dimensions of the two side lines 343a and 343b of the edge region 343. In other words, the lengths of the two side lines 362a and 362b are both greater than the lengths of the two side lines 343a and 343b. In some embodiments, the dimensions of the test structure 36 in a top view are larger than the dimensions of the memory element 14 in a top view.

[0188] In short, the dimensions of the edges 362a and 362b of the test edge region 362 are both larger than the dimensions of the edges 343a and 343b of the edge region 343. The test results of the test edge region 362 (e.g., the quality of capacitor 362c) may be better or worse than the test results of the edge region 343 of the memory element 34. For example, the capacitor 362c of the edge region 362a (extending in the Y direction) may have different test results compared to the capacitor 362c of the edge region 362b (extending in the X direction). Therefore, the structure of the edge region 343 of the memory element 34 can be redesigned based on the test edge region 362. Furthermore, based on the test results of the test edge region 362, the capacitor 342a in the edge region 343 of the memory element 34 can be redesigned for other purposes (e.g., as a decoupling capacitor). In other words, when the capacitance of the capacitor 362c in the test edge region 362 is greater than a predetermined parameter, the capacitor 342a in the edge region 343 of the memory element 34 may have different functional capabilities.

[0189] Figure 4 A top view schematic diagram illustrating a semiconductor structure 40 according to an embodiment of the present disclosure. (See also...) Figure 4 In some embodiments, the semiconductor structure 40 includes a semiconductor substrate 42, a memory element 44, and a test structure 46. In some embodiments, the memory element 44 includes a plurality of unit cells 442. Each memory element 442 includes a transistor and a capacitor 442a. In some embodiments, the memory element 44 may include a device region 441 and an edge region 443. The memory element 44 is similar to Figure 1 and Figure 2 For the sake of brevity, repeated details of memory element 14 are omitted.

[0190] Test structure 46 includes a dummy region 461, a test edge region 462, and a plurality of memory elements 463. In some embodiments, unit cell 463 has a first group of unit cells 463a and a second group of unit cells 463b. Test structure 46 and Figure 1 The difference between the test structures 16 is that the size of the edge line 462a of the test edge region 462 (extending along the Y direction) is smaller than the size of the edge line 443a of the edge region 443 (extending along the Y direction), and the size of the edge line 462b of the test edge region 462 (extending along the X direction) is larger than the size of the edge line 443b of the edge region 443 (extending along the X direction). In other words, the length of edge line 462a is smaller than the length of edge line 443a, and the length of edge line 462b is smaller than the length of edge line 443b.

[0191] In short, the length of edge line 462a (extending in the Y direction) of test edge region 462 is less than the length of edge line 443a (extending in the Y direction) of edge region 443, and the length of edge line 462b (extending in the X direction) of test edge region 462 is greater than the length of edge line 443b (extending in the X direction) of edge region 443. The test results of test edge region 462 (e.g., the quality of capacitor 462c) may be better or worse than the test results of edge region 443 of memory element 44. For example, capacitor 462c (extending in the Y direction) of edge line 462a may have different test results compared to capacitor 462c (extending in the X direction) of edge line 462b. Therefore, the structure of edge region 443 of memory element 44 can be redesigned based on test edge region 462. Furthermore, based on the test results of test edge region 462, capacitor 442a in edge region 443 of memory element 44 can be redesigned for other purposes (e.g., as a decoupling capacitor). In other words, when the capacitance of capacitor 462c in the test edge region 462 is greater than a predetermined parameter, capacitor 442a in the edge region 443 of memory element 44 may have different functional capabilities.

[0192] Figure 5 A top view schematic diagram illustrating a semiconductor structure 50 according to an embodiment of the present disclosure. (See reference...) Figure 5 In some embodiments, the semiconductor structure 50 includes a semiconductor substrate 52, a memory element 54, and a test structure 56. In some embodiments, the memory element 54 includes a plurality of unit cells 542. Each memory element 542 includes a transistor and a capacitor 542a. In some embodiments, the memory element 54 may include a device region 541 and an edge region 543. The memory element 54 is similar to Figure 1 and Figure 2 For the sake of brevity, repeated details of memory element 14 are omitted.

[0193] Test structure 56 includes a dummy region 561, a test edge region 562, and multiple memory elements 563. Test structure 56 and... Figure 1 The difference between the test structures 16 is that multiple memory elements 563 are disposed in the test edge region 562, and no memory elements 563 are disposed in a dummy region 561. In other words, the memory elements 563 are not disposed in the dummy region 561. In some embodiments, the dimension of the edge line 562a of the test edge region 562 (extending in the Y direction) is greater than the dimension of the edge line 543a of the edge region 543 (extending in the Y direction), and the dimension of the width of the edge line 562b of the test edge region 562 (extending in the X direction) is smaller than the dimension of the edge line 543b of the edge region 543 (extending in the X direction). In other words, the length of the edge line 562a is greater than the length of the edge line 543a, and the length of the edge line 562b is less than the length of the edge line 543b.

[0194] In short, the length of edge line 562a (extending in the Y direction) of test edge region 562 is greater than the length of edge line 543a (extending in the Y direction) of edge region 543, and the length of edge line 562b (extending in the X direction) of test edge region 562 is less than the length of edge line 543b (extending in the X direction) of edge region 543. The test results of test edge region 562 (e.g., the quality of capacitor 562c) may be better or worse than the test results of edge region 543 of memory element 54. For example, capacitor 562c (extending in the Y direction) of edge line 562a may have different test results compared to capacitor 562c (extending in the X direction) of edge line 562b. Therefore, the structure of edge region 543 of memory element 54 can be redesigned based on test edge region 562. Furthermore, based on the test results of test edge region 562, capacitor 542a in edge region 543 of memory element 54 can be redesigned for other purposes (e.g., as a decoupling capacitor). In other words, when the capacitance of capacitor 562c in the test edge region 562 is greater than a predetermined parameter, capacitor 542a in the edge region 543 of memory element 54 may have different functional capabilities.

[0195] Furthermore, the dummy region 561 may not have a memory element 563, and the test results of the test edge region 562 may not be affected by the structure of the dummy region 561.

[0196] Figure 6 A top view schematic diagram illustrating a semiconductor structure 60 according to an embodiment of the present disclosure. (See also...) Figure 6In some embodiments, the semiconductor structure 5 includes a semiconductor substrate 52, a memory element 54, and a test structure 56. In some embodiments, the memory element 64 includes a plurality of unit cells 642. Each memory element 642 includes a transistor and a capacitor 642a. In some embodiments, the memory element 64 may include a device region 641 and an edge region 643. The memory element 64 is similar to Figure 1 and Figure 2 For the sake of brevity, repeated details of memory element 14 are omitted.

[0197] Test structure 66 includes a dummy region 661, a test edge region 662, and multiple memory elements 663. Test structure 66 and... Figure 5 The difference between the test structures 56 is that the dimensions of the edge lines 662a (extending in the Y direction) and 662b (extending in the X direction) of the test edge region 662 are both larger than the dimensions of the edge lines 643a (extending in the Y direction) and 643b (extending in the X direction) of the edge region 643. In other words, the lengths of the two edge lines 662a and 662b are both greater than the lengths of the two edge lines 643a and 643b.

[0198] In short, the lengths of edge lines 662a (extending in the Y direction) and 662b (extending in the X direction) of the test edge region 662 are both greater than the lengths of edge lines 643a (extending in the Y direction) and 643b (extending in the X direction) of the test edge region 662. The test results for the test edge region 662 (e.g., the quality of capacitor 662c) may be better or worse than the test results for the edge region 643 of the memory element 64. For example, the capacitor 662c (extending in the Y direction) of edge line 662a may have different test results compared to the capacitor 662c (extending in the X direction) of edge line 662b. Therefore, the structure of the edge region 643 of the memory element 64 can be redesigned based on the test edge region 662. Furthermore, based on the test results of the test edge region 662, the capacitor 642a in the edge region 643 of the memory element 64 can be redesigned for other purposes (e.g., as a decoupling capacitor). In other words, when the capacitance of capacitor 662c in the test edge region 662 is greater than a predetermined parameter, capacitor 642a in the edge region 643 of memory element 64 may have different functional capabilities.

[0199] Furthermore, the dummy region 661 may not have a memory element 663, and the test results of the test edge region 662 may not be affected by the structure of the dummy region 661.

[0200] Figure 7 A top view schematic diagram illustrating a semiconductor structure 70 according to an embodiment of the present disclosure. (See reference...) Figure 7 In some embodiments, the semiconductor structure 70 includes a semiconductor substrate 72, a memory element 74, and a test structure 76. In some embodiments, the memory element 74 includes a plurality of unit cells 742. Each memory element 742 includes a transistor and a capacitor 742a. ​​In some embodiments, the memory element 74 may include a device region 741 and an edge region 743. The memory element 74 is similar to Figure 1 and Figure 2 For the sake of brevity, repeated details of memory element 14 are omitted.

[0201] Test structure 76 includes a dummy region 761, a test edge region 762, and multiple memory elements 763. Test structure 76 and... Figure 5 The difference between the test structures 56 is that the size of the edge line 762a of the test edge region 762 (extending in the Y direction) is smaller than the size of the edge line 743a of the edge region 743 (extending in the Y direction), and the size of the edge line 762b of the test edge region 762 (extending in the X direction) is larger than the size of the edge line 743b of the edge region 743 (extending in the X direction). In other words, the length of edge line 762a is smaller than the length of edge line 743a, and the length of edge line 762b is greater than the length of edge line 743b.

[0202] In short, the length of edge line 762a of test edge region 762 (extending in the Y direction) is less than the length of edge line 743a of edge region 743 (extending in the Y direction), and the length of edge line 762b of test edge region 762 (extending in the X direction) is greater than the length of edge line 743b of edge region 743 (extending in the X direction). The test results of test edge region 762 (e.g., the quality of capacitor 762c) may be better or worse than the test results of edge region 743 of memory element 74. For example, capacitor 762c of edge line 762a (extending in the Y direction) may have different test results compared to capacitor 762c of edge line 762b (extending in the X direction). Therefore, the structure of edge region 743 of memory element 74 can be redesigned based on test edge region 762. Furthermore, based on the test results of test edge region 762, capacitor 742a in edge region 743 of memory element 74 can be redesigned for other purposes (e.g., as a decoupling capacitor). In other words, when the capacitance of capacitor 762c in the test edge region 762 is greater than a predetermined parameter, capacitor 742a in the edge region 743 of memory element 74 may have different functional capabilities.

[0203] Furthermore, the dummy region 761 may not have a memory element 763, and the test results of the test edge region 762 may not be affected by the structure of the dummy region 761.

[0204] Figure 8 A top view schematic diagram illustrating a semiconductor structure 80 according to an embodiment of the present disclosure. (See reference...) Figure 8 In some embodiments, the semiconductor structure 80 includes a semiconductor substrate 82, a memory element 84, and a test structure 86. In some embodiments, the memory element 84 includes a plurality of unit cells 842. Each memory element 842 includes a transistor and a capacitor 842a. In some embodiments, the memory element 84 may include a device region 841 and an edge region 843. The memory element 84 is similar to Figure 1 and Figure 2 For the sake of brevity, repeated details of memory element 14 are omitted.

[0205] The test structure 86 includes a dummy region 861, a test edge region 862, and multiple memory elements 863. The test structure 86 and... Figure 5 The difference between the test structures 56 is that the dimensions of the edge lines 862a (extending along the Y direction) and 862b (extending along the X direction) of the test edge region 862 are both larger than the dimensions of the edge lines 843a (extending along the Y direction) and 843b (extending along the X direction) of the edge region 843. In other words, the lengths of the two edge lines 862a and 862b are both greater than the lengths of the two edge lines 843a and 843b. Furthermore, the memory elements 863 in the test structure 86 are arranged in an array.

[0206] In short, the test results for edge region 862 (e.g., the quality of capacitor 862c) may be better or worse than the test results for edge region 843 of memory element 84. For example, capacitor 862c (extending in the Y direction) on edge line 862a may have different test results compared to capacitor 862c on edge line 862b (extending in the X direction). Therefore, the structure of edge region 843 of memory element 84 can be redesigned based on test edge region 862. Furthermore, based on the test results for edge region 862, capacitor 842a in edge region 843 of memory element 84 can be redesigned for other purposes (e.g., as a decoupling capacitor). In other words, when the capacitance of capacitor 862c in edge region 862 is greater than a predetermined parameter, capacitor 842a in edge region 843 of memory element 84 may have different functional capabilities.

[0207] Furthermore, the dummy region 861 may not contain memory elements 863, and the test results of the test edge region 862 may be unaffected by the structure of the dummy region 861. Additionally, the memory elements 863 of the test structure 86 may be arranged in an array, and the distance between the memory elements 863 and the dummy region 861 can also be considered.

[0208] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0209] Furthermore, the scope of this invention is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this invention that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described in this invention can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this invention.

Claims

1. A semiconductor structure, comprising: A semiconductor substrate; A memory element disposed on the semiconductor substrate, and comprising: A component area; and An edge region, adjacent to the component region; and A test structure, disposed on the semiconductor substrate, includes: A fictitious area; A test edge area, adjacent to the virtual area; and Multiple unit cells, having a first group of unit cells disposed in the dummy region and a second group of unit cells disposed in the test edge region; The second group of unit cells includes the outermost unit cell among the plurality of unit cells. Furthermore, the shape of the edge region enclosed in a top view is different from the shape of the test edge region enclosed in a top view.

2. The semiconductor structure of claim 1, wherein a test edge region edge line in the top view is parallel to an edge region edge line in the top view; and The size of one edge region of the test edge region is larger than the size of another edge region of the test edge region.

3. The semiconductor structure of claim 2, wherein the edge line of the test edge region includes a portion of the second set of unit cells.

4. The semiconductor structure of claim 1, wherein a test edge region edge line in the top view is parallel to an edge region edge line in the top view; and The size of one edge of the test edge region is smaller than the size of another edge of the test edge region.

5. The semiconductor structure of claim 4, wherein the edge line of the test edge region includes a portion of the second set of unit cells.

6. The semiconductor structure of claim 1, wherein the size of the test structure in the top view is different from the size of the memory element in the top view.

7. The semiconductor structure of claim 6, wherein the size of the memory element in the top view is larger than the size of the test structure in the top view.

8. The semiconductor structure of claim 6, wherein the size of the memory element in the top view is smaller than the size of the test structure in the top view.

9. A semiconductor structure, comprising: A semiconductor substrate; A memory element disposed on the semiconductor substrate, and comprising: A component area; and An edge region, adjacent to the component region; and A test structure, disposed on the semiconductor substrate, includes: A fictitious area; A test edge region, surrounding the dummy region; and Multiple unit cells are set in the test edge region, wherein no unit cell is set in the dummy region; The size of the edge region enclosed in a top view is different from the size of the test edge region enclosed in a top view.

10. The semiconductor structure of claim 9, wherein a test edge region edge line in the top view is parallel to an edge region edge line in the top view; and The size of one edge region of the test edge region is larger than the size of another edge region of the test edge region.

11. The semiconductor structure of claim 10, wherein the edge line of the test edge region includes a portion of the plurality of unit cells.

12. The semiconductor structure of claim 9, wherein a test edge region edge line in the top view is parallel to an edge region edge line in the top view; and The size of one edge of the test edge region is smaller than the size of another edge of the test edge region.

13. The semiconductor structure of claim 12, wherein the edge line of the test edge region includes a portion of the plurality of unit cells.

14. The semiconductor structure of claim 9, wherein the edge region in the top view has a larger size than the test edge region in the top view.

15. The semiconductor structure of claim 9, wherein the edge region in the top view has a smaller size than the test edge region in the top view.

16. A semiconductor structure comprising: A semiconductor substrate; A memory element is disposed on the semiconductor substrate and includes a plurality of first unit cells; as well as A test structure is disposed on the semiconductor substrate and includes multiple second unit cells. The arrangement of the first unit cell in a top view is different from the arrangement of the second unit cell in the top view; The memory element also includes an element region and an edge region disposed adjacent to the element region. The test structure also includes a dummy region and a test edge region surrounding the dummy region.

17. The semiconductor structure of claim 16, wherein a first cell arrangement edge of the first unit cell in the top view is parallel to a second cell arrangement edge of the second unit cell in the top view; and The dimension of the first unit cell's first unit cell arrangement boundary is larger than the dimension of the second unit cell's second unit cell arrangement boundary.

18. The semiconductor structure of claim 16, wherein a first cell arrangement edge of the first unit cell in the top view is parallel to a second cell arrangement edge of the second unit cell in the top view; and The size of the first unit cell's first unit cell arrangement boundary is smaller than the size of the second unit cell's second unit cell arrangement boundary.

19. The semiconductor structure of claim 16, wherein the first cell arrangement size in the top view is larger than the second cell arrangement size in the top view.

20. The semiconductor structure of claim 16, wherein the size of the first cell arrangement in the top view is smaller than the size of the second cell arrangement in the top view.

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