Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device that operates at high speed. The semiconductor storage device of the embodiments includes a first chip including a semiconductor substrate, a plurality of transistors, a first wiring, and a plurality of first bonding electrodes, and a second chip including a memory cell array and a plurality of second bonding electrodes. The first chip or the second chip includes a plurality of bonding pad electrodes. The plurality of second bonding electrodes includes a plurality of third bonding electrodes that overlap the memory cell array when viewed in a first direction and are provided in a current path between the memory cell array and the plurality of transistors, and a plurality of fourth bonding electrodes that are not provided in such a current path. The first wiring is electrically connected to any one of the plurality of bonding pad electrodes without passing through any transistor, and is electrically connected to at least one of the plurality of fourth bonding electrodes without passing through any transistor.

Description

[0001] Related applications

[0002] This application claims priority based on Japanese Patent Application No. 2020-139279 (filed on August 20, 2020). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known to have a first chip and a second chip, wherein the first chip has a semiconductor substrate, a plurality of transistors and a plurality of first bonding electrodes, and the second chip has a memory cell array and a plurality of second bonding electrodes bonded to the plurality of first bonding electrodes. Summary of the Invention

[0005] One embodiment provides a semiconductor memory device that operates at high speed.

[0006] A semiconductor memory device according to a technical solution includes: a first chip having a semiconductor substrate, a plurality of transistors, a first wiring and a plurality of first bonding electrodes; and a second chip having a memory cell array and a plurality of second bonding electrodes bonded to the plurality of first bonding electrodes. One of the first and second chips has a plurality of bonding pad electrodes capable of being connected to bonding wires. The plurality of second bonding electrodes includes: a plurality of third bonding electrodes disposed at a position overlapping the memory cell array when viewed from a first direction intersecting the surface of the semiconductor substrate, and disposed in a current path between the memory cell array and the plurality of transistors; and a plurality of fourth bonding electrodes disposed at a position overlapping the memory cell array when viewed from the first direction, and not disposed in a current path between the memory cell array and the plurality of transistors. The first wiring is electrically connected to any of the bonding pad electrodes of the plurality of bonding pad electrodes without passing through any of the plurality of transistors, and is electrically connected to at least one of the plurality of fourth bonding electrodes without passing through any of the plurality of transistors.

[0007] A semiconductor memory device according to a technical solution includes: a first chip having a semiconductor substrate, a plurality of transistors, a first wiring and a plurality of first bonding electrodes; and a second chip having a memory cell array and a plurality of second bonding electrodes bonded to the plurality of first bonding electrodes. One of the first and second chips has a plurality of bonding pad electrodes capable of being connected to bonding wires. The plurality of second bonding electrodes includes: a plurality of third bonding electrodes disposed at a position that does not overlap with the memory cell array when viewed from a first direction intersecting the surface of the semiconductor substrate and overlaps with one of the plurality of bonding pad electrodes; and a plurality of fourth bonding electrodes disposed at a position that does not overlap with the memory cell array when viewed from the first direction and does not overlap with any of the plurality of bonding pad electrodes. The first wiring is electrically connected to any of the plurality of bonding pad electrodes without passing through any of the plurality of transistors, and is electrically connected to at least one of the plurality of fourth bonding electrodes without passing through any of the plurality of transistors.

[0008] A semiconductor memory device according to a technical solution includes: a first chip having a semiconductor substrate, a plurality of transistors, a first wiring and a plurality of first bonding electrodes; and a second chip having a memory cell array and a plurality of second bonding electrodes bonded to the plurality of first bonding electrodes. One of the first chip and the second chip has a plurality of bonding pad electrodes capable of being connected to a bonding wire. The first wiring is electrically connected to any one of the bonding pad electrodes of the plurality of bonding pad electrodes without passing through any of the plurality of transistors, and is electrically connected to a bonding electrode of the plurality of first bonding electrodes and the plurality of second bonding electrodes that is not located in the current path between the first wiring and the bonding pad electrodes without passing through any of the plurality of transistors. Attached Figure Description

[0009] Figure 1 This is a schematic block diagram showing the structure of the storage system 10 according to the first embodiment.

[0010] Figure 2 This is a schematic side view illustrating an example of the structure of the storage system 10.

[0011] Figure 3 This is a schematic top view representing an example of the structure.

[0012] Figure 4 This is a schematic perspective view showing the structure of the memory die (MD) according to the first embodiment.

[0013] Figure 5 This indicates that chip C M A schematic bottom view of the structure example.

[0014] Figure 6 This indicates that chip C M A schematic bottom view of the structure example.

[0015] Figure 7 This indicates that chip C P A schematic top view of a structural example.

[0016] Figure 8 Is with Figure 6 A schematic cross-sectional view corresponding to line A-A′.

[0017] Figure 9 Is with Figure 6 A schematic cross-sectional view corresponding to line B-B′.

[0018] Figure 10 yes Figure 9 A schematic enlarged view of a portion of the structure.

[0019] Figure 11 This is a schematic cross-sectional view showing the structure of a memory die (MD).

[0020] Figure 12 This indicates wiring m T A schematic top view of a structural example.

[0021] Figure 13 This indicates wiring m T A schematic cross-sectional view of a structural example.

[0022] Figure 14 This indicates wiring m T A schematic cross-sectional view of a structural example.

[0023] Figure 15 This is a schematic circuit diagram representing a portion of the structure of a memory die (MD).

[0024] Figure 16 This is a schematic circuit diagram representing a portion of the structure of a memory die (MD).

[0025] Figure 17 This is a schematic circuit diagram representing a portion of the structure of a memory die (MD).

[0026] Figure 18 This is a schematic cross-sectional view showing the structure of a memory die (MD).

[0027] Figure 19 This is a schematic cross-sectional view showing the structure of a memory die (MD). Detailed Implementation

[0028] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention. Additionally, the following drawings are schematic, and for ease of explanation, some structures may be omitted. Furthermore, descriptions of common parts in multiple embodiments may be omitted by assigning the same reference numerals.

[0029] Furthermore, when this specification refers to "semiconductor memory device," it can mean both a bare memory die and a storage system including a memory chip, memory card, SSD (Solid State Drive), and controller die. It can also refer to a structure including a mainframe computer, such as a smartphone, tablet computer, or personal computer.

[0030] Furthermore, in this specification, when referring to the first structure and the second structure as "electrically connected," it can mean that the first structure and the second structure are directly connected, or that the first structure and the second structure are connected via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the off state, the first transistor is still "electrically connected" to the third transistor.

[0031] Furthermore, in this specification, when it is said that the first structure is "connected between" the second and third structures, it means that the first, second, and third structures are connected in series, and the second structure is connected to the third structure via the first structure.

[0032] Furthermore, in this specification, when it is mentioned that a circuit or the like "conducts" two wirings, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is located in the current path between the two wirings, and that the transistor or the like is in a conducting (ON) state.

[0033] Furthermore, in this specification, the direction parallel to the upper surface of the substrate is referred to as the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and the direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0034] Furthermore, in this specification, the direction along a defined surface is referred to as the first direction, the direction along the defined surface intersecting the first direction is referred to as the second direction, and the direction intersecting the defined surface is referred to as the third direction. These first, second, and third directions may or may not correspond to one of the X, Y, and Z directions.

[0035] Furthermore, in this specification, the terms "upper" and "lower," etc., are used with reference to the semiconductor substrate. For example, the direction away from the semiconductor substrate along the Z direction is called "upper," and the direction approaching the semiconductor substrate along the Z direction is called "lower." Additionally, when referring to a structure as a lower surface or lower end, it means the surface or end of the structure on the semiconductor substrate side; when referring to an upper surface or upper end, it means the surface or end of the structure on the opposite side from the semiconductor substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0036] [First Implementation]

[0037] [Storage System 10]

[0038] Figure 1 This is a schematic block diagram showing the structure of the storage system 10 according to the first embodiment.

[0039] The storage system 10 reads, writes, and deletes user data based on signals sent from the host computer 20. The storage system 10 may be, for example, a memory chip, memory card, SSD, or other system capable of storing user data. The storage system 10 includes multiple memory dies (MDs) for storing user data and a controller die (CD) connected to these multiple memory dies and the host computer 20. The controller die (CD) may include, for example, a processor and RAM, and performs processing such as logical address to physical address translation, bit error detection / correction, garbage collection (compression), and wear leveling.

[0040] Figure 2 This is a schematic side view showing an example of the structure of the storage system 10 according to this embodiment. Figure 3 This is a schematic top view illustrating this structural example. For ease of explanation, in Figure 2 and Figure 3 A portion of the structure has been omitted.

[0041] like Figure 2 As shown, the storage system 10 of this embodiment includes a mounting substrate MSB, a plurality of memory dies MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory dies MD. Bonding pad electrodes P are provided in the region at the end in the Y direction on the upper surface of the mounting substrate MSB. X The remaining portion is bonded to the lower surface of the memory die MD using adhesives or similar bonding agents. On the upper surface of the memory die MD, bonding pad electrodes P are provided in the region at the end in the Y direction. X Other areas are bonded to the lower surface of other memory dies (MD) or controller dies (CD) using adhesives or similar bonding agents. On the upper surface of the controller die (CD), bonding pad electrodes P are provided in the region at the end in the Y direction.X .

[0042] like Figure 3 As shown, the mounting substrate MSB, multiple memory dies MD, and controller die CD each have multiple bonding pad electrodes P arranged in the X direction. X Multiple bonding pad electrodes P are disposed on the mounting substrate MSB, multiple memory dies MD, and controller die CD. X They are connected to each other via junction line B.

[0043] in addition, Figure 2 and Figure 3 The structure shown is merely an example; the actual structure can be adjusted accordingly. For example, in Figure 2 and Figure 3 In the example shown, a controller die CD is stacked on top of multiple memory dies MD, and these structures are connected by bonding wires B. In such a structure, multiple memory dies MD and controller die CD are contained within a single package. However, the controller die CD may also be contained in a different package than the memory dies MD. Furthermore, the multiple memory dies MD and controller die CD may also be interconnected via through electrodes or the like, instead of bonding wires B.

[0044] [Construction of Memory Die (MD)]

[0045] Figure 4 This is a schematic exploded perspective view showing an example of the structure of the semiconductor memory device according to this embodiment. Figure 4 As shown, the memory die MD has a chip C including a memory cell array MCA. M And chip C, including peripheral circuits P .

[0046] In chip C M The upper surface is provided with multiple bonding pad electrodes P X Furthermore, in chip C M The lower surface is provided with multiple bonding electrodes P I1 Furthermore, in chip C P The upper surface is provided with multiple bonding electrodes P I2 The following is about chip C. M Multiple bonding electrodes P will be provided. I1 The surface is called the surface, and multiple bonding pad electrodes P will be provided thereon. X The side facing out is called the back side. Furthermore, regarding the chip C... P Multiple bonding electrodes P will be provided. I2 The side facing out is called the surface, and the side opposite the surface is called the back face. In the example shown, chip C P The surface is set on the chip CP On the back, near the top, chip C M The back is located on the chip C M The surface is on the upper part.

[0047] Chip C M and chip C P With chip C M Surface and chip C P The surfaces are arranged in an opposing manner. Multiple bonding electrodes P are arranged in a manner that allows for surface-to-surface orientation. I1 With multiple bonding electrodes P I2 Each is configured to correspond to a specific electrode P, and can be configured to fit with multiple electrodes P. I2 The bonding location. Bonding electrode P I1 and bonding electrode P I2 As used to connect chip C M With chip C P The bonding electrode, which is attached and electrically conductive, performs its function. Bonding pad electrode P X As a reference Figure 2 and Figure 3 The pad electrode P is described as functioning correctly.

[0048] In addition, Figure 4 In the example, chip C M The corners a1, a2, a3, and a4 are respectively connected to chip C P The corners b1, b2, b3, and b4 correspond.

[0049] Figure 5 This indicates that chip C M A schematic bottom view of the structure example. Figure 6 This indicates that chip C M A schematic bottom view of a structural example, showing a structure with multiple bonding electrodes P. I1 chip C M The surface depends on the internal structure. Figure 7 This indicates that chip C P A schematic top view of a structural example. Figure 8 Is with Figure 6 A schematic cross-sectional view corresponding to line A-A′. Figure 9 Is with Figure 6 A schematic cross-sectional view corresponding to line B-B′. Figure 10 yes Figure 9 A schematic enlarged view of a portion of the structure.

[0050] [Chip C] M [Construction]

[0051] Chip C M For example, Figure 6As shown, an array region R has four memory cells arranged in the X and Y directions. MCA Storage cell array region R MCA The storage port area R is equipped with storage units. MH and relative to the storage hole region R MH Let it be on one side in the X direction (e.g.) Figure 6 (left side) and the other side (e.g.) Figure 6 Wiring area R (on the right side of the middle) HU In addition, chip C M Equipped with four memory cell array regions R MCA The outer region (in the example shown, it is the region R of two memory cell arrays arranged in the Y direction) MCA The area between, the storage cell array area R MCA With chip C M The region between the ends in the Y direction and the memory cell array region R MCA With chip C M The peripheral region R in the region between the ends in the X direction P In addition, in the surrounding area R P Part of it, provided with multiple bonding pad electrodes P X ( Figures 2-4 The corresponding input / output circuit area R is set up. IO .

[0052] Additionally, in the illustrated example, the hookup area R HU Relative to the storage hole region R MH This is assumed to be on one side and the other side in the X direction. However, this structure is merely an example, and the specific structure can be adjusted accordingly. For example, the wiring area R... HU It can also be set in the memory cell array region R MCA The central position or the position near the center in the X direction.

[0053] Chip C M For example, Figure 8 and Figure 9 As shown, it has a matrix layer L SB Let L be the base layer SB The lower storage cell array layer L MCA and set in the memory cell array layer L MCA The multiple wiring layers below it are 140, 150, and 160.

[0054] [Chip C] M The base layer L SB [Construction]

[0055] For example, Figure 8As shown, the matrix layer L SB It includes a semiconductor layer 100, an insulating layer 101 disposed on the upper surface of the semiconductor layer 100, and an insulating layer 102 disposed on the upper surface of the insulating layer 101. Furthermore, for example, Figure 9 As shown, in the input / output circuit region R IO In the middle, there is a bonding pad electrode P disposed between the insulating layer 101 and the insulating layer 102. X .

[0056] The semiconductor layer 100 is, for example, a silicon (Si) semiconductor layer implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). Furthermore, a metal such as tungsten (W) or a silicide such as tungsten silicide (WSi) may be provided between the semiconductor layer 100 and the insulating layer 101. Additionally, the semiconductor layer 100 is provided in multiple regions that are spaced apart from each other in the X or Y direction. For example, the semiconductor layer 100 is provided in regions adjacent to a reference layer. Figure 6 The four memory cell array regions R described above MCA The corresponding 4 areas.

[0057] The insulating layer 101 is an insulating layer made of an insulating material such as silicon oxide (SiO2). The insulating layer 101 is, for example, a... Figure 8 and Figure 9 As shown, the upper surface and side surfaces of the semiconductor layer 100, as well as those contained in the memory cell array layer L, are... MCA The upper surface of the insulating layer 103, such as silicon dioxide (SiO2), is completely covered.

[0058] The insulating layer 102 is a passivation layer made of an insulating material such as polyimide.

[0059] Bonding pad electrode P X Contains conductive materials such as aluminum (Al). Bonding pad electrode P X For example, Figure 9 As shown, it includes an external connection region 104 disposed on the upper surface of the semiconductor layer 100 through an insulating layer 101, and a memory cell array layer L. MCA The internal connection area 105 is provided on the upper surface of the insulating layer 103.

[0060] External connection area 104 is connected to junction line B ( Figure 2 , Figure 3 The area to be connected. In the insulating layer 102, at least a portion of the portion corresponding to the external connection area 104 is provided with an opening. The external connection area 104 is exposed in a region outside the memory die MD through this opening.

[0061] Internal connection region 105 is connected to the memory cell array layer L. MCAThe area connected by the contact portion 112. In addition, the internal connection area 105 is located below the external connection area 104.

[0062] [Chip C] M Storage cell array layer L MCA [Construction]

[0063] For example, Figure 9 As shown, in the storage cell array layer L MCA Storage cell array region R MCA The device includes a memory cell array (MCA). The memory cell array (MCA) has multiple memory blocks (BLK) arranged in the Y direction and inter-block insulating layers (106) of silicon oxide (SiO2) or the like disposed between these multiple memory blocks (BLK).

[0064] The storage hole region R contained in the storage block BLK MH The portion includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120. Figure 10 ).

[0065] Conductive layer 110, for example, Figure 8 As shown, a generally plate-shaped conductive layer extends in the X direction. The conductive layer 110 may also include a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Furthermore, the conductive layer 110 may, for example, include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 111, such as silicon oxide (SiO2), is provided between the plurality of conductive layers 110 arranged along the Z direction. These plurality of conductive layers 110 function, for example, as word lines and gate electrodes of a plurality of memory cells connected thereto.

[0066] The semiconductor layer 120 functions, for example, as a channel region for multiple memory cells. The semiconductor layer 120 is, for example, a polysilicon (Si) semiconductor layer. The semiconductor layer 120 has, for example, a generally cylindrical shape. Furthermore, the outer peripheral surfaces of the semiconductor layer 120 are each surrounded by a conductive layer 110, which is opposite to the conductive layer 110.

[0067] At the lower end of the semiconductor layer 120, there is an impurity region (not shown) containing N-type impurities such as phosphorus (P). This impurity region is connected to the bit line BL via contact 121 and contact 122.

[0068] At the upper end of the semiconductor layer 120, there is an impurity region (not shown) containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). This impurity region is connected to the semiconductor layer 100.

[0069] Gate insulating film 130 ( Figure 10 The gate insulating film 130 has a generally bottomed cylindrical shape that covers the outer peripheral surface of the semiconductor layer 120. The gate insulating film 130 includes a channel insulating film 131, a charge accumulation film 132, and a block insulating film 133 stacked between the semiconductor layer 120 and the conductive layer 110. The channel insulating film 131 and the block insulating film 133 are insulating films such as silicon oxide (SiO2). The charge accumulation film 132 is a film capable of accumulating charge, such as silicon nitride (Si3N4). The channel insulating film 131, the charge accumulation film 132, and the block insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120.

[0070] In addition, Figure 10 The diagram illustrates an example where the gate insulating film 130 comprises a charge accumulation film 132 such as silicon nitride. However, the gate insulating film 130 may also comprise a floating gate such as polysilicon containing N-type or P-type impurities.

[0071] The wiring area R contained in the storage block BLK HU For example, the parts in Figure 8 As shown, it has an end in the X direction of a plurality of conductive layers 110 arranged in the Z direction, and a plurality of contact portions 112 extending in the Z direction.

[0072] Conductive layer 110 in wiring area R HU The structure forms a roughly stepped shape. That is, the lower the conductive layer 110 is, the further away its end in the X direction is from the storage hole region R. MH The closer to the conductive layer 110 located on top, the further away the end of its X-direction portion is from the storage hole region R. MH The farther away.

[0073] The contact portion 112 includes a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The contact portion 112 has, for example, a generally cylindrical shape. The upper ends of the plurality of contacts 112 are respectively connected to different conductive layers 110. In addition, the lower ends of the plurality of contacts 112 are respectively connected to different wirings 141.

[0074] In addition, the storage cell array layer L MCA Input / output circuit area R IO For example, Figure 9 As shown, the device includes multiple contact portions 112 extending in the Z direction. The upper ends of these multiple contact portions 112, as described above, respectively connect to the bonding pad electrode P. X The lower surface of the internal connection area 105 is connected. In addition, multiple contacts 112 are connected to wiring 141 at their lower ends.

[0075] [Chip C] M [Construction of wiring layers 140, 150, and 160]

[0076] Multiple wirings included in wiring layers 140, 150, and 160, for example, with memory cell array layer L MCA The structure and chip C in P At least one of the structures in the structure is electrically connected.

[0077] Wiring layer 140 includes a plurality of wirings 141. These plurality of wirings 141 may, for example, comprise a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). Furthermore, a portion of the plurality of wirings 141 functions as bit lines BL. Bit lines BL, for example, are... Figure 8 Arranged in the X direction as shown, as Figure 9 As shown, they extend in the Y direction. Furthermore, these multiple bit lines BL are respectively connected to multiple semiconductor layers 120.

[0078] The wiring layer 150 includes a plurality of wirings 151. These plurality of wirings 151 may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0079] Wiring layer 160 includes multiple bonding electrodes P I1 These multiple bonded electrodes P I1 For example, it may also include barrier conductive films such as titanium nitride (TiN) and laminated films of metal films such as copper (Cu).

[0080] Here, as Figure 5 As shown, in the wiring area R HU Multiple bonding electrodes P are provided in the middle. I1 These multiple bonded electrodes P I1 By reference Figure 8 The contact portion 112, as described above, is electrically connected to the conductive layer 110.

[0081] In addition, such as Figure 5 As shown, in the storage hole region R MH The module is divided into regions R1 and R2. Region R1 is the region of the readout amplifier module, which will be described later, when viewed from the Z direction. SAM ( Figure 7 The overlapping region. Region R2 is the region that does not overlap with the readout amplifier module region R (described later) when viewed from the Z direction. SAM ( Figure 7 (overlapping areas)

[0082] like Figure 5 As shown, multiple bonding electrodes P are provided in region R1. I1 These multiple bonded electrodes PI1 Electrically connected to bit line BL.

[0083] In addition, such as Figure 5 As shown, multiple bonding electrodes P are also provided in region R2. I1 .

[0084] In addition, such as Figure 5 As shown, in the input / output circuit region R IO Multiple bonding electrodes P are provided in the middle. I1 These multiple bonded electrodes P I1 By reference Figure 9 The contact portion 112 described herein is connected to the bonding pad electrode P. X Electrical connection.

[0085] In addition, such as Figure 5 As shown, in the surrounding area R P Input / output circuit area R IO Multiple bonding electrodes P are also provided in areas other than the main area. I1 .

[0086] [Chip C] P [Construction]

[0087] Chip C P For example, Figure 7 As shown, it has four memory cell array regions R MCA ( Figure 6 The four circuit regions R are set at the corresponding positions. PC Circuit region R PC Equipped with storage hole area R MH ( Figure 6 The sense amplifier module region R is located at a position corresponding to a portion of the position. SAM And in the two wiring areas R HU The line decoder region R is set at the corresponding position. RD In addition, chip C P Possesses chip C M The surrounding area R P ( Figure 6 The corresponding surrounding area R is set. P and chip C M Multiple input / output circuit regions R IO ( Figure 6 The corresponding multiple input / output circuit regions R are set up. IO .

[0088] In addition, chip C P For example, Figure 8 and Figure 9As shown, the semiconductor substrate 200 includes a transistor layer L disposed above the semiconductor substrate 200. TR and located in transistor layer L TR The multiple wiring layers above it are 220, 230, 240, and 250.

[0089] [Chip C] P [Structure of semiconductor substrate 200]

[0090] The semiconductor substrate 200 is, for example, a semiconductor substrate made of p-type silicon (Si) containing p-type impurities such as boron (B). On the surface of the semiconductor substrate 200, a semiconductor substrate region 200S and an insulating region 200I are provided.

[0091] [Chip C] P transistor layer L TR [Construction]

[0092] An electrode layer 210 is provided on the upper surface of the semiconductor substrate 200, separated by an insulating layer 200G. The electrode layer 210 includes a plurality of electrodes 211 facing the surface of the semiconductor substrate 200. Furthermore, the plurality of electrodes 211 contained in each region of the semiconductor substrate 200 and in the electrode layer 210 are respectively connected to the contact portion 201.

[0093] The semiconductor substrate region 200S of the semiconductor substrate 200 functions as a channel region for multiple transistors Tr that constitute peripheral circuits.

[0094] The plurality of electrodes 211 contained in the electrode layer 210 function as gate electrodes of a plurality of transistors Tr constituting a peripheral circuit. The electrode 211 has a semiconductor layer such as polycrystalline silicon (Si) containing, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), and a metal layer such as tungsten (W) provided on the upper surface of the semiconductor layer.

[0095] The contact portion 201 extends in the Z direction and is connected at its lower end to the upper surface of the semiconductor substrate 200 or the electrode 211. The contact portion 201 may, for example, include a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0096] In addition, the multiple transistors Tr disposed on the semiconductor substrate 200 each constitute part of the peripheral circuit.

[0097] For example, set in the line decoder region R RD ( Figure 7The multiple transistors Tr constitute part of a line decoder that selectively transfers voltage to one of the multiple conductive layers 110. A portion of the multiple transistors Tr constituting the line decoder functions as word line switches that are not connected to the conductive layer 110 via other transistors Tr.

[0098] Furthermore, for example, in the sense amplifier module region R SAM ( Figure 7 The multiple transistors Tr in the sense amplifier module constitute part of a sense amplifier module that measures the voltage or current of multiple bit lines BL and selectively transfers the voltage to one of the multiple bit lines BL. A portion of the multiple transistors Tr constituting the sense amplifier module functions as a bit line switch connected to the bit line BL without passing through other transistors Tr.

[0099] Furthermore, for example, let R be the input / output circuit region. IO ( Figure 7 Multiple transistors Tr in the ) are connected via multiple bonding pad electrodes P X An input / output circuit, as part of a larger circuit, functions to input and output user data, command data, or address data. A portion of the multiple transistors Tr that constitute the input / output circuit acts as a connection to the bonding pad electrode P without passing through other transistors Tr. X A portion of the connected pull-up circuit, pull-down circuit, or comparator functions as a whole.

[0100] [Chip C] P [Construction of wiring layers 220, 230, 240, 250]

[0101] Multiple wirings included in wiring layers 220, 230, 240, and 250, for example, with transistor layer L TR The structure and chip C in M At least one of the structures in the structure is electrically connected.

[0102] Wiring layer 220 includes a plurality of wirings 221. These plurality of wirings 221 may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0103] The wiring layer 230 includes a plurality of wirings 231. These plurality of wirings 231 may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0104] Wiring layer 240 includes a plurality of wirings 241. These plurality of wirings 241 may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0105] Wiring layer 250 includes multiple bonding electrodes PI2 These multiple bonded electrodes P I2 For example, it may also include barrier conductive films such as titanium nitride (TiN) and laminated films of metal films such as copper (Cu).

[0106] Here, as Figure 7 As shown, in the line decoder region R RD Multiple bonding electrodes P are provided in the middle. I2 These multiple bonded electrodes P I2 By reference Figure 9 The contact portion 201, as described above, is electrically connected to the transistor Tr that constitutes the line decoder. Furthermore, it is connected via the bonding electrode P. i1 It is electrically connected to the conductive layer 110.

[0107] In addition, such as Figure 7 As shown, in the readout amplifier module region R SAM Multiple bonding electrodes P are provided in the middle. I2 These multiple bonded electrodes P I2 By reference Figure 9 The contact portion 201, as described above, is electrically connected to the transistor Tr that constitutes the sense amplifier module. Furthermore, it is connected via the bonding electrode P. i1 Electrically connected to bit line BL.

[0108] In addition, such as Figure 7 As shown, in circuit region R PC When viewed from the Z direction, it corresponds to the aforementioned region R2 ( Figure 5 The overlapping region R3 also has multiple bonding electrodes P. I2 .

[0109] In addition, such as Figure 7 As shown, in the input / output circuit region R IO Multiple bonding electrodes P are provided in the middle. I2 These multiple bonded electrodes P I2 By reference Figure 9 The contact portion 201, as described above, is electrically connected to the transistor Tr, which constitutes the input / output circuit. Furthermore, it is connected via the bonding electrode P. i1 With bonding pad electrode P X Electrical connection.

[0110] In addition, such as Figure 7 As shown, in the surrounding area R P Input / output circuit area R IO Multiple bonding electrodes P are also provided in areas other than the main area. I2 .

[0111] [Heat dissipation structure of memory die MD]

[0112] If read, write, or delete operations are performed on the memory die MD, then chip C P The transistor Tr in the memory generates heat. Here, it is preferable to suppress the temperature of the transistor Tr to below a predetermined level. Therefore, in the memory die MD, the temperature of the transistor Tr is monitored, and the operating speed of the memory die MD is suppressed if the temperature reaches a predetermined threshold.

[0113] In such a structure, it is difficult to make the memory die (MD) operate at high speed continuously for a long time.

[0114] Therefore, the memory die MD of this embodiment has a heat dissipation structure for efficiently releasing the heat of the transistor Tr to the outside of the memory die MD. This heat dissipation structure is, for example, as shown in... Figure 11 As shown, a wiring m is provided near the transistor Tr. T Without passing through any transistor Tr on the memory die MD and with wiring m T Electrical connection bonding pad electrode P XT and wiring m without passing through any transistor Tr on the memory die MD. T Electrically connected bonding electrode P I1T P I2T .

[0115] With this configuration, the heat generated by transistor Tr can be dissipated using nearby wiring m. T Absorption, via bonding pad electrode P XT and joint line B ( Figure 2 , Figure 3 Released to the outside of storage system 10.

[0116] Furthermore, based on this structure, it is possible to utilize multiple bonded electrodes P that are relatively large in volume and include materials such as copper (Cu) which have good heat absorption properties. I1T P I2T The heat generated by the transistor Tr will be absorbed efficiently.

[0117] The following section discusses the wiring m in the heat dissipation structure. T , bonding pad electrode P XT and bonding electrode P I1T P I2T Please provide an explanation.

[0118] [Wiring m] T ]

[0119] Wiring m T It is one of the multiple wiring 221 mentioned above.

[0120] Wiring m TPreferably, it is placed near a transistor Tr that generates a relatively large amount of heat. Examples of such a transistor Tr include those constituting a charge pump circuit C. CP ( Figure 12 The transistor Tr and the input / output circuit C constitute the input / output circuit. IO ( Figure 12 Transistors such as Tr and others constitute a charge pump circuit C. CP Transistor Tr, for example Figure 12 As shown, there is a case where the wiring is located in the aforementioned region R3. In this case, it is preferable to place the wiring m... T It is located in region R3. Furthermore, the charge pump circuit C is formed. CP For example, transistor Tr has Figure 12 As shown, it is set in the surrounding area R P Input / output circuit area R IO The situation outside the designated areas. In this case, it is preferable to route the wiring m T It is set in such an area. Furthermore, the transistors Tr that constitute the input / output circuits are, for example, as... Figure 12 As shown, there is a circuit in the input / output circuit region R. IO In this situation, it is preferable to route the wiring m. T Set in the input / output circuit area R IO middle.

[0121] In addition, wiring m T For example, it can also be like Figure 13 As shown, it is connected to the semiconductor substrate region 200S of the semiconductor substrate 200 via the contact portion 201. Furthermore, such a region on the semiconductor substrate region 200S may be, for example, a region that does not function as part of the transistor Tr.

[0122] In addition, wiring m T For example, it can also be like Figure 14 It is connected to an electrode 211 as shown. Furthermore, such an electrode 211 may also be a region that functions as a non-transistor Tr.

[0123] according to Figure 13 or Figure 14 The illustrated structure can substantially reduce wiring m T The distance from the transistor Tr. Furthermore, since the semiconductor substrate 200 conducts heat, the heat generated by the transistor Tr can also be absorbed via the semiconductor substrate 200. Therefore, heat absorption can be achieved more efficiently.

[0124] [Joint pad electrode P] XT ]

[0125] Bonding pad electrode PXT These are the multiple bonding pad electrodes P mentioned above. X one of the.

[0126] For example, the aforementioned multiple bonding pad electrodes P X This includes: bonding pad electrodes used for supplying ground voltage, bonding pad electrodes used for supplying operating voltages higher than ground voltage, bonding pad electrodes used for data or clock signal input, and bonding pad electrodes used for controlling the memory die (MD). Bonding pad electrode P XT For example, multiple bonding pad electrodes P used for supplying ground voltage. X one of the.

[0127] [Attached electrode P] I1T P I2T ]

[0128] Adhesive electrode P I1T P I2T These are the multiple bonding electrodes P mentioned above. I1 P I2 one of the.

[0129] For example, Figure 5 As shown, in chip C M The surface is provided with multiple bonding electrodes P I1 In addition, for example, Figure 7 As shown, in chip C P The surface is provided with multiple bonding electrodes P I2 These multiple bonded electrodes P I1 P I2 As described above, a portion of these components is disposed in the current path between the configuration of the memory cell array MCA (e.g., conductive layer 110, bit line BL, and semiconductor layer 100) and the transistor Tr. Furthermore, these plurality of bonding electrodes P... I1 P I2 A portion of it is disposed on the bonding pad electrode P as described above. X In the current path between the transistor Tr and the electrode P. In this embodiment, these bonding electrodes P I1 P I2 In addition to multiple bonding electrodes P I1 P I2 At least a portion of it is used as bonding electrode P I1T .

[0130] As used as bonding electrode P I1T bonding electrode P I1 For example, we can cite examples where... Figure 5 Multiple bonded electrodes P in region R2 I1 At least a part of it, or located in the surrounding area RP Input / output circuit area R IO Multiple bonding electrodes P in areas other than I1 At least a part of it.

[0131] As used as bonding electrode P I2T bonding electrode P I2 For example, we can cite examples where... Figure 7 Multiple bonded electrodes P in region R3 I2 At least a part of it, or located in the surrounding area R P Input / output circuit area R IO Multiple bonding electrodes P in areas other than I2 At least a part of it.

[0132] Furthermore, as described above, the bonding electrode P I1T P I2T Without passing through any transistor Tr on the memory die MD and with wiring m T and bonding pad electrode P XT Electrical connection.

[0133] Here, multiple bonding electrodes P I1T P I2T At least a part of it can also be, for example, Figure 15 As illustrated, it is set up in wiring m T With bonding pad electrode P XT In the current path between.

[0134] In this case, for example, it can also be like Figure 15 and Figure 11 As shown, the lower end of any contact electrode is attached to multiple bonding electrodes P. I1T At least a portion of the upper surface is connected via the contact electrode, the bonding electrode P I1T Electrically connected to any of the wirings 151 or 141. Alternatively, the upper end of any contact electrode can be attached to the attached electrode P. I1T bonding electrode P I2T The lower surface is connected via the contact electrode, the bonding electrode P I2T Electrically connected to either wiring 241 or 231.

[0135] In addition, multiple bonding electrodes P I1T P I2T At least a part of it can also be, for example, Figure 16 or Figure 17 As illustrated, suppose there is wiring m T With bonding pad electrode P XT In the current path between.

[0136] In this case, for example, it can also be like Figure 16 and Figure 18 As shown, multiple bonding electrodes P will be used. I1T The contact electrode connected to at least a portion of the upper surface is omitted. Alternatively, the upper end of any contact electrode may be attached to the bonding electrode P. I1T bonding electrode P I2T The lower surface is connected via the contact electrode, the bonding electrode P I2T Electrically connected to either wiring 241 or 231.

[0137] Furthermore, in this case, for example, it is also possible to... Figure 17 and Figure 19 As shown, the lower end of any contact electrode is connected to multiple bonding electrodes P. I1T At least a portion of the upper surface is connected via the contact electrode, the bonding electrode P I1T Electrically connected to any of the wirings 151, 141. Alternatively, it can be attached to the bonding electrode P. I1T bonding electrode P I2T The contact electrode connected to the lower surface is omitted.

[0138] [Other implementation methods]

[0139] The semiconductor memory device according to the first embodiment has been described above. However, this structure is merely an example, and the specific structure can be adjusted accordingly.

[0140] For example, in the first embodiment, chip C M Chip C has three wiring layers: 140, 150, and 160. P It has four wiring layers: 220, 230, 240, and 250. However, this structure is merely an example; the specific structure can be adjusted accordingly. For instance, it could be set at chip C... M The number of wiring layers can also be 4 or more, set in chip C P The number of wiring layers can also be 5 or more.

[0141] Furthermore, for example in the first embodiment, the bonding pad electrode P X Chip C, which contains the memory cell array MCA, is configured M However, this structure is merely an example; the specific structure can be adjusted accordingly. For example, the bonding pad electrode P... X It can also be set in chip C, which contains peripheral circuitry. P .

[0142] [other]

[0143] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit and scope of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are also included within the scope of the invention as described in the claims and its equivalents.

[0144] Label Explanation

[0145] C M C P …chip; MCA…memory cell array; P X …joint pad electrodes; m T …wiring; P I1 P I2 …attached electrodes.

Claims

1. A semiconductor memory device, wherein, have: The first chip includes a semiconductor substrate, multiple transistors, a first wiring, and multiple first bonding electrodes; and The second chip includes a memory cell array and multiple second bonding electrodes attached to the aforementioned multiple first bonding electrodes. One of the first chip and the second chip described above has a plurality of bonding pad electrodes that can be connected to bonding wires. The aforementioned plurality of second bonding electrodes include: A plurality of third bonding electrodes are disposed at positions overlapping the memory cell array when viewed from a first direction intersecting the surface of the semiconductor substrate, and are disposed in the current path between the memory cell array and the plurality of transistors; and Multiple fourth bonding electrodes are disposed at positions overlapping with the memory cell array when viewed from the first direction, and are not disposed in the current path between the memory cell array and the multiple transistors. The first wiring is electrically connected to any one of the plurality of bonding pad electrodes and to at least one of the plurality of fourth bonding electrodes. The first wiring is not electrically connected to any one of the plurality of transistors. The first wiring is located between a pair of transistors in a direction parallel to the surface of the semiconductor substrate.

2. A semiconductor memory device, wherein, have: The first chip includes a semiconductor substrate, multiple transistors, a first wiring, and multiple first bonding electrodes; and The second chip includes a memory cell array and multiple second bonding electrodes attached to the aforementioned multiple first bonding electrodes. One of the first chip and the second chip described above has a plurality of bonding pad electrodes that can be connected to bonding wires. The aforementioned plurality of second bonding electrodes include: Multiple third bonding electrodes are disposed at positions that do not overlap with the memory cell array when viewed from a first direction intersecting the surface of the semiconductor substrate, but overlap with one of the multiple bonding pad electrodes; and Multiple fourth bonding electrodes are positioned at locations that do not overlap with the memory cell array when viewed from the first direction and do not overlap with any of the multiple bonding pad electrodes. The first wiring is electrically connected to any one of the plurality of bonding pad electrodes and to at least one of the plurality of fourth bonding electrodes. The first wiring is not electrically connected to any one of the plurality of transistors. The first wiring is located between a pair of transistors in a direction parallel to the surface of the semiconductor substrate.

3. A semiconductor memory device, wherein, have: The first chip includes a semiconductor substrate, multiple transistors, a first wiring, and multiple first bonding electrodes; and The second chip includes a memory cell array and multiple second bonding electrodes attached to the aforementioned multiple first bonding electrodes. One of the first chip and the second chip described above has a plurality of bonding pad electrodes that can be connected to bonding wires. The first wiring is electrically connected to any one of the plurality of bonding pad electrodes, and is also electrically connected to a bonding electrode among the plurality of first bonding electrodes and the plurality of second bonding electrodes that is not located in the current path between the first wiring and the bonding pad electrode. The first wiring is not electrically connected to any one of the plurality of transistors. The first wiring is located between a pair of transistors in a direction parallel to the surface of the semiconductor substrate.

4. The semiconductor memory device according to any one of claims 1 to 3, wherein, The aforementioned multiple bonding pad electrodes have: The first bonding pad electrode is supplied with a ground voltage; The second bonding pad electrode is supplied with a driving voltage that is greater than the aforementioned grounding voltage. as well as The third bonding pad electrode is supplied with a signal. The first wiring is electrically connected to the first bonding pad electrode without passing through any of the plurality of transistors.

5. The semiconductor memory device according to any one of claims 1 to 3, wherein, The aforementioned first chip has multiple wiring layers. The first wiring is included in the wiring layer that is closest to the semiconductor substrate among the plurality of wiring layers.

6. The semiconductor memory device of claim 5, wherein, It has a first contact electrode, which is disposed between the first wiring and the semiconductor substrate and is connected to the first wiring and the semiconductor substrate.

7. The semiconductor memory device of claim 5, wherein, have: A first electrode is disposed between the first wiring and the semiconductor substrate, and faces the semiconductor substrate; and The second contact electrode is disposed between the first wiring and the first electrode, and is connected to both the first wiring and the first electrode.

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