Microelectronic devices including semiconductive pillar structures and related methods and electronic systems

Abstract

This application relates to microelectronic devices including semiconductive pillar structures and related methods and electronic systems. A microelectronic device includes a semiconductive pillar structure including a central portion, a first end portion, and a second end portion on an opposite side of the central portion from the first end portion, the first end portion oriented at an angle relative to the central portion and extending substantially parallel to the second end portion; a digit line contact on the central portion of the semiconductive pillar structure; a first storage node contact on the first end portion; and a second storage node contact on the second end portion. Related microelectronic devices, electronic systems, and methods are also described.

Description

[0001] Priority Claim

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 16 / 992,589 filed August 13, 2020, and titled “MICROELECTRONIC DEVICES INCLUDING SEMICONDUCTIVE PILLAR STRUCTURES, AND RELATED METHODS AND ELECTRONIC SYSTEMS.”

[0003] Priority Claim

[0004] This application is related to U.S. Patent Application No. 16 / 992,615 filed August 13, 2020, and titled “MICROELECTRONIC DEVICES INCLUDING SEMICONDUCTIVE PILLAR STRUCTURES, AND RELATED METHODS AND ELECTRONIC SYSTEMS.” TECHNICAL FIELD

[0005] In various embodiments, the present disclosure relates generally to the field of microelectronic device design and fabrication. More specifically, the present disclosure relates to methods of forming microelectronic devices including semiconductive pillar structures, and to related microelectronic devices and electronic systems. BACKGROUND

[0006] Semiconductor device designers often desire to increase the level of integration or density of features within a semiconductor device by reducing the size of individual features and by reducing the separation distance between adjacent features. Additionally, semiconductor device designers often desire to design architectures that are not only compact, but that also provide performance advantages and simplify design.

[0007] A relatively common semiconductor device is a memory device. A memory device can include a memory array having a number of memory cells arranged in a grid pattern. One type of memory cell is a dynamic random access memory (DRAM). In the simplest design configuration, a DRAM cell includes one access device (e.g., a transistor) and one storage device (e.g., a capacitor). Modern applications of memory devices can utilize a large number of DRAM unit cells arranged in arrays of rows and columns. DRAM cells can be electrically accessed through digit lines and word lines arranged along the rows and columns of the array.

[0008] Decreasing the size and spacing of memory device features places increasing demands on methods used to form memory device features. For example, one of the limiting factors in the continued scaling of memory devices is the unintended shorting between contacts associated with various components of a DRAM cell. As used herein, a "contact" refers to a connection that facilitates a conductive path between at least two structures. For example, in a DRAM device exhibiting a dual bit memory cell structure, a digit line contact is disposed between a digit line and an access device (e.g., a transistor) formed in or on a substrate, and a storage node contact is formed between the access device and a storage node (e.g., a capacitor) in which charge can be stored. As the size of memory device (e.g., DRAM device) features decreases, the packing density of contacts associated therewith increases, resulting in an increased likelihood of unintentionally shorting the various components together, which can adversely affect the performance of the memory device. In some examples, a digit line contact can unintentionally contact a storage node contact, thereby electrically shorting the digit line to the storage node and causing the memory cell associated with the storage node to fail. SUMMARY

[0009] In some embodiments, a microelectronic device includes a semiconductive pillar structure including a central portion, a first end portion, and a second end portion on an opposite side of the central portion from the first end portion, the first end portion being oriented at an angle relative to the central portion and extending substantially parallel to the second end portion; a digit line contact on the central portion of the semiconductive pillar structure; a first storage node contact on the first end portion; and a second storage node contact on the second end portion.

[0010] In other embodiments, a method of forming a microelectronic device includes forming first spacers extending along a first direction; forming second spacers adjacent to the first spacers, the first spacers being between two second spacers, adjacent second spacers being separated by a first trench extending along the first direction; forming a second trench extending along a second direction to form an isolation structure including a portion of the first spacers between portions of the second spacers; forming a sacrificial material within the first trench and the second trench; removing portions of the sacrificial material from intersections of the first trench and the second trench along a first lateral direction to form an elongated opening; forming an oxide material in the elongated opening; removing the sacrificial material to form a pattern of pillar structures; and transferring the pattern of pillar structures to a semiconductive material to form a semiconductive pillar structure.

[0011] In yet other embodiments, a method of forming a microelectronic device, the method comprising: forming an isolation structure comprising a silicon-containing material and an oxide material on sides of the silicon-containing material, the isolation structure separated by a first trench extending along a first direction and a second trench extending along a second direction; forming a sacrificial material in at least a portion of the first trench and the second trench; removing at least some of the sacrificial material at intersections of the first trench and the second trench to form an elongated opening; filling the elongated opening with an additional oxide material; selectively removing the silicon-containing material and the sacrificial material relative to the oxide material and the additional oxide material; removing portions of semiconductive material exposed by remaining portions of the oxide material and the additional oxide material to form semiconductive pillar structures; and forming a storage node contact on an end portion of at least one of the semiconductive pillar structures and a digit line contact on a central portion of the at least one semiconductive pillar structure.

[0012] In further embodiments, an electronic system comprises: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising at least one microelectronic device. The at least one microelectronic device comprises: semiconductive pillar structures, each semiconductive pillar structure comprising a central portion electrically coupled to a bit line contact and located between end portions electrically coupled to storage node contacts; and a word line oriented at an angle relative to the end portions and located between and separating the bit line contact and the storage node contacts. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figures 1A to 1S is a simplified partial top-down view of a method of forming a microelectronic device structure according to embodiments of the present disclosure Figure 1A , Figure 1C , Figures 1F to 1J , Figure 1L , Figure 1M and Figure 1P are simplified partial cross-sectional views of a method of forming a microelectronic device structure according to embodiments of the present disclosure Figure 1B , Figure 1D , Figure 1K , Figure 1N , Figure 1O and Figures 1Q to 1S ;

[0014] Figure 2 is a block diagram of an electronic system according to embodiments of the present disclosure; and

[0015] Figure 3 is a block diagram of a processor-based system according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] The accompanying drawings are not intended to be actual views of any particular system, microelectronic structure, microelectronic device, or integrated circuit thereof, but are merely idealized representations which are utilized to describe the embodiments herein. Elements and features common to the drawings can retain the same number across the drawings, but the reference numbers begin with the number of the drawing on which the element is first introduced or most fully described for ease of the following description.

[0017] The following description provides specific details, such as material types, material thicknesses, and processing conditions, in order to provide a thorough description of the embodiments described herein. However, a person of ordinary skill in the art will understand that the embodiments disclosed herein can be practiced without employing these specific details. Indeed, the described embodiments can be practiced in conjunction with conventional manufacturing technology employed in the semiconductor industry. In addition, the description provided herein is not a complete process flow for manufacturing a microelectronic device (e.g., a memory device such as a DRAM memory device, a 3D NAND flash memory device), or a complete microelectronic device. The structures described below do not form a complete microelectronic device. Only those process acts and structures necessary for understanding the embodiments described herein are described in detail below. Additional acts performed to form a complete microelectronic device from the structures can be performed by conventional techniques.

[0018] The materials described herein can be formed by conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD). Alternatively, the materials can be grown in situ. Depending on the particular material to be formed, a person of ordinary skill in the art can select the technique for depositing or growing the material. Removal of materials can be accomplished by any suitable technique, including but not limited to etching, abrasive planarization (e.g., chemical mechanical planarization), or other known methods, unless the context indicates otherwise.

[0019] As used herein, the term“configured” refers to the size, shape, material composition, orientation, and arrangement of one or more of the structures and devices to facilitate operation of one or more of the structures and devices in a predetermined manner.

[0020] As used herein, the terms "longitudinal," "vertical," "lateral," and "horizontal" are with reference to a major surface of a substrate (e.g., base material, base structure, base construction, etc.) in or on which one or more structures and / or features are formed and are not necessarily defined by the Earth's gravitational field. A "lateral" or "horizontal" direction is a direction substantially parallel to a major plane of the substrate, while a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the major plane of the substrate. The major plane of the substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate.

[0021] As used herein, the term "substantially" with respect to a given parameter, property, or condition, means and includes the degree of such fulfillment of the given parameter, property, or condition as would be understood by one of ordinary skill in the art to be acceptable. For example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition can be at least 90.0% met, at least 95.0% met, at least 99.0% met, at least 99.9% met, or even 100.0% met.

[0022] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes the numerical value and a degree of deviation from the numerical value that would be understood by one of ordinary skill in the art to be within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value can include additional numerical values that are within a range from 90.0% to 110.0% of the numerical value, such as within a range from 95.0% to 105.0% of the numerical value, within a range from 97.5% to 102.5% of the numerical value, within a range from 99.0% to 101.0% of the numerical value, within a range from 99.5% to 100.5% of the numerical value, or within a range from 99.9% to 100.1% of the numerical value.

[0023] As used herein, spatial relative terms, such as "under", "below", "lower", "bottom", "over", "upper", "top", "front", "back", "left", "right", and the like, can be used for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatial relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if a material in the figures is inverted, elements described as "under" or "below" other elements or features would then be oriented "over" the other elements or features. Thus, the term "under" can encompass both an orientation of over and under, depending on the context in which the term is used. The materials can be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped) and the spatial relative descriptors used herein interpreted accordingly.

[0024] As used herein, features (e.g., regions, materials, structures, devices) described as being "adjacent" to one another mean and include features of the disclosed identity(ies) positioned closest (e.g., nearest, next to) to one another. Additional features (e.g., additional regions, additional materials, additional structures, additional devices) that do not match the disclosed identity(ies) of the "adjacent" features can be disposed between the "adjacent" features. In other words, "adjacent" features can be positioned directly next to one another, such that no other features intervene between the "adjacent" features; or the "adjacent" features can be positioned indirectly adjacent to one another, such that at least one feature having an identity different from the identity(ies) associated with at least one of the "adjacent" features is positioned between the "adjacent" features. Thus, features described as being "vertically adjacent" to one another mean and include features of the disclosed identity(ies) positioned closest vertically (e.g., nearest vertically, vertically next to) to one another. Moreover, features described as being "horizontally adjacent" to one another mean and include features of the disclosed identity(ies) positioned closest horizontally (e.g., nearest horizontally, horizontally next to) to one another.

[0025] As used herein, the term "memory device" means and includes microelectronic devices that exhibit memory functionality, but are not necessarily limited to memory functionality. In other words, and by way of example only, the term "memory device" means and includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application specific integrated circuits (ASICs) (e.g., systems on a chip (SoCs)), microelectronic devices that are combinations of logic and memory, and graphics processing units (GPUs) that incorporate memory.

[0026] As used herein, “conductive material” means and includes conductive materials, such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., Co The term "conductive structure" refers to and includes structures formed from and containing conductive materials, such as basic alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co and Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, and stainless steel. It also includes conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, and conductive metal oxides) and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), and conductive doped silicon-germanium (SiGe)). Furthermore, "conductive structure" indicates and includes structures formed from conductive materials and containing conductive materials.

[0027] As used herein, “insulating material” means and includes electrically insulating materials, such as one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus glass, fluorosilicone glass, alumina (AlO) x ), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide material (e.g., silicon oxynitride (SiO) x N y and at least one dielectric carbonitride material (e.g., silicon oxynitride (SiO2)). x C z N y This text contains formulas that include one or more of "x", "y", and "z" (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiOx N y SiO x C z N y This indicates a material containing, for each atom of another element (e.g., Si, Al, Hf, Nb, Ti), an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if any). Because the formula represents relative atomic ratios rather than strict chemical structures, insulating materials can include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if any) can be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes compounds composed of elements that cannot be expressed by a ratio of well-defined natural numbers and violate the law of definite proportions. Additionally, "insulating structure" means and includes structures formed from and containing insulating materials.

[0028] As used herein, “selectively removable” material means and includes materials that exhibit a greater removal rate in response to the same process conditions relative to another material exposed to process conditions (e.g., exposure to radiation (e.g., heat)). A material that is selectively removable relative to another material can be removed substantially completely without removing substantially any portion of the other material (e.g., without removing substantially any portion of the other material).

[0029] As used herein, "selectively etchable" material means and includes materials that exhibit a greater etching rate than another material exposed to a given etching chemical and / or process condition in response to the same etching chemical and / or process condition. For example, the material may exhibit an etching rate at least about five times greater than that of another material, such as about ten times, about twenty times, or about forty times greater. Those skilled in the art can select the etching chemical and etching conditions used for selectively etching the desired material.

[0030] According to embodiments described herein, a microelectronic device includes: a semiconducting pillar structure (e.g., an elongated semiconducting pillar structure having a length greater than its width); the elongated semiconducting pillar structure including bit line contact areas laterally disposed between two memory node contact areas. The bit line contact areas are electrically connected to bit line contacts, which in turn are electrically connected to bit lines extending along a first lateral direction. Each of the memory node contact areas is individually electrically connected to a memory node contact, and each of the memory node contacts is electrically connected to a memory node (e.g., a capacitor, which may also be referred to herein as a unit capacitor). Each semiconducting pillar structure may include: a central portion including the bit line contact areas; a first end portion at a first end of the central portion; and a second end portion at a second opposite end of the central portion. The first end portion includes a first of the memory node contact areas, and the second end portion includes a second of the memory node contact areas. The central portion may extend along the first lateral direction and includes a longitudinal axis substantially parallel to the bit lines. In other words, the central portion may elongate along the direction in which the bit lines extend. Each of the first and second end portions includes a longitudinal axis oriented at an angle relative to the longitudinal axis of the central portion. In other words, each of the first and second end portions extends at an angle relative to the central portion. In some embodiments, the semiconducting strut structure exhibits a so-called "S" shape.

[0031] Orienting the first and second end portions at an angle relative to the central portion increases the distance between the memory node contact area and the bit line contact area of ​​the semiconductive pillar structure, thereby reducing the likelihood of accidental short circuits between such features compared to conventional microelectronic devices. Additionally, orienting the first and second end portions at an angle relative to the central portion increases the effective area of ​​the semiconductive pillar structure (e.g., increasing the effective area of ​​each of the bit line contacts and the memory node contacts). Furthermore, forming the end portions at an angle relative to the central portion increases the area (e.g., larger boundaries) for forming the bit line contacts on the bit line contact area and for forming spacers along the bit lines, which can reduce capacitive coupling between the bit lines. In some embodiments, the shape of the semiconductive pillar structure reduces (e.g., eliminates) the overlap between the word line structure and the bit line contact area of ​​the semiconductive pillar structure compared to conventional pillar structures. In some embodiments, forming the first and second end portions at an angle relative to the central portion increases the mechanical stability (and reduces tipping) of the semiconductive pillar structure compared to conventional pillar structures exhibiting a linear shape. In addition, the distance between so-called through-line structures that are vertically overlaid on the semiconducting support structure but not electrically coupled to it can be increased, thereby reducing accidental coupling between adjacent line segments and so-called "line hammering".

[0032] The microelectronic device can be formed by patterning first and second spacers adjacent to a base material (e.g., on or above the base material), the first and second spacers extending along a first lateral direction. For example, the first spacer can be formed on the base material by a pitch doubling process, and the second spacer can be formed on a side of each of the first spacers. A first trench can be located between adjacent second spacers. A second trench can be formed through the first and second spacers along a second lateral direction to form an isolation structure, each isolation structure including a portion of the first spacer between portions of the second spacers. Sacrificial material can be formed within the first and second trenches and between the isolation structures. In some embodiments, an opening can be retained within the intersection point between the first and second trenches. Sacrificial material can be selectively removed (e.g., relative to the first and second spacers) from the intersection point and between adjacent isolation structures. In some embodiments, the sacrificial material is selectively (e.g., preferentially) removed along a third lateral direction. The elongated opening is filled with material bridging the second spacers of the first isolation structure and the second spacers of the second isolation structure. The material filling the elongated opening exhibits etch selectivity relative to the material of the first spacer and the sacrificial material. The first spacer and sacrificial material are selectively removed to form a pattern of the pillar structure from portions of the second spacer and the material filling the elongated opening. The pattern of the pillar structure is transferred to a base material to form the semiconductive pillar structure. Digital line contacts may be formed on the central portion of each half-conductive pillar structure, and memory node contacts may be formed on each end portion of each half-conductive pillar structure. Digital lines extending in a third lateral direction may be configured to be electrically connected to the digital line contacts, and memory node structures may be configured to be electrically connected to the memory node contacts.

[0033] Figures 1A to 1S This is a simplified partial top view illustrating a method for forming a microelectronic device (e.g., a memory device, such as a DRAM device) according to embodiments of the present disclosure. Figure 1A , Figure 1C , Figures 1F to 1J , Figure 1L , Figure 1M and Figure 1P ) and simplified partial cross-sectional view ( Figure 1B , Figure 1D , Figure 1K , Figure 1N , Figure 1O and Figures 1Q to 1S From the description provided below, it will be readily apparent to those skilled in the art that the methods described herein can be used in a variety of devices. In other words, the methods of this disclosure can be used whenever it is desired to form a microelectronic device comprising an elongated pillar structure.

[0034] Common Reference Figure 1A and Figure 1B The microelectronic device structure 100 may include: a base material 102; an etch stop material 104 adjacent to the base material 102 (e.g., on, above, or vertically covering the base material 102); and a first line 105 of a photoresist material 106 adjacent to the etch stop material 104 (e.g., on, above, or vertically covering the etch stop material 104). A first spacer 108 may be formed on the side of the first line 105 of the photoresist material 106. Figure 1B It is intercepted through the cross-section line BB. Figure 1A A simplified cross-sectional view of the microelectronic device structure 100.

[0035] refer to Figure 1A The first line 105 of the photoresist material 106 may extend at an angle relative to a first lateral direction (e.g., the X direction), wherein one or more features of the microelectronic device structure 100 (e.g., word lines 164) will be formed. Figure 1M , Figure 1N As will be described herein. For example, the longitudinal axis L1 of the first line 105 may be oriented at a first angle α relative to the X direction. The first angle α may be greater than about 0 (0) degrees and less than about 90 (90) degrees relative to the first lateral direction, for example, in the range of about 20 (20) degrees to about 70 (70) degrees, about 30 (30) degrees to about 60 (60) degrees, or about 40 (40) degrees to about 50 (50) degrees. The first angle α may be selected at least in part based on the desired architecture of the microelectronic device structure 100 and the desired dimensions of the features formed from the base material 102, as will be described below. In some embodiments, the first angle α is about 41 (41) degrees.

[0036] The base material 102 may include a semiconductor substrate, a base semiconductor material on a support substrate, a metal electrode, or a semiconductor substrate on which one or more materials, structures, or regions are formed. The base material 102 may include a semiconducting material, such as a conventional silicon substrate or other bulk substrate containing semiconductor material. As used herein, the term "bulk substrate" refers not only to and includes silicon wafers but also to silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") or silicon-on-glass ("SOG") substrates, silicon epitaxial layers on a base semiconductor substrate, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si... 1- x Ge xWhere x is, for example, a mole fraction between 0.2 and 0.8, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), etc. Furthermore, when "substrate" or "base material" is mentioned in the following description, the material, region, or junction may have been formed in the base semiconductor structure or substrate using prior process stages. Base material 102 may comprise one or more materials associated with integrated circuit manufacturing. Such materials may comprise one or more of, for example, refractory metals, barrier materials, diffusion materials, and insulating materials. Base material 102 may comprise, for example, a complementary metal-oxide-semiconductor (CMOS) structure or other semiconductor structures. Different portions of base material 102 may be electrically isolated from each other by one or more dielectric materials.

[0037] The etch stop material 104 may be formed of and comprise one or more materials exhibiting etch selectivity with respect to various mask materials (e.g., spacer materials), as described herein. As a non-limiting example, the etch stop material 104 may exhibit etch selectivity with respect to various materials, such as sacrificial materials (e.g., amorphous carbon) and dielectric materials (e.g., silicon dioxide, silicon nitride). The etch stop material 104 may be formed of and comprise one or more of the following: metal nitrides (e.g., titanium nitride, tungsten nitride, tantalum nitride, aluminum nitride), metal oxides (e.g., aluminum oxide, titanium oxide, tungsten oxide, tantalum oxide, hafnium oxide, zirconium oxide), oxynitride materials, silicon carbon oxynitride, silicon carbonitride materials, amorphous carbon, or another material. In some embodiments, the etch stop material 104 comprises titanium nitride.

[0038] The photoresist material 106 may be formed from one or more of the following and includes one or more of the following: a 193 nm photoresist material, a 248 nm photoresist material, or a photoresist material sensitive to radiation of different wavelengths. The photoresist material 106 may be a positive or negative photoresist material, a photopolymerizable photoresist material, a photodegradable photoresist material, or a photocrosslinked photoresist material. Photoresist materials, such as positive and negative resists, are known in the art and therefore will not be described in detail herein.

[0039] Each of the first lines 105 of the photoresist material 106 may have substantially the same width W1 (e.g., a small lateral dimension) and may be regularly spaced by substantially the same distance. Therefore, the pitch between the centerlines of adjacent first lines 105 may be substantially uniform throughout the photoresist material 106. The size and spacing of the first lines 105 may be selected to provide the desired lateral dimensions and lateral spacing to features subsequently formed from the base material 102, as will be further described below.

[0040] The width W1 can be in the range of about 20 nm to about 50 nm, for example, from about 20 nm to about 30 nm, from about 30 nm to about 40 nm, or from about 40 nm to about 50 nm. However, this disclosure is not limited thereto and the width W1 may be different from the width described above.

[0041] The first spacer 108 may extend as a line substantially parallel to the first line 105 of the photoresist material 106. The first spacer 108 may be formed and comprised of a material exhibiting etch selectivity relative to one or more oxide materials (e.g., silicon dioxide) and one or more nitride materials (e.g., silicon nitride, titanium nitride). In some embodiments, the first spacer 108 is formed and comprises amorphous silicon, such as hydrogenated amorphous silicon. The material of the first spacer 108 may be formed adjacent to the first line 105 and patterned using conventional techniques to form the first spacer 108.

[0042] In some embodiments, forming the first spacers 108 on the sides of the first lines 105 of the photoresist material 106 can be performed using a so-called "pitch doubling" process, wherein the pitch of the photoresist material 106 is halved by forming the first spacers 108 on the sides of the first lines 105. In other words, the microelectronic device structure 100 may include two first spacers 108 for each of the first lines 105, thereby facilitating a reduction in the pitch of the first lines 105.

[0043] refer to Figure 1C and Figure 1D The photoresist material 106 can be removed (e.g., stripped) from the surface of the microelectronic device structure 100. Figure 1A , Figure 1B The first line 105 ( Figure 1A , Figure 1B This leaves the pattern of the first spacer 108. After removing the photoresist material 106, a second spacer 110 can be formed on the side of the first spacer 108. The material of the second spacer 110 can be formed by conventional techniques to be adjacent to and patterned to form the second spacer 110. Thus, two second spacers 110 can be formed for each of the first spacers 108 (and four second spacers 110 can be formed for each of the first lines 105). Therefore, the formation of the second spacers 110 may be referred to herein as a so-called "pitch quadruple" process, since there are four second spacers 110 for each first line 105.

[0044] The second spacer 110 may be formed of and comprise one or more materials exhibiting etch selectivity relative to the first spacer 108. As a non-limiting example, the second spacer 110 may be formed of and comprise an oxide material (e.g., a dielectric oxide material), such as silicon dioxide. In some embodiments, the second spacer 110 comprises silicon dioxide.

[0045] A first trench 115 may be located between adjacent second spacers 110. Etch-stop material 104 may be exposed at the lower portion of the first trench 115 (e.g., along the Z-direction). The width W2 of the first trench 115 between adjacent second spacers 110 may range from about 5 nanometers (nm) to about 20 nm, for example, from about 5 nm to about 10 nm, from about 10 nm to about 15 nm, or from about 15 nm to about 20 nm. However, this disclosure is not limited thereto, and the width W2 may differ from the width described above.

[0046] In some embodiments, the width W2 can be selected and customized to influence the size and shape of one or more features to be formed in the microelectronic device structure 100, as will be described herein. For example, the width W2 can at least partially determine the spacing between one or more features to be formed in the microelectronic device structure 100.

[0047] Since the first spacer 108, the second spacer 110, and the first groove 115 are substantially parallel to the first line 105 ( Figure 1A , Figure 1B The longitudinal axis of the first spacer 108, the second spacer 110, and the first groove 115 can extend in the same direction as the longitudinal axis L1. Therefore, the reference to the longitudinal axis L1 in this document refers to the direction in which the first spacer 108, the second spacer 110, and the first groove 115 extend.

[0048] refer to Figure 1E A mask (e.g., a chopping mask) can be used to form and pattern a second line 112 of the third spacer 114 on the microelectronic device structure 100. The second line 112 may run along a path different from the first photoresist material 106. Figure 1A , Figure 1B The first line 105 ( Figure 1A , Figure 1B The first lateral direction extends into the second lateral direction.

[0049] The second line 112 may extend at a second angle β relative to the directions in which the first spacer 108 and the second spacer 110 extend. In other words, the longitudinal axis L2 of the second line 112 may be oriented at a second angle β relative to the longitudinal axis L1 of the first spacer 108 and the second spacer 110.

[0050] The second angle β may be in the range of about 70° to about 90°, for example, from about 70° to about 75°, from about 75° to about 80°, from about 80° to about 85°, or from about 85° to about 90°. In some embodiments, the second angle β is about 82°. However, the invention is not limited thereto, and the first angle α may be different from the angle described above.

[0051] The second line 112 of the third spacer 114 may be formed and comprise one or more materials exhibiting etch selectivity relative to the first spacer 108 and the second spacer 110. As a non-limiting example, the third spacer 114 may be formed and comprise a dielectric nitride, such as silicon nitride, aluminum nitride, oxide nitride, photoresist material, or one or more of another material. In some embodiments, the third spacer 114 comprises silicon nitride.

[0052] The second line 112 can be patterned, for example, by forming lines of a second photoresist material on the microelectronic device structure 100. After forming the lines of the second photoresist material, the lines of the second photoresist material can be exposed to etching (e.g., trimming) chemicals to form the desired spacing between adjacent lines of the second photoresist material and to form the desired width of the lines. A third spacer 114 can be formed on the side of the lines of the second photoresist material, and the lines of the second photoresist material can be removed (e.g., stripped), as referenced above to the first photoresist material 106 ( Figure 1A , Figure 1B The first line 105 ( Figure 1A , Figure 1B The removal of ) is discussed.

[0053] The distance D1 between the third spacers 114 may be in the range of about 30 nm to about 60 nm, for example, from about 30 nm to about 40 nm, from about 40 nm to about 50 nm, or from about 50 nm to about 60 nm. However, this disclosure is not limited thereto and the distance D1 may be different from the distance described above.

[0054] refer to Figure 1F After the pattern of the second line 112 of the third spacer 114 is formed, the third spacer 114 can be used as a mask to transfer the pattern of the third spacer 114 to the underlying portion of the microelectronic device structure 100. For example, and as a non-limiting example, a sacrificial material can be formed between the third spacers 114 and the third spacers 114 can be removed to expose portions of the first spacers 108 and the second spacers 110. The exposed portions of the first spacers 108 and the second spacers 110 can be removed through openings in the sacrificial material to form a second trench 116 at a position corresponding to the location of the third spacer 114. For ease of understanding, Figure 1FWhile the etch stop material 104 is not explicitly described, it should be understood that the etch stop material 104 may be located at the lower portion of the second trench 116. In other words, the second trench 116 may extend into the etch stop material 104.

[0055] Each of the second trenches 116 may have a width W3 in the range of about 30 nm to about 60 nm, for example, from about 30 nm to about 40 nm, from about 40 nm to about 50 nm, or from about 50 nm to about 60 nm. In some embodiments, the second trench 116 has a width W2 greater than that of the first trench 115. Figure 1C , Figure 1D The width W3 of the second groove 116 is approximately the same as the width W2 of the first groove 115. However, this disclosure is not limited thereto, and the width W3 of the second groove 116 may differ from the described width.

[0056] As mentioned above, refer to the width W2 of the first groove 115 ( Figure 1C , Figure 1D As described herein, the width W3 of the second trench 116 can be selected to influence the size and shape of one or more features to be formed in the microelectronic device structure 100, as will be described herein.

[0057] Removal of portions of the exposed portions of the first spacer 108 and the second spacer 110, and the formation of the second trench 116, can form an isolation structure 125, each isolation structure 125 comprising a portion of the first spacer 108 between portions of the two second spacers 110. In some embodiments, the isolation structure 125 comprises amorphous silicon located between silicon dioxide. In some such embodiments, silicon dioxide may be located on a first side of the amorphous silicon and additional silicon dioxide may be located on a second opposing side of the amorphous silicon. The isolation structure 125 may extend vertically (e.g., along the Z direction) over the first trench 115 and the second trench 116.

[0058] Now for reference Figure 1G In forming the second trench 116 ( Figure 1F After that, it can be placed in the first trench 115 ( Figure 1F Sacrificial material 118 is formed within the second trench 116 and the first spacer 108. Sacrificial material 118 may be at least partially located between portions of the first spacer 108 and the second spacer 110 of the isolation structure 125. For example, sacrificial material 118 may be located between and separate different isolation structures 125 within the isolation structure 125. As will be described herein, one or more features of the microelectronic device structure 100 may be relative to the longitudinal axis L1 ( Figure 1E ) and vertical axis L2 ( Figure 1E (The image is) patterned at a certain angle. For clarity and ease of understanding, Figure 1GAnd subsequent figures are described as relative to Figures 1A to 1F A view of the microelectronic device structure 100 rotated.

[0059] In some embodiments, the groove formed in the first trench 115 can be removed. Figure 1F ) and the second trench 116 ( Figure 1F The portion of the sacrificial material 118 outside the first trench 115 and the upper surface of the second trench 110. For example, the microelectronic device structure 100 may be exposed to a CMP process to remove the portion of the sacrificial material 118 outside the first trench 115 and the second trench 116, such that the upper surface of the sacrificial material 118 is substantially coplanar with the upper surfaces of the first trench 108 and the second trench 110.

[0060] The sacrificial material 118 may be formed of and comprise one or more materials exhibiting etch selectivity relative to the first spacer 108 and the second spacer 110. In some embodiments, the sacrificial material 118 comprises the third spacer 114 (referenced above). Figure 1E One or more of the materials described herein. In some embodiments, the sacrificial material 118 comprises the same material composition as the third spacer 114. In some embodiments, the sacrificial material 118 comprises silicon nitride.

[0061] The sacrificial material 118 may be formed by one or more of CVD, ALD, PVD, LPCVD, PECVD, spin coating, blanket coating, or other methods. In some embodiments, the sacrificial material 118 is formed by ALD or CVD.

[0062] After the sacrificial material 118 is formed, the opening 120 (e.g., gap, space, void) may be retained in the first groove 115. Figure 1F ) and the second trench 116 ( Figure 1F The opening 120 is formed at the intersection point 122 of the first groove 115 and the second groove 116 by the so-called "pinching" of the sacrificial material 118 during the formation of the sacrificial material 118 within the first groove 115 and the second groove 116. For example, and without being limited by any particular theory, due to the width W2 of the first groove 115 ( Figure 1C , Figure 1D ) and the width W3 of the second groove 116 Figure 1F The distance between the opposite diagonal corners 124 of the intersection point 122 (e.g., opposite corners of diagonally adjacent isolation structures 125) is less than that between the opposite corners of the intersection point 122, so that the opening 120 can be formed during the formation (e.g., deposition) of the sacrificial material 118. In some embodiments, since the opening 120 is located substantially at the central portion of the intersection point 122, the opening 120 may be referred to as a “self-aligned” opening.

[0063] The opening 120 may have a substantially elliptical (e.g., substantially circular, substantially oval), rectangular, square, triangular, cross-shaped, or other cross-sectional shape. In some embodiments, the opening 120 is substantially circular. In other embodiments, the opening 120 is substantially oval. The size and shape of the opening 120 may be at least partially determined by the first groove 115 ( Figure 1F The width W2 () Figure 1C , Figure 1D ) and the second trench 116 ( Figure 1F The width W3 () Figure 1F )Influence.

[0064] Figure 1G Box A illustrates an enlarged portion of the microelectronic device structure 100. Referring to box A, opening 120 may be substantially located within the first trench 115. Figure 1F ) and the second trench 116 ( Figure 1F At the central part of the intersection point 122 of )

[0065] As described above, in some embodiments, the distance D8 between the relative corners 124 of the relative isolation structures 125 may be greater than the distance D8 between the first trenches 115 and the relative corners 124 of the isolation structures 125. Figure 1F The width W2 () Figure 1C , Figure 1D ) and the second trench 116 ( Figure 1F The width W3 () Figure 1F In some embodiments, the distance D8 is in the range of about 30 nm to about 60 nm, for example, from about 30 nm to about 40 nm, from about 40 nm to about 50 nm, or from about 50 nm to about 60 nm. However, this disclosure is not limited thereto and the distance D8 may be different from the distance described above.

[0066] In some embodiments, oxide material (not shown) may be formed on the outer portion of the sacrificial material 118. As a non-limiting example, in some embodiments, oxide material may be formed on the exposed portion of the sacrificial material 118 after the sacrificial material 118 has been formed.

[0067] Now for reference Figure 1H The microelectronic device structure 100 may be exposed to one or more material removal processes via opening 120 ( Figure 1G An elongated opening 126 is formed. In some embodiments, the opening 120 may selectively elongate along one or more directions (e.g., the Y direction) relative to other directions (e.g., the X direction). In some embodiments, the elongated opening 126 may have a dimension along a first direction (e.g., the Y direction) that is larger than the corresponding dimension of the opening 120 along the same direction. The elongated opening 126 may have a dimension along a second direction (e.g., the X direction) that is substantially the same as the corresponding dimension of the opening 120 along the same direction.

[0068] In some embodiments, each elongated opening 126 extends from one of the isolation structures 125 to an adjacent isolation structure 125. For example, each elongated opening 126 may extend along the Y direction from the upper one of the second spacers 110 of the isolation structure 125 (in Figure 1H In the view; for example, along the Y direction) extending to one of the adjacent second spacers 110 in the isolation structure 125. In other words, an elongated opening 126 may extend from one of the second spacers 112 of the isolation structure 125 across the second groove 116 ( Figure 1F And to the nearest second spacer 112 of the other in the isolation structure 125.

[0069] In some embodiments, the elongated opening 126 is brought closer to the opening 120 by means of a condition configured to preferentially remove sacrificial material 118 along one lateral direction (e.g., the Y direction) relative to another lateral direction (e.g., the X direction). Figure 1G The sacrificial material 118 is exposed to one or more etchants to form the opening 126. In some embodiments, the elongated opening 126 is formed by exposing the microelectronic device structure 100 to one or more dry etchants (e.g., plasma) directed in the Y direction rather than the X direction to the opening 120. In other words, the dry etchant may be directed in the Y direction and may have no velocity in the X direction or may have a velocity in the X direction that is substantially less than the velocity of the dry etchant in the Y direction. In some such embodiments, the opening 120 may elongate in the direction in which the dry etchant is oriented (e.g., the Y direction) without substantially increasing the size of the opening 120 in another direction (e.g., the X direction). In other words, the opening 120 may be preferentially etched in the Y direction relative to the X direction.

[0070] refer to Figure 1I An elongated opening 126 may be filled with an oxide material 128. The oxide material 128 may extend from one of the second spacers 110 of one of the isolation structures 125 to the nearest (e.g., closest) second spacer 110 of an adjacent (e.g., along the Y direction; diagonally adjacent) spacer 110 of the isolation structure 125. For example, the oxide material may extend from a corner 124 of the intersection point 122 (…). Figure 1G The isolation structure at the intersection 122 extends to another isolation structure 125 at the diagonally opposite corner 124 of the intersection 122. In some embodiments, the oxide material 128 may contact the second spacer 110 of the isolation structure 125. In other words, in some embodiments, the oxide material 128 may be in contact with the second spacer 110 of the isolation structure 125 corresponding to the first trench 115. Figure 1F ) and the second trench ( Figure 1F At the location of the first trench 115 and the second trench 116 (e.g., at the intersection of the first trench 115 and the second trench 116), it bridges across the sacrificial material 118 and can extend diagonally across the intersection 122.

[0071] The oxide material 128 may be formed of and comprise one or more oxide materials. The oxide material 128 may be formulated to exhibit etch selectivity relative to the sacrificial material 118 and the first spacer 108. In some embodiments, the oxide material 128 comprises silicon dioxide. In some embodiments, the oxide material 128 comprises the same material composition as the second spacer 110.

[0072] The oxide material 128 and the second spacer 110 connected by one of the oxide materials 128 can be formed into a so-called “S”-shaped structure with rounded (e.g., arcuate) edges. As will be described herein, the oxide material 128 and the second spacer 110 can be used to form (e.g., pattern) a semiconducting pillar structure on which one or more features will be formed.

[0073] refer to Figure 1J and Figure 1K The sacrificial material 118 can be selectively removed relative to the second spacer 110 and the oxide material 128. Figure 1I ) and the first spacer 108 ( Figure 1I This leaves a pattern of pillar structures 130, each pillar structure 130 individually including a central portion 132 located between the end portions 134. In other words, each pillar structure 130 may include a first end portion 134, a central portion 132, and a second end portion 134 located on the side of the central portion 132 opposite to the first end portion 134. Figure 1K Is it through Figure 1J The cross-section line KK cuts Figure 1J A simplified partial cross-sectional view of the microelectronic device structure 100.

[0074] In some embodiments, the strut structure 130 is formed by exposing the microelectronic device structure 100 to one or more etchants formulated and configured to selectively remove the sacrificial material 118 and the first spacer 108 while substantially not removing the second spacer 110 or the oxide material 128. As a non-limiting example, the microelectronic device structure 100 may be exposed to a plasma comprising one or more of methane (CH4), trifluoromethane (CHF3) (also known as chloroform), difluoromethane (CH2F2), sulfur hexafluoride (SF6), or another material to selectively remove the sacrificial material 118 and the first spacer 108 relative to the second spacer 110 and the oxide material 128. In other embodiments, the microelectronic device structure 100 is exposed to a wet etchant, such as phosphoric acid, to selectively remove the sacrificial material 118 and the first spacer 108 relative to the second spacer 110 and the oxide material 128.

[0075] refer to Figure 1L 130 column structureFigure 1J The pattern of the support structure 130 can be used as a mask and can be transferred to the etch stop material 104. Figure 1K The patterned etch stop material 104' and the base material 102 are used to form a patterned etch stop material and a patterned base material 102'. The patterned etch stop material can be used to transfer the pattern of the pillar structure 130 onto the base material 102 to form a semiconductive pillar structure 140, each of the semiconductive pillar structures 140 individually including a central portion 142 and an end portion 144, as described above with reference to the central portion 132 and the end portion 144 of the pillar structure 130. For example, the microelectronic device structure 100 may be exposed to a formulation and configuration for selective removal of the etch stop material 104' without substantially removing the second spacer 110. Figure 1J ) or oxide material 128 ( Figure 1J One or more etchants. As a non-limiting example, the etch stop material 104 may be exposed to a plasma containing one or more of xenon difluoride (XF2), chlorine (Cl2) (e.g., a mixture of Cl2, nitrogen (N2), and argon (Ar), fluorine (F2), nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), hydrogen fluoride (HF), or another material. However, the invention is not limited thereto, and the etch stop material 104 may be removed by methods different from those described above.

[0076] In the column structure 130 ( Figure 1J After the pattern of the patterned etch stop material 104 is transferred to the etch stop material 104, a patterned etch stop material can be used to transfer the pattern of the patterned etch stop material to the underlying base material 102 to form a semiconductive pillar structure 140 (e.g., an elongated semiconductive pillar structure). The semiconductive pillar structure 140 may include rounded edges and correspond to the effective area of ​​the microelectronic device structure 100. As a non-limiting example, a portion of the base material 102 exposed by the patterned etch stop material may be removed (e.g., partially removed) to transfer the first trench 115 and the second trench 116 into the base material 102 and form the pattern of the semiconductive pillar structure 140.

[0077] The semiconductive strut structure 140 may exhibit an elongated shape having a length (e.g., along the longitudinal axis of the central portion 142 and the longitudinal axis of the end portion 144), said length being greater than the width of the semiconductive strut structure 140 along a direction substantially perpendicular to said length. The semiconductive strut structure 140 may include curved (e.g., bow-shaped) sides. Since the end portion 144 is angled relative to the central portion 142, the orientation of the semiconductive strut structure 140 may be non-linear.

[0078] Adjacent semiconducting pillar structures 140 may be spaced apart from each other by a first trench 115 and a second trench 116. The end portion 144 of the semiconducting pillar structure 140 may be oriented at a first angle α relative to a first lateral direction (e.g., the X direction) along which one or more features of the microelectronic device structure 100 will be formed. In other words, the longitudinal axis L3 of the end portion 144 may be oriented at a first angle α relative to the first lateral direction.

[0079] The third angle θ between the longitudinal axis L3 of the end portion 144 and the longitudinal axis L4 of the central portion 142 can be greater than about zero (0) degrees and less than about ninety (90) degrees, for example, in the range of about twenty (20) degrees to about seventy (70) degrees, about thirty (30) degrees to about sixty (60) degrees, or about forty (40) degrees to about fifty (50) degrees. In some embodiments, the third angle θ is about forty-nine (49) degrees.

[0080] In some embodiments, the first trench 115 can separate the end portions 144 of the semiconducting strut structures 140 from each other. For example, the upper end portion 144 of the first semiconducting strut structure 140 can be separated from the lower end portion 144 of a laterally adjacent second semiconducting strut structure 140 by the first trench 115. Additionally, the upper end portion 144 of the first semiconducting strut structure 140 can be separated from the lower end portion 144 of a laterally adjacent third semiconducting strut structure 140 by another of the first trenches 115. Similarly, the lower end portion 144 of the first semiconducting strut structure 140 can be separated from the upper end portion 144 of a laterally adjacent fourth semiconducting strut structure 140 by one of the first trenches 115 and from the upper end portion 144 of a laterally adjacent fifth semiconducting strut structure 140 by another of the first trenches 115.

[0081] The central portion 142 may extend across the second trench 116 in a first lateral direction (e.g., along the Y direction). Therefore, the second trench 116 may be divided (e.g., interrupted) by the central portion 142 of the semiconducting strut structure 140. The second trench 116 may separate the lower end portion 144 of one of the semiconducting strut structures 140 from the central portion 142 of the semiconducting strut structure 140. Additionally, the second trench 116 may separate the upper end portion 144 of one of the semiconducting strut structures 140 from the adjacent central portion 142 of the semiconducting strut structure 140.

[0082] Continue to refer to Figure 1LEach of the semiconducting strut structures 140 may include a digital line (e.g., bit line) contact area 160 located on a central portion 142 and a memory node (e.g., memory cell) contact area 162 located on an end portion 144. As will be described herein, bit line contacts and memory node contacts may be formed on corresponding portions of the bit line contact area 160 and memory node contact area 162. Although the bit line contact area 160 and memory node contact area 162 have been illustrated in FIG. 1 as having the same lateral dimensions as the semiconducting strut structure 140, it should be understood that the lateral dimensions of the digital line contact area 160 and memory node contact area 162 may be smaller than the lateral dimensions of the semiconducting strut structure 140.

[0083] Storage node contact area 162 may be positioned adjacent to end portion 144 (e.g., on or above end portion 144). Digital line contact area 160 may be positioned adjacent to the central portion 142 of semiconducting strut structure 140 (e.g., on or above the central portion 142 of semiconducting strut structure 140). In some embodiments, the digital line contact area 160 of the first semiconducting strut structure is laterally aligned with the storage node contact areas 162 of the adjacent second and third semiconducting strut structures 140.

[0084] The lateral dimensions and shapes of the storage node contact area 162 and the digital line contact area 160 of the semiconducting pillar structure 140 can correspond to the lateral dimensions and shapes of the first trench 115 and the second trench 116.

[0085] Continue to refer to Figure 1L The distance D2 (corresponding to the length of the central portion 142 of the semiconducting strut structure 140) can be in the range of about 20 nm to about 40 nm, for example, from about 20 nm to about 25 nm, from about 25 nm to about 30 nm, from about 30 nm to about 35 nm, or from about 35 nm to about 40 nm. However, this disclosure is not limited thereto and the distance D2 may be different from the distance described.

[0086] The distance D3 between the end portion 144 of the first semiconducting pillar structure 140 and the central portion 142 of the adjacent second semiconducting pillar structure 140 (e.g., the distance between the memory node contact region 162 and the bit line contact region 160 of the first semiconducting pillar structure 140) can be in the range of about 10 nm to about 20 nm, for example, from about 10 nm to about 15 nm or from about 15 nm to about 20 nm. However, this disclosure is not limited thereto and the distance D3 may be different from the distance described.

[0087] The distance D4 between the end portion 144 of the semiconducting strut structure 140 and the central portion 142 of the adjacent semiconducting strut structure 140 can be in the range of about 5 nm to about 20 nm, for example, from about 5 nm to about 10 nm, from about 10 nm to about 15 nm, or from about 15 nm to about 20 nm. However, this disclosure is not limited thereto and the distance D4 may be different from the distance described.

[0088] The distance D5 between opposite sides of the central portion 142 may be in the range of about 5 nm to about 15 nm, for example, from about 5 nm to about 10 nm or from about 10 nm to about 15 nm. However, this disclosure is not limited thereto and the distance D5 may be different from the distance described.

[0089] The distance D6 between the upper end portion 144 of the semiconducting strut structure 140 and the lower end portion 144 of the vertically adjacent semiconducting strut structure 140, in a direction substantially parallel to the longitudinal axis L4 of the central portion 142, may range from about 10 nm to about 30 nm, for example, from about 10 nm to about 15 nm, from about 15 nm to about 20 nm, from about 20 nm to about 25 nm, or from about 25 nm to about 30 nm. In some embodiments, the distance D6 is about 26 nm. However, this disclosure is not limited thereto and the distance D6 may differ from the distance described.

[0090] The distance D7 between the upper end portion 144 of the semiconducting strut structure 140 and the adjacent lower end portion 144 of the semiconducting strut structure 140 in a direction perpendicular to the sides of the upper end portion 144 and the lower end portion 144 can be in the range of about 5 nm to about 20 nm, for example, from about 5 nm to about 10 nm, from about 10 nm to about 15 nm, or from about 15 nm to about 20 nm. However, this disclosure is not limited thereto and the distance D7 may be different from the distance described.

[0091] The distance D9 between the opposing sidewalls of the end portion 144 may be in the range of about 5 nm to about 15 nm, for example, from about 5 nm to about 10 nm or from about 10 nm to about 15 nm. In some embodiments, the distance D9 is substantially the same as the distance D5.

[0092] After the semiconducting pillar structure 140 is formed, the microelectronic device structure 100 may undergo additional processing. In some embodiments, the microelectronic device structure 100 may be exposed to one or more ion implantation processes to form so-called source, drain, and channel regions of a transistor structure at least partially formed by the semiconducting pillar structure 140. In some embodiments, the semiconducting pillar structure 140 is exposed to ion implantation to dope at least the upper portion of the patterned base material 102'.

[0093] refer to Figure 1M , Figure 1N andFigure 1O The word line 164 may be formed in an isolation trench between the storage node contact area 162 and the digital line contact area 160. Figure 1M This is a top view of the microelectronic device structure 100 after it has undergone additional processing. Figure 1N Is it through Figure 1M The section line NN intercepts Figure 1M A simplified cross-sectional view of the microelectronic device structure 100, and Figure 1O Is it through Figure 1M The cross-section line OO intercepts Figure 1M A simplified cross-sectional view of the microelectronic device structure 100.

[0094] refer to Figure 1M and Figure 1N Insulating material 180 (not listed for clarity and ease of understanding) Figure 1M (As described in the text) It can be formed on the microelectronic device structure 100 and can fill the area between adjacent semiconducting pillar structures 140 (e.g., first trench 115 and second trench 116). The insulating material 180 can be formed of and contain a dielectric material. In some embodiments, the insulating material 180 includes silicon dioxide.

[0095] After the insulating material 180 is formed, a portion of the insulating material 180 and a portion of the semiconductive pillar structure 140 between the central portion 142 and the end portion 144 can be removed. For example, a mask material can be formed on the microelectronic device structure 100, wherein openings (e.g., trenches) extend along a first lateral direction (e.g., the X direction) and portions of the insulating material 180 and the semiconductive pillar structure 140 can be removed through the openings in the mask material.

[0096] In some embodiments, after the opening is formed, the exposed portion of the patterned base material 102' can be exposed to an ion implantation process to form a channel region 181 of a transistor structure. A dielectric material 182 (e.g., a gate dielectric material) can be formed within the opening, and a conductive material 184 can be formed on the dielectric material 182 to form a word line 164. The dielectric material 182 can be formed from and includes the following: one or more phosphosilicate glasses, borosilicate glasses, borosilicate phosphosilicate glasses (BPSG), fluorosilicone glasses, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride materials (e.g., silicon nitride (Si3N4)), oxynitrides (e.g., silicon oxynitride), another gate dielectric material, dielectric carbon nitride material (e.g., silicon carbon nitride (SiCN)), dielectric carbonitride material (e.g., silicon carbonitride (SiOCN)), or combinations thereof.

[0097] The conductive material 184 may be formed from one or more of the following and includes one or more of the following: titanium nitride, tantalum nitride, aluminum titanium nitride, elemental titanium, elemental platinum, elemental rhodium, elemental iridium, iridium oxide, elemental ruthenium, elemental ruthenium oxide, elemental molybdenum, elemental tungsten, elemental cobalt, polycrystalline silicon, germanium, and silicon-germanium. In some embodiments, the conductive material 184 includes one or more of elemental molybdenum, elemental tungsten, and elemental cobalt and one or more of polycrystalline silicon, germanium, and silicon-germanium.

[0098] In some embodiments, and with reference to Figure 1M Word lines 164 can separate the central portion 142 from the end portion 144. In other words, in some embodiments, word lines 164 may be located between the central portion 142 and the end portion 144. Thus, word lines 164 may be located in an isolation trench (e.g., containing insulating material 180) that includes word lines 164 and separates the digital line contact area 160 from the memory node contact area 162 of each of the semiconducting strut structures 140. Thus, the semiconducting strut structure 150 as described herein may each include a central portion 142 separated from the end portions 144 (e.g., the first end portion 144 and the second end portion 144) by word lines 164 (e.g., the first word line 164 and the second word line 164). After the word lines 164 are formed, the remaining portion of the opening may be filled with insulating material 186, which may comprise one or more of the materials described above with reference to insulating material 180. In some embodiments, insulating material 186 comprises the same material composition as insulating material 180.

[0099] refer to Figure 1N and Figure 1O After the word line 164 is formed, an opening 185 may be formed through portions of insulating material 186 and insulating material 180 to expose the surface of the digital line contact area 160 of the semiconducting strut structure 140. The opening 185 may be formed, for example, by forming and patterning a mask on the microelectronic device structure 100 and exposing the microelectronic device structure 100 to a suitable etchant.

[0100] Now for reference Figure 1P , Figure 1Q and Figure 1R This allows the microelectronic device structure 100 to undergo additional processing to form the microelectronic device 190. Figure 1P This is a top view of the microelectronic device 190. Figure 1Q Is it through Figure 1P The cross-sectional view intercepted by the section line QQ; and Figure 1R Is it through Figure 1P The cross-sectional view taken by the section line RR. (Reference) Figures 1P to 1RDigital line contacts 160' may be formed within opening 185 and on digital line contact area 160. Digital line contacts 160' may be formed of and contain at least one conductive material. In some embodiments, digital line contacts 160' include one or more of the following: titanium nitride, tantalum nitride, aluminum titanium nitride, elemental titanium, elemental platinum, elemental rhodium, elemental iridium, iridium oxide, elemental ruthenium, elemental ruthenium oxide, elemental molybdenum, elemental tungsten, elemental cobalt, polycrystalline silicon, germanium, and silicon-germanium. In some embodiments, digital line contacts 160' include one or more of elemental molybdenum, elemental tungsten, and elemental cobalt and one or more of polycrystalline silicon, germanium, and silicon-germanium. In some embodiments, digital line contacts 160' include doped polycrystalline silicon. As a non-limiting example, digital line contacts 160' may contain at least about 10 20 atoms / cm 3 Or even at least about 10 21 atoms / cm 3 .

[0101] In some embodiments, the digital line contact 160' is recessed in the opening 185 ( Figure 1O Within. After forming the digital line contact 160', conductive material 188 may be formed above the microelectronic device structure 100 and in contact with the digital line contact 160' to form a digital line 166. The conductive material 188 of the digital line 166 may be formed from one or more of the materials described above with reference to the word line 164 and may include said one or more materials.

[0102] After forming the digital line contact 160' and the digital line 166, an insulating material 192 may be formed on the digital line 166. In some embodiments, a spacer 165 (e.g., a "bit line spacer", "digital line spacer") may be formed on the side of the digital line 166. The insulating material 192 and the spacer 165 may be individually formed from and comprise one or more of the materials described above with reference to insulating materials 180 and 186. In some embodiments, the digital line 166 does not completely fill the opening 185 ( Figure 1O The spacer 165 may be located on the side of the digital line 166 within the opening 185.

[0103] The width of the spacer 165 (e.g., along a direction substantially perpendicular to the longitudinal axis L4 of the digit line 166 (e.g., the X direction)) may be in the range of about 5 nm to about 20 nm, such as from about 5 nm to about 10 nm, from about 10 nm to about 15 nm, or from about 15 nm to about 20 nm. However, this disclosure is not limited thereto and the width may differ from the width described.

[0104] refer to Figure 1SThe storage node contact 162' may be formed on the storage node contact area 162 of the semiconducting strut structure 140. The storage node contact 162' may be formed of and include one or more of the materials described above with reference to the digital line contact 160'.

[0105] Storage node contact 162' may be electrically connected to storage node contact region 162 of semiconductive strut structure 140. Storage node contact 162' may be located between adjacent portions of insulating material 186 and insulating material 192. Storage node contact 162' may be formed of and comprise one or more of the materials described above with reference to digital line contact 160'. In some embodiments, storage node contact 162' comprises doped polysilicon. As a non-limiting example, storage node contact 162' may comprise at least about 10 20 atoms / cm 3 Or even at least about 10 21 atoms / cm 3 In some embodiments, the microelectronic device structure 190 is exposed to annealing conditions to diffuse dopant from digital line contacts 160' and memory node contacts 162' to form source regions, drain regions, and channel regions 181 of, for example, transistor structures.

[0106] Continue to refer to Figures 1P to 1S In some embodiments, digital line contacts 160' may be aligned in the Y direction and may be offset from storage node contacts 162' in the X direction. In some embodiments, digital line contacts 160' may not be aligned with any of the storage node contacts 162' in the direction in which digital line 166 extends. Additionally, storage node contacts 162' may be aligned with each other in the Y direction.

[0107] The microelectronic device 190 may include memory cells, each memory cell including an access transistor (e.g., a transistor including a gate along one of the word lines 164) coupled to a memory node structure 194 (e.g., a capacitor structure). Figure 1S The description states that there is only one storage node structure 194, but it should be understood that all storage node contacts 162' can be coupled to the storage node structure 194.

[0108] Continue to refer to Figure 1S The storage node structure 194 may be formed on and electrically connected to the storage node contact 162'. For clarity and ease of understanding of this disclosure, Figure 1P The storage node structure is not described in section 194.

[0109] In some embodiments, a re-laid material (RDM) structure 196 (also referred to as a “re-laid layer (RDL) structure”) may be formed on or above a storage node contact 162', and a storage node structure 194 may be electrically connected to the storage node structure 194 and the storage node contact 162'.

[0110] RDM structure 196 can be configured to effectively shift (e.g., interleave, adjust, modify) the lateral position (e.g., along the X direction, along the Y direction) of memory node contacts 162' to accommodate the desired arrangement (e.g., hexagonal close-packed arrangement) of memory node structures 194 above and electrically connected to memory node contacts 162'. RDM structures 196 can each be individually formed of and contain conductive materials, including, but not limited to, one or more of the following: metals (e.g., tungsten, titanium, nickel, platinum, gold), metal alloys, metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), and conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium). As a non-limiting example, RDM structure 196 can individually include W, TiN, TaN, WN, TiAlN, Ti, Pt, Rh, Ir, IrO. x 、Ru、RuO x One or more of its alloys.

[0111] Storage node structure 194 can be configured to store charges representing programmable logic states. For example, a charged state of storage node structure 194 can represent a first logic state (e.g., logic 1), and an uncharged state of storage node structure 170 can represent a second logic state (e.g., logic 0). In some embodiments, storage node structure 194 includes a dielectric material configured to store charges associated with logic states. The dielectric material may include, for example, one or more of the following: silicon dioxide, silicon nitride, polyimide, titanium dioxide (TiO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), oxide-nitride-oxide materials (e.g., silicon dioxide-silicon nitride-silicon dioxide), strontium titanate (SrTiO3) (STO), barium titanate (BaTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), ferroelectric materials (e.g., ferroelectric hafnium oxide, ferroelectric zirconium oxide, lead zirconate titanate (PZT), etc.), and high-k dielectric materials. In some embodiments, the storage node structure 170 includes zirconium oxide.

[0112] The RDM structure 196 and the memory node structure 194 can each be individually formed using conventional processes (e.g., conventional deposition processes, such as one or more of in-situ growth, spin coating, blanket coating, CVD, ALD and PVD; conventional patterning and material removal processes, such as conventional alignment processes, conventional photolithography exposure processes, conventional development processes, conventional etching processes) and conventional processing equipment, which are not detailed herein.

[0113] Return to reference Figures 1P to 1S In an additional embodiment, the microelectronic device 190 is formed to modify the first line 105 ( Figure 1A The first angle α (and the corresponding angle of each of the first spacer 108, the second spacer 110 and the first groove 115), the second line 112 ( Figure 1E The second angle β corresponding to the second groove 116, and the third angle θ of the end portion 144 relative to the central portion 142. Figure 1L One or more of these can be used to represent different lateral geometric configurations of the semiconducting strut 140 (e.g., different lateral shapes, different lateral dimensions).

[0114] Compared to conventional microelectronic devices, forming a semiconductive pillar structure 140 including a central portion 142 and an end portion 144 extending at a first angle α relative to the central portion 142 can facilitate an increase in the effective area of ​​the digital line contacts 160' on the central portion 142. Additionally, compared to conventional microelectronic device structures, the size and shape of the semiconductive pillar structure 140 can facilitate an increase in the landing area of ​​the memory node contacts 162' from the lateral edges of the spacers 165 (e.g., from about 4 nm to more than about 5 nm). Furthermore, compared to conventional microelectronic devices, the spacing of the semiconductive pillar structures 140 facilitates an increase in the width of the spacers 165 (e.g., along the X direction), which can facilitate a reduction in the capacitive coupling of the bit lines 166. Furthermore, the size, shape, and orientation of the semiconductive pillar structures 140 can facilitate an increase in the distance between the base material 102 of the semiconductive pillar structures 140 to which the word lines 164 are not coupled (e.g., through the word lines) and such semiconductive pillar structures 140.

[0115] Therefore, according to embodiments of the present disclosure, a microelectronic device includes: a semiconducting pillar structure including a central portion, a first end portion, and a second end portion on a side of the central portion opposite to the first end portion, the first end portion being oriented at an angle relative to the central portion and extending substantially parallel to the second end portion; a digital line contact on the central portion of the semiconducting pillar structure; a first storage node contact on the first end portion; and a second storage node contact on the second end portion.

[0116] Therefore, according to an additional embodiment of the present disclosure, a method of forming a microelectronic device includes: forming an isolation structure comprising a silicon-containing material and an oxide material on the side of the silicon-containing material, the isolation structure being separated by a first trench extending in a first direction and a second trench extending in a second direction; forming a sacrificial material in at least a portion of the first trench and the second trench; removing at least some of the sacrificial material at the intersection of the first trench and the second trench to form an elongated opening; filling the elongated opening with additional oxide material; selectively removing the silicon-containing material and the sacrificial material relative to the oxide material and the additional oxide material; removing portions of semiconductive material exposed through the remaining portions of the oxide material and the additional oxide material to form a semiconductive pillar structure; and forming a storage node contact on an end portion of at least one of the semiconductive pillar structures and forming a digital line contact on a central portion of the at least one semiconductive pillar structure.

[0117] Therefore, according to a further embodiment of the present disclosure, a method of forming a microelectronic device includes: forming a first trench between lines of an oxide material; forming a second trench through a portion of the oxide material and a silicon-containing material to form an isolation structure including the silicon-containing material and the oxide material on the side of the silicon-containing material; forming a sacrificial material in at least a portion of the first trench and the second trench; removing at least some of the sacrificial material at the intersection of the first trench and the second trench to form an elongated opening; selectively removing the silicon-containing material and the sacrificial material relative to the oxide material; removing a portion of the semiconductive material exposed through the remaining portion of the oxide material to form a semiconductive pillar structure; and forming a storage node contact on the end portion of at least one of the semiconductive pillar structures and forming a digital line contact on the central portion of the at least one semiconductive pillar structure.

[0118] Microelectronic devices comprising microelectronic devices (e.g., microelectronic device 190) and microelectronic device structures (e.g., microelectronic device structure 100) formed according to embodiments described herein can be used in embodiments of the electronic systems of this disclosure. For example, Figure 2 This is a block diagram of an electronic system 203 according to an embodiment of the present disclosure. The electronic system 203 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer, for example... or Tablet computers, e-books, navigation devices, etc. Electronic system 203 includes at least one memory device 205. Memory device 205 may include, for example, the microelectronic device architecture previously described herein (e.g., microelectronic device architecture 100) or previously referenced... Figures 1A to 1S Embodiments of the described microelectronic device (e.g., microelectronic device 100).

[0119] The electronic system 203 may further include at least one electronic signal processor device 207 (generally referred to as a “microprocessor”). The electronic signal processor device 207 may optionally include embodiments of the microelectronic devices or microelectronic device structures previously described herein (e.g., previously referenced...). Figures 1A to 1S (One or more of the described microelectronic device 190 or microelectronic device architecture 100). Electronic system 203 may further include one or more input devices 209 for inputting information into electronic system 203 by a user, such as, for example, a mouse or other pointing device, keyboard, touchpad, button, or control panel. Electronic system 203 may further include one or more output devices 211 for outputting information (e.g., visual or audio output) to a user, such as, for example, a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, input device 209 and output device 211 may include a single touchscreen device that can be used both to input information into the electronic system and to output visual information to a user. Input device 209 and output device 211 may be in electrical communication with one or more of memory device 205 and electronic signal processor device 207.

[0120] refer to Figure 3 The present invention describes a processor-based system 300. The processor-based system 300 may include various microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic devices 190 or microelectronic device structures 100). The processor-based system 300 may be any of a variety of types, such as a computer, pager, cellular phone, personal notebook, control circuitry, or other electronic device. The processor-based system 300 may include one or more processors 302, such as microprocessors, to control system functions and request processing within the processor-based system 300. The processor 302 and other sub-components of the processor-based system 300 may include microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic devices 190 or microelectronic device structures 100).

[0121] The processor-based system 300 may include a power supply 304 operatively connected to the processor 302. For example, if the processor-based system 300 is a portable system, the power supply 304 may include one or more of a fuel cell, a power harvesting device, a permanent battery, a replaceable battery, and a rechargeable battery. The power supply 304 may also include an AC adapter; thus, for example, the processor-based system 300 can be plugged into a wall outlet. For example, the power supply 304 may also include a DC adapter, allowing the processor-based system 300 to be plugged into a vehicle cigarette lighter or a vehicle power port.

[0122] Depending on the functions performed by the processor-based system 300, various other devices may be coupled to the processor 302. For example, a user interface 306 may be coupled to the processor 302. The user interface 306 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. A display 308 may also be coupled to the processor 302. The display 308 may include an LCD display, a SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a 3D projector, an audio display, or combinations thereof. Furthermore, an RF subsystem / baseband processor 310 may also be coupled to the processor 302. The RF subsystem / baseband processor 310 may include antennas coupled to an RF receiver and an RF transmitter (not shown). A communication port 312 or more communication ports 312 may also be coupled to the processor 302. For example, communication port 312 may be adapted to couple to one or more peripheral devices 314, such as a modem, printer, computer, scanner or camera, or to a network, such as a local area network, remote local area network, intranet or the Internet.

[0123] Processor 302 can control processor-based system 300 by implementing software programs stored in memory. For example, the software programs may include operating systems, database software, graphics software, word processing software, media editing software, or media playback software. Memory is operatively coupled to processor 302 to store various programs and facilitate their execution. For example, processor 302 may be coupled to system memory 316, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), race memory, and other known memory types. System memory 316 may include volatile memory, non-volatile memory, or combinations thereof. System memory 316 is typically large enough to store dynamically loaded application programs and data. In some embodiments, system memory 316 may include semiconductor devices, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic device 190 and microelectronic device structure 100), or combinations thereof.

[0124] Processor 302 may also be coupled to non-volatile memory 318, which does not imply that system memory 316 is necessarily volatile. Non-volatile memory 318 may include one or more of STT-MRAM, MRAM, read-only memory (ROM) (e.g., EPROM, resistive read-only memory (RROM)), and flash memory used in conjunction with system memory 316. The size of non-volatile memory 318 is typically chosen to be just large enough to store any necessary operating system, applications, and fixed data. Additionally, non-volatile memory 318 may include high-capacity memory, such as disk drive memory, for example, a hybrid drive containing resistive memory or other types of non-volatile solid-state memory. Non-volatile memory 318 may include microelectronic devices, such as the microelectronic devices and microelectronic device architectures described above (e.g., microelectronic device 190 and microelectronic device architecture 100), or combinations thereof.

[0125] Therefore, according to embodiments of this disclosure, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes: a semiconductive pillar structure, each semiconductive pillar structure including a central portion electrically coupled to a bit line contact and located between end portions electrically coupled to a memory node contact; and a word line oriented at an angle relative to the end portions and located between the bit line contact and the memory node contact, separating the bit line contact and the memory node contact.

[0126] Additional non-limiting example embodiments of this disclosure are described below.

[0127] Example 1: A microelectronic device comprising: a semiconductive pillar structure including a central portion, a first end portion, and a second end portion on a side of the central portion opposite to the first end portion, the first end portion being oriented at an angle relative to the central portion and extending substantially parallel to the second end portion; a digital line contact on the central portion of the semiconductive pillar structure; a first storage node contact on the first end portion; and a second storage node contact on the second end portion.

[0128] Example 2: The microelectronic device according to Example 1, wherein the angle is in the range of about 40° to about 50°.

[0129] Example 3: The microelectronic device according to Example 1 or Example 2, wherein the digital line contact is laterally aligned with the storage node contact of the adjacent semiconducting pillar structure.

[0130] Example 4: The microelectronic device according to any one of Examples 1 to 3 further includes a word line that extends laterally between the digital line contact and the first memory node contact and separates the first end portion from the central portion.

[0131] Example 5: The microelectronic device according to any one of Examples 1 to 4 further includes a digital line electrically coupled to the digital line contact.

[0132] Example 6: The microelectronic device according to Example 5 further includes an insulating material adjacent to the digital line.

[0133] Example 7: The microelectronic device according to Example 6, wherein the width of the insulating material is in the range of about 5 nm to about 20 nm.

[0134] Example 8: A microelectronic device according to any one of Examples 1 to 7, wherein the lower storage node contact is laterally aligned with the upper storage node contact of the adjacent semiconducting pillar structure.

[0135] Example 9: A method of forming a microelectronic device, the method comprising: forming a first spacer extending along a first direction; forming a second spacer adjacent to the first spacer, the first spacer being located between two second spacers, the adjacent second spacers being separated by a first trench extending along the first direction; forming a second trench extending along a second direction to form an isolation structure including a portion of the first spacer located between portions of the second spacers; forming a sacrificial material in the first trench and the second trench; removing a portion of the sacrificial material from the intersection of the first trench and the second trench along a first transverse direction to form an elongated opening; forming an oxide material in the elongated opening; removing the sacrificial material to form a pattern of a pillar structure; and transferring the pattern of the pillar structure to a semiconductive material to form a semiconductive pillar structure.

[0136] Example 10: According to the method of Example 9, forming a second groove extending in a second direction includes forming the second groove to extend at an angle in the range of about 70° to about 90° relative to the first groove.

[0137] Example 11: The method according to Example 9 or Example 10, wherein: forming the first spacer includes forming the first spacer comprising amorphous silicon; and forming the second spacer includes forming the second spacer comprising silicon dioxide.

[0138] Example 12: The method according to any one of Examples 9 to 11, wherein forming the sacrificial material includes forming the sacrificial material comprising silicon nitride.

[0139] Example 13: The method according to any one of Examples 9 to 12, wherein forming the oxide material in the elongated opening comprises filling the elongated opening with the oxide material comprising a material substantially the same as that of the second spacer.

[0140] Example 14: The method according to any one of Examples 9 to 13, wherein forming the semiconductive pillar structure includes forming the semiconductive pillar structure to include digital line contact areas located between the contact areas of the storage nodes.

[0141] Example 15: A method of forming a microelectronic device, the method comprising: forming an isolation structure including a silicon-containing material and an oxide material on the side of the silicon-containing material, the isolation structure being separated by a first trench extending in a first direction and a second trench extending in a second direction; forming a sacrificial material in at least a portion of the first trench and the second trench; removing at least some of the sacrificial material at the intersection of the first trench and the second trench to form an elongated opening; filling the elongated opening with additional oxide material; selectively removing the silicon-containing material and the sacrificial material relative to the oxide material and the additional oxide material; removing portions of semiconductive material exposed through the remaining portions of the oxide material and the additional oxide material to form a semiconductive pillar structure; and forming a storage node contact on an end portion of at least one of the semiconductive pillar structures and forming a digital line contact on a central portion of the at least one semiconductive pillar structure.

[0142] Example 16: According to the method of Example 15, forming a semiconductive pillar structure includes forming the end portion of the semiconductive pillar structure at an angle ranging from about 30° to about 60° relative to the central portion.

[0143] Example 17: The method according to Example 15 or Example 16 further includes forming a digital line electrically connected to the digital line contact, the digital line extending at an angle relative to the end portion of the at least one semiconductive pillar structure.

[0144] Example 18: The method according to Example 17 further includes forming an insulating spacer on the side of the digital line.

[0145] Example 19: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device, the at least one microelectronic device including: a semiconductive pillar structure, each semiconductive pillar structure including a central portion electrically coupled to bit line contacts and located between end portions electrically coupled to memory node contacts; and a word line oriented at an angle relative to the end portions and located between the bit line contacts and the memory node contacts, separating the bit line contacts and the memory node contacts.

[0146] Example 20: The electronic system according to Example 19, wherein the angle is in the range of about 40° to about 50°.

[0147] Example 21: The electronic system according to Example 19, wherein the angle is approximately 41°.

[0148] Example 22: An electronic system according to any of Examples 19 to 21, wherein the distance between the storage node contact of the first semiconducting pillar structure and the digital line contact of the adjacent second semiconducting pillar structure in a direction parallel to the word line is in the range of about 10 nm to about 20 nm.

[0149] Example 23: An electronic system according to any one of Examples 19 to 22, wherein the semiconducting pillar structure exhibits an S-shape.

[0150] Example 24: An electronic system according to any of Examples 19 to 23, further comprising a bit line electrically coupled to the bit line contact and oriented at another angle relative to the end portion.

[0151] While certain illustrative embodiments have been described with reference to the figures, those skilled in the art will recognize and understand that the embodiments covered by this disclosure are not limited to those explicitly shown and described herein. Rather, many additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments covered by this disclosure, such as those claimed below, including legal equivalents. Furthermore, features from one disclosed embodiment may be combined with features from another disclosed embodiment while still being covered within the scope of this disclosure.

Claims

1. A microelectronic device comprising: A semiconducting strut structure includes a central portion, a first end portion, and a second end portion on the side of the central portion opposite to the first end portion, the first end portion being oriented at an angle relative to the central portion and extending substantially parallel to the second end portion. Digital line contact, located on the central portion of the semiconducting strut structure; A digital line electrically coupled to the digital line contact, wherein the longest portion of the digital line is parallel to the longest portion of the central portion; The first storage node contact is located on the first end portion; and The second storage node contact is located on the second end portion.

2. The microelectronic device according to claim 1, wherein the angle is in the range of 40° to 50°.

3. The microelectronic device of claim 1, wherein the digital line contact is laterally aligned with the storage node contact of the adjacent semiconducting strut structure.

4. The microelectronic device of claim 1, further comprising a word line extending laterally between the digital line contact and the first memory node contact and separating the first end portion from the central portion.

5. The microelectronic device of claim 1, further comprising an insulating material adjacent to the digital line.

6. The microelectronic device of claim 5, wherein the width of the insulating material is in the range of 5 nm to 20 nm.

7. The microelectronic device of claim 1, wherein the first storage node contact is laterally aligned with the second storage node contact of the adjacent semiconducting strut structure.

8. The microelectronic device according to claim 1, wherein the angle is about 41°.

9. The microelectronic device of claim 1, wherein the semiconducting pillar structure exhibits an S-shape with rounded edges.

10. The microelectronic device of claim 1, further comprising an additional semiconducting pillar structure, wherein the distance between the first memory node contact of the semiconducting pillar structure and the second memory node contact of the additional semiconducting pillar structure is in the range of 10 nm to 20 nm.

11. The microelectronic device of claim 1, wherein the digital line is in contact with an additional digital line contact of an additional semiconducting pillar structure adjacent to the semiconducting pillar structure.

12. The microelectronic device of claim 11, further comprising two word lines laterally located between the digital line contact of the semiconducting pillar structure and the additional digital line contact of the additional semiconducting pillar structure.

13. The microelectronic device of claim 1, wherein the semiconductive strut structure has a rounded edge at the intersection of the central portion with each of the first end portion and the second end portion.

14. The microelectronic device of claim 1, wherein the semiconducting pillar structure intersects only two word lines.

15. The microelectronic device of claim 1, wherein the semiconductive strut structure does not include other storage node contacts besides the first storage node contact and the second storage node contact.

16. The microelectronic device of claim 1, wherein each storage node contact of the semiconductive strut structure is offset from the longest portion of the central portion.

17. The microelectronic device of claim 1, further comprising word lines extending in a lateral direction perpendicular to the digital lines, wherein the digital line contacts are laterally aligned with additional first storage node contacts of an additional semiconducting pillar structure adjacent to the semiconducting pillar structure in the lateral direction perpendicular to the digital lines.

18. The microelectronic device of claim 17, wherein the digital line contact is laterally located between the additional first storage node contact of the additional semiconducting strut structure and the additional second storage node contact of another additional semiconducting strut structure.

19. The microelectronic device of claim 1, further comprising word lines oriented at an angle ranging from 20 degrees to 70 degrees relative to the first end portion and the second end portion.

20. A microelectronic device comprising: A semiconducting strut structure includes a central portion, a first end portion, and a second end portion on the side of the central portion opposite to the first end portion, the first end portion being oriented at an angle relative to the central portion and extending substantially parallel to the second end portion. Digital line contact, located on the central portion of the semiconducting strut structure; A digital line electrically coupled to the digital line contact and extending parallel to the longitudinal axis of the central portion; The first storage node contact is located on the first end portion; The second storage node contact is located on the second end portion; and Two word lines intersect with the semiconducting pillar structure, which intersects only with the two word lines.

21. A method of forming a microelectronic device, the method comprising: Forming a first spacer extending along a first direction; A second spacer is formed adjacent to the first spacer, the first spacer being located between the two second spacers, and the adjacent second spacers are separated from each other by a first groove extending along the first direction; A second groove extending in a second direction is formed to form an isolation structure including a portion of a first spacer located between portions of the second spacer; Sacrificial material is formed in the first trench and the second trench; A portion of the sacrificial material is removed from the intersection of the first trench and the second trench along a first transverse direction to form an elongated opening; An oxide material is formed in the elongated opening; Remove the sacrificial material to form a pattern for the pillar structure; The pattern of the pillar structure is transferred onto a semiconductive material to form a semiconductive pillar structure, each semiconductive pillar structure comprising: Central section; The first end portion is located on one side of the central portion; The second end portion is located on the side of the central portion opposite to the first end portion. The first end portion is oriented at a certain angle relative to the central portion and extends substantially parallel to the second end portion; Digital line contacts formed on the central portion of the semiconductive pillar structure, a first storage node contact on the first end portion, and a second storage node contact on the second end portion; and The digital line is electrically coupled to the digital line contact, wherein the longest portion of the digital line is parallel to the longest portion of the central portion.

22. The method of claim 21, wherein forming the second trench extending in the second direction comprises forming the second trench to extend at an angle in the range of 70° to 90° relative to the first trench.

23. The method according to claim 21, wherein: Forming the first spacer includes forming the first spacer comprising amorphous silicon; and Forming the second spacer includes forming the second spacer comprising silicon dioxide.

24. The method of claim 23, wherein forming the sacrificial material comprises forming the sacrificial material comprising silicon nitride.

25. The method according to any one of claims 21 to 24, wherein forming the oxide material in the elongated opening comprises filling the elongated opening with the oxide material comprising a material substantially the same as that of the second spacer.

26. The method according to any one of claims 21 to 24, wherein forming the semiconductive pillar structure includes forming the semiconductive pillar structure to include digital line contact areas located between the contact areas of the storage nodes.

27. A method of forming a microelectronic device, the method comprising: An isolation structure is formed comprising a silicon-containing material and an oxide material on the side of the silicon-containing material, the isolation structure being separated by a first trench extending along a first direction and a second trench extending along a second direction; Sacrificial material is formed in at least a portion of the first trench and the second trench; At least some of the sacrificial material is removed at the intersection of the first and second trenches to form an elongated opening; The elongated opening is filled with additional oxide material; The silicon-containing material and the sacrificial material are selectively removed relative to the oxide material and the additional oxide material; Removing portions of the semiconductive material exposed through the remaining portions of the oxide material and the additional oxide material to form a semiconductive pillar structure, each of the semiconductive pillar structures comprising: Central section; The first end portion is located on one side of the central portion; The second end portion is located on the side of the central portion opposite to the first end portion. The first end portion is oriented at an angle relative to the central portion and extends substantially parallel to the second end portion; a storage node contact is formed on the end portion of at least one of the semiconductive pillar structures, and a digital line contact is formed on the central portion of the at least one semiconductive pillar structure; and A digital line is formed to communicate electrically with the digital line contact, wherein the longest portion of the digital line is parallel to the longest portion of the central portion.

28. The method of claim 27, wherein forming the semiconductive strut structure includes forming the end portion of the semiconductive strut structure at an angle ranging from 30° to 60° relative to the central portion.

29. The method of claim 27, further comprising forming an insulating spacer on the side of the digital line.

30. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; and A memory device operatively coupled to the processor device and including at least one microelectronic device, the at least one microelectronic device comprising: The semiconductive pillar structure, each semiconductive pillar structure including a central portion electrically coupled to the digital line contact. The first end portion is located on one side of the central portion; The second end portion is located on the side of the central portion opposite to the first end portion. A first storage node contact is located on the first end portion; and a second storage node contact is located on the second end portion, the first end portion being oriented at an angle relative to the central portion and extending substantially parallel to the second end portion; and A digital line, oriented at an angle relative to the first and second end portions and located between the digital line contact and each of the first and second storage node contacts, separating the digital line contact from each of the first and second storage node contacts; and A digital line electrically coupled to a digital line contact, wherein the longest portion of the digital line is parallel to the longest portion of the central portion of the semiconductive strut structure electrically coupled to the digital line.

31. The electronic system of claim 30, wherein the angle is in the range of 40° to 50°.

32. The electronic system of claim 30, wherein the angle is about 41°.

33. The electronic system of claim 30, wherein the distance between the storage node contact of the first semiconducting pillar structure and the digital line contact of the adjacent second semiconducting pillar structure in a direction parallel to the word line is in the range of 10 nm to 20 nm.

34. The electronic system of claim 30, wherein the semiconducting pillar structure exhibits an S-shape.

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