Semiconductor device, three-dimensional memory, and method for manufacturing semiconductor device

Abstract

The present invention provides a semiconductor device, a three-dimensional memory, and a method for manufacturing a semiconductor device. The semiconductor device includes a substrate, a plurality of gates, first contacts corresponding to the plurality of gates, and several second contacts. The plurality of gates are spaced on the surface of the substrate, and there are spacer regions between every two adjacent gates. A source electrode is provided on the surface of the substrate in the spacer regions. Each gate includes a connection surface, and one of the first contacts is provided on the connection surface of each gate. The orthographic projection of the first contact on the connection surface is in a strip shape, and the length extension direction of the first contact is the same as the gate length direction. The several second contacts are provided on the substrate and are connected to the source electrode in the spacer regions. The second contacts have the same structure as the first contacts, and the second contacts and the first contacts are arranged in parallel.

Description

[0001] This invention is a divisional application of the patent with the application date of October 29, 2020, application number 202011186371.5, and invention title "Semiconductor Device, 3D Memory and Method for Preparing Semiconductor Device". Technical Field

[0002] This invention relates to the technical field of semiconductor memory devices, and particularly relates to a semiconductor device, a 3D memory, and a method for preparing a semiconductor device. Background Art

[0003] A 3D memory is a flash memory device with three-dimensional stacking of memory cells. Compared with planar memories, it has a higher storage density per unit area. Existing 3D NAND memory cell architectures are usually designed with vertical channels and horizontal control gate layers, which can double the integration density on a wafer per unit area.

[0004] In a 3D memory device formed by the X_tacking process, as the number of array layers continuously increases, the size of the CMOS (Complementary Metal Oxide Semiconductor) chip has a greater impact on the final size of the entire chip, and the requirement for miniaturization of CMOS is also higher. Therefore, there is an increasing need for a capacitor structure with a larger capacitance density. Summary of the Invention

[0005] The purpose of this invention is to provide a 3D memory and a method for preparing the same, so as to achieve a capacitor structure with a large density for semiconductor devices and 3D memory devices.

[0006] This invention provides a semiconductor device, including a substrate, multiple gates, first contacts corresponding to the multiple gates, and several second contacts;

[0007] The multiple gates are spaced on the surface of the substrate, and there is a spacer region between every two adjacent gates. A source electrode is provided on the surface of the substrate in the spacer region.

[0008] Each gate includes a connection surface, and one of the first contacts is provided on the connection surface of each gate. The orthographic projection of the first contact on the connection surface is strip-shaped, and the length extension direction of the first contact is the same as the gate length direction.

[0009] The several second contacts are provided on the substrate and are connected to the source electrode in the spacer region. The second contacts have the same structure as the first contacts, and the second contacts and the first contacts are arranged in parallel.

[0010] Among them, the cross-section of the first contact in the gate width direction is trapezoidal, and the top side of the trapezoid is connected to the gate.

[0011] Among them, in the width direction of the gate, the orthographic projection of each of the first contacts and the second contacts is rectangular.

[0012] Among them, the distance between the second contact located in the spacer region and the two gates forming the spacer region is 50 - 70 nanometers.

[0013] Among them, the semiconductor device further includes a metal layer, the metal layer is formed on the surfaces of the plurality of first contacts and several second contacts away from the substrate, and a drain corresponding to the source is provided on the metal layer.

[0014] Among them, an ILD layer is formed on the substrate, the ILD covers the surfaces of the gate and the substrate, and the first contacts and the second contacts are formed in the ILD layer.

[0015] The present invention also provides a three-dimensional memory, including the semiconductor device and a memory array, and the semiconductor device and the memory array are electrically connected.

[0016] The present invention also provides a method for manufacturing a semiconductor device, the method includes,

[0017] Providing a substrate;

[0018] Forming a plurality of gates and sources on the substrate, and having a spacer region between every two of the gates, and each spacer region is provided with one of the sources; among them, the gate includes a connection surface,

[0019] Forming a contact on the connection surface of each of the gates and on the substrate in each of the spacer regions, the orthographic projection of the contact on the substrate is strip-shaped, and the length extension direction of the contact is the same as the gate length direction.

[0020] Among them, the step of forming a contact on the connection surface of each of the gates and on the substrate in each of the spacer regions includes,

[0021] Forming a first contact on the connection surface of each of the gates through a mask and etching process, the orthographic projection of the first contact on the connection surface is strip-shaped, and the length extension direction of the first contact is the same as the gate length direction.

[0022] Among them, the step of forming a contact on the connection surface of each of the gates and on the substrate in each of the spacer regions includes forming a second contact on the substrate in each of the spacer regions through a masking and etching process, connecting the second contact to the source electrode, wherein the second contact has the same structure as the first contact, and the second contact and the first contact are arranged in parallel.

[0023] The step of forming a contact on the connection surface of each of the gates and on the substrate in each of the spacer regions includes,

[0024] forming a first contact on the connection surface of each of the gates, the orthographic projection of the first contact on the connection surface being strip-shaped, and the length extension direction of the first contact being the same as the gate length direction; the step of forming a contact on the connection surface of each of the gates and on the substrate in each of the spacer regions includes forming a second contact on the substrate in each of the spacer regions, connecting the second contact to the source electrode, wherein the second contact has the same structure as the first contact, and the second contact and the first contact are arranged in parallel.

[0025] In the method for manufacturing a semiconductor device, the step of forming a plurality of gates and source electrodes on the substrate further includes forming an ILD layer on the substrate, the ILD covering the gates and the source electrodes, and the first contact and the second contact being formed in the ILD layer.

[0026] In the semiconductor device provided by the present invention, the orthographic projection of the first contact on the connection surface of the gate is strip-shaped, and the length extension direction of the first contact is the same as the gate length direction; the second contact has the same structure as the first contact, and the independent first contact and second contact are not in a dot matrix form, and the unit area of the contact is increased, which can increase the capacitance to realize a high-density capacitance structure for the semiconductor device and the three-dimensional storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0028] Figure 1 is a top view structural schematic diagram of the semiconductor device provided by the present invention.

[0029] Figure 2 is a cross-sectional schematic diagram of the semiconductor device provided by the embodiment of the present invention.

[0030] Figure 3 It is a flowchart of a method for manufacturing a semiconductor device provided by the present invention.

[0031] Figures 4 - 5 They are schematic diagrams of each step of the semiconductor device provided by the present invention. Detailed implementation manners

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0033] Existing three-dimensional memories include a memory array and peripheral circuits. Memory transistors with a vertical serial direction are formed in the memory array on a lateral substrate, and the memory transistors extend along the vertical direction with respect to the substrate. The peripheral circuit can be understood as the peripheral device of the memory, that is, it can be a semiconductor device, which includes any suitable digital, analog, and / or mixed-signal peripheral circuits for promoting memory operations. For example, the peripheral device may include a page buffer, a decoder (for example, a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, a current or voltage reference, or one or more of the active or passive components (such as transistors, diodes, resistors, or capacitors) in any circuit. In the X-tacking technology, the semiconductor device is usually formed using complementary metal-oxide-semiconductor (CMOS) technology, and the interlayer dielectric (ILD) layer of the semiconductor device under the X-tacking technology is relatively thin.

[0034] Based on the X-tacking technology, the present invention provides a semiconductor device and a three-dimensional memory, including a semiconductor device and a memory array, and the semiconductor device and the memory array are electrically connected. Please refer to Figure 1 and Figure 2 , the semiconductor device in the embodiment of the present invention includes a substrate 10, a plurality of gates 12, first contacts 14 corresponding to the plurality of gates 12, and several second contacts 16.

[0035] The plurality of gates 12 are spaced on the surface 101 of the substrate 10, and there is a spacer 102 between every two adjacent gates 12. A source electrode (not shown in the figure) is provided on the surface 101 of the substrate 10 in the spacer 102.

[0036] Each of the gates 12 includes a connection surface 121, and a first contact 14 is provided on the connection surface 121 of each gate 12. The orthographic projection of the first contact 14 on the connection surface 121 is strip-shaped, and the length extension direction of the first contact 14 is the same as the length direction of the gate 12.

[0037] A plurality of the second contacts 16 are provided on the substrate 10 and are located in the spacer region 102 and connected to the source electrode (not shown in the figure). The second contacts 16 have the same structure as the first contacts 14, and the second contacts 16 and the first contacts 14 are arranged in parallel.

[0038] Such as Figure 2 Specifically, the semiconductor device is a peripheral circuit that provides electrical connection for the 3D memory. Each gate 12 is electrically connected through a first contact 14, and each source electrode is connected to a second contact. An ILD layer (not shown in the figure) is formed on the substrate 10, and the ILD layer covers the surfaces of the gate 12 and the substrate 10. The first contacts 14 and the second contacts 16 are formed in the ILD layer. In the width direction of the gate 12, the orthographic projections of each first contact 14 and second contact 16 are rectangular, that is, the first contacts 14 and the second contacts 16 are in the shape of rectangular plates when viewed perpendicular to the length direction of the gate. The thickness of the ILD layer is relatively thin, which is more convenient for the first contacts 14 and the second contacts 16 to be formed in the form of plates. In the same unit area, the first contacts 14 and the second contacts 16 are in the form of plates rather than dot matrices, so as to increase the areas of the first contacts 14 and the second contacts 16 and increase the capacitance provided by them in the semiconductor device.

[0039] Furthermore, such as Figure 5 , the cross-section of the first contact 14 in the width direction of the gate 12 is trapezoidal, and the top side A of the trapezoid is connected to the connection surface of the gate 12. Specifically, with reference to Figure 1 , the width direction of the gate 12 is understood as the X direction, the length direction of the gate 12 is the Y direction, and a plurality of the gates 12 are arranged at intervals in the X direction, and a plurality of first contacts 14 are arranged at intervals in the X direction. When viewed from the X direction, the first contacts 14 are in the shape of rectangular plates, and when viewed along the Y direction, the cross-section of the first contact 14 is trapezoidal, and the shorter top side of the trapezoid is connected to the connection surface of the gate 12. On the premise of ensuring the connection performance, the contact area between the first contact 14 and the gate 12 is ensured in the X direction, that is, the contact surface area between the first contact 14 and the surface of the gate 12 is large enough. To ensure that the distance between the first contact 14 and the second contact 16 is reduced, the distance a between the first contact 14 and the surface edge of the gate 12 is 50 - 70 nanometers or more, which can ensure that the first contact can accurately contact the gate surface and can also ensure that the distance between the two contacts is reduced.

[0040] Further, the distance b between the second contact 16 located within the spacer region 102 and the two gates 12 forming the spacer region is 50 - 70 nanometers. The distance between every two contacts (the first contact 14 and the second contact 16) can be reduced, and the capacitance can be increased. The structure of the second contact 16 is the same as that of the first contact 14. When viewed in the X direction, the second contact 16 is a rectangular plate. When viewed along the Y direction, the cross-section of the second contact 16 is trapezoidal, and the shorter top side of the trapezoid is connected to the source electrode on the substrate 10. The dimension c of the end of the second contact 16 connected to the source electrode on the substrate 10 in the X direction is reduced, thereby reducing the gate density and increasing the number of second contacts per unit area, and further increasing the capacitance.

[0041] In the present application, the first contact 14 and the second contact 16 are rectangular plates. Compared with the setting method of multiple contacts, the surface area of the contacts is increased, and thus the capacitance is increased.

[0042] Further, the semiconductor device further includes a metal layer 18 formed on the surfaces of the plurality of first contacts and several second contacts away from the substrate, for electrically connecting the first contact 14 and the second contact 16 to other devices of the memory. Specifically, the metal layer 18 includes a first metal layer and a second metal layer that are stacked and spaced by an insulating layer, and the first metal layer and the second metal layer are connected by vias.

[0043] Next, a method for manufacturing a semiconductor device provided by the present application will be introduced in detail in combination with the foregoing semiconductor device. In other embodiments, the semiconductor device obtained by using the manufacturing method of the present semiconductor device may also be different from the semiconductor device of the foregoing embodiments.

[0044] The present invention provides a method for manufacturing a semiconductor device, characterized in that the method includes,

[0045] Please refer to Figure 3, step S1, provide a substrate 10; the substrate 10 is used to support the device structure thereon. In this embodiment, the material of the substrate 10 is single crystal silicon (Si). Of course, in other embodiments, the material of the substrate 10 can be elemental semiconductors such as germanium (Ge), compound semiconductors such as germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and / or indium antimonide (InSb), alloy semiconductors such as gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP) and / or gallium indium arsenide phosphide (GaInAsP) or a combination of the above materials. In addition, the substrate 10 can be a "semiconductor on insulator" wafer.

[0046] Please refer to Figure 4 , step S2, form a plurality of gates 12 and source electrodes (not shown in the figure) on the substrate 10, and there is a spacer 102 between every two of the gates 12, and each spacer 102 is provided with one of the source electrodes; wherein, the gate 12 includes a connection surface 121. The gate 12 can be made of polysilicon, silicon nitride (SixNy, such as SiN), amorphous silicon, polysilicon, aluminum oxide or a combination of the above materials. The gate 12 is formed by coating, etching or photomask method. Specifically, a gate sacrificial layer is first formed, and the gate sacrificial layer will be replaced by metal in subsequent processes to serve as the gate.

[0047] Furthermore, the step of forming a plurality of gates 12 and source electrodes on the substrate 10 further includes forming an ILD layer (not shown in the figure) on the substrate 10, and the ILD layer covers the gates 12 and the source electrodes.

[0048] Please refer to Figure 5 , step S3, through a mask and etching process, form a first contact 14 on the connection surface 121 of each gate 12. The orthographic projection of the first contact 14 on the connection surface 121 is strip-shaped, and the length extension direction of the first contact 14 is the same as the length direction of the gate 12. Moreover, the orthographic projection of the first contact 14 on the connection surface 121 is located within the orthographic projection of the gate 12. The first contact 14 can be composed of W, Ru, Co or other suitable conductive materials. The first contact 14 can be formed by filling after forming a through hole in the ILD layer. The specific method of forming the through hole can be formed in the ILD layer by a mask plate combined with an etching method, which will not be elaborated here.

[0049] This embodiment further includes Step 4. Through a masking and etching process, a second contact 16 is formed on the substrate 10 within each of the spacer regions 102, such that the second contact 16 is connected to the source electrode. Among them, the second contact 16 has the same structure as the first contact 14, and the second contact 16 and the first contact 14 are arranged in parallel. The second contact 16 may be composed of W, Ru, Co, or other suitable conductive materials. The second contact 16 may be formed by filling a through hole formed in the ILD layer. The specific method of forming the through hole may be to form it in the ILD layer by combining a mask plate with an etching method, which will not be elaborated here

[0050] It should be noted that when forming the first contact 14, the cross-section of the first contact 14 in the width direction of the gate 12 is trapezoidal, and the top side of the trapezoid is connected to the gate 12; and in the width direction of the gate 12, the orthographic projection of each of the first contact 14 and the second contact 16 is rectangular. In other embodiments, the first contact 14 and the second contact 15 are formed simultaneously.

[0051] The method for manufacturing the semiconductor device further includes forming a metal layer 18. The metal layer 18 is formed on the surfaces of a plurality of the first contacts 14 and several second contacts 16 away from the substrate 10 and on the ILD layer, and a drain electrode corresponding to the source electrode is provided on the metal layer 18. The metal layer may be composed of Cu, Al, Ru, Co, W, or other suitable conductive materials.

[0052] What is disclosed above is only the preferred embodiment of the present invention. Of course, the scope of the rights of the present invention cannot be limited thereby. Those of ordinary skill in the art can understand the entire or part of the processes of implementing the above embodiments, and the equivalent changes made according to the claims of the present invention still fall within the scope covered by the invention.

Claims

1. A semiconductor device, characterized in that, It includes a substrate, multiple gates, first contacts corresponding to the multiple gates, and multiple second contacts; The multiple gates are spaced on the surface of the substrate, and there is a spacer region between every two adjacent gates, and a source electrode is provided in the substrate of the spacer region; Each gate includes a connection surface, and one of the first contacts is provided on the connection surface of each gate. The orthographic projection of the first contact on the connection surface is strip-shaped, and the length extension direction of the first contact is the same as the gate length direction; The multiple second contacts are provided on the substrate in the spacer region and are connected to the source electrode. The second contacts have the same structure as the first contacts, and the second contacts and the first contacts are arranged in parallel; A drain electrode is provided on the side of the first contact and the second contact away from the substrate; 2. The semiconductor device according to claim 1, wherein The cross-section of the first contact in the gate width direction is trapezoidal, and the top side of the trapezoid is connected to the gate; 3. The semiconductor device according to claim 2, wherein, In the width direction of the gate, the orthographic projection of each of the first contact and the second contact is rectangular; 4. The semiconductor device according to claim 2, wherein The distance between the second contact located in the spacer region and the two gates forming the spacer region is 50-70 nanometers; 5. The semiconductor device according to any one of claims 1-4, characterized in that, The semiconductor device further includes a metal layer, and the metal layer is formed on the surfaces of the multiple first contacts and the multiple second contacts away from the substrate; 6. The semiconductor device according to any one of claims 1-4, characterized in that, An interlayer dielectric (ILD) layer is formed on the substrate, and the ILD covers the surfaces of the gates and the substrate, and the first contacts and the second contacts are formed in the ILD layer; 7. A three-dimensional memory, characterized in that, It includes the semiconductor device according to any one of claims 1-6 and a memory array, and the semiconductor device and the memory array are electrically connected; 8. A method for manufacturing a semiconductor device, characterized in that, The method includes, Providing a substrate; Forming multiple gates and source electrodes on the substrate, and making there be a spacer region between every two gates, and one of the source electrodes is provided in each spacer region; wherein, the gate includes a connection surface; Forming a contact on the connection surface of each gate and on the substrate in each spacer region. The orthographic projection of the contact on the substrate is strip-shaped, and the length extension direction of the contact is the same as the gate length direction; Providing a drain electrode on the side of the contact away from the substrate; 9. The method for manufacturing a semiconductor device according to claim 8, wherein, The step of forming a contact on the connection surface of each gate and on the substrate in each spacer region includes, Forming a first contact on the connection surface of each gate through a mask and etching process. The orthographic projection of the first contact on the connection surface is strip-shaped, and the length extension direction of the first contact is the same as the gate length direction; 10. The method for manufacturing a semiconductor device according to claim 9, wherein, The step of forming a contact on the connection surface of each gate and on the substrate in each spacer region includes, through a mask and etching process, forming a second contact on the substrate in each spacer region, and connecting the second contact to the source electrode. Wherein, the second contact has the same structure as the first contact, and the second contact and the first contact are arranged in parallel; 11. The method for manufacturing a semiconductor device according to claim 8, wherein, The step of forming a contact on the connection surface of each gate and on the substrate in each spacer region includes, A first contact is formed on the connection surface of each of the gates. The orthographic projection of the first contact on the connection surface is strip-shaped, and the length extension direction of the first contact is the same as the gate length direction; the step of forming a contact on the connection surface of each of the gates and on the substrate in each of the spacer regions includes forming a second contact on the substrate in each of the spacer regions, connecting the second contact to the source electrode, wherein the second contact has the same structure as the first contact, and the second contact and the first contact are arranged side by side.

12. The method for manufacturing a semiconductor device according to claim 10, wherein, The step of forming a plurality of gates and source electrodes on the substrate further includes forming an interlayer dielectric (ILD) layer on the substrate, the ILD covering the gates and the source electrodes, and the first contact and the second contact are formed within the ILD layer.

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