Semiconductor memory devices

Abstract

An embodiment provides a semiconductor memory device that can be preferably manufactured. The semiconductor memory device of the embodiment includes: a substrate having first to fourth regions arranged along a first direction; a first conductive layer from the first region to a second region; a second conductive layer from the fourth region to the second region; a third conductive layer from the first region to the third region; and a fourth conductive layer from the fourth region to the third region. It also includes: a first semiconductor pillar facing the first and third conductive layers in the first region; and a second semiconductor pillar facing the second and fourth conductive layers in the fourth region. Furthermore, it includes: a first contact connected to the first conductive layer in the second region; a second contact connected to the second conductive layer in the second region; a third contact connected to the third conductive layer in the third region; a fourth contact connected to the fourth conductive layer in the third region; a first wiring electrically connected to the first and second contacts in the second region; and a second wiring electrically connected to the third and fourth contacts in the third region.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2020-139234 (filed on August 20, 2020). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known, comprising: a semiconductor substrate; a plurality of conductive layers deposited in a direction intersecting the surface of the semiconductor substrate; a semiconductor pillar extending in a direction intersecting the surface of the semiconductor substrate and facing the plurality of conductive layers; and a gate insulating film disposed between the conductive layers and the semiconductor pillar. Summary of the Invention

[0005] The embodiments provide a semiconductor memory device that can be preferably manufactured.

[0006] A semiconductor memory device according to one embodiment includes: a substrate having first to fourth regions sequentially arranged in a first direction; a plurality of first conductive layers extending from the first region along a first direction to a second region and arranged in a second direction intersecting the surface of the substrate; a plurality of second conductive layers extending from the fourth region along a first direction to the second region and arranged in a second direction; a plurality of third conductive layers extending from the first region along a first direction to the third region and arranged in a second direction, with their positions in the second direction different from those of the plurality of first conductive layers; a plurality of fourth conductive layers extending from the fourth region along a first direction to the third region and arranged in a second direction, with their positions in the second direction different from those of the plurality of second conductive layers; a first semiconductor pillar disposed in the first region, extending in a second direction, and facing the plurality of first conductive layers and the plurality of third conductive layers; and a second semiconductor pillar. A plurality of first contacts are disposed in the fourth region, extending along the second direction and facing the plurality of second conductive layers and the plurality of fourth conductive layers; a plurality of first contacts are disposed in the second region, extending along the second direction and connected to the ends of the plurality of first conductive layers in the first direction; a plurality of second contacts are disposed in the second region, extending along the second direction and connected to the ends of the plurality of second conductive layers in the first direction; a plurality of third contacts are disposed in the third region, extending along the second direction and connected to the ends of the plurality of third conductive layers in the first direction; a plurality of fourth contacts are disposed in the third region, extending along the second direction and connected to the ends of the plurality of fourth conductive layers in the first direction; a plurality of first wirings are disposed in the second region and electrically connected to the plurality of first contacts and the plurality of second contacts; and a plurality of second wirings are disposed in the third region and electrically connected to the plurality of third contacts and the plurality of fourth contacts.

[0007] A semiconductor memory device according to one embodiment includes: a substrate having first to fourth regions sequentially arranged in a first direction; a plurality of first conductive layers and a plurality of first insulating layers extending from the first region along the first direction to the fourth region and alternately arranged in a second direction intersecting the surface of the substrate; a plurality of second conductive layers and a plurality of second insulating layers extending from the first region along the first direction to the fourth region and alternately arranged in a second direction, wherein the positions in the second direction are different from those of the plurality of first conductive layers; a first semiconductor pillar disposed in the first region, extending along the second direction and facing the plurality of first conductive layers and the plurality of second conductive layers; a second semiconductor pillar disposed in the fourth region, extending along the second direction and facing the plurality of first conductive layers and the plurality of second conductive layers; a plurality of first contacts disposed in the second region, extending along the second direction and connected to the plurality of first conductive layers; and a plurality of second contacts disposed in the third region, extending along the second direction and connected to the plurality of second conductive layers. The third contact, being one of a plurality of first contacts, penetrates the plurality of first insulating layers and extends along the second direction. In a first cross-section extending along both the first and second directions and including the third contact, the distance between the first conductive layer disposed closer to the plurality of second conductive layers and the third contact in the first direction is greater. Attached Figure Description

[0008] Figure 1 This is an equivalent circuit diagram illustrating the schematic configuration of the semiconductor memory device according to the first embodiment.

[0009] Figure 2 This is a schematic top view of the semiconductor memory device.

[0010] Figure 3 yes Figure 2 A schematic enlarged view of part A shown.

[0011] Figure 4 It is Figure 3 The structure shown is a schematic cross-sectional view when cut along line B-B' and viewed in the direction of the arrow.

[0012] Figure 5 It is Figure 3 The structure shown is a schematic cross-sectional view when cut along line C-C' and viewed in the direction of the arrow.

[0013] Figure 6 It is Figure 3 The schematic cross-sectional view shown is obtained by cutting along line D-D' and observing in the direction of the arrow.

[0014] Figure 7 yes Figure 6 A schematic enlarged view of the part shown as E.

[0015] Figure 8This is a schematic line connection diagram illustrating an example of a connection between a contact point and a through contact point.

[0016] Figures 9-16 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0017] Figure 17 This is a schematic cross-sectional view of a comparative example semiconductor memory device.

[0018] Figure 18 It is a line connection diagram that schematically shows the line connection status of the nodes in the comparative example.

[0019] Figure 19 This is a schematic cross-sectional view showing the semiconductor memory device of the first embodiment.

[0020] Figure 20 It is a line connection diagram that schematically shows the line connection state of the contacts in the first embodiment.

[0021] Figure 21 This is a schematic enlarged view of the semiconductor memory device according to the second embodiment.

[0022] Figure 22 It is Figure 21 The schematic cross-sectional view shown is obtained by cutting along line F-F' and observing in the direction of the arrow.

[0023] Figures 23-25 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

[0024] Figure 26 This is a schematic enlarged view of the semiconductor memory device according to the third embodiment.

[0025] Figure 27 It is Figure 26 The schematic cross-sectional view shown is obtained by cutting along line G-G' and observing in the direction of the arrow.

[0026] Figure 28 This is a schematic enlarged view of the semiconductor memory device according to the fourth embodiment.

[0027] Figure 29 It is Figure 28 The schematic cross-sectional view shown is obtained by cutting along the H-H' line and observing in the direction of the arrow.

[0028] Figure 30 It is Figure 28 The schematic cross-sectional view shown is obtained by cutting along line I-I' and observing in the direction of the arrow.

[0029] Figure 31This is a schematic enlarged view of the semiconductor memory device according to the fifth embodiment.

[0030] Figure 32 It is a schematic cross-sectional view of a semiconductor memory device with other forms as a roughly stepped structure.

[0031] Figure 33 It is Figure 32 The schematic cross-sectional view shown is obtained by cutting along line J-J' and observing in the direction of the arrow.

[0032] Figure 34 It is Figure 32 The schematic cross-sectional view shown is obtained by cutting along line K-K' and observing in the direction of the arrow.

[0033] Figure 35 This is a top view showing the configuration of contacts and through contacts in other examples where contacts are connected to through contact lines.

[0034] Figure 36 This is a top view showing the line connection status in other examples where the contact point is connected to the through contact line.

[0035] Figure 37 This is a top view showing the line connection status in other examples where the contact point is connected to the through contact line.

[0036] Figure 38 This is a top view showing the line connection status in other examples where the contact point is connected to the through contact line.

[0037] Figure 39 It is Figure 35 The schematic cross-sectional view shown is obtained by cutting along the L-L' line and observing in the direction of the arrow.

[0038] Figure 40 It is Figure 35 The schematic cross-sectional view shown is obtained by cutting along the M-M' line and observing in the direction of the arrow. Detailed Implementation

[0039] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention.

[0040] In addition, in this specification, the specified direction parallel to the surface of the semiconductor substrate is called the X direction, the direction parallel to the surface of the semiconductor substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the surface of the semiconductor substrate is called the Z direction.

[0041] In addition, in this specification, the direction along a specified plane is sometimes referred to as the first direction, the direction along the specified plane and intersecting the first direction is referred to as the second direction, and the direction intersecting the specified plane is referred to as the third direction. These first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond.

[0042] Furthermore, in this specification, expressions such as "upper" or "lower" are based on the semiconductor substrate. For example, the direction away from the semiconductor substrate along the Z-direction is called "upper," and the direction closer to the semiconductor substrate along the Z-direction is called "lower." Additionally, when referring to a configuration as a lower surface or lower end, it refers to the surface or end on the semiconductor substrate side of that configuration; when referring to an upper surface or upper end, it refers to the surface or end on the opposite side of that configuration from the semiconductor substrate. Furthermore, the surface intersecting the X or Y direction is called a side surface, etc. Moreover, regarding configurations with two or more semiconductor substrates, any one of the semiconductor substrates can be used as a reference.

[0043] Furthermore, in this specification, when it is stated that the first component is "electrically connected" to the second component, the first component can be directly connected to the second component, or the first component can be connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an off state, the first transistor is "electrically connected" to the third transistor.

[0044] In addition, in this specification, when it is said that the first component is "interconnected" between the second and third components, it sometimes means that the first, second and third components are connected in series, and the first component is located in the current path of the second and third components.

[0045] Furthermore, in this specification, when it is said that a circuit or the like "conducts" two wirings, it sometimes means that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings and is in a switched-on state.

[0046] [First Implementation]

[0047] [Overall Composition]

[0048] Hereinafter, the configuration of the semiconductor memory device according to the first embodiment will be described with reference to the accompanying drawings. Furthermore, the following drawings are schematic diagrams, and some configurations may be omitted for ease of explanation.

[0049] [Equivalent Circuit]

[0050] Figure 1 This is a schematic equivalent circuit diagram showing the configuration of the semiconductor memory device according to the first embodiment.

[0051] The semiconductor memory device of the first embodiment includes a memory cell array (MCA) and peripheral circuitry (PC) for controlling the memory cell array (MCA).

[0052] The memory cell array (MCA) has multiple memory blocks (BLK). Each memory block (BLK) has multiple string components (SU). Each string component (SU) has multiple memory strings (MS). One end of each memory string (MS) is connected to the peripheral circuitry (PC) via a bit line (BL). The other end of each memory string (MS) is connected to the PC via a common source line (SL).

[0053] The memory string (MS) has a drain-side selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MC), and a source-side selection transistor (STS). Hereinafter, the drain-side selection transistor (STD) and the source-side selection transistor (STS) are sometimes simply referred to as selection transistors (STD, STS).

[0054] The memory cell MC in the first embodiment is a field-effect transistor with a charge accumulation film included in the gate insulating film. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge accumulation film. Furthermore, word lines WL are connected to the gate electrodes of multiple memory cells MC corresponding to one memory string MS. These word lines WL are commonly connected to all memory strings MS in one memory block BLK.

[0055] The select transistors (STD, STS) are field-effect transistors. The gate electrodes of the select transistors (STD, STS) are connected to select gate lines (SGD, SGS). The drain-side select gate line SGD is configured for a string assembly SU and is commonly connected to all memory strings MS within a single string assembly SU. The source-side select gate line SGS is commonly connected to all memory strings MS within a single memory block BLK.

[0056] The peripheral circuit PC includes: an operating voltage generating circuit 21 that generates an operating voltage; an address decoder 22 that decodes address data; a block selection circuit 23 and a voltage selection circuit 24 that transmit the operating voltage to the memory cell array MCA according to the output signal of the address decoder 22; a sense amplifier module 25 connected to the bit line BL; and a sequencer 26 that controls the operating voltage generating circuit 21, the address decoder 22, the block selection circuit 23 and the voltage selection circuit 24, and the sense amplifier module 25.

[0057] The operating voltage generation circuit 21 has multiple operating voltage output terminals 31. The operating voltage generation circuit 21 includes, for example, a buck circuit such as a regulator and a boost circuit such as a charge pump circuit. The operating voltage generation circuit 21 generates, for example, based on a control signal from the sequencer 26, multiple operating voltages applied to the bit line BL, source line SL, word line WL, and select gate lines (SGD, SGS) during read, write, and erase operations on the memory cell array MCA, and simultaneously outputs them to the multiple operating voltage output terminals 31. The operating voltages output from the operating voltage output terminals 31 are appropriately adjusted according to the control signal from the sequencer 26.

[0058] The address decoder 22 has multiple block select lines BLKSEL and multiple voltage select lines 33. For example, based on control signals from the sequencer 26, the address decoder 22 sequentially refers to the address data in the address register and decodes the address data, turning on the block drive transistor 35 and voltage select transistor 37 corresponding to the address data, and turning off the other block drive transistors 35 and voltage select transistors 37. For example, the voltage of the block select line BLKSEL and voltage select line 33 corresponding to the address data is set to "H" (High), and the voltage of the other lines is set to "L" (Low). Furthermore, when using P-channel transistors instead of N-channel transistors, the opposite voltage is applied to these lines.

[0059] Furthermore, in the illustrated example, each memory block BLK in address decoder 22 is provided with one block select line BLKSEL. However, this configuration can be modified appropriately. For example, each of two or more memory blocks BLK can also be equipped with one block select line BLKSEL.

[0060] The block select circuit 23 includes multiple block select sections 34 corresponding to memory blocks BLK. Each block select section 34 includes multiple block drive transistors 35 corresponding to word lines WL and select gate lines (SGD, SGS). The block drive transistors 35 are, for example, field-effect transistors. The drain electrodes of the block drive transistors 35 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS). The source electrodes are electrically connected to the operating voltage output terminal 31 via wiring CG and voltage selection circuit 24. The gate electrodes are commonly connected to the corresponding block select line BLKSEL.

[0061] In addition, the block selection circuit 23 also includes a plurality of transistors (not shown). These transistors are field-effect transistors connected between the select gate lines (SGD, SGS) and the ground voltage supply terminal. These transistors enable the select gate lines (SGD, SGS) contained in the non-select memory block BLK to conduct to the ground voltage supply terminal. Furthermore, the multiple word lines WL contained in the non-select memory block BLK are in a floating state.

[0062] The voltage selection circuit 24 includes multiple voltage selection sections 36 corresponding to word lines WL and select gate lines (SGD, SGS). Each of the multiple voltage selection sections 36 includes multiple voltage selection transistors 37. The voltage selection transistors 37 are, for example, field-effect transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS) via wiring CG and block selection circuit 23. The source terminals are electrically connected to the corresponding operating voltage output terminals 31. The gate electrodes are connected to the corresponding voltage selection lines 33.

[0063] The sensing amplifier module 25 is connected to multiple bit lines BL. The sensing amplifier module 25, for example, has multiple sensing amplifier components corresponding to the bit lines BL. Each sensing amplifier component has: a clamping transistor that charges the bit line BL based on the voltage generated in the operating voltage generation circuit 21; a sensing transistor that senses the voltage or current of the bit line BL; and multiple latching circuits that store the output signal of the sensing transistor or write data, etc.

[0064] The sequencer 26 outputs control signals to the operating voltage generation circuit 21, the address decoder 22, and the sensing amplifier module 25 based on the input command and the state of the semiconductor storage device. For example, the sequencer 26 sequentially refers to the instruction data in the instruction register according to the clock signal, decodes the instruction data, and outputs it to the operating voltage generation circuit 21, the address decoder 22, and the sensing amplifier module 25.

[0065] [structure]

[0066] Figure 2 This is a schematic top view of the semiconductor memory device according to the first embodiment. Figure 3 yes Figure 2 The diagram shown in Figure A is a schematic enlarged view, illustrating the configuration of the upper memory cell array layer. Figure 4 It is Figure 3 The schematic cross-sectional view shown is obtained by cutting along line B-B' and observing in the direction of the arrow. Figure 5 It is Figure 3 The schematic cross-sectional view shown is obtained by cutting along line C-C' and observing in the direction of the arrow. Figure 6 It is Figure 3The schematic cross-sectional view shown is obtained by cutting along line D-D' and observing in the direction of the arrow. Figure 7 yes Figure 6 A schematic enlarged view of the part shown as E.

[0067] The semiconductor memory device of the first embodiment is, for example, like... Figure 2 As shown, a semiconductor substrate 100 is provided. In the illustrated example, four memory cell arrays (MCAs) arranged along the X and Y directions are disposed in the semiconductor substrate 100.

[0068] For example, like Figure 4 and Figure 5 As shown, the semiconductor memory device of the first embodiment includes a semiconductor substrate 100 and a transistor layer L disposed on the semiconductor substrate 100. TR Set in transistor layer L TR The upper wiring layer D0, the wiring layer D1 above wiring layer D0, the wiring layer D2 above wiring layer D1, and the lower storage cell array layer L above wiring layer D2. MCA1 , set in the storage cell array layer L MCA1 The upper storage cell array layer L above MCA2 , set in the storage cell array layer L MCA2 The wiring layer M0 above the wiring layer M0, the wiring layer M1 above the wiring layer M0, and the wiring layer M2 above the wiring layer M1.

[0069] [Structure of semiconductor substrate 100]

[0070] Semiconductor substrate 100 is, for example, a semiconductor substrate containing P-type silicon (Si) with P-type impurities such as boron (B). For example, like... Figure 4 and Figure 5 As shown, a semiconductor substrate region 100S and an insulating region 100I are provided on the surface of the semiconductor substrate 100.

[0071] [Transistor layer L] TR [Structure]

[0072] For example, like Figure 4 and Figure 5 As shown, a wiring layer GC is disposed on the upper surface of the semiconductor substrate 100, separated by an insulating layer (not shown). The wiring layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 100. Furthermore, each region of the semiconductor substrate 100 and the plurality of electrodes gc included in the wiring layer GC are respectively connected to a contact CS.

[0073] The semiconductor substrate region 100S of the semiconductor substrate 100 functions as a channel region for multiple transistors Tr that constitute the peripheral circuit PC, and as an electrode for multiple capacitors, etc.

[0074] The multiple electrodes gc contained in the wiring layer GC function as the gate electrodes of multiple transistors Tr that constitute the peripheral circuit PC, and as the other electrode of multiple capacitors.

[0075] The contact CS extends along the Z direction and is connected at its lower end to the upper surface of the semiconductor substrate 100 or the electrode gc. An impurity region containing N-type or P-type impurities is provided at the connection point between the contact CS and the semiconductor substrate 100. The contact CS may also include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) or a metal film such as tungsten (W).

[0076] [Structure of wiring layers D0, D1, and D2]

[0077] For example, like Figure 4 and Figure 5 As shown, the multiple wirings contained in the wiring layers D0, D1, and D2 are electrically connected to at least one of the configurations in the memory cell array MCA and the peripheral circuit PC.

[0078] The wiring layers D0, D1, and D2 each contain multiple wirings d0, d1, and d2. These multiple wirings d0, d1, and d2 may, for example, comprise laminated films of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W).

[0079] [Storage cell array layer L] MCA1 L MCA2 [Structure]

[0080] like Figure 3 As shown, the storage cell array layer L MCA1 L MCA2 It has multiple memory blocks BLK arranged along the Y direction, and an inter-block insulating layer ST such as silicon oxide (SiO2) disposed between two adjacent memory blocks BLK in the Y direction.

[0081] The memory block BLK is divided into two regions arranged in the Y direction by an intra-block insulating layer st, such as silicon oxide (SiO2), extending along the X direction. One of the two regions has two memory hole regions R that extend along the X direction and are arranged in the X direction. MH1 R MH2 and the wiring area R between them. HU1 and wiring area R HU2 Additionally, another region R in the two regions has two memory hole regions extending along the X direction and arranged along the X direction. MH1 R MH2and the wiring area R between them. HU3 and wiring area R HU4 Furthermore, the insulating layer st within the block has multiple notches st'. Therefore, a portion of the storage block BLK is formed between two regions arranged along the Y direction, electrically connected via these notches st'.

[0082] Memory hole region R MH1 R MH2 Each component comprises multiple string modules SU arranged along the Y direction, and a silicon dioxide (SiO2) inter-string insulating layer SHE disposed between two adjacent string modules SU in the Y direction. Figure 6 ).

[0083] [Storage cell array layer L] MCA1 L MCA2 memory hole area R MH1 R MH2 [Structure]

[0084] Storage cell array layer L MCA1 L MCA2 memory hole area R MH1 R MH2 ( Figure 3 , Figure 4 , Figure 5 For example, like Figure 6 As shown, it includes: a plurality of conductive layers 110 arranged along the Z direction; a plurality of semiconductor pillars 120 extending along the Z direction; and a plurality of gate insulating films 130 respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120.

[0085] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction. The conductive layer 110 may also comprise a laminated film of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W). Alternatively, the conductive layer 110 may comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged along the Z direction.

[0086] A conductive layer 111 is disposed below the conductive layer 110. The conductive layer 111 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). In addition, an insulating layer 101 such as silicon oxide (SiO2) is disposed between the conductive layer 111 and the conductive layer 110.

[0087] A conductive layer 112 is disposed below the conductive layer 111. The conductive layer 112 includes: a semiconductor layer 113 bonded to the lower end of the semiconductor pillar 120; and a conductive layer 114 bonded to the lower surface of the semiconductor layer 113. The semiconductor layer 113 may, for example, contain polycrystalline silicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). The conductive layer 114 may, for example, contain a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers. In addition, an insulating layer 101 such as silicon oxide (SiO2) is disposed between the conductive layer 112 and the conductive layer 111.

[0088] Conductive layer 112 serves as the source line SL ( Figure 1 To fulfill its function.

[0089] Conductive layer 111 serves as the source-side selected gate line (SGS). Figure 1 The gate electrodes of the multiple source-side selection transistors (STS) connected to it function. The conductive layer 111 is electrically independent for each memory block (BLK).

[0090] In addition, among the multiple conductive layers 110, one or more conductive layers 110 located at the bottom layer serve as the source-side selected gate line (SGS). Figure 1 The gate electrodes of the multiple source-side selection transistors (STS) connected to it function. The multiple conductive layers 110 are electrically independent for each memory block (BLK).

[0091] Additionally, the plurality of conductive layers 110 located above the conductive layer 110 serve as word lines WL ( Figure 1 ) and multiple storage units MC connected to it Figure 1 The gate electrode of the memory block BLK functions. The plurality of conductive layers 110 are electrically independent for each memory block BLK.

[0092] Additionally, one or more conductive layers 110 located above the conductive layer 110 serve as drain-side selected gate lines (SGD) and multiple drain-side selected transistors (STD) connected thereto. Figure 1 The gate electrode of the array functions. The plurality of conductive layers 110 are electrically independent for each string assembly SU.

[0093] Semiconductor pillars 120 are arranged in a specified pattern in the X and Y directions. Semiconductor pillars 120 serve as a memory string (MS). Figure 1 The semiconductor pillar 120 contains multiple memory cells (MCs) and channel regions of selection transistors (STDs, STSs) that function. The semiconductor pillar 120 is, for example, a semiconductor layer such as polysilicon (Si). The semiconductor pillar 120 is, for example, like... Figure 6 As shown, it has a roughly cylindrical shape with a bottom, and an insulating layer 125 such as silicon oxide is provided in the central part.

[0094] For example, like Figure 6 As shown, the semiconductor pillar 120 has a memory cell array layer L MCA1 Semiconductor region 120 L and included in the memory cell array layer L MCA2 Semiconductor region 120 U Additionally, the semiconductor pillar 120 includes: a semiconductor region 120 J Set in semiconductor region 120 L With semiconductor region 120 U Between; impurity region 122, located in semiconductor region 120 L Below; and impurity region 121, disposed in semiconductor region 120. U Above.

[0095] Semiconductor Area 120 L It is a roughly cylindrical region extending along the Z-direction. Semiconductor region 120 L The outer periphery is contained in the memory cell array layer L. MCA1 It is surrounded by a plurality of conductive layers 110 and conductive layers 111, and is oriented toward the plurality of conductive layers 110 and conductive layers 111.

[0096] Semiconductor Area 120 U It is a roughly cylindrical region extending along the Z-direction. Semiconductor region 120 U The outer periphery is contained in the memory cell array layer L. MCA2 The semiconductor region 120 is surrounded by and faces multiple conductive layers 110. U The width in the X direction and the width in the Y direction are related to the semiconductor region 120. L The width in the X direction and the width in the Y direction are approximately the same.

[0097] Semiconductor Area 120 J Set in the memory cell array layer L MCA1 Above multiple conductive layers 110, and disposed within the memory cell array layer L MCA2 Below the multiple conductive layers 110. Semiconductor region 120 J The width in the X direction and the width in the Y direction are 120 times greater than the semiconductor region. L The width in the X direction and the width in the Y direction are larger, and are larger than those of the semiconductor region 120. U The width in the X direction and the width in the Y direction are large.

[0098] Impurity region 122 is bonded to semiconductor layer 113 of conductive layer 112. Impurity region 122 contains, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). The outer peripheral surface of impurity region 122 is surrounded by conductive layer 111 and faces conductive layer 111.

[0099] Impurity region 121 contains, for example, N-type impurities such as phosphorus (P). Impurity region 121 is connected to bit line BL via contact Ch, etc.

[0100] The gate insulating film 130 has a generally bottomed cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. The gate insulating film 130 is, for example, like... Figure 7 As shown, a tunnel insulating film 131, a charge storage film 132, and a barrier insulating film 133 are deposited between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are, for example, insulating films such as silicon oxide (SiO2). The charge storage film 132 is, for example, a film capable of storing charge such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend along the Z-direction along the outer peripheral surface of the semiconductor pillar 120.

[0101] also, Figure 7 The diagram shows an example where the gate insulating film 130 has a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also have a floating gate, such as polysilicon containing N-type or P-type impurities.

[0102] [Storage cell array layer L] MCA1 L MCA2 Wiring area R HU1 R HU2 R HU3 R HU4 [Structure]

[0103] For example, like Figure 4 and Figure 5 As shown, in the memory cell array layer L MCA1 L MCA2 Each wiring area R HU1 R HU2 R HU3 R HU4 , with memory hole region R MH1 R MH2 Similarly, multiple conductive layers 110 are arranged in the Z direction. The actual number of conductive layers 110 can range from, for example, tens to hundreds of layers, but... Figure 4 and Figure 5 For ease of understanding, the diagram below shows the L-layer of the memory cell array. MCA1 L MCA2Each layer has eight conductive layers 110. Here, the memory cell array layer L... MCA1 The eight conductive layers 110 configured in the middle are sequentially referred to as conductive layers 110 from bottom to top, and the memory cell array layer L... MCA2 The eight conductive layers 110 configured in the middle are referred to as the 9th to 16th conductive layers 110 from the bottom to the top.

[0104] [Storage cell array layer L] MCA1 L MCA2 Wiring area R HU1 [Structure]

[0105] For example, like Figure 4 As shown, in the lower storage cell array layer L MCA1 Wiring area R HU1 A roughly stepped structure is formed within it. This roughly stepped structure is configured as follows: That is, in the lower storage cell array layer L... MCA1 Wiring area R HU1 In this configuration, conductive layers 110, for example, the first to eighth layers, extending along the X direction, are arranged along the Z direction. An insulating layer 101 is provided between the first to eighth conductive layers 110. At this time, the first conductive layer 110 is continuous in the X direction, but the second to eighth conductive layers 110 are physically separated midway along the X direction. That is, in the wiring region R... HU1 In the middle, the memory hole area R is set. MH1 Extending along the X direction to the memory hole region R MH2 A portion of the first conductive layer 110, from the memory hole region R MH1 Extending along the X direction to the wiring area R HU1 The ends of the 2nd to 8th conductive layers 110 in the X direction, and from the memory hole region R MH2 Extending along the X direction to the wiring area R HU1 The ends of the 2nd to 8th conductive layers 110 in the X direction. Additionally, in the 2nd to 8th conductive layers 110, one side in the X direction is provided ( Figure 4 The end of the conductive layer in the X direction (on the left side) is located at the lower end of the conductive layer, closer to the memory hole region R. MH1 The farther away, the higher the conductive layer is located, the further away from the memory hole region R. MH1 The closer. Additionally, in the 2nd to 8th conductive layers 110, one layer is located on the other side in the X direction ( Figure 4 The X-direction end of the conductive layer (on the right side of the image) is located at the lower end of the conductive layer, closer to the memory hole region R. MH2 The farther away, the higher the conductive layer is located, the further away from the memory hole region R. MH2The closer. Therefore, as it moves from the 2nd layer toward the 8th conductive layer 110 (as it moves upward in the Z direction), it is located on one side in the X direction ( Figure 4 The conductive layer 110 on the left side of the image is disposed on the other side in the X direction. Figure 4 The spacing between the conductive layers 110 (on the right side of the image) gradually increases. Furthermore, the central position of the spacing between the 2nd to 8th conductive layers 110 is consistent in the X direction. This forms a roughly stepped structure with V-shaped depressions. The V-shaped depressions are filled with an insulating layer 140 such as silicon oxide (SiO2).

[0106] In addition, for example, like Figure 4 As shown, in the upper storage cell array layer L MCA2 Wiring area R HU1 In the middle, multiple conductive layers 110 extending in the X direction are arranged along the Z direction. An insulating layer 101 is disposed between the multiple conductive layers 110 arranged along the Z direction.

[0107] In addition, for example, like Figure 4 As shown, in the memory cell array layer L MCA1 L MCA2 Wiring area R HU1 In the middle, multiple contacts CC are arranged along the X direction. These multiple contacts CC extend along the Z direction, penetrating the memory cell array layer L. MCA2 Multiple conductive layers 110 are present, and they extend through the memory cell array layer L. MCA1 The insulating layer 140 is filled in the roughly stepped structure, and at the lower end it is connected to the memory cell array layer L. MCA1 The conductive layers 110 are connected to each other. Each contact CC may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, an insulating layer 102 such as silicon oxide (SiO2) is provided on the outer peripheral surface of each contact CC.

[0108] In addition, Figure 4 In the illustrated cross-section, contact CC is connected to the memory cell array layer L. MCA1 The structure is roughly stepped. Therefore, for example, the distance in the X direction between the contact CC connected to the first conductive layer 110 and the second to eighth conductive layers 110 or the insulating layer 101 disposed between them is at least greater than the film thickness of the insulating layer 102. On the other hand, in Figure 4 In the illustrated cross-section, the junction CC penetrates the memory cell array layer L. MCA2 The structure contains multiple conductive layers 110 and insulating layers 101. Therefore, for example, the distance in the X direction between the contact CC connected to the first conductive layer 110 and the 9th to 16th conductive layers 110 or the insulating layer 101 disposed between them is approximately the film thickness of the insulating layer 102, which is relatively small.

[0109] In addition, Figure 3 In the example shown, it is set in the wiring area R HU1 Multiple contacts CC are arranged in a row along the X direction. Hereinafter, the wiring area R is sometimes referred to as... HU1 This type of area is called the contact area CR1.

[0110] [Storage cell array layer L] MCA1 L MCA2 Wiring area R HU2 [Structure]

[0111] For example, like Figure 4 As shown, in the lower storage cell array layer L MCA1 Wiring area R HU2 In the middle, multiple conductive layers 110 extending in the X direction are arranged along the Z direction. An insulating layer 101 is disposed between the multiple conductive layers 110 arranged along the Z direction.

[0112] In addition, for example, like Figure 4 As shown, in the upper storage cell array layer L MCA2 Wiring area R HU2 A roughly stepped structure is formed within it. This roughly stepped structure is configured as follows: That is, in the upper storage cell array layer L... MCA2 Wiring area R HU2 In this configuration, conductive layers 110, for example, layers 9 to 16, extending along the X direction, are arranged along the Z direction. An insulating layer 101 is provided between the conductive layers 9 to 16. At this time, the 9th conductive layer 110 is continuous in the X direction, but the 10th to 16th conductive layers 110 are physically separated midway along the X direction. That is, in the wiring region R... HU2 In the middle, the memory hole area R is set. MH1 Extending along the X direction to the memory hole region R MH2 Part of the 9th conductive layer 110, from the memory hole region R MH1 Extending along the X direction to the wiring area R HU2 The ends of the 10th to 16th conductive layers 110 in the X direction, and from the memory hole region R MH2 Extending along the X direction to the wiring area R HU2 The ends of the 10th to 16th conductive layers 110 in the X direction. Additionally, in the 10th to 16th conductive layers 110, one side is provided in the X direction ( Figure 4 The end of the conductive layer in the X direction (on the left side) is located at the lower end of the conductive layer, closer to the memory hole region R. MH1 The farther away, the higher the conductive layer is located, the further away from the memory hole region R. MH1The closer. Additionally, in the 10th to 16th conductive layers 110, one layer is located on the other side in the X direction ( Figure 4 The X-direction end of the conductive layer (on the right side of the image) is located at the lower end of the conductive layer, closer to the memory hole region R. MH2 The farther away, the higher the conductive layer is located, the further away from the memory hole region R. MH2 The closer. Therefore, as it moves from the 10th layer toward the 16th conductive layer 110 (as it moves upward in the Z direction), it is positioned on one side in the X direction ( Figure 4 The conductive layer 110 on the left side of the image is disposed on the other side in the X direction. Figure 4 The spacing between the conductive layers 110 (on the right side of the image) gradually increases. Furthermore, the center position of the spacing between the 10th to 16th conductive layers 110 is consistent in the X direction. This forms a generally stepped structure with V-shaped depressions. The V-shaped depressions are filled with an insulating layer 141 such as silicon oxide (SiO2).

[0113] In addition, for example, like Figure 4 As shown, in the memory cell array layer L MCA2 Wiring area R HU2 Multiple contacts CC are arranged along the X direction. These multiple contacts CC extend along the Z direction, penetrating the memory cell array layer L. MCA2 The insulating layer 141 is filled in the roughly stepped structure, and at the lower end it is connected to the memory cell array layer L. MCA2 The conductive layers 110 are connected to each other. Each contact CC may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, an insulating layer 102 such as silicon oxide (SiO2) is provided on the outer peripheral surface of each contact CC.

[0114] In addition, Figure 4 In the illustrated cross-section, contact CC is connected to the memory cell array layer L. MCA2 The structure is roughly stepped. Therefore, for example, the distance in the X direction between the contact CC connected to the 9th conductive layer 110 and the 10th to 16th conductive layers 110 or the insulating layer 101 disposed between them is at least greater than the film thickness of the insulating layer 102.

[0115] In addition, Figure 3 In the example shown, it is set in the wiring area R HU2 Multiple contacts CC are arranged in a row along the X direction. Hereinafter, the wiring area R is sometimes referred to as... HU2 This type of area is called the contact area CR2.

[0116] [Storage cell array layer L] MCA1 L MCA2 Wiring area R HU3 [Structure]

[0117] For example, like Figure 5 As shown, in the memory cell array layer L MCA1 L MCA2 Wiring area R HU3 Multiple through-connectors C4 are arranged along the X direction. These multiple through-connectors C4 extend along the Z direction and penetrate the memory cell array layer L. MCA1 L MCA2 The system contains multiple conductive layers 110. Each through-contact C4 is connected at its upper end to wiring m0 in wiring layer M0 and at its lower end to wiring d2 in wiring layer D2. Each through-contact C4 may also comprise a laminated film of barrier conductive film such as titanium nitride (TiN) and metal film such as tungsten (W). Furthermore, each through-contact C4 is electrically insulated from the conductive layers 110 via an insulating layer 103 such as silicon oxide (SiO2).

[0118] In addition, Figure 3 In the example shown, it is set in the wiring area R HU3 Multiple through-connection points C4 are arranged in a row along the X direction. Hereinafter, the wiring area R is sometimes referred to as... HU3 This type of area is called the through-connection area TR1.

[0119] [Storage cell array layer L] MCA1 L MCA2 Wiring area R HU4 [Structure]

[0120] For example, like Figure 5 As shown, in the memory cell array layer L MCA1 L MCA2 Wiring area R HU4 Multiple through-connectors C4 are arranged along the X direction. These multiple through-connectors C4 extend along the Z direction and penetrate the memory cell array layer L. MCA1 L MCA2 The system contains multiple conductive layers 110. Each through-contact C4 is connected at its upper end to wiring m0 in wiring layer M0 and at its lower end to wiring d2 in wiring layer D2. Each through-contact C4 may also comprise a laminated film of barrier conductive film such as titanium nitride (TiN) and metal film such as tungsten (W). Furthermore, each through-contact C4 is electrically insulated from the conductive layers 110 via an insulating layer 103 such as silicon oxide (SiO2).

[0121] In addition, Figure 3 In the example shown, it is set in the wiring area R HU4 Multiple through-connection points C4 are arranged in a row along the X direction. Hereinafter, the wiring area R is sometimes referred to as... HU4 This type of area is called the through-connection area TR2.

[0122] [Structure of wiring layers M0, M1, and M2]

[0123] For example, like Figure 4 and Figure 5 As shown, the wiring layers M0, M1, and M2 contain multiple wirings that are electrically connected to at least one of the configurations in the memory cell array MCA and the peripheral circuit PC.

[0124] Each wiring layer M0 comprises multiple wirings m0. These multiple wirings m0 may, for example, comprise a laminated film of barrier conductive films such as titanium nitride (TiN) and metal films such as copper (Cu). Furthermore, a portion of the multiple wirings m0 functions as bit lines BL.

[0125] The wiring layer M1 contains multiple wirings m1. The multiple wirings m1 may also include, for example, a laminated film of barrier conductive films such as titanium nitride (TiN) and metal films such as copper (Cu).

[0126] The wiring layer M2 contains multiple wirings m2. These multiple wirings m2 may, for example, be multilayer films containing barrier conductive films such as titanium nitride (TiN) and metal films such as aluminum (Al).

[0127] Here, for example, like Figure 3 As shown, in the two memory hole regions R MH1 R MH2 Between them, two line connection areas CNR1 and CNR2 are arranged along the X direction.

[0128] Line connection area CNR1 includes wiring m0, m1 (for connecting contacts CC in contact area CR1 to through contacts C4 in through contact area TR1, or for connecting designated contacts CC in contact area CR1 to each other). Figure 4 , Figure 5 The area where the line connection area CNR1 overlaps with the contact area CR1 and the through contact area TR1 when viewed from the Z direction.

[0129] Line connection area CNR2 includes wiring m0, m1 (for connecting contacts CC in contact area CR2 to through contacts C4 in through contact area TR2, or for connecting designated contacts CC in contact area CR2 to each other). Figure 4 , Figure 5 The area where the line connection area CNR2 overlaps with the contact area CR2 and the through contact area TR2 when viewed from the Z direction.

[0130] Next, for example, refer to Figure 8 For Figure 3An example of connecting contact CC to through contact C4 in the line connection area CNR1 will be illustrated. Furthermore, Figure 8 This schematically represents a line connection state; various forms of line connection states can be used as specific examples. Furthermore, Figure 8 In this document, the 15 contact points CC are referred to as contact points CC-1 to CC-15. Additionally, the 8 through contact points C4 are referred to as through contact points C4-1 to C4-8. Furthermore, the wirings m0 and m1 are also explained with appropriately labeled numbers to distinguish each wiring.

[0131] A wiring m0-1 extending in the X direction is connected to the upper end of contact CC-1 and contact CC-15 of the 8th conductive layer 110. Similarly, wiring m0-2 to m0-7 extending in the X direction are connected to contacts CC-2 to CC-7 of the 7th to 2nd conductive layers 110 and contacts CC-14 to CC-9 of the 7th to 2nd conductive layers 110, respectively. A wiring m0-8 is connected to the upper end of contact CC-8 of the 1st conductive layer 110.

[0132] Wiring lines m0-41 to m0-48 are connected to the upper ends of the through-connection points C4-1 to C4-8 in the through-connection area TR1, respectively.

[0133] Wiring m0-1 and wiring m0-41 are connected to wiring m1-1 extending in the Y direction. Similarly, wiring m0-2 to m0-7 and wiring m0-42 to m0-48 are respectively connected to wiring m1-2 to m1-7 extending in the Y direction.

[0134] Because of this configuration, for example, transistor layer L TR ( Figure 4 , Figure 5 ) Operating voltage generation circuit 21 ( Figure 1 The generated operating voltage passes through the through contacts C4-1 to C4-8. Figure 8 The wiring connections and contacts CC1 to CC15 shown are individually supplied to the lower memory cell array layer L. MCA1 The conductive layers 110 from layer 1 to layer 8.

[0135] Figure 3 The wire connection between contact CC in contact area CR2 of line connection area CNR2 and through contact C4 in through contact area TR2 can, for example, be made using... Figure 8 The line connection status shown is the same as the line connection.

[0136] By making such line connections, for example, transistor layer LTR ( Figure 4 , Figure 5 ) Operating voltage generation circuit 21 ( Figure 1 The generated operating voltage is transmitted through each through contact C4 located in the through contact area TR2, for example, with... Figure 8 The wiring connections shown, along with the corresponding connections in the contact area CR2, are individually supplied to the upper memory cell array layer L. MCA2 The 9th to 16th conductive layers 110.

[0137] [Manufacturing Method]

[0138] Next, referring to the schematic XZ section... Figures 9-16 A portion of the manufacturing method of the semiconductor memory device according to the first embodiment will be described.

[0139] [Preparation Steps]

[0140] In this manufacturing method, firstly, a transistor layer L is formed on a semiconductor substrate 100. TR and wiring layers D0, D1, D2 ( Figure 4 , Figure 5 Additionally, an insulating layer is formed on the upper surface of wiring layer D2, a conductive layer 112 is formed on the upper surface of this insulating layer, and a conductive layer 111 is formed above the conductive layer 112. Figure 6 ).

[0141] Step 1: Figure 9 ]

[0142] Reference Figure 9 The first step will be explained.

[0143] In step 1, firstly, in conductive layer 111 ( Figure 6 Multiple insulating layers 101 and multiple sacrificial layers 110A are alternately formed on the surface. The sacrificial layers 110A may contain, for example, silicon nitride (SiN). This process is performed, for example, by CVD (Chemical Vapor Deposition).

[0144] Next, in the wiring area R HU1In this process, a portion of the insulating layer 101 and the sacrificial layer 110A is removed, forming a generally stepped structure with a V-shaped depression. This process is performed by repeatedly removing the insulating layer 101, the sacrificial layer 110A, and the resist by forming a photoresist on the upper surfaces of the alternately formed insulating layer 101 and the sacrificial layer 110A. The process of removing the insulating layer 101, the sacrificial layer 110A, and the photoresist is performed, for example, by wet etching or dry etching (hereinafter sometimes referred to as "etching, etc.") such as Reactive Ion Etching.

[0145] After forming a generally stepped structure with a V-shaped depression, an etch stop layer 115 is formed on the upper and side surfaces of the generally stepped structure, as well as on the upper surface of the uppermost sacrificial layer 110A. The etch stop layer 115 may contain, for example, silicon nitride (SiN). This process is performed, for example, by reduced pressure CVD (Low-Pressure Chemical Vapor Deposition).

[0146] Step 2: Figure 10 ]

[0147] Reference Figure 10 The second step will be explained.

[0148] In step 2, firstly, excess etch stop layer 115 formed on the upper surface and sides of the uppermost sacrificial layer 110A is removed. This process is performed, for example, by etching.

[0149] Next, the uppermost sacrificial layer 110A is removed. After removing the uppermost sacrificial layer 110A, the surface portion of the uppermost insulating layer 101 among the multiple insulating layers 101 is removed to the required thickness. This process is performed, for example, by chemical mechanical polishing (CMP).

[0150] Step 3: Figure 11 ]

[0151] Reference Figure 11 Step 3 will be explained.

[0152] In step 3, firstly, an insulating layer 140 is filled into the upper surface of the generally stepped structure with a V-shaped depression and the uppermost insulating layer 101. The insulating layer 140 contains, for example, silicon oxide (SiO2). This process is performed, for example, by CVD.

[0153] Next, the upper surface of the insulating layer 140 is ground to make it flat. This process is performed, for example, by CMP.

[0154] Next, in the memory hole region R MH1 and memory hole area R MH2 Multiple memory holes MH are formed L Memory port MH L Extending along the Z direction and penetrating the insulating layer 101 and the sacrificial layer 110A. Memory hole MH L The formation of [something] occurs, for example, through RIE (Rich Internet of Things).

[0155] Next, to the memory port MH L The internal filling of the memory via MH is amorphous silicon 120A. This process is performed, for example, by methods such as CVD. Alternatively, in this process, the memory via MH can be filled with amorphous silicon 120A before filling it with the amorphous silicon 120A. L Insulating films such as silicon oxide (SiO2) and silicon nitride (SiN) are formed on the inner circumferential surface.

[0156] Step 4: Figure 12 ]

[0157] Reference Figure 12 Step 4 will be explained.

[0158] In step 4, the portion above the insulating layer 140 is manufactured using a manufacturing method that is substantially the same as that used in steps 1 through 3.

[0159] In other words, firstly, a plurality of insulating layers 101 and a plurality of sacrificial layers 110A are alternately formed on the insulating layer 140. The sacrificial layer 110A may contain, for example, silicon nitride (SiN). This process is performed, for example, by CVD.

[0160] Furthermore, the insulating layer 101 and sacrificial layer 110A formed above the insulating layer 140 are sometimes referred to as the upper insulating layer 101 and sacrificial layer 110A. In addition, the insulating layer 101 and sacrificial layer 110A formed below the insulating layer 140 are sometimes referred to as the lower insulating layer 101 and sacrificial layer 110A.

[0161] Next, in the wiring area R HU2 In this process, a portion of the upper insulating layer 101 and the sacrificial layer 110A is removed, for example by etching, to form a generally stepped structure with a V-shaped depression.

[0162] Next, in the wiring area R HU2 The upper and side surfaces of the generally stepped structure, as well as the upper surface of the uppermost insulating layer 101, are formed with an etch stop layer 116, for example, by reduced pressure CVD. The etch stop layer 116 may contain, for example, silicon nitride (SiN).

[0163] Next, the excess etch stop layer 116 formed on the upper surface and side of the uppermost insulating layer 101 is removed by etching or the like.

[0164] Next, the wiring area R is formed. HU2 The structure has a generally stepped, V-shaped recess, and the upper surface of the top insulating layer 101 is filled with an insulating layer 141. The insulating layer 141 may contain, for example, silicon oxide (SiO2). This process is performed, for example, by CVD.

[0165] Next, the upper surface of the insulating layer 141 is ground to make it flat. This process is performed, for example, by CMP.

[0166] Next, in the memory hole region R MH1 and memory hole area R MH2 In the middle, multiple memory holes MH are formed in the upper insulating layer 101 and sacrificial layer 110A. H Multiple memory holes MH H Extending along the Z direction, it penetrates the upper insulating layer 101 and the sacrificial layer 110A, and reaches the memory hole MH formed in the lower insulating layer 101 and the sacrificial layer 110A. L The upper end. A memory hole MH is formed there. H The process is carried out, for example, through RIE.

[0167] Next, the memory hole MH L The amorphous silicon 120A filling inside is removed. This process is performed, for example, by wet etching. Thus, the memory hole MH... H The memory hole MH is formed by removing amorphous silicon 120A, resulting in a hollow state. L Connected.

[0168] Next, in the memory hole region R MH1 and memory hole area R MH2 The memory hole MH formed in L MH H A gate insulating film 130, a semiconductor pillar 120, and an insulating layer 125 are formed on the inner peripheral surface. Figure 6 This process is performed, for example, by CVD.

[0169] Step 5: Figure 13 ]

[0170] Reference Figure 13 Step 5 will be explained.

[0171] In step 5, in the wiring area R HU1 In the middle, a contact hole CCA is formed in the upper insulating layer 101 and the sacrificial layer 110A. This contact hole CCA is formed in the wiring area R. HU1The contact CC ( Figure 4 The corresponding position. Contact holes (CCAs) are formed, for example, by methods such as RIE.

[0172] Next, in the wiring area R HU1 The contact holes CCA are filled with amorphous silicon.

[0173] Next, in the inter-block insulation layer ST and the intra-block insulation layer st ( Figure 3 , Figure 6 A replacement groove (not shown) is formed at the corresponding position. The replacement groove extends along the Z and X directions, not only separating the insulating layer 101 and the sacrificial layer 110A, but also the conductive layer 111 (…). Figure 6 ), and semiconductor layer 113 ( Figure 6 The upper part of the structure is split in the Y direction. This process is performed, for example, by RIE.

[0174] Step 6: Figure 14 ]

[0175] Reference Figure 14 Step 6 will be explained.

[0176] In step 6, the sacrificial layer 110A is selectively removed by wet etching with a solution such as phosphoric acid in a replacement tank.

[0177] Next, a conductive layer 110 is formed in the portion after the sacrificial layer 110A has been removed. This process is performed, for example, by forming the conductive layer 110 via a replacement tank using CVD or the like. The conductive layer 110 may also comprise a laminated film of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W).

[0178] Furthermore, in the following description, the process of selectively removing the sacrificial layer 110A by means of wet etching, and then forming the conductive layer 110 in the portion after the removal of the sacrificial layer 110A, is sometimes referred to as "replacement".

[0179] Next, the replacement trench is filled with silicon dioxide (SiO2) to form an inter-block insulating layer ST and an intra-block insulating layer st.

[0180] Step 7: Figure 15 ]

[0181] Reference Figure 15 Step 7 will be explained.

[0182] In step 7, in the wiring area R HU1 In this process, the amorphous silicon filling the contact hole CCA is removed. This step is performed, for example, by wet etching.

[0183] Next, in the wiring area R HU1In this process, a hole is formed extending in the Z direction from the lower end of the contact hole CCA toward the insulating layer 140, causing the contact hole CCA to extend downwards. The lower end of the contact hole CCA extends downwards to the etch stop layer 115. This process is performed, for example, by a method such as RIE.

[0184] In wiring area R HU1 While extending the contact hole CCA downwards, in the wiring area R HU2 In the insulating layer 141, a hole extending along the Z direction is formed to form a contact hole CCA. That is, in the wiring area R... HU2 The contact CC ( Figure 4 A contact hole (CCA) is formed at the corresponding location. The lower end of the contact hole (CCA) reaches the etch stop layer 116. This process is performed, for example, by a method such as RIE.

[0185] Next, in the wiring area R HU1 The inner surface of the contact hole CCA and the area formed in the wiring region R HU2 An insulating film is formed on the inner surface of the contact hole CCA using silicon oxide (SiO2) and the like.

[0186] Furthermore, the wiring area R HU1 The portion reached by the lower end of the contact hole CCA in the etch stop layer 115, and the wiring area R HU2 The portion of the contact hole CCA reached in the etch termination layer 116 is removed by wet etching or the like.

[0187] Wiring area R formed like this HU1 The contact hole CCA is a through hole that extends along the Z direction and exposes the upper surface of the lower conductive layer 110.

[0188] Additionally, the wiring area R formed in this way HU2 The contact hole CCA is a through hole that extends along the Z direction and exposes the upper surface of the upper conductive layer 110.

[0189] Step 8: Figure 16 ]

[0190] Reference Figure 16 Step 8 will be explained.

[0191] In step 8, in the wiring area R HU1 Contact holes CCA and formed in wiring area R HU2 After forming a barrier conductive film such as titanium nitride (TiN) on the inner surface of the contact hole CCA, tungsten (W) or the like is used to fill each contact hole CCA. Thus, in the wiring area R... HU1 and wiring area R HU2 Forming contact CC.

[0192] [Comparative Example]

[0193] Here, refer to Figure 17 and Figure 18 The comparative example semiconductor memory device will be described. Figure 17 This is a simplified schematic cross-sectional view used to illustrate a comparative example of a semiconductor memory device. Figure 18 This schematically illustrates the line connection status of the contacts CC' in the comparative example.

[0194] like Figure 17 As shown, in the comparative example semiconductor memory device, in the lower memory cell array layer L having alternating layers of conductive layer 110' and insulating layer 101'... MCA1 Above this, an upper memory cell array layer L is formed, consisting of alternating layers of conductive layers 110' and insulating layers 101'. MCA2 Additionally, it extends to the lower storage cell array layer L. MCA1 'and the upper storage unit array layer L MCA2 It forms a roughly stepped structure with a V-shaped depression.

[0195] Because of this roughly stepped structure, the lower memory cell array layer L is configured... MCA1 The multilayer conductive layer 110, except for the bottommost conductive layer 110, is physically separated into one side in the X direction. Figure 17 The left side of the middle, and the other side in the X direction ( Figure 17 The right side of the image. Configured in the upper storage cell array layer L. MCA2 The multilayer conductive layer 110' is physically separated into one side in the X direction ( Figure 17 The left side of the middle, and the other side in the X direction ( Figure 17 (The right side of the text)

[0196] Each conductive layer 110' is connected to contacts CC11', CC21', CC22' to CC81', CC82' extending along the Z direction. These contacts CC11', CC21', CC22' to CC81', CC82' are arranged as follows: Figure 18 The state shown is connected via wiring m1' to m7'. Therefore, it is physically separated into one side in the X direction ( Figure 17 The left side and the other side Figure 17 The conductive layer 110' on the right side of the image is electrically connected via contacts CC21', CC22' to CC81', CC82' and wiring m1' to m7'.

[0197] In addition, such as Figure 18As shown, to connect contacts CC21', CC22' to CC81', and CC82', seven wirings m1' to m7' are required arranged along the Y direction. The width of the Y-direction area for the wirings m1' to m7' is called W. Y .

[0198] [Effects of the first embodiment]

[0199] Figure 19 It is a comparison Figure 17 A simplified schematic cross-sectional view of the semiconductor memory device according to the first embodiment. Figure 20 schematic representation Figure 19 The schematic structure shows the line connection status of the contacts C and C in the diagram.

[0200] like Figure 19 As shown, in the first embodiment, the lower storage cell array layer L MCA1 The roughly stepped structure formed in the middle and the upper storage cell array layer L MCA2 The roughly stepped structure formed in the middle is located at a position offset in the X direction.

[0201] Each conductive layer 110 is connected to contacts CC11, CC12 to CC71, CC72 extending along the Z direction. These contacts CC11, CC12 to CC71, CC72 are arranged as follows: Figure 20 The states shown are connected via wiring m1 to m6.

[0202] Therefore, configured in the lower storage cell array layer L MCA1 In the conductive layer 110, it is physically separated into one side in the X direction ( Figure 19 The left side of the middle part and the other side ( Figure 19 The conductive layer 110 on the right side of the image is as follows: Figure 20 As shown, the electrical connection is achieved through contacts CC21, CC22 to CC41, CC42 and wiring m1 to m3.

[0203] Additionally, configured in the upper storage cell array layer L MCA2 In the conductive layer 110, it is physically separated into one side in the X direction ( Figure 19 The left side of the middle part and the other side ( Figure 19 The conductive layer 110 on the right side of the image is as follows: Figure 20 As shown, the electrical connection is achieved through contacts CC51, CC52 to CC71, CC72 and wiring m4 to m6.

[0204] In this configuration, the wirings m1 to m3 arranged along the Y direction are staggered with the wirings m4 to m6 arranged along the Y direction in the X direction. Therefore, the number of wirings arranged along the Y direction becomes... Figure 18The number of wirings arranged along the Y direction in the comparative example shown is about half that of the other two. Therefore, in the first embodiment, the width of the Y-direction of the wire connection area where wirings m1 to m6 are arranged is approximately W. Y / 2, becoming about half of the comparative example.

[0205] In this way, compared with the comparative example, the width of the wire connection region in the Y direction is narrower in the first embodiment. Therefore, in the first embodiment, even if the number of wires arranged in the Y direction increases corresponding to the increase in the number of stacked layers of conductive layer 110, it is possible to suppress the wire connection regions CNR1 and CNR2 ( Figure 3 The width of the Y direction of the storage block BLK ( Figure 3 The width in the Y direction increases.

[0206] [Second Implementation]

[0207] Next, the configuration of the semiconductor memory device according to the second embodiment will be described with reference to the accompanying drawings. Furthermore, in the following description, the same reference numerals are used for components identical to those in the first embodiment, and descriptions are simplified or omitted.

[0208] [structure]

[0209] Figure 21 This is a schematic enlarged top view of the semiconductor memory device according to the second embodiment, equivalent to... Figure 2 The diagram shown in Figure A is a schematic enlarged view, illustrating the configuration of the upper memory cell array layer. Figure 22 It is Figure 21 The schematic cross-sectional view shown is obtained by cutting along line F-F' and observing in the direction of the arrow.

[0210] like Figure 21 As shown, the semiconductor memory device of the second embodiment has a contact region CR3 instead of a contact region CR1. Furthermore, the semiconductor memory device of the second embodiment has a contact region CR4 instead of a contact region CR2.

[0211] Storage cell array layer L MCA1 The structure in the contact region CR3 is similar to the memory cell array layer L in the first embodiment. MCA1 The structure is the same in the contact area CR1.

[0212] Storage cell array layer L MCA2 The contact area CR3 includes: a pair of terminating insulating layers ST' extending in the X direction; a sacrificial layer 110A extending in the X direction between the pair of terminating insulating layers ST'; and a plurality of contacts CC arranged in the X direction and surrounded by the sacrificial layer 110A on their outer peripheral surfaces.

[0213] A pair of terminating insulating layers ST' may contain, for example, silicon oxide (SiO2). The pair of terminating insulating layers ST' are spaced apart in the Y direction and extend along the X and Z directions with a plurality of contacts CC disposed in the contact region CR3 in between.

[0214] The lengths of the pair of terminating insulating layers ST' in the X direction are longer than the lengths of the sacrificial layer 110A in the X direction. In the X direction, one end of the sacrificial layer 110A and the other end are located between one end of the terminating insulating layer ST' and the other end.

[0215] One side of the pair of terminating insulating layers ST' in the Y direction is connected to the plurality of sacrificial layers 110A and insulating layers 101 included in the contact region CR3. The other side of the pair of terminating insulating layers ST' in the Y direction is connected to the plurality of conductive layers 110 and insulating layers 101 not included in the contact region CR3. Furthermore, the depth of the pair of terminating insulating layers ST' in the Z direction reaches the upper memory cell array layer L. MCA2 ( Figure 22 up to the lower end of the position.

[0216] Sacrificial layer 110A, such as Figure 22 As shown, multiple layers are deposited in the Z direction instead of the conductive layer 110. The two ends of the sacrificial layer 110A in the X direction are respectively connected to the conductive layer 110. In addition, the two ends of the sacrificial layer 110A in the Y direction are respectively connected to the terminating insulating layer ST'. Furthermore, an insulating layer 101 is provided between the multiple sacrificial layers 110A arranged along the Z direction.

[0217] The reason why the sacrificial layer 110A remains in the portion sandwiched between the pair of terminating insulating layers ST' is as follows. Details will be described below in the manufacturing method of the second embodiment. However, in the process of selectively removing the sacrificial layer 110A by wet etching with a solution such as phosphoric acid via a replacement tank, the travel of the solution is suppressed in the portion sandwiched between the pair of terminating insulating layers ST'. As a result, the sacrificial layer 110A remains in the portion sandwiched between the pair of terminating insulating layers ST'.

[0218] The contact CC in the contact area CR3 is connected to the memory cell array layer L. MCA2 Multiple sacrificial layers 110A are formed in the memory cell array layer L. MCA1 The insulating layer 140 is filled in the roughly stepped structure, and its lower end is connected to the memory cell array layer L. MCA1 The conductive layers 110 are connected. Furthermore, in this embodiment, no insulating layer 102 is provided on the outer peripheral surface of the contact CC. Figure 4 In this embodiment, the outer peripheral surface of the contact CC is connected to the memory cell array layer L. MCA2 The sacrificial layer 110A and the insulating layer 101 disposed between them are connected.

[0219] The contact region CR4 is configured to be substantially the same as that of the contact region CR2. However, an insulating layer 102 is not provided on the outer peripheral surface of the contact CC located in the contact region CR4. Figure 4 ).

[0220] [Manufacturing Method]

[0221] Next, referring to the schematic XZ section... Figures 23-25 A portion of the manufacturing method of the semiconductor memory device according to the second embodiment will be described. Furthermore, characteristic aspects of the manufacturing method of the second embodiment will be described here.

[0222] [Status before replacement]

[0223] Figure 23 This indicates the state before the replacement.

[0224] like Figure 23 As shown, the lower insulating layer 101 and sacrificial layer 110A are alternately laminated. In the alternately laminated lower insulating layer 101 and sacrificial layer 110A, in the wiring region R... HU1 A roughly stepped structure with V-shaped depressions is formed in the middle. An insulating layer 140 is filled in this stepped structure.

[0225] Furthermore, the upper insulating layer 101 and the sacrificial layer 110A are alternately laminated. In the alternately laminated upper insulating layer 101 and sacrificial layer 110A, in the wiring area R... HU2 A roughly stepped structure with V-shaped depressions is formed in the middle. An insulating layer 141 is filled in this stepped structure.

[0226] Additionally, in the memory hole region R MH1 R MH2 Semiconductor pillars 120, etc. are formed.

[0227] also, Figure 23 The area with additional dots is a pair of terminating insulation layers ST' ( Figure 21 The area enclosed by the upper insulating layer 101 and a portion of the sacrificial layer 110A.

[0228] [Replaced Status]

[0229] Figure 24 This indicates the state after the replacement.

[0230] To become like Figure 23 When the insulating layer 101 and sacrificial layer 110A, as shown, are selectively removed by wet etching with a solution such as phosphoric acid in a replacement tank to form a conductive film 110, it becomes as shown in the figure. Figure 24 The state shown.

[0231] That is to say, in the sacrificial layer 110A, there is a pair of terminating insulating layers ST' ( Figure 21 The area enclosed by ) Figure 23 In the area with additional points, the movement of the drug solution is inhibited, thus the sacrificial layer 110A remains.

[0232] On the other hand, other parts of the sacrificial layer 110A are removed.

[0233] In the portion after the sacrificial layer 110A is removed, a conductive film 110 is formed by CVD or the like via a replacement trench.

[0234] [Formation of contact holes and contacts]

[0235] Figure 25 This indicates the state after a contact hole is formed, and subsequently, a contact point CC is formed within the contact hole.

[0236] In such Figure 24 In the state shown, a through-connection area R is formed. HU1 The upper insulating layer 101 and sacrificial layer 110A, and the contact holes of the lower insulating layer 140.

[0237] At the same time, a through-connection area R is formed. HU2 The contact hole of the upper insulating layer 141.

[0238] In the wiring area R HU1 After forming a barrier metal such as titanium nitride (TiN) on the inner surface of the contact hole, tungsten (W) or similar material is used to fill the contact hole. This creates a barrier in the wiring area R. HU1 Forming contact CC.

[0239] At the same time, in the wiring area R HU2 After forming a barrier metal such as titanium nitride (TiN) on the inner surface of the contact hole, tungsten (W) or similar material is used to fill the contact hole. This creates a barrier in the wiring area R. HU2 Forming contact CC.

[0240] [Third Implementation]

[0241] Next, the configuration of the semiconductor memory device according to the third embodiment will be described with reference to the accompanying drawings. Furthermore, in the following description, the same reference numerals are used for components identical to those in the first embodiment, and descriptions are simplified or omitted.

[0242] [structure]

[0243] Figure 26 This is a schematic enlarged top view of the semiconductor memory device according to the third embodiment, equivalent to... Figure 2The diagram shown in Figure A is a schematic enlarged view, illustrating the configuration of the memory cell array layer. Figure 27 It is Figure 26 The schematic cross-sectional view shown is obtained by cutting along line G-G' and observing in the direction of the arrow.

[0244] like Figure 27 As shown, the semiconductor memory device of the third embodiment is a device that includes a memory cell array (MCA). Figure 1 ) chip C M With PC containing peripheral circuitry ( Figure 1 ) chip C P It is formed by fitting together.

[0245] Chip C M The chip C contains multiple bonding electrodes PI1. P The chip contains multiple bonding electrodes PI2. The arrangement of the multiple bonding electrodes PI2 corresponds to the arrangement of the multiple bonding electrodes PI1. By bonding the bonding electrodes PI1 and PI2, the chip C can be bonded together. M With chip C P The bonding electrodes PI1 and PI2 are bonded together and electrically connected. The bonding electrodes PI1 and PI2 may contain conductive materials such as copper (Cu).

[0246] As mentioned above, chip C can be... M With chip C P bonding, therefore, chip C M The multiple conductive layers 110 and bit lines BL are electrically connected to the chip C via contacts CC, wiring m0 to m2, bonding electrodes PI1 and PI2, and wiring d0 to d2. P The transistor Tr is present in the device.

[0247] Chip C M With storage cell array layer L MCA1 Storage cell array layer L MCA2 Bit line BL, wiring layer M0, wiring layer M1, and wiring layer M2. However, chip C M The vertical arrangement of the components described above and their corresponding positions are as follows: Figure 4 The memory cell array layer L shown in the first embodiment MCA1 Storage cell array layer L MCA2 The wiring layers BL, M0, M1, and M2 are opposite.

[0248] Therefore, in the third embodiment, the storage cell array layer L MCA1 Located on the upper side, storage cell array layer L MCA2 Located on the lower layer. Additionally, it is formed on the memory cell array layer L. MCA1Its roughly stepped structure is inverted V-shaped and located in the wiring area R. HU2 Formed in the memory cell array layer L MCA2 Its roughly stepped structure is also inverted V-shaped and located in the wiring area R. HU1 .

[0249] The third embodiment is also similar to the first embodiment, and is formed on the memory cell array layer L. MCA1 The roughly stepped structure and the structure formed in the memory cell array layer L MCA2 The roughly stepped structure is formed at positions offset in the X direction.

[0250] Chip C P and Figure 4 Similarly, the first embodiment shown includes a semiconductor substrate 100 and a transistor layer L. TR Wiring layer D0, wiring layer D1 and wiring layer D2.

[0251] like Figure 26 As shown, the storage cell array layer L in this embodiment MCA1 L MCA2 The structure is basically the same as the reference. Figure 3 The memory cell array layer L of the first embodiment described above MCA1 L MCA2 The structure is the same. However, the memory cell array layer L in this embodiment is... MCA1 L MCA2 The wiring area R of the first embodiment is not present. HU3 and wiring area R HU4 The composition of.

[0252] Furthermore, the semiconductor memory device of the third embodiment may also include the contact region CR3 and contact region CR4 of the second embodiment instead of the contact region CR1 and contact region CR2 of the first embodiment.

[0253] [Fourth Implementation]

[0254] Next, the configuration of the semiconductor memory device according to the fourth embodiment will be described with reference to the accompanying drawings. Furthermore, in the following description, the same reference numerals are used for components identical to those in the first embodiment, and descriptions are simplified or omitted.

[0255] Figure 28 This is a schematic enlarged top view of the semiconductor memory device according to the fourth embodiment, equivalent to... Figure 2 The diagram shown in Figure A is a schematic enlarged view, illustrating the configuration of the upper memory cell array layer. Figure 29 It is Figure 28 The schematic cross-sectional view shown is obtained by cutting along the H-H' line and observing in the direction of the arrow. Figure 30 It is Figure 28 The schematic cross-sectional view shown is obtained by cutting along line I-I' and observing in the direction of the arrow.

[0256] like Figures 28-30 As shown, the semiconductor memory device of the fourth embodiment includes a wiring area R. HU11 R HU12 R HU13 R HU14 To replace the wiring area R HU1 R HU2 R HU3 R HU4 .

[0257] Wiring area R HU11 Wiring area wl extending along the X direction 11a and the junction area wl extending along the X direction 11b Wiring area wl 11a With the contact area wl 11b Arranged along the Y direction.

[0258] Wiring area R HU12 Wiring area wl extending along the X direction 12a and the junction area wl extending along the X direction 12b Wiring area wl 12a With the contact area wl 12b Arranged along the Y direction.

[0259] Wiring area R HU13 Wiring area wl extending along the X direction 13a and the junction area wl extending along the X direction 13b Wiring area wl 13a With the contact area wl 13b Arranged along the Y direction.

[0260] Wiring area R HU14 Wiring area wl extending along the X direction 14a and the junction area wl extending along the X direction 14b Wiring area wl 14a With the contact area wl 14b Arranged along the Y direction.

[0261] [Wiring area wl] 11a wl 12a wl 13a wl 14a [Structure]

[0262] Wiring area R HU11 Wiring area wl 11aWith wiring area R HU12 Wiring area wl 12a It is continuous in the X direction and includes a portion of a plurality of conductive layers 110 arranged in the Z direction. A portion of these conductive layers 110 extends in the X direction along the inter-block insulating layer ST and the intra-block insulating layer st.

[0263] Additionally, wiring area R HU13 Wiring area wl 13a With wiring area R HU14 Wiring area wl 14a It is continuous in the X direction and includes a portion of a plurality of conductive layers 110 arranged in the Z direction. A portion of these conductive layers 110 extends in the X direction along the inter-block insulating layer ST and the intra-block insulating layer st.

[0264] Therefore, the wiring area wl 11a wl 12a and wiring area wl 13a wl 14a The multiple conductive layers 110 contained herein are continuous in the X direction in each of the layers. As a result, the memory hole region R MH1 It includes multiple conductive layers 110 arranged along the Z-direction and memory hole region R. MH2 The multiple conductive layers 110 included, arranged along the Z-direction, are connected through the wiring region wl in each of the layers. 11a wl 12a wl 13a wl 14a It contains multiple conductive layers 110 arranged along the Z direction and is electrically connected.

[0265] [Connection Area wl] 11b [Structure]

[0266] Wiring area R HU11 The contact area wl 11b ( Figure 28 It includes a portion of a plurality of conductive layers 110 arranged along the Z-direction. An insulating layer 101 is disposed between the plurality of conductive layers 110 arranged along the Z-direction. Furthermore, in the contact region wl... 11b It forms a roughly stepped structure. That is to say, as... Figure 29 As shown, in the lower storage cell array layer L MCA1 Wiring area R HU11 The middle is equivalent to the contact area wl 11b The portion forms a roughly stepped structure, which extends from the other side in the X direction ( Figure 29 (right side of the middle) facing one side ( Figure 29 (On the left side) the concave part gradually deepens.

[0267] This roughly stepped structure is achieved by etching the contact area wl. 11b ( Figure 28 Configured in the lower storage cell array layer L) MCA1 Wiring area R HU11 ( Figure 29 It is formed by removing a portion of the 3rd to 8th conductive layers 110, etc. The recessed portion formed by forming a generally stepped structure is filled with an insulating layer 150 such as silicon oxide (SiO2).

[0268] In wiring area R HU11 The contact area wl 11b ( Figure 28 The connections are configured as CC2, CC4, CC6, and CC8. For example... Figure 29 As shown, contacts CC2, CC4, CC6, and CC8 connect to the memory cell array layer L. MCA2 Multiple conductive layers 110 and memory cell array layer L in MCA1 The insulating layer 150 is connected at its lower end to the conductive layers 110 of the second, fourth, sixth, and eighth layers.

[0269] In addition, Figure 29 In the illustrated cross-section, contacts CC2, CC4, CC6, and CC8 are connected to the memory cell array layer L. MCA1 The structure is roughly stepped. Therefore, for example, the distance in the X direction between the contact CC2 connected to the second conductive layer 110 and the third to eighth conductive layers 110 or the insulating layer 101 disposed between them is at least greater than the film thickness of the insulating layer 102. On the other hand, in Figure 29 In the illustrated cross-section, contacts CC2, CC4, CC6, and CC8 penetrate the memory cell array layer L. MCA2 The structure contains multiple conductive layers 110 and insulating layers 101. Therefore, for example, the distance in the X direction between the contact CC2 connected to the second conductive layer 110 and the 9th to 16th conductive layers 110 or the insulating layer 101 disposed between them is approximately the film thickness of the insulating layer 102, which is relatively small.

[0270] [Connection Area wl] 12b [Structure]

[0271] Wiring area R HU12 The contact area wl 12b ( Figure 28 It includes a portion of multiple conductive layers 110 arranged along the Z-direction. Furthermore, in the contact region wl... 12b It forms a roughly stepped structure. That is to say, as... Figure 29 As shown, in the upper storage cell array layer L MCA2 Wiring area RHU12 The middle is equivalent to the contact area wl 12b The portion forms a roughly stepped structure, the roughly stepped structure extending from one side in the X direction ( Figure 29 (left side) towards the other side ( Figure 29 (On the right side) the concave part deepens in stages.

[0272] This roughly stepped structure is achieved by etching the contact area wl. 12b ( Figure 28 Configured in the upper storage cell array layer L) MCA2 Wiring area R HU12 ( Figure 29 It is formed by removing a portion of the 11th to 16th conductive layers 110, etc. The recessed portion formed by forming a generally stepped structure is filled with an insulating layer 151 such as silicon oxide (SiO2).

[0273] In wiring area R HU12 The contact area wl 12b ( Figure 28 The contacts CC10, CC12, CC14, and CC16 are configured. For example... Figure 29 As shown, contacts CC10, CC12, CC14, and CC16 connect to the memory cell array layer L. MCA2 The insulating layer 151 is connected at its lower end to the conductive layers 110 of the 10th, 12th, 14th and 16th layers.

[0274] In addition, Figure 29 In the illustrated cross-section, contacts CC10, CC12, CC14, and CC16 are connected to the memory cell array layer L. MCA2 The structure is roughly stepped. Therefore, for example, the distance in the X direction between the contact CC10 connected to the 10th conductive layer 110 and the 11th to 16th conductive layers 110 or the insulating layer 101 disposed between them is at least greater than the film thickness of the insulating layer 102.

[0275] [Connection Area wl] 13b [Structure]

[0276] Wiring area R HU13 The contact area wl 13b ( Figure 28 It includes a portion of multiple conductive layers 110 arranged along the Z-direction. Furthermore, in the contact region wl... 13b It forms a roughly stepped structure. That is to say, as... Figure 30 As shown, in the upper storage cell array layer L MCA2 Wiring area R HU13 The middle is equivalent to the contact area wl 13bThe portion forms a roughly stepped structure, which extends from the other side in the X direction ( Figure 30 (right side of the middle) facing one side ( Figure 30 (On the left side) the concave part gradually deepens.

[0277] This roughly stepped structure is achieved by etching the contact area wl. 13b ( Figure 28 Configured in the upper storage cell array layer L) MCA2 Wiring area R HU13 ( Figure 30 It is formed by removing a portion of the 10th to 16th conductive layers 110, etc. The recessed portion formed by forming a generally stepped structure is filled with an insulating layer 152 such as silicon oxide (SiO2).

[0278] In wiring area R HU13 The contact area wl 13b ( Figure 28 It is configured with contacts CC9, CC11, CC13, and CC15. For example... Figure 30 As shown, contacts CC9, CC11, CC13, and CC15 connect to the memory cell array layer L. MCA2 The insulating layer 152 is connected at its lower end to the conductive layers 110 of the 9th, 11th, 13th and 15th layers.

[0279] In addition, Figure 30 In the illustrated cross-section, contacts CC9, CC11, CC13, and CC15 are connected to the memory cell array layer L. MCA2 The structure is roughly stepped. Therefore, for example, the distance in the X direction between the contact CC9 connected to the 9th conductive layer 110 and the 10th to 16th conductive layers 110 or the insulating layer 101 disposed between them is at least greater than the film thickness of the insulating layer 102.

[0280] [Connection Area wl] 14b [Structure]

[0281] Wiring area R HU14 The contact area wl 14b ( Figure 28 It includes a portion of multiple conductive layers 110 arranged along the Z-direction. Furthermore, in the contact region wl... 14b It forms a roughly stepped structure. That is to say, as... Figure 30 As shown, in the lower storage cell array layer L MCA1 Wiring area R HU14 The middle is equivalent to the contact area wl 14b The portion forms a roughly stepped structure, the roughly stepped structure extending from one side in the X direction ( Figure 30(left side) towards the other side ( Figure 30 (On the right side) the concave part deepens in stages.

[0282] This roughly stepped structure is achieved by etching the contact area wl. 14b ( Figure 28 Configured in the lower storage cell array layer L) MCA1 Wiring area R HU14 ( Figure 30 It is formed by removing a portion of the 2nd to 8th conductive layers 110, etc. The recessed portion formed by forming a generally stepped structure is filled with an insulating layer 153 such as silicon oxide (SiO2).

[0283] In wiring area R HU14 The contact area wl 14b ( Figure 28 The contacts are configured as CC1, CC3, CC5, and CC7. For example... Figure 30 As shown, contacts CC1, CC3, CC5, and CC7 connect to the memory cell array layer L. MCA2 Multiple conductive layers 110 and memory cell array layer L in MCA1 The insulating layer 153 is connected at its lower end to the conductive layers 110 of the first, third, fifth, and seventh layers.

[0284] In addition, Figure 30 In the illustrated cross-section, contacts CC1, CC3, CC5, and CC7 are connected to the memory cell array layer L. MCA1 The structure is roughly stepped. Therefore, for example, the distance in the X direction between the contact CC1 connected to the first conductive layer 110 and the second to eighth conductive layers 110 or the insulating layer 101 disposed between them is at least greater than the film thickness of the insulating layer 102. On the other hand, in Figure 30 In the illustrated cross-section, contacts CC1, CC3, CC5, and CC7 penetrate the memory cell array layer L. MCA2 The structure contains multiple conductive layers 110 and insulating layers 101. Therefore, for example, the distance in the X direction between the contact CC1 connected to the first conductive layer 110 and the 9th to 16th conductive layers 110 or the insulating layer 101 disposed between them is approximately the film thickness of the insulating layer 102, which is relatively small.

[0285] [Wiring Area R] HU3 R HU4 [Configuration]

[0286] Like a reference Figures 28-30 As explained, in this embodiment, a wiring area R is provided, similar to that in the first embodiment. HU3 R HU4 The corresponding location is set with wiring area RHU13 R HU14 In the semiconductor memory device of this embodiment, a wiring area R is provided in a location not shown. HU3 R HU4 For example, wiring area R HU3 R HU4 It can also be set in the memory hole area R MH1 With wiring area R HU11 Between, wiring area R HU11 With wiring area R HU12 Between, or in the wiring area R HU12 With memory hole region R MH2 Between. Additionally, for example, the wiring area R. HU3 R HU4 It can also be set in the memory hole area R MH1 With wiring area R HU13 Between, wiring area R HU13 With wiring area R HU14 Between, or in the wiring area R HU14 With memory hole region R MH2 between.

[0287] Furthermore, the semiconductor memory device of the fourth embodiment can also, like the semiconductor memory device of the third embodiment, include a memory cell array (MCA). Figure 1 ) chip C M With PC containing peripheral circuitry ( Figure 1 ) chip C P It is formed by fitting together.

[0288] [Fifth Implementation]

[0289] Next, the configuration of the semiconductor memory device according to the fifth embodiment will be described with reference to the accompanying drawings. Furthermore, in the following description, the same reference numerals are used for components identical to those in the fourth embodiment, and descriptions are simplified or omitted.

[0290] Figure 31 This is a schematic enlarged top view of the semiconductor memory device according to the fifth embodiment, equivalent to... Figure 2 The diagram shown in Figure A is a schematic enlarged view, illustrating the configuration of the upper memory cell array layer.

[0291] like Figure 31 As shown, the semiconductor memory device of the fifth embodiment includes a contact area wl 11b 'To replace the contact area wl 11b Furthermore, the semiconductor memory device of the fifth embodiment includes a contact area wl. 14b 'To replace the contact area wl 14b .

[0292] Storage cell array layer L MCA1 The contact area wl 11b The structure in ' and the memory cell array layer L in the fourth embodiment MCA1 The contact area wl 11b The structure in Figure 29 )same.

[0293] Storage cell array layer L MCA2 The contact area wl 11b The structure in ' and the memory cell array layer L in the second embodiment MCA2 The structure in the junction region CR3 ( Figure 22 )same.

[0294] Storage cell array layer L MCA1 The contact area wl 14b The structure in ' and the memory cell array layer L in the fourth embodiment MCA1 The contact area wl 14b The structure in Figure 30 )same.

[0295] Storage cell array layer L MCA2 The contact area wl 14b The structure in ' and the memory cell array layer L in the second embodiment MCA2 The structure in the junction region CR3 ( Figure 22 )same.

[0296] Furthermore, the semiconductor memory device of the fifth embodiment can also, like the semiconductor memory device of the third embodiment, include a memory cell array (MCA). Figure 1 ) chip C M With PC containing peripheral circuitry ( Figure 1 ) chip C P It is formed by fitting together.

[0297] [Other Implementation Methods]

[0298] As described above, in each embodiment, the wiring area where contacts are arranged in the memory cell array layer forms a generally stepped structure. Various patterns can be used as the pattern for this generally stepped structure.

[0299] For example, in the fourth embodiment, the following is employed: Figures 28-30 The structure shown is roughly stepped, but is not limited to this.

[0300] Therefore, refer to Figures 32-34The following describes an embodiment in which, similar to the fourth embodiment, a wiring area and a contact area are provided in the wiring area, and a generally stepped structure of other forms is formed.

[0301] Figure 32 This is a schematic enlarged top view of a semiconductor memory device according to other embodiments, equivalent to... Figure 2 The diagram shown in Figure A is a schematic enlarged view, illustrating the configuration of the upper memory cell array layer. Figure 33 It is Figure 32 The schematic cross-sectional view shown is obtained by cutting along line J-J' and observing in the direction of the arrow. Figure 34 It is Figure 32 The schematic cross-sectional view shown is obtained by cutting along line K-K' and observing in the direction of the arrow.

[0302] like Figure 32 As shown, in other embodiments, multiple memory blocks BLK (BLK_A~BKL_D) are also arranged along the Y direction, and an inter-block insulation layer ST is provided between two adjacent memory blocks BLK in the Y direction.

[0303] Furthermore, the storage block BLK in the fourth embodiment ( Figure 28 ) has an in-block insulating layer st, but other implementations of the storage block BLK ( Figure 32 ) does not have an in-block insulating layer. Additionally, other implementations of the storage block BLK ( Figure 32 The Y-direction width of the storage block BLK in the fourth embodiment is [missing information]. Figure 28 It is about half the width of the Y direction.

[0304] In storage block BLK_B, such as Figure 32 and Figure 33 As shown, in the lower storage cell array layer L MCA1 Wiring area R HU11 The middle is equivalent to the contact area wl 11b The portion forms a roughly stepped structure, which extends from the other side in the X direction ( Figure 33 The right side of the image (in the middle) moves to one side (the left side of the image) and the concave part deepens in stages. Figure 33 Wiring area R HU11 The number of levels in the roughly stepped structure formed in the middle is Figure 29 The number of stages in the roughly stepped structure shown is twice that of the given structure. In the junction region wl 11b It is equipped with 8 contacts CC1 to CC8.

[0305] Additionally, in storage block BLK_B, such as Figure 32 and Figure 33 As shown, in the upper storage cell array layer L MCA2Wiring area R HU12 The middle is equivalent to the contact area wl 12b The portion forms a roughly stepped structure, the roughly stepped structure extending from one side in the X direction ( Figure 33 The concave portion deepens in stages, moving from the left side of the image to the right side (in the image). Figure 33 Wiring area R HU12 The number of levels in the roughly stepped structure formed in the middle is Figure 29 The number of stages in the roughly stepped structure shown is twice that of the given structure. In the junction region wl 12b It is equipped with 8 contacts CC9 to CC16.

[0306] In addition, in storage block BLK_D, a roughly stepped structure is formed that is similar to the roughly stepped structure formed in storage block BLK_B, and contacts CC1~CC8 and CC9~CC16 are configured.

[0307] In storage block BLK_C, such as Figure 32 and Figure 34 As shown, in the upper storage cell array layer L MCA2 Wiring area R HU13 The middle is equivalent to the contact area wl 13b The portion forms a roughly stepped structure, and the roughly stepped structure is related to... Figure 33 The upper storage cell array layer L shown MCA2 Wiring area R HU12 The middle is equivalent to the contact area wl 12b The roughly stepped structure formed in the part is the same.

[0308] Additionally, in storage block BLK_C, such as Figure 32 and Figure 34 As shown, in the lower storage cell array layer L MCA1 Wiring area R HU14 The middle is equivalent to the contact area wl 14b The portion forms a roughly stepped structure, and the roughly stepped structure is related to... Figure 33 The lower storage cell array layer L shown MCA1 Wiring area R HU11 The middle is equivalent to the contact area wl 11b The roughly stepped structure formed in the part is the same.

[0309] Furthermore, in storage block BLK_A, a roughly stepped structure is formed that is similar to the roughly stepped structure formed in storage block BLK_C, and contacts CC1~CC8 and CC9~CC16 are configured.

[0310] In the first to fifth embodiments, only one contact area is provided in the wiring area, and the contacts CC in each contact area are arranged in a row along the X direction. However, this configuration is merely an example, and the specific configuration can be adjusted appropriately. For example, in the first to fifth embodiments, two contact areas arranged along the Y direction may be provided in any wiring area, or the contacts CC may be arranged in two rows along the X direction in any contact area.

[0311] Furthermore, the semiconductor memory devices of the first to fifth embodiments include two memory cell array layers L arranged along the Z direction. MCA1 L MCA2 However, this configuration is merely an example, and the specific configuration can be adjusted appropriately. For example, three or more memory cell array layers arranged along the Z direction may be provided in the semiconductor memory device of the first to fifth embodiments. In addition, in this case, the positions of the wiring regions (the connection portions between the conductive layer 110 included in each memory cell array layer and the contact CC) in the X direction corresponding to each memory cell array layer may be distributed in three or more locations.

[0312] [Other examples of wire connection states between contact CC and through contact C4]

[0313] Figure 8 The image shows an example of connecting contact CC to through contact C4, but the connection is not limited to this.

[0314] Therefore, refer to Figures 35-40 Another example of connecting contact CC to through contact C4 will be described. In this example, the wire connection is made using wiring m0 of wiring layer M0, wiring m1 of wiring layer M1, and wiring m2 of wiring layer M2.

[0315] Furthermore, for ease of understanding, in Figure 35 In the text, only the configuration status of contact CC and through contact C4 is indicated. Figure 36 In the text, it only indicates the line connection status using wiring m0. Figure 37 In the text, it only indicates the connection status of wiring m0 and wiring m1. Figure 38 In the middle, it represents the wire connection status using wiring m0, wiring m1 and wiring m2.

[0316] also, Figure 39 It is Figure 38 The schematic cross-sectional view shown is obtained by cutting along line L-L' and observing in the direction of the arrow. Figure 40 It is Figure 38 The schematic cross-sectional view shown is obtained by cutting along the M-M' line and observing in the direction of the arrow.

[0317] For example, such as Figure 35 As shown, the line connection state is explained in the following cases: in the through-connection area TR10, multiple through-connection points C4 arranged along the X direction are arranged in one row; in the connection area CR10, multiple connection points CC arranged along the X direction are arranged in two rows.

[0318] like Figure 36 As shown, multiple wirings m0 extending in the X direction and arranged in the Y direction are arranged above the through contact C4 and above the contact CC. The lower surface of the specified wiring m0 is connected to the upper end of the through contact C4 and the contact CC. The contact ct0 is connected to a specified position on the upper surface of each wiring m0.

[0319] like Figure 37 As shown, multiple wires m1 extending along the Y direction and arranged along the X direction are arranged above wire m0. The lower surface of wire m1 is connected to contact ct0. Figure 36 On the upper surface of each wire m1, wire m1 is electrically connected to wire m0 via contact ct0. Contact ct1 is connected at a designated position on the upper surface of each wire m1.

[0320] like Figure 38 As shown, multiple wires m2 extending along the X direction and arranged along the Y direction are arranged above wire m1. The lower surface of wire m2 is connected to contact ct1. Figure 37 On the upper surface of the ), wiring m2 is electrically connected to wiring m1 via contact ct1.

[0321] Also Figure 39 and Figure 40 As shown, wiring m0 and wiring m1 are electrically connected via contact ct0, and wiring m1 and wiring m2 are electrically connected via contact ct1.

[0322] In this line connection, multiple wires m1 extending in the Y direction are arranged between multiple wires m0 extending in the X direction and multiple wires m2 extending in the X direction. Therefore, the Y-direction separate contact CC and the through contact C4 can be easily electrically connected.

[0323] [other]

[0324] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

[0325] [Explanation of Symbols]

[0326] 100 Semiconductor Substrate

[0327] 110 conductive layer

[0328] 120 Semiconductor Pillar

[0329] 130 gate insulating film

[0330] CC, CC1 to CC16 contacts.

Claims

1. A semiconductor memory device comprising: The substrate has a first region to a fourth region arranged sequentially in a first direction; A plurality of first conductive layers extend from the first region along the first direction to the second region and are arranged along a second direction intersecting the surface of the substrate; Multiple second conductive layers extend from the fourth region along the first direction to the second region and are arranged along the second direction; Multiple third conductive layers extend from the first region along the first direction to the third region, are arranged along the second direction, and are positioned differently from the multiple first conductive layers in the second direction; A plurality of fourth conductive layers extend from the fourth region along the first direction to the third region, are arranged along the second direction, and are positioned differently from the plurality of second conductive layers in the second direction; A first semiconductor pillar is disposed in the first region, extends along the second direction, and faces the plurality of first conductive layers and the plurality of third conductive layers; A second semiconductor pillar is disposed in the fourth region, extends along the second direction, and faces the plurality of second conductive layers and the plurality of fourth conductive layers; A plurality of first contacts are disposed in the second region, extend along the second direction, and are connected to the ends of the plurality of first conductive layers in the first direction; A plurality of second contacts are disposed in the second region, extend along the second direction, and are connected to the ends of the plurality of second conductive layers in the first direction; A plurality of third contacts are disposed in the third region, extend along the second direction, and are connected to the ends of the plurality of third conductive layers in the first direction; A plurality of fourth contacts are disposed in the third region, extend along the second direction, and are connected to the ends of the plurality of fourth conductive layers in the first direction; Multiple first wirings are provided in the second area and are electrically connected to the multiple first contacts and the multiple second contacts; and Multiple second wirings are provided in the third area and are electrically connected to the multiple third contacts and the multiple fourth contacts.

2. The semiconductor memory device according to claim 1, comprising: A plurality of first insulating layers are alternately arranged with the plurality of first conductive layers in the second direction; A plurality of second insulating layers are alternately arranged with the plurality of second conductive layers in the second direction; A plurality of third insulating layers are alternately arranged with the plurality of third conductive layers in the second direction; and Multiple fourth insulating layers are alternately arranged with the multiple fourth conductive layers in the second direction; In a first cross section extending along the first direction and the second direction and including at least one of the plurality of first contacts, The fifth contact, being one of the plurality of first contacts, penetrates the plurality of third insulating layers and extends along the second direction, and The closer the first conductive layer is to the plurality of third conductive layers, the greater the distance between the first conductive layer and the fifth contact point in the first direction.

3. The semiconductor memory device according to claim 2, wherein... The fifth contact is connected to at least one of the plurality of third insulating layers.

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