Three-dimensional memory and method for manufacturing the same

Abstract

The present invention provides a three-dimensional memory and a method for manufacturing the same. The method includes the following steps: providing a semiconductor structure, the semiconductor structure including a substrate and a stacked structure located on the substrate, the stacked structure including alternately stacked gate layers and dielectric layers; or, the stacked structure including alternately stacked dummy gate layers and the dielectric layers, wherein the gate layers can replace the dummy gate layers; forming a groove in a gate line gap region of the stacked structure, wherein the groove penetrates through multiple layers of the gate layers and the dielectric layers; or, the groove penetrates through multiple layers of the dummy gate layers and the dielectric layers; forming an insulating layer on a surface of the stacked structure and in the groove, wherein the insulating layer above the groove has a depression on a surface relatively far from the substrate; and polishing the insulating layer to flatten the depression.

Description

[0001] This application is a divisional application of the patent with the application date of October 28, 2020, application number 202011174467.X, and invention title "Three-Dimensional Memory and Manufacturing Method Thereof". 1.1.1 Technical Field

[0003] The present invention mainly relates to the field of semiconductor design and manufacturing, and in particular, to a three-dimensional memory and a manufacturing method thereof. 1.1.2 Background Art

[0005] With the continuous development of 3D NAND technology, the number of layers that can be vertically stacked in three-dimensional memories is increasing, from 24 layers, 32 layers, 64 layers to high-order stacked structures of more than 100 layers, which can greatly improve the storage density and reduce the price per storage unit.

[0006] Existing memories generally include a plurality of memory blocks (Blocks) and a plurality of finger storage areas (Fingers) located in the memory blocks (Blocks). Between the memory blocks and between the finger storage areas, they are generally separated by a gate line gap that penetrates the stacked structure in the vertical direction. The gate line gap is filled with an insulating layer for separating the gates and an array common source for leading out the source from the substrate. In order to improve the strength of the stacked structure and prevent the stacked structure from tilting or collapsing, some array common sources of three-dimensional memories are made into an "H" shape. Specifically, a plurality of sub-array common sources that penetrate the stacked structure are first formed in the stacked structure, and adjacent sub-array common sources are separated by a partition structure formed in the stacked structure. Then, a connection bridge for connecting the plurality of sub-array common sources is formed on the partition structure. The upper part of the partition structure is an insulating layer that penetrates multiple gate layers and dielectric layers, and is used to separate the gate layer at the top of the stacked structure. When forming this insulating layer through steps such as deposition, it is easy to form relatively small depressions on the upper surface of the insulating layer. In subsequent processes, this depression is likely to be filled and remain with materials such as polysilicon. This residual material is likely to form potential hazards, such as falling off in certain processes and interfering with the current process. 1.1.3 Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a three-dimensional memory and a manufacturing method thereof, which can reduce the material residue of the insulating layer on the upper part of the partition structure.

[0009] To solve the above technical problems, the present invention provides a method for manufacturing a three-dimensional memory, comprising the following steps: providing a semiconductor structure, the semiconductor structure comprising a substrate and a stacked structure located on the substrate, the stacked structure comprising alternately stacked gate layers and dielectric layers; or, the stacked structure comprising alternately stacked dummy gate layers and the dielectric layers, wherein the gate layers can replace the dummy gate layers; forming a groove in a gate line gap region of the stacked structure, wherein the groove penetrates through multiple layers of the gate layers and the dielectric layers; or, the groove penetrates through multiple layers of the dummy gate layers and the dielectric layers; forming an insulating layer on the surface of the stacked structure and in the groove, wherein the insulating layer above the groove has a depression on a surface relatively far from the substrate; and polishing the insulating layer to flatten the depression.

[0010] In an embodiment of the present invention, the insulating layer comprises a first insulating layer and a second insulating layer;

[0011] The forming an insulating layer on the surface of the stacked structure and in the groove, wherein the insulating layer above the groove has a depression on a surface relatively far from the substrate, comprises:

[0012] Sequentially forming the first insulating layer and the second insulating layer on the surface of the stacked structure and in the groove;

[0013] The polishing the insulating layer to flatten the depression comprises:

[0014] Polishing the second insulating layer to flatten the depression.

[0015] In an embodiment of the present invention, after polishing the insulating layer to flatten the depression, further comprising: forming a gate line gap in the gate line gap region, the gate line gap being blocked by the groove; filling a conductive material in the gate line gap to form an array common source.

[0016] In an embodiment of the present invention, after filling a conductive material in the gate line gap to form an array common source, further comprising: forming a connection bridge spanning the insulating layer in the groove, the connection bridge connecting the array common sources separated by the insulating layer.

[0017] In an embodiment of the present invention, the thickness of the insulating layer on the surface of the stacked structure is 150 - 250 nm.

[0018] In an embodiment of the present invention, the step of polishing the insulating layer to flatten the depression comprises controlling the polishing thickness by controlling the polishing time.

[0019] In an embodiment of the present invention, the groove is located in a core region of the stacked structure.

[0020] In an embodiment of the present invention, the above method further includes forming a top select gate cut line in the stacking structure, and filling an insulating layer in the top select gate cut line, wherein the top select gate cut line and the groove are formed in the same etching process, and the insulating layer in the top select gate cut line and the insulating layer in the groove are formed in the same filling process.

[0021] In an embodiment of the present invention, the above method further includes forming a channel structure array in the core region of the stacking structure, and the channel structure array is divided into multiple regions by the gate line gaps.

[0022] In an embodiment of the present invention, the above method further includes forming conductive plugs on top of each channel structure in the channel structure array.

[0023] In an embodiment of the present invention, the stacking structure includes one stack or multiple stacked stacks.

[0024] Another aspect of the present invention provides a three-dimensional memory, including a substrate, a stacking structure, gate line gaps, and an insulating layer. The stacking structure is located on the substrate and includes alternately stacked gate electrode layers and dielectric layers. The gate line gaps penetrate through the stacking structure to reach the substrate and are blocked by a blocking structure. The insulating layer is disposed on the upper part of the blocking structure, wherein the surface of the insulating layer relatively far from the substrate is flat.

[0025] In an embodiment of the present invention, the insulating layer includes a first insulating layer located on the blocking structure and a second insulating layer located on the first insulating layer, wherein the surface of the second insulating layer relatively far from the first insulating layer is flat.

[0026] In an embodiment of the present invention, the three-dimensional memory further includes an array common source electrode located in the gate line gaps.

[0027] In an embodiment of the present invention, the three-dimensional memory further includes a connection bridge spanning the insulating layer, and the connection bridge connects the array common source electrodes separated by the insulating layer.

[0028] In an embodiment of the present invention, the multiple insulating layers are located in the core region of the stacking structure.

[0029] In an embodiment of the present invention, the three-dimensional memory further includes: a top select gate cut line that penetrates through multiple gate electrode layers and dielectric layers in the stacking structure; an insulating layer filled in the top select gate cut line, wherein the insulating layer in the top select gate cut line and the insulating layer on the upper part of the blocking structure are formed in the same filling process.

[0030] Compared with the prior art, in the method for manufacturing a three-dimensional memory of the present invention, after forming an insulating layer for a groove covering the gate line gap region and then performing grinding, the depression on the surface of the insulating layer can be eliminated, thereby avoiding the residue of materials in subsequent processes. Therefore, the present invention can reduce potential hazards such as the shedding of residual materials. 1.1.4 BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are provided to provide a further understanding of the present application, and they are incorporated into and constitute a part of the present application. The drawings illustrate embodiments of the present application and, together with this specification, serve to explain the principles of the present utility model. In the drawings:

[0033] Figure 1 is a flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present application.

[0034] Figures 2A - 2D is a top view schematic diagram in an exemplary manufacturing process of a three-dimensional memory according to an embodiment of the present application.

[0035] Figures 3A - 3G is a cross-sectional schematic diagram along the Y direction in an exemplary manufacturing process of a three-dimensional memory according to an embodiment of the present application.

[0036] Figures 4A - 4E is a cross-sectional schematic diagram along the X direction in an exemplary manufacturing process of a three-dimensional memory according to an embodiment of the present application. 1.1.5 DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without creative efforts, the present application can also be applied to other similar scenarios based on these drawings. Unless obvious from the language context or otherwise stated, the same reference numerals in the drawings represent the same structure or operation.

[0039] As shown in the present application and the claims, unless the context clearly indicates an exceptional situation, words such as "a", "an", "one", and / or "the" are not specifically singular and may also include plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0040] Unless otherwise specifically stated, the relative arrangements, numerical expressions, and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for the sake of convenience of description, the dimensions of the various parts shown in the drawings are not drawn in actual proportional relationships. Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the said technologies, methods, and devices should be regarded as part of the authorization specification. In all the examples shown and discussed here, any specific value should be construed as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.

[0041] In the description of the present application, it should be understood that the orientation or positional relationships indicated by orientation terms such as "front, rear, upper, lower, left, right", "lateral, vertical, perpendicular, horizontal", and "top, bottom" are generally based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Without contrary description, these orientation terms do not indicate and imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and thus should not be construed as limiting the protection scope of the present application; the orientation terms "inside, outside" refer to the inside and outside relative to the contour of each component itself.

[0042] For the convenience of description, spatial relative terms such as "above...", "over...", "on the upper surface of...", "above" can be used here to describe the spatial positional relationship between a device or feature shown in the drawings and other devices or features. It should be understood that the spatial relative terms are intended to encompass different orientations in use or operation in addition to the orientation of the device described in the drawings. For example, if the device in the drawing is inverted, the device described as "above other devices or structures" or "over other devices or structures" will then be positioned as "below other devices or structures" or "under other devices or structures". Thus, the exemplary term "above..." can include both the orientations of "above..." and "below...". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and corresponding interpretations should be made for the spatial relative descriptions used here.

[0043] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is merely for the convenience of distinguishing the corresponding components. Without additional statements, the above terms have no special meaning, and thus should not be construed as a limitation on the protection scope of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some of the terms mentioned in the specification of this application may be selected by the applicant according to his or her judgment, and their detailed meanings are described in the relevant parts of this description. In addition, it is required to understand this application not only through the actual terms used, but also through the meaning implied by each term.

[0044] It should be understood that when a component is referred to as "on another component", "connected to another component", "coupled to another component", or "in contact with another component", it can be directly on, connected to, or coupled to, or in contact with the other component, or there may be an intervening component. In contrast, when a component is referred to as "directly on another component", "directly connected to", "directly coupled to", or "directly in contact with" another component, there is no intervening component. Similarly, when the first component is referred to as "electrically contacting" or "electrically coupled to" the second component, there is an electrical path allowing current to flow between the first component and the second component. The electrical path may include capacitors, coupled inductors, and / or other components allowing current to flow, even if there is no direct contact between the conductive components.

[0045] Flowcharts are used in this application to illustrate the operations performed by the systems according to the embodiments of this application. It should be understood that the operations before or below do not necessarily have to be performed precisely in sequence. Instead, various steps can be processed in reverse order or simultaneously. Also, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0046] Embodiments of the present disclosure describe a method for manufacturing a three-dimensional memory. The method forms a plurality of through-subarray common sources in a stacked structure, and adjacent subarray common sources are separated by a partition structure formed in the stacked structure. The upper part of the partition structure is an insulating layer that penetrates through multiple gate layers and dielectric layers, and is used to separate the gate layers at the top of the stacked structure. This method can reduce the material residue of the insulating layer in the upper part of the partition structure.

[0047] Figure 1 It is a flowchart of the method for manufacturing a three-dimensional memory according to an embodiment of this application. Figures 2A - 2D It is a top view schematic diagram in an exemplary manufacturing process of a three-dimensional memory according to an embodiment of this application. Figures 3A - 3G It is a cross-sectional schematic diagram along the Y direction in an exemplary manufacturing process of a three-dimensional memory according to an embodiment of this application. Figures 4A - 4EIt is a schematic cross-sectional view along the X direction in an exemplary manufacturing process of a three-dimensional memory in an embodiment of the present application. The manufacturing method of the embodiment of the present application will be described below with reference to Figures 1 - 4E and

[0048] In step 101, a semiconductor structure is provided, including a substrate and a stacked structure located on the substrate. The stacked structure includes alternately stacked gate layers and dielectric layers.

[0049] Figure 3A is Figure 2A a cross-sectional view taken along line A-A of Figure 2A and 3A As shown, the semiconductor structure includes a substrate 201 and a stacked structure including a first stack 210 and a second stack 220 located on the substrate. For simplicity, only the semiconductor structure for forming the core area of the three-dimensional memory is shown. The core area is used to form a memory cell array. The stacked structure includes a plurality of dummy gate layers 211 and a plurality of dielectric layers 212 stacked alternately. The dummy gate layers 211 may include a top select dummy gate layer 211a located on one or more top layers of the second stack 220, and may also include a bottom select dummy gate layer 211b located at the bottom of the first stack 210.

[0050] The substrate 201 may be a silicon substrate (Si), a germanium substrate (Ge), a silicon germanium substrate (SiGe), silicon on insulator (SOI), germanium on insulator (GOI), etc. In some embodiments, the substrate 201 may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc. It may also be a stacked structure, such as Si / SiGe, etc. It may also include other epitaxial structures, such as silicon germanium on insulator (SGOI), etc. In some embodiments, the substrate 201 may be made of a non-conductive material, such as glass, plastic, or sapphire wafer, etc.

[0051] The dummy gate layers 211 and the dielectric layers 212 may be selected from the following materials and at least include an insulating medium, such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, etc. and their combinations. The dummy gate layers 211 and the dielectric layers 212 have different etching selectivities. For example, it may be a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, etc. The deposition methods of the dummy gate layers 211 and the dielectric layers 212 may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition methods such as molecular beam epitaxy (MBE), thermal oxidation, evaporation, sputtering, etc.

[0052] Various manufacturing techniques (such as gate-first manufacturing techniques, gate-last manufacturing techniques, etc.) can be used to manufacture 3D memories. As Figure 3A shown, the gate-last manufacturing technique uses a dummy gate layer to facilitate the formation of the channel structure of the memory cells, and replaces the dummy gate layer with the gates of the memory cells after the formation of the channel structure. To replace the dummy gate layer with a gate, the dummy gate layer is removed and then the gate layer is formed. The gate-first manufacturing technique forms the gates of the memory cells earlier than the channel structure of the memory cells. In this manufacturing technique, the material of the gate layer can be a conductive material such as tungsten, cobalt, copper, nickel, etc., or polysilicon, doped silicon, or any combination thereof.

[0053] Continuing to refer to Figure 2A and 3A shown, in the first stack 210 at the bottom, first channel holes 215 have been previously formed and filled with a sacrificial layer 214. The material of the sacrificial layer 214 can be polysilicon. As Figure 2A shown, the array of the first channel holes 215 is divided into a plurality of memory blocks (such as 202 and 203), and each memory block is separated by a gate line gap region 204.

[0054] In addition, conductive portions 217 are respectively formed at the bottoms of the first channel holes 215. The conductive portions 217 are, for example, silicon formed by a Selective Epitaxial Growth (SEG) process.

[0055] It should be noted that although Figure 3A the example diagram shows a stacked structure including 2 stacks, more or fewer stacks are also within the scope of implementation of this application. In other examples, a single stack can be used, and in this case, there will be no structures such as the pre-formed first channel holes 215, sacrificial layer 214, conductive portions 217, etc. in the stacked structure.

[0056] In step 102, a plurality of grooves are formed at intervals in the gate line gap region of the stacked structure that has been planarized and unpolished, and each groove penetrates through multiple gate layers and dielectric layers.

[0057] Figure 3B is Figure 2B the A-A cross-sectional view of Figure 2B and 3B shown, after the second stack 220 of the stacked structure is planarized and before grinding, a plurality of grooves 221a are formed at intervals in the gate line gap region 204. It can be understood that the grooves 221a are distributed in the core area of the 3D memory. The grooves 221a penetrate through the stack of multiple gate layers and dielectric layers. There are still many stacks of gate layers and dielectric layers below the grooves 221a.

[0058] In one embodiment, in this step, a top select gate cut line 221b extending in the X direction is also formed in the stack structure. The top select gate cut line 221b is used to divide multiple finger memory regions in a memory block. Each top select gate cut line 221b faces a row of underlying dummy first channel holes 215. Therefore, the top select gate cut line 221b and the groove 221a are formed in the same etching process. This approach enables the formation of the groove 221a to be completed relying on the existing process, simply by changing the photomask pattern originally used for etching the top select gate cut line, without the need for additional photomasks and etching processes. In one embodiment, the depths of the groove 221a and the top select gate cut line 221b are the same. In one embodiment, the width of the groove 221a in the Y direction is greater than the width of the top select gate cut line 221b in the Y direction.

[0059] Here, the polishing is typically Chemical Mechanical Polishing (CMP). Conventionally, there is a CMP step after planarization. The inventors of the present application found that removing the CMP step here can alleviate the problem of non-uniform layer thickness, further making the process window of the aforementioned etching (usually dry etching) wider and the etching stop depth more consistent.

[0060] In step 103, an insulating layer is covered on the surface of the stack structure and in the plurality of grooves, wherein the surface of the insulating layer above the plurality of grooves has depressions.

[0061] Figure 3C Yes Figure 2C is a cross-sectional view taken along A-A. As Figure 2C and 3C shown, a first insulating layer 222a is covered on the surface of the stack structure and in the plurality of grooves 221a. The first insulating layer 222a can be formed using a furnace tube process. Then, as Figure 3D shown, a second insulating layer 222b is covered on the surface of the stack structure and in the plurality of grooves 221a. The second insulating layer 222b can be formed using Physical Vapor Deposition (PVD) process. The first insulating layer 222a and the second insulating layer 222b together constitute the insulating layer 222.

[0062] In an example where the top select gate cut line is formed simultaneously, an insulating layer, more specifically the first insulating layer 222a, is also filled in the top select gate cut line 221b. The insulating layer in the top select gate cut line 221b and the insulating layer in the groove 221a are formed in the same filling process.

[0063] In one embodiment, the thickness of the insulating layer 222 (including the first insulating layer and the second insulating layer) on the surface of the stack structure is between 150 - 250 nm. The material of the insulating layer 222 is, for example, silicon oxide.

[0064] Reference Figure 3D As shown, the stacked structure has a depression 223 on the surface of the insulating layer above the groove 221a and the top select gate cut line 221b.

[0065] In step 104, the insulating layer is polished to flatten the depression.

[0066] Figure 4A Yes Figure 2C is the cross-sectional view taken along line B-B. Refer to 2C, Figure 3E and Figure 4A As shown, the insulating layer is polished using a CMP process to flatten the depression 223, resulting in a flat surface of the insulating layer. In one embodiment, the polishing time is controlled to control the polishing thickness. For example, the polishing thickness can be set to 20 nm, and the polishing time is set accordingly.

[0067] Compared with the conventional technology, polishing after forming the insulating layer can eliminate the depression, thus avoiding the residue of materials in subsequent processes.

[0068] In step 105, a channel structure array is formed in the core region of the stacked structure, and the channel structure array is divided into multiple regions by gate line gaps.

[0069] Reference Figure 3F As shown, a plurality of channel structures 216 are formed vertically through the stacked structure. Overall, in the channel structure, a memory layer and a channel layer are sequentially arranged from the outside to the inside along the radial direction of the channel hole. The memory layer may include a blocking layer, a charge trapping layer, and a tunneling layer sequentially arranged from the outside to the inside along the radial direction of the channel hole. A filling layer may also be provided in the channel layer. The filling layer can act as a support. The material of the filling layer can be silicon oxide. The filling layer can be solid or hollow without affecting the device reliability. The formation of the vertical channel structure can be achieved by using one or more thin film deposition processes, such as ALD, CVD, PVD, etc. or any combination thereof.

[0070] In step 106, conductive plugs are formed on top of each channel structure in the channel structure array.

[0071] Reference Figure 3F As shown, a part of the material is removed on top of each channel structure, and then a conductive material 218a is covered. The conductive material 218a is, for example, polysilicon. Then as Figure 3G shown, the conductive material on the surface of the stacked structure is removed, and the conductive material on top of the channel structure is retained as the conductive plug 218.

[0072] Here, since the insulating layer under the conductive material 218a is already flat, there will be no residual conductive material left on the surface of the insulating layer, causing potential hazards.

[0073] In step 107, a gate line gap is formed in the gate line gap region, and the gate line gap is interrupted by a plurality of grooves.

[0074] Figure 4B Yes Figure 2D is a sectional view taken along line B-B. Refer to 2D and Figure 4B As shown, in the region where there are no grooves 221a and insulating layer 222 in the gate line gap region 204, etching is performed vertically to form a gate line gap 205. Here, the gate line gap 205 will be interrupted by a partition structure composed of the insulating layer in the groove 221a and the stacked layer under the groove 221a.

[0075] Due to the support of the partition structure, the stacked structure is not easily collapsed when forming the gate line gap 205, improving the stability of the stacked structure.

[0076] Refer to Figure 4B As shown, in the final gate manufacturing technology, after forming the gate line gap 205, the dummy gate layer 211 in the stacked layer can be removed through the gate line gap 205 to form a gap, and the dummy gate layer 211 is replaced with a gate layer 211g. The material of the gate layer 211g is, for example, metal tungsten, cobalt, copper, nickel, etc., or it can also be polysilicon, doped silicon, or any combination thereof.

[0077] In step 108, a conductive material is filled in the gate line gap to form an array common source.

[0078] As shown in reference step 4C, a gap wall 225 is first covered in the gate line gap 205, and then a conductive material is filled to form an array common source 226. In one embodiment, the material of the gap wall 225 is silicon oxide, and the conductive material is, for example, polysilicon. The array common source 226 will still be separated by a partition structure composed of the insulating layer in the groove 221a and the stacked layer under the groove 221a.

[0079] In step 109, a connection bridge is formed across the insulating layer in each groove, and the connection bridge connects the array common sources separated by the insulating layer.

[0080] Refer to Figure 4D As shown, an insulating layer 227 is covered on the surface of the semiconductor structure, and then the insulating layer above the gate line gap 205 is removed to form an opening. Subsequently, as Figure 4E shown, a conductive material is covered at the opening of the gate line gap 205 as a connection bridge 228. The conductive material is, for example, metal tungsten, cobalt, copper, nickel, etc.

[0081] Here, a flowchart is used to illustrate the operations performed by the method according to an embodiment of the present invention. It should be understood that the previous operations are not necessarily executed precisely in order. On the contrary, various steps can be processed in reverse order or simultaneously. Also, one or more operations can be added to these processes, or one or several operations can be removed from these processes.

[0082] After the above method, conventional steps are then carried out to obtain a three-dimensional memory according to an embodiment of the present application. The following will describe the structure of a three-dimensional memory according to an embodiment of the present application with reference to Figure 3G and Figure 4E The three-dimensional memory includes a substrate 201 and a stacked structure 206 located on the substrate 201. The stacked structure 206 includes alternately stacked gate layers 211g and dielectric layers 212. A gate line gap 205 penetrates through the stacked structure 206 and reaches the substrate 201. The gate line gap 205 is partitioned by a plurality of spaced partition structures. Each partition structure has an insulating layer 222 on the upper part, and below the insulating layer 222 are alternately stacked gate layers 211g and dielectric layers 212. Each insulating layer 222 penetrates through multiple layers of gate layers 211g and dielectric layers 212. As described in the previous reference Figure 3E The upper surface of each insulating layer 222 is flat without small depressions, so it will not accommodate impurity particles such as polysilicon.

[0083] Continuing to refer to Figure 4E As shown, the three-dimensional memory further includes an array common source 226 located in each gate line gap 205. At each gate line gap, a connection bridge 228 spanning each insulating layer 222 is provided to connect the array common sources 226 separated by the partition structures.

[0084] Referring to Figure 3G As shown, the three-dimensional memory further includes a top select gate cut line 221b that penetrates through multiple layers of gate layers and dielectric layers in the stacked structure. The insulating layer fills both the groove 221a and the top select gate cut line 221b at the same time. In one embodiment, the insulating layer in the top select gate cut line and the insulating layer on the upper part of the partition structure are formed in the same filling process, thus saving the process.

[0085] In the context of the present invention, the three-dimensional storage device can be a 3D flash memory, such as a 3D NAND flash memory.

[0086] The basic concepts have been described above. Obviously, for those skilled in the art, the above invention disclosure is only an example and does not constitute a limitation to the present application. Although not explicitly stated here, those skilled in the art may make various modifications, improvements, and corrections to the present application. Such modifications, improvements, and corrections are proposed in the present application, so such modifications, improvements, and corrections still fall within the spirit and scope of the exemplary embodiments of the present application.

[0087] Meanwhile, this application uses specific terms to describe the embodiments of this application. For example, "one embodiment", "an embodiment", and / or "some embodiments" mean a certain feature, structure, or characteristic related to at least one embodiment of this application. Therefore, it should be emphasized and noted that the "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more at different positions in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of this application can be appropriately combined.

[0088] Similarly, it should be noted that, in order to simplify the description of this application disclosure and thus help the understanding of one or more inventive embodiments, in the foregoing description of the embodiments of this application, sometimes multiple features are grouped into one embodiment, drawing, or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than those mentioned in the claims. In fact, the features of the embodiment are fewer than all the features of the single embodiment disclosed above.

[0089] In some embodiments, numbers are used to describe the components and the quantity of attributes. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately", or "substantially" in some examples. Unless otherwise stated, "about", "approximately", or "substantially" indicate that the said numbers allow a variation of ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, and this approximate value can change according to the characteristics required by individual embodiments. In some embodiments, the numerical parameters should consider the specified significant digits and adopt the method of retaining the general number of digits. Although the numerical ranges and parameters used to confirm the scope breadth in some embodiments of this application are approximate values, in specific embodiments, the setting of such numerical values is as precise as possible within the feasible range.

[0090] Although this application has been described with reference to the current specific embodiments, those of ordinary skill in the art in this technical field should recognize that the above embodiments are only used to illustrate this application, and various equivalent changes or substitutions can be made without departing from the spirit of this application. Therefore, as long as the changes and variations of the above embodiments are within the scope of the spirit of this application, they will fall within the scope of the claims of this application.

Claims

1. A manufacturing method of a three-dimensional memory, characterized in that, Comprising the following steps: Providing a semiconductor structure, the semiconductor structure comprising a substrate and a stacked structure located on the substrate, the stacked structure comprising alternately stacked gate layers and dielectric layers; Alternatively, the stacked structure comprises alternately stacked dummy gate layers and dielectric layers, wherein the gate layer can replace the dummy gate layer; Forming a groove in the gate line gap region of the stacked structure that has been planarized and not polished, wherein the groove penetrates through multiple layers of the gate layers and the dielectric layers, and there are still gate layers and dielectric layers below the groove; or, the groove penetrates through multiple layers of the dummy gate layers and the dielectric layers, and there are still dummy gate layers and dielectric layers below the groove; Forming an insulating layer on the surface of the stacked structure and in the groove, wherein the insulating layer above the groove has a depression on the surface relatively far from the substrate; and Polishing the insulating layer to flatten the depression, wherein the polished insulating layer covers the surface of the stacked structure.

2. The method according to claim 1, characterized in that The insulating layer comprises a first insulating layer and a second insulating layer; The forming an insulating layer on the surface of the stacked structure and in the groove, wherein the insulating layer above the groove has a depression on the surface relatively far from the substrate, comprises: Sequentially forming the first insulating layer and the second insulating layer on the surface of the stacked structure and in the groove; The polishing the insulating layer to flatten the depression, comprises: Polishing the second insulating layer to flatten the depression.

3. The method according to claim 1, characterized in that After polishing the insulating layer to flatten the depression, further comprising: Forming a gate line gap in the gate line gap region, the gate line gap being separated by the groove; Filling a conductive material in the gate line gap to form an array common source.

4. The method according to claim 3, wherein After filling a conductive material in the gate line gap to form an array common source, further comprising: Forming a connection bridge spanning the insulating layer in the groove, the connection bridge connecting the array common sources separated by the insulating layer.

5. The method according to claim 1, wherein The thickness of the insulating layer on the surface of the stacked structure is 150 - 250 nm.

6. The method according to claim 1, wherein The step of polishing the insulating layer to flatten the depression comprises controlling the polishing thickness by controlling the polishing time.

7. The method according to claim 1, wherein The groove is located in the core region of the stacked structure.

8. The method according to claim 1, wherein Further comprising forming a top select gate cut line in the stacked structure and filling an insulating layer in the top select gate cut line, wherein the top select gate cut line and the groove are formed in the same etching process, and the insulating layer in the top select gate cut line and the insulating layer in the groove are formed in the same filling process.

9. The method according to claim 1, wherein Further comprising forming a channel structure array in the core region of the stacked structure, the channel structure array being separated into multiple regions by the gate line gap regions.

10. The method according to claim 9, characterized in that, Further comprising forming conductive plugs on top of each channel structure of the channel structure array.

11. The method according to claim 1, characterized in that, The stacked structure comprises one stack or multiple stacked stacks.

12. A three-dimensional memory, characterized in that, Comprising: A substrate; A stacked structure located on the substrate, the stacked structure comprising alternately stacked gate layers and dielectric layers; A gate line gap penetrating the stacked structure to reach the substrate, the gate line gap being separated by a separation structure; And An insulating layer is provided on the upper part of the partition structure and covers the surface of the stacked structure relatively far from the substrate, and the insulating layer penetrates through multiple layers of the gate layer and the dielectric layer; wherein, the surface of the insulating layer relatively far from the substrate is flat; A channel structure array includes a plurality of channel structures located in the stacked structure; the channel structure array is separated into multiple regions by the gate line gap.

13. The three-dimensional memory according to claim 12, wherein The insulating layer includes a first insulating layer located on the partition structure and a second insulating layer located on the first insulating layer, wherein the surface of the second insulating layer relatively far from the first insulating layer is flat.

14. The three-dimensional memory according to claim 12, wherein An array common source is further included in the gate line gap.

15. The three-dimensional memory according to claim 14, wherein A connection bridge spanning the insulating layer is further included, and the connection bridge connects the array common sources separated by the insulating layer.

16. The three-dimensional memory according to claim 12, wherein The insulating layer is located in the core area of the stacked structure.

17. The three-dimensional memory according to claim 12, wherein Further included are: A top selection gate tangent line penetrates through multiple layers of the gate layer and the dielectric layer in the stacked structure; An insulating layer filled in the top selection gate tangent line, wherein the insulating layer in the top selection gate tangent line and the insulating layer on the upper part of the partition structure are formed in the same filling process.

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