Display device

Abstract

A display device is provided. The display device includes a display panel and an input sensor. The input sensor includes a first electrode and a second electrode crossing each other and a bridge pattern at a crossing area of the first electrode and the second electrode. One of the first electrode and the second electrode includes a plurality of center patterns each having a first opening, a plurality of first patterns at one side of the plurality of center patterns each having a second opening, a plurality of second patterns at the other side of the plurality of center patterns each having a third opening, and a plurality of third patterns for electrically connecting two adjacent patterns among the plurality of center patterns, the plurality of first patterns, and the plurality of second patterns.

Description

Technical Field

[0001] This disclosure generally relates to a display device, and more specifically, to a display device with improved sensing performance. Background Technology

[0002] Multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation devices, and game consoles all have display devices for displaying images. In addition to typical input methods such as buttons, keyboards, or mice, electronic devices may also include input sensors that provide touch-based input methods that allow users to easily input information or commands in an intuitive and convenient manner.

[0003] Input sensors can detect touch or pressure from parts of a user's body. Meanwhile, there is a growing need to sense input from an active pen to provide detailed touch input information in guidance of users familiar with writing tools, or to provide detailed touch input information for specific applications (e.g., applications for sketching or drawing). Summary of the Invention

[0004] One or more embodiments of this disclosure relate to a display device that has improved sensing performance for both passive and active type inputs.

[0005] An embodiment of the present invention provides a display device including a display panel and an input sensor. The input sensor is located on the display panel and includes a first electrode extending in a first direction, a second electrode extending in a second direction intersecting the first direction, and a bridging pattern at the intersection of the first and second electrodes. One of the first and second electrodes includes a plurality of center patterns, a plurality of first patterns, a plurality of second patterns, and a plurality of third patterns. The plurality of center patterns are arranged along the second direction and each has a first opening. The plurality of first patterns are located on one side of the plurality of center patterns in the first direction, arranged along the second direction, and each has a second opening. The plurality of second patterns are located on the other side of the plurality of center patterns in the first direction, arranged along the second direction, and each has a third opening. The plurality of third patterns are configured to electrically connect two adjacent patterns among the plurality of center patterns, the plurality of first patterns, and the plurality of second patterns. The other of the first and second electrodes includes a plurality of line elements between two adjacent patterns among the plurality of center patterns, the plurality of first patterns, and the plurality of second patterns.

[0006] In an embodiment, the width of the first electrode in the second direction may be substantially uniform, and the width of the second electrode in the first direction may also be substantially uniform.

[0007] In an embodiment, the plurality of center patterns may include a first group of center patterns having the same shape and a second group of center patterns having a shape different from that of each center pattern in the first group.

[0008] In an embodiment, the central patterns of the first group may all have a rhombus shape.

[0009] In an embodiment, the plurality of first patterns may include a first group of first patterns having the same shape and a second group of first patterns having a shape different from that of each of the first patterns in the first group.

[0010] In an embodiment, the first patterns in the first group may all have a rectangular shape.

[0011] In an embodiment, the plurality of second patterns may include a first group of second patterns having the same shape and a second group of second patterns having a shape different from that of the first group of second patterns. Each of the first patterns in the first group may extend in a direction intersecting the first direction and the second direction, and the first patterns of the first group and the second patterns of the first group may extend in directions intersecting each other, respectively.

[0012] In an embodiment, the plurality of first patterns and the plurality of second patterns may be symmetrical with respect to the plurality of central patterns.

[0013] In one embodiment, a plurality of first patterns may form a plurality of first pattern rows arranged along a first direction. A plurality of second patterns may form a plurality of second pattern rows arranged along the first direction.

[0014] In an embodiment, the bridging pattern may include a first bridging pattern. The second electrode may include a first portion and a second portion that are separate from each other. The first bridging pattern can electrically connect the first portion and the second portion. A plurality of center patterns, a plurality of first patterns, a plurality of second patterns, and a plurality of third patterns may form the first portion and the second portion.

[0015] In one embodiment, the first bridging pattern may be located in the current path of the second electrode.

[0016] In one embodiment, the bridging pattern may include a second bridging pattern. The first electrode may include a first portion and a second portion that are separate from each other. The second bridging pattern may electrically connect the first portion and the second portion.

[0017] In one embodiment, the input sensor may further include an insulating layer. A bridging pattern may be located below the insulating layer. The first electrode and the second electrode may be located above the insulating layer.

[0018] In an embodiment, the plurality of line elements may include a plurality of first line elements extending in a first intersecting direction and a plurality of second line elements extending in a second intersecting direction. A first opening region through which a corresponding third pattern in a plurality of third patterns passes may be defined within a first line element among the plurality of first line elements. A second opening region through which a corresponding third pattern in a plurality of third patterns passes may be defined within a second line element among the plurality of second line elements.

[0019] In one embodiment, the plurality of wire elements may include a plurality of first wire elements extending in a first crossing direction and a plurality of second wire elements extending in a second crossing direction. A portion of the plurality of first wire elements and a portion of the plurality of second wire elements may have an integral shape in the crossing region of the first electrode and the second electrode.

[0020] In this embodiment, the display panel may include multiple light-emitting areas and non-light-emitting areas adjacent to the multiple light-emitting areas. Multiple center patterns, multiple first patterns, multiple second patterns, and multiple line elements may be superimposed on the non-light-emitting areas.

[0021] In this embodiment, the multiple light-emitting regions can form multiple unit light-emitting regions, and each of the multiple unit light-emitting regions can include a first light-emitting region for generating light of a first color, a second light-emitting region for generating light of a second color, a third light-emitting region for generating light of a third color, and a fourth light-emitting region for generating light of the third color. Corresponding unit light-emitting regions among the multiple unit light-emitting regions can be located inside the first opening.

[0022] In an embodiment, the area of ​​each of the second and third openings may be larger than the area of ​​the first opening.

[0023] In an embodiment, the display device may further include an input device configured to provide a drive signal to an input sensor. The input sensor can sense user input in a first mode via a change in capacitance between a first electrode and a second electrode, and can sense input from the input device based on the drive signal in a second mode.

[0024] In an embodiment of the present invention, a display device includes: a display panel configured to display an image; and an input sensor located on the display panel, including a sensing region having a plurality of unit sensing regions arranged in a matrix along intersecting first and second directions. The input sensor includes a plurality of center patterns, a plurality of first patterns, a plurality of second patterns, a plurality of third patterns, a plurality of line elements, and a bridging pattern. The plurality of center patterns are arranged along the second direction and each has a first opening. The plurality of first patterns are located on one side of the plurality of center patterns in the first direction, arranged along the second direction, and each has a second opening. The plurality of second patterns are located on the other side of the plurality of center patterns in the first direction, arranged along the second direction, and each has a third opening. The plurality of third patterns are configured to electrically connect two adjacent patterns among the plurality of center patterns, the plurality of first patterns, and the plurality of second patterns. The plurality of line elements are located between two adjacent patterns among the plurality of center patterns, the plurality of first patterns, and the plurality of second patterns. The bridging pattern is configured to connect at least one of a first opening region defined in a line element among the plurality of line elements and a second opening region defined in a third pattern among the plurality of third patterns.

[0025] In an embodiment, the display device may further include: a plurality of fourth patterns located at the boundary of two adjacent unit sensing regions in a first direction among a plurality of unit sensing regions, and each having a fourth opening.

[0026] In an embodiment, each of the plurality of fourth patterns may be symmetrical with respect to the second direction.

[0027] In an embodiment, a plurality of center patterns, a plurality of first patterns, a plurality of second patterns, and a plurality of third patterns may be electrically connected to form a current path in one of a first direction and a second direction, a plurality of line elements may be electrically connected to form a current path in the other of the first direction and the second direction, and the plurality of line elements may be electrically insulated from the plurality of center patterns.

[0028] In an embodiment of the present invention, a display device includes: a display panel configured to display an image; and an input sensor located on the display panel, the input sensor including a sensing region having a plurality of unit sensing regions arranged in a matrix along intersecting first and second directions. In each of the plurality of unit sensing regions, the input sensor includes a plurality of center patterns, a plurality of first patterns, a plurality of second patterns, a plurality of third patterns, a plurality of line elements, and a bridging pattern. The plurality of center patterns are arranged along the second direction and each has a first opening. The plurality of first patterns are located on one side of the plurality of center patterns in the first direction, arranged along the second direction, and each has a second opening. The plurality of second patterns are located on the other side of the plurality of center patterns in the first direction, arranged along the second direction, and each has a third opening. The plurality of third patterns are configured to electrically connect two adjacent patterns among the plurality of center patterns, the plurality of first patterns, and the plurality of second patterns. The plurality of line elements are located between two adjacent patterns among the plurality of center patterns, the plurality of first patterns, and the plurality of second patterns. The bridging pattern is configured to connect two adjacent first patterns among the plurality of first patterns or two adjacent second patterns among the plurality of second patterns. Attached Figure Description

[0029] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to describe the principles of the inventive concept. In the drawings:

[0030] Figure 1A This is a perspective view of an electronic device according to an embodiment of the present invention.

[0031] Figure 1B This is an exploded perspective view of an electronic device according to an embodiment of the present invention.

[0032] Figure 2A and Figure 2B All are embodiments of the concept of the present invention. Figure 1B The cross-sectional view of the electronic device shown is taken by line II′;

[0033] Figure 2C and Figure 2D All are embodiments of the concept of the present invention. Figure 1B The cross-sectional view of the display device shown is taken by line II′.

[0034] Figure 3A It is a block diagram used to describe the operation of an electronic device according to an embodiment of the concept of the present invention;

[0035] Figure 3B This is an embodiment of the concept of the present invention. Figure 3ABlock diagram of the input device shown;

[0036] Figure 4 This is an enlarged cross-sectional view of a display device according to an embodiment of the present invention;

[0037] Figure 5 This is a plan view illustrating an input sensor according to an embodiment of the concept of the present invention;

[0038] Figure 6 This is a view used to describe the operation of an input sensor in a first mode according to an embodiment of the concept of the present invention;

[0039] Figure 7A and Figure 7B This is a view used to describe the operation of the input sensor in a second mode according to an embodiment of the present invention;

[0040] Figure 8A This is an embodiment of the concept of the present invention. Figure 5 A schematic plan view of the input sensor shown;

[0041] Figure 8B This is an embodiment of the concept of the present invention. Figure 8A A magnified plan view of four of the multiple unit sensing regions shown;

[0042] Figure 8C This is an embodiment of the concept of the present invention. Figure 8B A magnified plan view of one of the multiple unit sensing regions shown;

[0043] Figure 8D This illustrates an embodiment based on the concept of the present invention. Figure 8C A floor plan of an example of the first region shown;

[0044] Figure 8E This illustrates an embodiment based on the concept of the present invention. Figure 8C A floor plan of an example of the second region shown;

[0045] Figure 8F This illustrates an embodiment based on the concept of the present invention. Figure 8C A floor plan of an example of the third region shown;

[0046] Figure 8G This illustrates an embodiment based on the concept of the present invention. Figure 8C A floor plan of an example of the fourth region shown;

[0047] Figure 8H It is along the embodiment of the concept of the present invention. Figure 8F A sectional view taken from line II-II′;

[0048] Figure 8I and Figure 8J All of these illustrate embodiments based on the concept of the present invention. Figure 8C A floor plan of an example of the third region shown;

[0049] Figures 9A to 9C All are enlarged plan views of a portion of the unit sensing area according to embodiments of the present invention; and

[0050] Figure 10 and Figure 11 All of these are enlarged planar views of the unit sensing area according to embodiments of the present invention. Detailed Implementation

[0051] This disclosure will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are illustrated. In the drawings, the same reference numerals consistently denote the same elements, and their repeated description may be omitted.

[0052] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to limit the example embodiments described herein.

[0053] It will be understood that when an element or layer (or region, part, etc.) is referred to as being "on", "connected to", or "bonded to" another element or layer, it can be directly on, directly connected to, or directly bonded to another element or layer, or there may be an intermediate element or layer.

[0054] Throughout this specification, the same reference numerals denote the same elements. In the drawings, for the purpose of effectively describing the technical content, the thickness, scale, and dimensions of the elements are exaggerated. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0055] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part without departing from the teachings of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms.

[0056] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or feature to other elements or features as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation.

[0057] It will be further understood that the terms “comprising,” “including,” and / or “having” as used in this specification indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0058] Furthermore, in describing embodiments of this disclosure, the use of "may" indicates "one or more embodiments of this disclosure".

[0059] As used here, expressions such as “at least one of…” and “one of…” modify the entire list of elements after a list of elements, without modifying any individual elements in the list.

[0060] As used herein, the terms “basically,” “about,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for the inherent biases in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0061] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0062] In the following sections, embodiments of the present disclosure will be explained in detail with reference to the accompanying drawings.

[0063] Figure 1A This is a perspective view of an electronic device ELD according to an embodiment of the present invention. Figure 1B This is an exploded perspective view of an electronic device ELD according to an embodiment of the present invention. Figure 2A and Figure 2B All are embodiments of the concept of the present invention. Figure 1B The cross-sectional view of the electronic device ELD is shown by line II′. Figure 2C and Figure 2D All are embodiments of the concept of the present invention. Figure 1BThe cross-sectional view of the display device DD is shown by line II′.

[0064] Reference Figure 1A and Figure 1B An electronic device (ELD) can be a device activated by an electrical signal. Electronic devices (ELDs) can include various embodiments. For example, electronic devices (ELDs) can be applied to smartphones, tablet computers, laptop computers, personal computers, smart TVs, etc.

[0065] The electronic device ELD may display an image IM on a display surface IS, either facing a third direction DR3 or on a third direction DR3. The display surface IS may be parallel to each of the first direction DR1 and the second direction DR2. In one or more embodiments, the display surface IS on which the image IM is displayed may correspond to the front surface of the electronic device ELD. The image IM may include still images and / or moving images.

[0066] In the illustrated embodiment, the front (or top) surface and rear (or bottom) surface of each component are defined in relation to the orientation of the displayed image IM. The front and rear surfaces may be opposite each other on a third direction DR3, and the direction orthogonal to each of the front and rear surfaces may be parallel to the third direction DR3.

[0067] The separation distance between the front and rear surfaces in the third direction DR3 can correspond to the thickness of the electronic device ELD in the third direction DR3. As used herein, the direction indicated by the first direction DR1 to the third direction DR3 (i.e., the first direction DR1, the second direction DR2, and the third direction DR3) can also be... Figure 1A The direction specified in the middle is different.

[0068] An electronic device ELD can sense external input applied from the outside. External input can include various inputs provided from outside the electronic device ELD. According to the illustrated embodiment, the electronic device ELD can sense a first input TC1 applied from the outside. The first input TC1 can be an input via a passive type of input device (e.g., a passive stylus, etc.), an input via the user's body, and can include all inputs that can change capacitance. The electronic device ELD can also sense the first input TC1 applied to any suitable surface of the electronic device ELD (such as a side surface or a rear surface), depending on the structure of the electronic device ELD. Therefore, the inventive concept is not limited to any one embodiment.

[0069] Furthermore, according to the illustrated embodiment, the electronic device ELD can sense a second input TC2 of a different type than the first input TC1. The second input TC2 can be an input from an active input device AP (e.g., an active pen). The input device AP can provide a drive signal to the input sensor ISP.

[0070] The front surface of an electronic device ELD may include an image area IA and a border area BZA. The image area IA may be the area in which an image IM is displayed. A user views the image IM through the image area IA. In the illustrated embodiment, the image area IA is shown as a quadrilateral shape with rounded vertices. However, this is shown by way of example, and in other embodiments, the image area IA may have various suitable shapes, and is therefore not limited to any one embodiment.

[0071] The border region BZA is adjacent to the image region IA. The border region BZA may have a set color (e.g., a predetermined color). The border region BZA may surround the image region IA. Therefore, the shape of the image region IA may be substantially defined by the border region BZA. However, this is shown as an example, and in other embodiments, the border region BZA may be provided only on one side adjacent to the image region IA or may be omitted. Therefore, the electronic device ELD conceived according to the present invention is not limited to any one embodiment.

[0072] like Figure 1B As shown, the electronic device ELD may include a display device DD, an optical component AF, a window WM, an electronic module EM, a power module PSM, and a housing EDC. The display device DD generates images and senses external inputs. The display device DD may include a display panel DP and an input sensor ISP. The display device DD includes image areas IA respectively associated with the electronic device ELD (e.g., see...). Figure 1A ) and border area BZA (for example, see Figure 1A The corresponding effective region AA and the outer region NAA.

[0073] The display panel (DP) can be, but is not specifically limited to, light-emitting display panels (such as organic light-emitting display panels and quantum dot light-emitting display panels). A more detailed description of the input sensor (ISP) is provided below.

[0074] The display device DD may further include a main circuit board MCB, a flexible circuit film FCB, and a driver chip DIC. Any one or more of these may be omitted. The main circuit board MCB may be connected to the flexible circuit film FCB for connection (e.g., electrical connection) to the display panel DP. The main circuit board MCB may include multiple driving elements. The multiple driving elements may include an integrated chip for driving the display panel DP. The main circuit board MCB may be connected (e.g., electrical connection) to the electronics module EM via a connector.

[0075] A flexible circuit film (FCB) is attached to the display panel (DP) to connect the display panel (DP) and the main circuit board (MCB) (e.g., electrical connection). The FCB can be bent such that the MCB faces the rear surface of the display device (DD). A driver chip (DIC) can be mounted on the FCB. The driver chip (DIC) may include driving elements (e.g., data driving circuitry) for driving the pixels of the display panel (DP). Figure 1B The diagram illustrates a structure in which the driver chip DIC is mounted on the flexible circuit film FCB, but the inventive concept is not limited thereto. For example, the driver chip DIC can be directly mounted on the display panel DP. A portion of the display panel DP can be bent, and when the driver chip DIC is mounted on this portion, this portion can be configured to face the rear surface of the display device DD.

[0076] In one or more embodiments, an additional flexible circuit film can connect (e.g., electrically connect) the input sensor ISP to the main circuit board MCB. However, the inventive concept is not limited thereto. The input sensor ISP can be connected (e.g., electrically connect) to the display panel DP, and can also be connected (e.g., electrically connect) to the main circuit board MCB via the flexible circuit film FCB.

[0077] Optical components (AF) reduce the reflection of external light. AF can include polarizers and retarders. Polarizers and retarders can be stretched or coated. In coated optical films, the optical axis is defined according to the stretching direction of the functional film. Coated optical films can include liquid crystal molecules disposed on a substrate film.

[0078] In embodiments of the present invention, the optical component AF can be omitted. In this case, the display device DD can further include a color filter and a black matrix to replace the optical component AF. The window WM provides the outer surface of the electronic device ELD. The window WM includes a substrate and may also include functional layers (such as an anti-reflective layer and an anti-fingerprint layer).

[0079] In one or more embodiments, the display device DD may further include at least one adhesive layer. The adhesive layer can bond adjacent components of the display device DD. The adhesive layer may be an optically transparent adhesive layer or a pressure-sensitive adhesive layer.

[0080] The electronic module (EM) includes at least a main controller. The EM may include a wireless communication module, an image input module, a sound input module, a sound output module, a memory, an external interface module, etc. These modules can be mounted on a circuit board or connected via a flexible circuit board (e.g., electrical connection). The EM is connected (e.g., electrically connected) to the power supply module (PSM).

[0081] The main controller controls the overall operation of the electronic device (ELD). For example, the main controller activates or deactivates the display device (DD) based on user input. The main controller can control the operation of the display device (DD), wireless communication module, image input module, sound input module, sound output module, etc. The main controller may include at least one microprocessor.

[0082] The housing EDC can be combined with the window WM. The housing EDC protects the components housed within it by absorbing externally applied impacts and preventing or substantially preventing the ingress of foreign objects / moisture into the display device DD. Furthermore, in embodiments of the present invention, the housing EDC can be provided as a combination of multiple storage components.

[0083] Reference Figure 2A The input sensor ISP can be disposed (e.g., directly disposed) on the display panel DP. According to embodiments of the present invention, the input sensor ISP can be formed on the display panel DP via a continuous or substantially continuous process. That is, when the input sensor ISP is disposed (e.g., directly disposed) on the display panel DP, an adhesive layer is not disposed between the input sensor ISP and the display panel DP. However, as... Figure 2B As shown, the adhesive layer ADL can be disposed between the input sensor ISP and the display panel DP. In this case, the input sensor ISP is not manufactured together with the display panel DP using a continuous or substantially continuous process, but rather using a process separate from that of the display panel DP, and can then be fixed to the top surface of the display panel DP by the adhesive layer ADL. Figure 2A and Figure 2B In some embodiments, there may be Figure 1B The optical component AF is shown in the diagram, but not explicitly shown. Alternatively, in other embodiments, a color filter and a black matrix may replace the optical component AF. Furthermore, components disposed below the display device DD may be present (e.g., see...). Figure 1B ), but not in Figure 2A and Figure 2B As shown in the image.

[0084] like Figure 2A As shown, the window WM may include a border area BZA for defining the border region (e.g., see...). Figure 1A Light-blocking patterned WBM. The light-blocking patterned WBM is a colored organic film and can be formed on a surface of a substrate layer WM-BS using, for example, a coating method.

[0085] like Figure 2C As shown, the display panel DP includes a substrate layer BL, a circuit element layer DP-CL disposed on the substrate layer BL, a display element layer DP-OLED and an encapsulation substrate ES, and a sealant SM that bonds the substrate layer BL and the encapsulation substrate ES.

[0086] The substrate layer BL may include at least one plastic film. The substrate layer BL may include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite substrate, etc. In the illustrated embodiment, the substrate layer BL may be a thin glass substrate having a thickness of tens to hundreds of micrometers. The substrate layer BL may have a multilayer structure. For example, the substrate layer BL may include a polyimide film / at least one inorganic layer / polyimide film.

[0087] The DP-CL circuit element layer includes at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines, pixel driving circuits, etc. A more detailed description is provided below.

[0088] The display element layer of a DP-OLED includes at least a light-emitting element. The display element layer of a DP-OLED may also include an organic layer (such as a pixel-defining film).

[0089] The encapsulation substrate ES can be separated from the display element layer DP-OLED (e.g., spaced apart), and there is a defined gap (e.g., a predetermined gap) GP between them. The substrate layer BL and the encapsulation substrate ES can include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite substrate, etc. The sealant SM can include an organic adhesive, glass frit, etc. The gap GP can be filled with a defined material (e.g., a predetermined material). The gap GP can be filled with a desiccant or a resin material.

[0090] like Figure 2D As shown, the display panel DP includes a substrate layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and an upper insulating layer TFL disposed on the substrate layer BL. The upper insulating layer TFL includes multiple thin films. The upper insulating layer TFL may include a protective layer for protecting the light-emitting elements. The upper insulating layer TFL may include a thin film encapsulation layer comprising at least an inorganic layer / organic layer / inorganic layer (i.e., a multilayer structure comprising an inorganic layer / organic layer / inorganic layer). The thin film encapsulation layer may be disposed on the protective layer.

[0091] Figure 3A This is a block diagram illustrating the operation of an electronic device ELD according to an embodiment of the present invention. Figure 3B This is an embodiment of the concept of the present invention. Figure 3A The block diagram of the input device AP shown is shown.

[0092] Reference Figure 3A and Figure 3BAn electronic device ELD according to an embodiment of the present invention may include a main controller 200 for controlling the drive of a display device DD and a sensor controller 100 connected to an input sensor ISP. The main controller 200 can control the drive of the sensor controller 100. In an embodiment of the present invention, the main controller 200 and the sensor controller 100 may be mounted on a main circuit board MCB (e.g., see...). Figure 1B In embodiments of the present invention, the sensor controller 100 may be embedded in a driver chip DIC (e.g., see...). Figure 1B )middle.

[0093] An input sensor ISP may include sensing electrodes. These sensing electrodes may include a first sensing electrode and a second sensing electrode. The structure of the input sensor ISP will be described in more detail below.

[0094] Sensor controller 100 can be connected to the sensing electrodes of input sensor ISP. Sensor controller 100 can operate input sensor ISP in a first mode to sense a first input TC1 (e.g., see...). Figure 1A ), and can operate the input sensor ISP in a second mode to sense the second input TC2 (e.g., see Figure 1A The operations of the first and second modes can be performed alternately or at different times under a preset method or according to a preset method.

[0095] like Figure 3B As shown, the input device AP may include a housing 11, a conductive tip 12, and a communication module 13. The housing 11 may be pen-shaped and may have a receiving space formed therein. The conductive tip 12 may protrude outward from the side of the housing 11 with an opening. The conductive tip 12 may be a part of the input device AP that contacts (e.g., directly contacts) the input sensor ISP.

[0096] The communication module 13 may include a transmitting circuit 13a and a receiving circuit 13b. The transmitting circuit 13a can send downlink signals to the sensor controller 100. The downlink signals may include the position of the input device AP, the tilt of the input device AP, status information, etc. When the input device AP contacts the input sensor ISP, the sensor controller 100 can receive the downlink signals through the input sensor ISP.

[0097] The receiving circuit 13b can receive uplink signals from the sensor controller 100. The uplink signals may include information such as panel information and / or protocol version. The sensor controller 100 can provide the uplink signals to the input sensor ISP, and the input device AP can receive the uplink signals by contacting the input sensor ISP.

[0098] The input device AP also includes an input controller 14 for controlling the drive of the input device AP. The input controller 14 can be configured to operate according to a predetermined program. A transmitting circuit 13a receives signals provided from the input controller 14 to modulate the signals into signals that can be sensed by the input sensor ISP, and a receiving circuit 13b demodulates the signals received by the input sensor ISP into signals that can be processed by the input controller 14. The input device AP may also include a power supply module 15 for supplying power to the input device AP.

[0099] Figure 4 This is an enlarged cross-sectional view of a display device DD according to an embodiment of the present invention. Figure 4 Based on Figure 2D The view of the display device DD.

[0100] Reference Figure 4 The display device DD may include a display panel DP and an input sensor ISP set (e.g., directly set) on the display panel DP. The display panel DP may include a substrate layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and an upper insulating layer TFL.

[0101] The substrate layer BL can provide a substrate surface on which the circuit element layer DP-CL is disposed. The circuit element layer DP-CL can be disposed on the substrate layer BL. The circuit element layer DP-CL may include insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layer, semiconductor layer, and conductive layer can be formed on the substrate layer BL by methods including processes such as coating and / or deposition, and thereafter, the insulating layer, semiconductor layer, and conductive layer can be selectively patterned by multiple photolithography processes. Subsequently, semiconductor patterns, conductive patterns, and signal lines included in the circuit element layer DP-CL can be formed.

[0102] At least one inorganic layer is formed on the top surface of the substrate layer BL. In the illustrated embodiment, the display panel DP is shown to include a buffer layer BFL. The buffer layer BFL can improve the adhesion between the substrate layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer, and the silicon oxide layer and the silicon nitride layer may be stacked alternately.

[0103] Semiconductor patterns can be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, the semiconductor pattern is not limited to this and may also include amorphous silicon or metal oxide. In other words, the semiconductor pattern may include any suitable material (such as polycrystalline silicon, amorphous silicon, and / or metal oxide). In one or more embodiments, multiple semiconductor patterns may be disposed.

[0104] Figure 4Only some of the semiconductor patterns are shown, and other semiconductor patterns may be further arranged in another region. The semiconductor patterns may be arranged across pixels according to a specific rule or based on a specific rule. Depending on whether the semiconductor patterns are doped, they may have different electrical properties. A semiconductor pattern may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with N-type or P-type dopant. A P-type transistor includes a doped region doped with P-type dopant. The second region may be an undoped region, or it may be doped at a lower concentration than the first region.

[0105] The first region has higher conductivity than the second region and can be used substantially as an electrode or signal line. The second region can substantially correspond to the active region (or channel region) of the transistor TR. In other words, a portion of the semiconductor pattern can be the active region of the transistor, while another portion can be the source or drain region of the transistor.

[0106] Each pixel can have an equivalent circuit including seven transistors, one capacitor, and a light-emitting element, and the equivalent circuit diagram of a pixel can be modified into various forms. Figure 4 The example illustrates a transistor TR and a light-emitting element ED included in a pixel.

[0107] The source region SR, channel region CHR, and drain region DR of a transistor TR can be formed by a semiconductor pattern. When viewed in cross-section, the source region SR and drain region DR can be positioned in opposite directions to the channel region CHR. For example, the source region SR and drain region DR can be located on corresponding sides of the channel region CHR. Figure 4 A portion of a signal transmission region SCL formed by a first region of a semiconductor pattern is shown. In one or more embodiments, when viewed in a plane, the signal transmission region SCL may be connected (e.g., electrically connected) to a transistor TR.

[0108] A first insulating layer IL1 may be disposed on a buffer layer BFL. The first insulating layer IL1 may be stacked together with multiple pixels (e.g., multiple pixels may be stacked with the same first insulating layer IL1) and cover a semiconductor pattern. The first insulating layer IL1 may include an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer IL1 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the illustrated embodiment, the first insulating layer IL1 may be a single-layer silicon oxide layer. In addition to the first insulating layer IL1, the insulating layer of the circuit element layer DP-CL, which will be described in more detail below, may include an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the materials described above, but is not limited thereto.

[0109] The gate GE of transistor TR is disposed on the first insulating layer IL1. Gate GE may be part of a metal pattern. Gate GE is stacked with the channel region CHR. In the process of doping semiconductor patterning, gate GE can be used as a mask.

[0110] A second insulating layer IL2 may be disposed on the first insulating layer IL1 and may cover the gate GE. The second insulating layer IL2 may be stacked together with multiple pixels (e.g., multiple pixels may be stacked with the same second insulating layer IL2). The second insulating layer IL2 may include inorganic and / or organic layers and may have a single-layer or multi-layer structure. In the illustrated embodiment, the second insulating layer IL2 may be a single-layer silicon oxide layer.

[0111] A third insulating layer IL3 may be disposed on the second insulating layer IL2, and in the illustrated embodiment, the third insulating layer IL3 may be a single layer of silicon oxide. A first connection electrode CNE1 may be disposed on the third insulating layer IL3. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a contact hole CNT1 penetrating the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3. In one or more embodiments, the first connection electrode CNE1 may be stacked with the signal transmission region SCL in a third direction DR3 (e.g., the thickness direction of the substrate layer BL).

[0112] The fourth insulating layer IL4 can be disposed on the third insulating layer IL3. The fourth insulating layer IL4 can be a single layer of silicon oxide. The fifth insulating layer IL5 can be disposed on the fourth insulating layer IL4. The fifth insulating layer IL5 can be an organic layer.

[0113] The second connecting electrode CNE2 can be disposed on the fifth insulating layer IL5. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through a contact hole CNT2 penetrating the fourth insulating layer IL4 and the fifth insulating layer IL5. In one or more embodiments, the second connecting electrode CNE2 can be stacked with the first connecting electrode CNE1 in a third direction DR3 (e.g., the thickness direction of the substrate layer BL).

[0114] The sixth insulating layer IL6 can be disposed on the fifth insulating layer IL5 and can cover the second connecting electrode CNE2. The sixth insulating layer IL6 can be an organic layer. The display element layer DP-OLED can be disposed on the circuit element layer DP-CL. The display element layer DP-OLED can include a light-emitting element ED. The light-emitting element ED can include a first electrode AE, a light-emitting layer EL, and a second electrode CE. For example, the light-emitting layer EL can include organic light-emitting materials, quantum dots, quantum rods, microLEDs, or nanoLEDs.

[0115] The first electrode AE ​​can be disposed on the sixth insulating layer IL6. The first electrode AE ​​can be connected to the second connecting electrode CNE2 through the contact hole CNT3 that penetrates the sixth insulating layer IL6.

[0116] A pixel defining film IL7 may be disposed on a sixth insulating layer IL6 and may cover a portion of the first electrode AE. An opening OP7 is defined in the pixel defining film IL7. The opening OP7 of the pixel defining film IL7 exposes at least a portion of the first electrode AE. In the illustrated embodiment, the light-emitting region PXA is defined to correspond to the portion of the first electrode AE ​​exposed by the opening OP7. A non-light-emitting region NPXA may surround the light-emitting region PXA.

[0117] The light-emitting layer EL can be disposed on the first electrode AE. The light-emitting layer EL can be disposed in the opening OP7. That is, the light-emitting layer EL can be formed separately in each of multiple pixels. Therefore, multiple light-emitting layers EL can be disposed. When the light-emitting layer EL is formed separately in each of multiple pixels, each of the light-emitting layer EL can emit light having at least one color among blue, red, and green (e.g., a light beam). However, the light-emitting layer EL is not limited to this, and can also be connected to pixels and disposed commonly for multiple pixels (e.g., multiple pixels can share the light-emitting layer EL). In this case, the light-emitting layer EL can provide blue light or white light.

[0118] The second electrode CE can be disposed on the light-emitting layer EL. The second electrode CE can have a monolithic shape and can be commonly disposed in multiple pixels (e.g., multiple pixels can share the second electrode CE). A common voltage can be provided to the second electrode CE, and the second electrode CE can be referred to as the common electrode.

[0119] In one or more embodiments, a hole control layer may be disposed between the first electrode AE ​​and the light-emitting layer EL. The hole control layer may be commonly disposed in the light-emitting region PXA and the non-light-emitting region NPXA. The hole control layer may include a hole transport layer and may also include a hole injection layer. An electron control layer may be disposed between the light-emitting layer EL and the second electrode CE. The electron control layer may include an electron transport layer and may also include an electron injection layer. The hole control layer and the electron control layer may be commonly formed in multiple pixels using an aperture mask.

[0120] The input sensor ISP can be directly formed on the top surface of the upper insulating layer TFL using a continuous or largely continuous process. The input sensor ISP may include a first sensor insulating layer IIL1, a first conductive layer ICL1, a second sensor insulating layer IIL2, a second conductive layer ICL2, and a third sensor insulating layer IIL3. In embodiments of this invention, the first sensor insulating layer IIL1 may be omitted.

[0121] Each of the first conductive layer ICL1 and the second conductive layer ICL2 may have a monolayer structure, or may include multiple patterns having a multilayer structure stacked on a third-direction DR3. The monolayer conductive layer may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may include transparent conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or indium zinc tin oxide (IZTO)). Furthermore, the transparent conductive layer may include conductive polymers (such as PEDOT), metal nanowires, graphene, etc.

[0122] The conductive layer in a multilayer structure may include a metal layer. The metal layer may have a three-layer structure, such as titanium / aluminum / titanium. The conductive layer in a multilayer structure may include at least one metal layer and at least one transparent conductive layer.

[0123] The second sensor insulating layer IIL2 covers the first conductive layer ICL1, and the third sensor insulating layer IIL3 covers the second conductive layer ICL2. The first sensor insulating layer IIL1 to the third sensor insulating layer IIL3 (i.e., the first sensor insulating layer IIL1, the second sensor insulating layer IIL2, and the third sensor insulating layer IIL3) are all shown as a single layer, but are not limited thereto.

[0124] At least one of the first sensor insulating layer IIL1 and the second sensor insulating layer IIL2 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0125] The third sensor insulating layer IIL3 may include an organic film. The organic film may include at least one of acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, polyurethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins.

[0126] As the distance between the display element layer (DP-OLED) and the input sensor (ISP) decreases, the input sensor ISP becomes significantly affected by the signal supplied from the DP-OLED. The capacitance of the load capacitor Cb formed between the first conductive layer ICL1 and / or the second conductive layer ICL2 and the second electrode CE varies depending on the operation of the DP-OLED. Interference signals from the DP-OLED act as noise in the input sensor ISP.

[0127] Figure 5 This is a plan view illustrating an input sensor ISP according to an embodiment of the present invention. Figure 6This is a view used to describe the operation of the input sensor ISP in a first mode according to an embodiment of the present invention. Figure 7A and Figure 7B This is a view used to describe the operation of the input sensor ISP in a second mode according to an embodiment of the present invention. In the following, reference will be made additionally to... Figure 3A Let's describe the input sensor ISP in more detail.

[0128] Reference Figure 3A and Figure 5 The input sensor ISP can include a sensing area (ISA) and a non-sensing area (NSA). The sensing area (ISA) and the non-sensing area (NSA) can respectively correspond to... Figure 1B The effective area AA and the peripheral area NAA of the display device DD shown are illustrated.

[0129] The input sensor ISP includes first sensing electrodes SE1_1 to SE1_n (hereinafter referred to as first electrodes SE1) and second sensing electrodes SE2_1 to SE2_m (hereinafter referred to as second electrodes SE2). The first electrodes SE1 and the second electrodes SE2 are electrically insulated from each other and intersect each other. Each region where the first electrode SE1 intersects with the second electrode SE2 can be defined as an intersecting region ECA. Each region where the first electrode SE1 does not intersect with the second electrode SE2 can be defined as a non-intersecting region N-CA. As the widths of the first electrode SE1 and the second electrode SE2 increase, the non-intersecting regions N-CA decrease. In the illustrated embodiment, the first electrodes SE1 are shorter than the second electrodes SE2 and are arranged in a greater number than the number of second electrodes SE2, but the inventive concept is not limited thereto. In other words, in one or more embodiments, the length of the first electrode SE1 in the second direction DR2 may be smaller than the length of the second electrode SE2 in the first direction DR1, and the number of first electrodes SE1 is greater than the number of second electrodes SE2.

[0130] Each of the first electrodes SE1 may have a strip or band shape and may extend in the second direction DR2. The first electrodes SE1 may be arranged to be separated from each other in the first direction DR1 (e.g., spaced apart). The first electrodes SE1 may have a substantially constant width W1 in the first direction DR1. The first electrodes SE1 may have a constant width W1 in the cross region ECA and the non-cross region N-CA. The separation distance between the first electrodes SE1 (e.g., adjacent first electrodes SE1) in the first direction DR1 may be constant.

[0131] Each of the second electrodes SE2 may have a strip shape or a band shape and may extend in the first direction DR1. The second electrodes SE2 may be arranged to be separated from each other in the second direction DR2 (e.g., spaced apart). The second electrodes SE2 may have a substantially constant width W2 in the second direction DR2. The second electrodes SE2 may have a constant width W2 in the cross region ECA and the non-cross region N-CA. The separation distance between the second electrodes SE2 (e.g., adjacent second electrodes SE2) in the second direction DR2 may be constant.

[0132] The input sensor ISP may further include multiple first sensing signal lines SL1_1 to SL1_n (hereinafter referred to as first signal lines SL1) and multiple second sensing signal lines SL2_1 to SL2_m (hereinafter referred to as second signal lines SL2). The first signal lines SL1 and SL2 may be disposed in the non-sensing region NSA. The first signal lines SL1 may be connected (e.g., electrically connected) to at least one side of the first electrode SE1, and the second signal lines SL2 may be connected (e.g., electrically connected) to one side of the second electrode SE2.

[0133] The first electrode SE1 is connected (e.g., electrically connected) to the sensor controller 100 via the first signal line SL1 (e.g., see...). Figure 3A The second electrode SE2 is connected (e.g., electrically connected) to the sensor controller 100 via the second signal line SL2.

[0134] In a first mode of an embodiment of the present invention, one of the first electrode SE1 and the second electrode SE2 can operate as a transmitting electrode, and the other of the first electrode SE1 and the second electrode SE2 can operate as a receiving electrode. The input sensor ISP can operate in the first mode or in a second mode. In the first mode, information about the first input TC1 is obtained through changes in the mutual capacitance between the first electrode SE1 and the second electrode SE2 (e.g., see...). Figure 3A In the second mode, the second input TC2 is sensed by the change in capacitance of each of the first electrode SE1 and the second electrode SE2 (e.g., see...). Figure 3A ).

[0135] Figures 6 to 7B The diagram schematically illustrates two first electrodes SE1_1 and SE1_2 in the first electrode SE1 and two second electrodes SE2_1 and SE2_2 in the second electrode SE2. Figure 6 In the diagram, the second electrodes SE2_1 and SE2_2 are shown as receiving electrodes.

[0136] Reference Figure 6In a first mode, the sensor controller 100 can provide drive signals TS1 and TS2 to the first electrodes SE1_1 and SE1_2, respectively. Although drive signals TS1 and TS2 are shown as being provided to one end of the corresponding first electrode in SE1_1 and SE1_2, each of drive signals TS1 and TS2 can be provided to both ends of the corresponding first electrode in SE1_1 and SE1_2 simultaneously. In the first mode, the sensor controller 100 can receive sensing signals RS1 and RS2 from the second electrodes SE2_1 and SE2_2, respectively. Therefore, the sensor controller 100 can compare drive signals TS1 and TS2 with sensing signals RS1 and RS2 corresponding to drive signals TS1 and TS2, and generate coordinate values ​​of the position provided with the first input TC1 based on their changes.

[0137] Reference Figure 7A and Figure 7B When the input device AP approaches the input sensor ISP, the input sensor ISP can enter a second mode for sensing the second input TC2. The input device AP can send data to and / or receive data from the sensor controller 100 through the input sensor ISP.

[0138] In the second mode, at least one of the first electrodes SE1_1 and SE1_2 and the second electrodes SE2_1 and SE2_2 can be used as a transmitting electrode for providing uplink signals TSa, TSb, TSC, and TSd from the sensor controller 100 to the input device AP. In the second mode, the first electrodes SE1_1 and SE1_2 and the second electrodes SE2_1 and SE2_2 can be used as receiving electrodes for providing downlink signals RSa, RSb, RSC, and RSd from the input device AP to the sensor controller 100, respectively. That is, all electrodes of the first electrodes SE1_1 and SE1_2 and the second electrodes SE2_1 and SE2_2 can be used as either transmitting or receiving electrodes in the second mode.

[0139] Because each of the first electrodes SE1_1 and SE1_2 and the second electrodes SE2_1 and SE2_2 has a strip shape, the change in mutual capacitance between the first electrodes SE1_1 and SE1_2 and the second electrodes SE2_1 and SE2_2 can remain substantially constant even when the input device AP moves. Therefore, even when the second input TC2 moves, the movement of the second input TC2 can be accurately sensed in the second mode. That is, when writing or drawing using the input device AP, the second input TC2 is not distorted when provided in a line shape. As a result, the linearity of the second input TC2 can be improved.

[0140] Figure 8A yes Figure 5 The diagram shows a schematic plan view of the input sensor ISP. Figure 8B yes Figure 8A The image shows a magnified plan view of four of the multiple unit sensing regions UA shown. Figure 8C yes Figure 8B An enlarged plan view of one of the multiple unit sensing regions UA shown. Figure 8D It is shown Figure 8C A plan view of an example of the first region CA1 (or the first opening region) shown. Figure 8E It is shown Figure 8C A plan view of an example of the second region CA2 (or the second opening region) shown. Figure 8F It is shown Figure 8C A plan view of an example of the third region CA3 (or the third opening region) shown. Figure 8G This is a plan view illustrating an example of a fourth region CA4 (or a fourth opening region) according to an embodiment of the concept of the present invention. Figure 8H It is along Figure 8F A sectional view taken from line II-II′. Figure 8I and Figure 8J All are shown Figure 8C The plan view of the third region CA3 shown is an example.

[0141] Reference Figure 8A The sensing area ISA comprises multiple unit sensing areas UA. The multiple unit sensing areas UA are arranged in a matrix form defined by a first direction DR1 and a second direction DR2. In other words, the multiple unit sensing areas UA are arranged in a matrix form along the first direction DR1 and the second direction DR2. The unit sensing areas UA can form sensing columns extending respectively along the first direction DR1 and sensing rows extending respectively along the second direction DR2. In other words, the multiple unit sensing areas UA can be arranged along the first direction DR1 to form sensing columns and along the second direction DR2 to form sensing rows. Although the input sensor ISP is shown as an example where the entire sensing area ISA is composed solely of unit sensing areas UA, the input sensor ISP is not limited thereto. In embodiments of the inventive concept, the input sensor ISP may include a first sensing area and a second sensing area distinct from each other. The first sensing area may consist solely of unit sensing areas UA, while the second sensing area disposed outside the first sensing area may include areas other than the unit sensing areas UA or include unit sensing areas different from each of the unit sensing areas UA. In other words, at least a portion of the sensing area ISA may be uniformly or substantially uniformly divided into multiple unit sensing areas UA.

[0142] Each of the unit sensing regions UA includes at least Figure 5 The cross region ECA is shown in the diagram. In the unit sensing region UA, depending on the percentage of the surface area (or "surface area") of each of the regions where the first electrode SE1 and the second electrode SE2 intersect, the unit sensing region UA ​​may include only the cross region ECA of the first electrode SE1 and the second electrode SE2, or it may also include the non-cross region N-CA of the first electrode SE1 and the second electrode SE2.

[0143] Reference Figure 8B The diagram shows two first electrodes SE1 and two second electrodes SE2 disposed in four unit sensing regions UA. The width W1 of each of the first electrodes SE1 in the cross region ECA is substantially the same as the width W1 of the first electrode SE1 in the non-cross region N-CA, and the width W2 of each of the second electrodes SE2 in the cross region ECA is substantially the same as the width W2 of the second electrode SE2 in the non-cross region N-CA.

[0144] Due to the curvature of the pattern, each of the first electrode SE1 and the second electrode SE2 may include relatively wide and relatively narrow regions, but the width is measured based on points of the same shape due to the curvature of the pattern after comparing the intersecting region ECA with the non-intersecting region N-CA. Because the widths of the intersecting region ECA and the non-intersecting region N-CA are substantially the same, the shapes of the first electrode SE1 and the second electrode SE2 can be defined as strip or band shapes. In one or more embodiments, dummy electrodes may be further provided in the input sensor ISP according to the illustrated embodiment to eliminate the visual difference between areas where the first electrode SE1 and the second electrode SE2 are not provided and areas where the first electrode SE1 and the second electrode SE2 are provided.

[0145] Reference Figure 8C The first electrode SE1 and the second electrode SE2 have a grid shape. Each of the first electrode SE1 and the second electrode SE2 substantially includes a plurality of first wire elements LE1 and a plurality of second wire elements LE2. Each first wire element LE1 extends in a first intersecting direction CDR1 that intersects a first direction DR1 and a second direction DR2, and each second wire element LE2 extends in a second intersecting direction CDR2 that intersects the first intersecting direction CDR1. The first wire elements LE1 and the second wire elements LE2 define or form a pattern constituting the first electrode SE1 and the second electrode SE2. In one or more embodiments, the angle formed between the first wire elements LE1 and the second wire elements LE2 can be a right angle (i.e., a 90-degree angle) or a substantially right angle.

[0146] Reference Figure 8CIn the unit sensing area UA, the second electrode SE2 includes multiple center patterns CP, multiple first patterns P1, multiple second patterns P2, and multiple third patterns P3. In the cross region ECA, line elements LE1 and LE2 of the first electrode SE1 are disposed in at least some regions between two adjacent patterns among the multiple center patterns CP, multiple first patterns P1, multiple second patterns P2, and multiple third patterns P3. Because the gap between the line elements LE1 and LE2 of the first electrode SE1 and the line elements LE1 and LE2 of the second electrode SE2 becomes narrower, and the length of the region of the line elements LE1 and LE2 of the first electrode SE1 facing the line elements LE1 and LE2 of the second electrode SE2 increases, the mutual capacitance between the first electrode SE1 and the second electrode SE2 increases. This also increases the amount of capacitance change before and after input is applied through a passive type input device. As a result, the input sensitivity of the passive type input device is improved.

[0147] The central pattern CP is arranged on or along the second direction DR2, and both provide a first opening OP1. Eight central patterns CP are shown by way of example. In the illustrated embodiment, two sets of central patterns CP are shown. The central patterns CP1 of the first set may have the same shape (e.g., the same shape as each other), and the central patterns CP2 of the second set may have a shape different from each of the central patterns CP1 in the first set. The central patterns CP1 of the first set may have a quadrilateral shape. In the illustrated embodiment, the central patterns CP1 of the first set are shown as having a rhombus shape. In the illustrated embodiment, the central patterns CP1 of the first set may have a square shape.

[0148] The center patterns CP2 of the second group can each have a shape obtained by removing or omitting a portion of any one of the center patterns CP1 of the first group. In the illustrated embodiment, two center patterns CP2 of the second group are shown disposed on each side of the center patterns CP1 of the first group and have different shapes (e.g., shapes different from the center patterns CP1 of the first group and / or shapes different from each other). In some embodiments of the inventive concept, all center patterns CP can also have the same shape (e.g., the same shape as each other). In other words, in one or more embodiments, the center patterns CP1 of the first group and the center patterns CP2 of the second group can have the same shape as each other.

[0149] A first pattern P1 is disposed on one side of the central pattern CP in the first direction DR1. The first pattern P1 may define or form a plurality of first pattern rows PL1. The first pattern rows PL1 are arranged in the first direction DR1. In each of the first pattern rows PL1, the first pattern P1 may be arranged in or along the second direction DR2, and may each be provided with a second opening OP2.

[0150] In the illustrated embodiment, two sets of first patterns P1 are shown. The first patterns P1-1 of the first set may have the same shape (e.g., identical to each other), and the first patterns P1-2 of the second set may have a shape different from each of the first patterns P1-1 in the first set. The first patterns P1-1 of the first set may all have a quadrilateral shape. In the illustrated embodiment, the first patterns P1-1 of the first set are shown as all having a rectangular shape. The first patterns P1-1 of the first set may all have a shape extending in the second intersecting direction CDR2. For example, the long side of the first patterns P1-1 of the first set may be parallel to or substantially parallel to the second intersecting direction CDR2.

[0151] The first patterns P1-2 of the second group can each have a shape obtained by removing or omitting a portion of any one of the first patterns P1-1 of the first group. In the illustrated embodiment, two first patterns P1-2 of the second group are shown, each disposed on a separate side of each of the first pattern rows PL1 and having different shapes (e.g., shapes different from the first patterns P1-1 of the first group and / or shapes different from each other). In embodiments of the inventive concept, all first patterns P1 may also have the same shape (e.g., the same shape as each other). In other words, in one or more embodiments, the first patterns P1-1 of the first group and the first patterns P1-2 of the second group may have the same shape as each other.

[0152] The second pattern P2 is disposed on or on the opposite side of the central pattern CP in the first direction DR1. The second pattern P2 may define or form a plurality of second pattern rows PL2. The second pattern rows PL2 are arranged in the first direction DR1. In each of the second pattern rows PL2, the second pattern P2 may be arranged in or along the second direction DR2, and may each be provided with a third opening OP3.

[0153] In the illustrated embodiment, two sets of second patterns P2 are shown. The second patterns P2-1 of the first set may have the same shape (e.g., identical to each other), while the second patterns P2-2 of the second set may have a shape different from each of the second patterns P2-1 in the first set. The second patterns P2-1 of the first set may all have a quadrilateral shape. In the illustrated embodiment, the second patterns P2-1 of the first set are shown as all having a rectangular shape. The second patterns P2-1 of the first set may all have a shape extending in a first intersecting direction CDR1. For example, the long side of the second patterns P2-1 of the first set may be parallel to or substantially parallel to the first intersecting direction CDR1.

[0154] The second patterns P2-2 of the second group can each have a shape obtained by removing or omitting a portion of any one of the second patterns P2-1 of the first group. In the illustrated embodiment, two second patterns P2-2 of the second group are shown, each disposed on a separate side of each of the second pattern rows PL2 and having different shapes (e.g., shapes different from the second patterns P2-1 of the first group and / or shapes different from each other). In embodiments of the inventive concept, all second patterns P2 can also have the same shape (e.g., the same shape as each other). In other words, in one or more embodiments, the second patterns P2-1 of the first group and the second patterns P2-2 of the second group can have the same shape as each other.

[0155] The first pattern P1 and the second pattern P2 can be symmetrical with respect to the central pattern CP. In other words, with respect to an imaginary reference axis parallel to the second direction DR2 and superimposed on the central pattern CP (e.g., the center point of the central pattern CP), the first pattern P1-1 and the second pattern P2-1 of the first group can be symmetrical to each other, and the first pattern P1-2 and the second pattern P2-2 of the second group can be symmetrical to each other. The second opening OP2 and the third opening OP3 can have the same or substantially the same surface area. Each of the second opening OP2 and the third opening OP3 defines a surface area larger than that of the first opening OP1. The reason for this is to reduce the capacitance of the load capacitor Cb by increasing the percentage of the surface area of ​​the second opening OP2 and the third opening OP3 in the second electrode SE2. A more detailed description of this will be provided below.

[0156] The third pattern P3 connects (e.g., electrically connects) two adjacent patterns among the plurality of center patterns CP, the plurality of first patterns P1, and the plurality of second patterns P2. The plurality of center patterns CP, the plurality of first patterns P1, the plurality of second patterns P2, and the plurality of third patterns P3 are substantially of a single, integral shape. In other words, the plurality of center patterns CP, the plurality of first patterns P1, the plurality of second patterns P2, and the plurality of third patterns P3 can be integrally formed with each other (i.e., forming a monolithic structure). The grid-shaped second electrode SE2 is formed by etching the conductive layer.

[0157] In the illustrated embodiment, three third patterns P3 are shown by way of example for connecting each of the central pattern CP (e.g., electrical connections) to adjacent patterns. Four third patterns P3 are shown for connecting each of the first pattern P1 and the second pattern P2 (e.g., electrical connections) to adjacent patterns. The number of third patterns P3 connected to each of the central pattern CP need not be limited to the same number. The number of third patterns P3 connected to each of the first pattern P1 and the second pattern P2 need not be limited to the same number. The third patterns P3 can disconnect the line elements LE1 and LE2 of the first electrode SE1, which will be described in more detail below, and can divide the first electrode SE1 into multiple parts. To adjust the number of parts constituting the first electrode SE1, some of the third patterns P3 associated with the central pattern CP, the first pattern P1, and the second pattern P2 can be removed or disconnected.

[0158] The third pattern P3 may include two groups. The third patterns P3-1 of the first group each extend in the first intersecting direction CDR1, and the third patterns P3-2 of the second group each extend in the second intersecting direction CDR2.

[0159] Some of the first wire elements LE1 and some of the second wire elements LE2 of the first electrode SE1 have an integral shape. In other words, some of the first wire elements LE1 and some of the second wire elements LE2 of the first electrode SE1 can be integral with each other (i.e., forming a monolithic structure). In one or more embodiments, the integral shape can extend through the intersection region ECA. Some of the first wire elements LE1 and some of the second wire elements LE2 of the first electrode SE1 may include multiple opening regions SE1-OP.

[0160] In the first region CA1, such as Figure 8D As shown, one of the multiple opening regions SE1-OP can be defined in one of the multiple first line elements LE1 of the first electrode SE1. The third pattern P3-2 of the second group can pass through the opening region SE1-OP.

[0161] In the second region CA2, such as Figure 8EAs shown, one of the multiple opening regions SE1-OP can be confined within one of the multiple second line elements LE2 of the first electrode SE1. The third pattern P3-1 of the first group can pass through the opening region SE1-OP.

[0162] Refer again Figure 8C Even when the first electrode SE1 has multiple opening regions SE1-OP formed therein and includes multiple separate portions, the line elements LE1 and LE2 of the first electrode SE1 can also form a first current path 1000 that intersects with the cross region ECA on the second direction DR2.

[0163] exist Figure 8C In the diagram, a first current path 1000 is shown using a dashed arrow. Figure 8F The third region CA3, shown in magnification, is disposed in the first current path 1000. The third region CA3 is the region where the bridging pattern BRP is disposed. Although the first current path 1000 is shown as an example above the center pattern CP in the illustrated embodiment, the first current path 1000 may be formed below the center pattern CP or may be formed from above the center pattern CP through the center pattern CP to below the center pattern CP.

[0164] Reference Figure 8F An opening region P3-OP is formed in the third pattern P3-2 of the second group. One of the multiple first line elements LE1 of the first electrode SE1 passes through the opening region P3-OP.

[0165] Reference Figure 8G The opening region P3-OP is also formed in the third pattern P3-2 of the second group in the fourth region CA4, and one of the first line elements LE1 of the plurality of first line elements LE1 of the first electrode SE1 passes through the opening region P3-OP. Bridging pattern BRP (see reference) Figure 8F It is not set in the fourth region CA4.

[0166] according to Figure 8CIn the embodiment shown, the second electrode SE2 includes two portions SE2-P1 and SE2-P2, separated from and respectively disposed above and below the first current path 1000. An embodiment is illustrated by way of example where a bridging pattern BRP is configured to connect (e.g., electrically connect) the first portion SE2-P1 and the second portion SE2-P2 of the second electrode SE2. In one or more embodiments, the first portion SE2-P1 and the second portion SE2-P2 may be defined or formed by a plurality of center patterns CP, a plurality of first patterns P1, a plurality of second patterns P2, and a plurality of third patterns P3. To reduce manufacturing defects by reducing the number of bridging patterns BRP, a third region CA3 and six fourth regions CA4 may be applied in the first current path 1000. In embodiments of the inventive concept, some of the fourth regions CA4 may be replaced by the third regions CA3.

[0167] Reference Figure 8C and Figure 8F A second current path 2000, intersecting the cross region ECA in the first direction DR1, is formed in the second electrode SE2. A bridging pattern RP constitutes the second current path 2000. Simultaneously, Figure 8C The second current path 2000 shown is merely an example. After converging on and then passing through the bridging pattern BRP, it can branch back into multiple current paths.

[0168] Reference Figure 8H The bridging pattern BRP can be disposed on the first sensor insulating layer IIL1. The second sensor insulating layer IIL2 covers the bridging pattern BRP. The third pattern P3-2 of the second group is connected to the bridging pattern BRP through the contact hole CH. Generally, the first electrode SE1 and the second electrode SE2 are disposed on the same layer, and the bridging pattern BRP is disposed on a layer different from the layer on which the first electrode SE1 is disposed. In one or more embodiments, the bridging pattern BRP can be located on a layer different from the first electrode SE1. In the embodiments of the present invention, the bridging pattern BRP can be disposed on the second sensor insulating layer IIL2, and the first electrode SE1 and the second electrode SE2 can be disposed on the first sensor insulating layer IIL1.

[0169] Figure 8I The third region CA3 is shown according to an embodiment of the present invention. The third pattern P3-2 of the second group is not located in the third region CA3. It can be seen that the object connected by the bridging pattern BRP is different from... Figure 8F The objects connected by the bridging pattern BRP shown are illustrated. The bridging pattern BRP can connect (e.g., electrically connect) adjacent first patterns P1.

[0170] Figure 8J The third region CA3 is shown according to an embodiment of the concept of the present invention. It can be seen that the object connected by the bridging pattern BRP is... Figure 8F The objects connected by the bridging pattern BRP shown are different. The opening region SE1-OP can be formed in the first line element LE1 of the first electrode SE1, and the third pattern P3-2 of the second group can pass through the opening region SE1-OP. The bridging pattern BRP is disposed on a layer different from the layer on which the first line element LE1 is disposed, and can connect (e.g., electrically connect) the first line element LE1 in the opening region SE1-OP. The bridging pattern BRP constitutes... Figure 8C The first current path is 1000.

[0171] Return to reference Figure 8B The second electrode SE2 may further include a fourth pattern P4. The fourth pattern P4 is disposed at the boundary between two adjacent unit sensing regions UA in the first direction DR1 among the plurality of unit sensing regions UA. The fourth pattern P4 provides a fourth opening OP4.

[0172] In one or more embodiments, a plurality of fourth patterns P4 are provided, and the fourth patterns P4 are arranged on or along the second direction DR2. Each of the fourth patterns P4 may have a shape symmetrical with respect to the second direction DR2 (e.g., an imaginary reference axis extending in the second direction DR2). The fourth pattern P4 may have a shape symmetrical with respect to the boundary line extending in the second direction DR2 between two adjacent unit sensing regions UA in the first direction DR1.

[0173] The fourth pattern P4 is connected (e.g., electrically connected) to the adjacent first pattern P1 and the adjacent second pattern P2 via the third pattern P3.

[0174] Figures 9A to 9C These are all enlarged plan views of a portion of the unit sensing region UA ​​according to embodiments of the present invention.

[0175] Figure 9A It shows the relationship with Figure 4 The luminescent region PXA shown corresponds to luminescent regions PXA-R, PXA-B, PXA-G1, and PXA-G2. Four types of luminescent regions PXA-R, PXA-B, PXA-G1, and PXA-G2 with different shapes are illustrated by way of example, but the inventive concept is not limited thereto. Although the illustrated embodiment shows two types of luminescent regions PXA-R, PXA-B, PXA-G1, and PXA-G2 that generate light of the same color, the inventive concept is not limited thereto.

[0176] The first emitting region PXA-R is the emitting region of a pixel of the first color, the second emitting region PXA-B is the emitting region of a pixel of the second color, and the third emitting region PXA-G1 and the fourth emitting region PXA-G2 are the emitting regions of pixels of the third color. In one or more embodiments, the light of the first color (e.g., a beam of light) can be red light (e.g., a red beam of light), the light of the second color (e.g., a beam of light) can be blue light (e.g., a blue beam of light), and the light of the third color (e.g., a beam of light) can be green light (e.g., a green beam of light). However, this disclosure is not limited thereto. For example, the light (e.g., beams of light) of the first to third colors (i.e., the first, second, and third colors) can be any suitable color, such as light (e.g., beams of light) of three other primary colors (e.g., the three primary colors). In embodiments of the inventive concept, the third emitting region PXA-G1 and the fourth emitting region PXA-G2 can have the same shape (e.g., the same shape as each other).

[0177] The luminescent regions PXA-R, PXA-B, PXA-G1, and PXA-G2 can define or form multiple unit luminescent regions PUA. Each unit luminescent region PUA can include multiple luminescent regions, and can include the same number of luminescent regions. The unit luminescent regions PUA can have luminescent regions arranged in the same way. When viewed in a plane, the multiple unit luminescent regions PUA can have the same or substantially the same surface area.

[0178] Each of the unit light-emitting regions PUA includes a first light-emitting region PXA-R, a second light-emitting region PXA-B, a third light-emitting region PXA-G1, and a fourth light-emitting region PXA-G2. The first light-emitting region PXA-R and the second light-emitting region PXA-B can be arranged to face each other in the second direction DR2, and the third light-emitting region PXA-G1 and the fourth light-emitting region PXA-G2 can be arranged to face each other in the first direction DR1.

[0179] First line elements LE1 and second line elements LE2 constituting the first electrode SE1 and the second electrode SE2 are disposed in the non-light-emitting region NPXA. In other words, multiple center patterns CP, multiple first patterns P1, multiple second patterns P2, and multiple third patterns P3 are superimposed on the non-light-emitting region NPXA. A single unit light-emitting region PUA can be disposed inside the first opening OP1. Two single unit light-emitting regions PUA can be disposed inside each of the second opening OP2 and the third opening OP3, which have a surface area larger than the first opening OP1. As the surface areas of the first opening OP1, the second opening OP2, and the third opening OP3 increase, the load capacitance can be reduced due to the second electrode SE2 because the surface area of ​​the region where the first line elements LE1 and the second line elements LE2 of the second electrode SE2 are superimposed on the display panel DP decreases. Since the surface area of ​​the first electrode SE1 is in the cross region ECA (for example, see...), the load capacitance can be reduced due to the second electrode SE2. Figure 8B The surface area of ​​the first electrode SE1 is proportional to the surface area of ​​the second electrode SE2. Therefore, the surface area of ​​the first electrode SE1 decreases due to the decrease in the surface area of ​​the second electrode SE2. As a result, the load capacitance between the display panel DP and the first electrode SE1 can be reduced. As the load capacitance of the first electrode SE1 and the second electrode SE2 relative to the display panel decreases, the sensing sensitivity of the active input device can be improved.

[0180] Reference Figure 9B Each of the unit light-emitting regions PUA includes a first light-emitting region PXA-R, a second light-emitting region PXA-B, and a third light-emitting region PXA-G. Although a unit light-emitting region PUA in which the third light-emitting region PXA-G is disposed between the first light-emitting region PXA-R and the second light-emitting region PXA-B is shown, the arrangement of the light-emitting regions can be varied. Each of the first light-emitting region PXA-R, the second light-emitting region PXA-B, and the third light-emitting region PXA-G may have a shape extending in a first intersecting direction CDR1. The first light-emitting region PXA-R, the second light-emitting region PXA-B, and the third light-emitting region PXA-G may have the same or substantially the same surface area. However, this disclosure is not limited thereto.

[0181] Reference Figure 9C Each of the unit light-emitting areas PUA includes a first light-emitting area PXA-R, a second light-emitting area PXA-B, and a third light-emitting area PXA-G. The second light-emitting area PXA-B has the largest surface area. The first light-emitting area PXA-R and the third light-emitting area PXA-G can be located on one side or on one side of the second light-emitting area PXA-B. The first light-emitting area PXA-R and the third light-emitting area PXA-G can have the same or substantially the same surface area.

[0182] Figure 10 and Figure 11These are all enlarged plan views of the unit sensing area UA according to embodiments of the present invention. In the following text, references to Figures 1 to 12 will not be repeated. Figure 9C The component being described is the same as the component being described.

[0183] Reference Figure 10 The second electrode SE2 comprises two portions SE2-P1 and SE2-P2, which are separated relative to the first current path 1000 and are respectively disposed above and below the first current path 1000. An embodiment in which one of the first bridging patterns BRP1 is configured to connect (e.g., electrically connect) the first portion SE2-P1 and the second portion SE2-P2 of the second electrode SE2 is illustrated by way of example. It can be seen that the first current path 1000 has a... Figure 8C The path of the first current path 1000 shown is different from the path of the first bridging pattern BRP1. This is because the position of the first bridging pattern BRP1 is different. Figure 8C The position of the bridging pattern BRP.

[0184] The first electrode SE1 may also include multiple parts. A first electrode SE1 comprising two parts SE1-P1 and SE1-P2 is shown. An embodiment in which a second bridging pattern BRP2 is configured to connect (e.g., electrically connect) the first part SE1-P1 and the second part SE1-P2 of the first electrode SE1 is shown by way of example. Figure 10 Two second current paths 2000-1 and 2000-2 are shown. Both second current paths 2000-1 and 2000-2 pass through the first bridging pattern BRP1. The second portion SE1-P2 of the first electrode SE1 is disposed inside the two second current paths 2000-1 and 2000-2.

[0185] In the unit sensing region UA, refer to Figure 11 The first electrode SE1 includes a plurality of center patterns CP, a plurality of first patterns P1, a plurality of second patterns P2, and a plurality of third patterns P3. In the cross region ECA, the line elements LE1 and LE2 of the second electrode SE2 are disposed in at least some regions between two adjacent patterns among the plurality of center patterns CP, the plurality of first patterns P1, the plurality of second patterns P2, and the plurality of third patterns P3.

[0186] A unit sensing region UA ​​is illustrated by way of example, in which a first current path 1000 and a second current path 2000 intersect each other. The first electrode SE1 may include two portions SE1-P1 and SE1-P2 separated relative to the second current path 2000. In the illustrated embodiment, three bridging patterns BRPs are shown as an example connecting the first portion SE1-P1 and the second portion SE1-P2 of the first electrode SE1. However, this disclosure is not limited thereto, and the unit sensing region UA ​​is illustrated by way of example in which the first current path 1000 passes through the leftmost bridging pattern BRP of the three bridging patterns BRPs.

[0187] As described above, the gap between the first and second electrodes is narrowed, and the length of the portion of the first electrode facing the second electrode is increased, thereby increasing the capacitance between the first and second electrodes. Furthermore, the change in capacitance before and after input through the passive input device is also increased. This can improve the sensing sensitivity of the passive input device.

[0188] The load capacitance (or base capacitance) between the display panel and the first and second electrodes can be reduced by increasing the surface area of ​​the openings of the first and second electrodes. As the load capacitance between the display panel and the first and second electrodes decreases, the sensing sensitivity of active input devices can be improved.

[0189] Manufacturing defects can be reduced by decreasing the number of bridging patterns in the intersection area of ​​the first and second electrodes.

[0190] Although embodiments of the inventive concept have been described herein, it is understood that various changes and modifications can be made by those skilled in the art within the spirit and scope of the inventive concept as defined by the claims or their equivalents. Therefore, the embodiments described herein are not intended to limit the technical spirit and scope of this disclosure, and the entire technical spirit within the scope of the claims or their equivalents shall be construed as being included within the scope of this disclosure and its equivalents.

Claims

1. A display device, the display device comprising: Display panel; as well as An input sensor, located on the display panel, includes a first electrode extending in a first direction, a second electrode extending in a second direction intersecting the first direction, and a bridging pattern at the intersection of the first and second electrodes. Wherein, one of the first electrode and the second electrode includes: Multiple central patterns are arranged along the second direction, and each has a first opening; Multiple first patterns are located on one side of the multiple central patterns in the first direction, arranged along the second direction, and each has a second opening; A plurality of second patterns, located on the opposite side of the plurality of central patterns in the first direction, are arranged along the second direction and each has a third opening; and Multiple third patterns are configured to electrically connect two adjacent patterns among the multiple central patterns, the multiple first patterns, and the multiple second patterns, and The other of the first and second electrodes includes multiple line elements located between two adjacent patterns among the plurality of center patterns, the plurality of first patterns, and the plurality of second patterns.

2. The display device according to claim 1, wherein, The width of the first electrode in the second direction is uniform, and the width of the second electrode in the first direction is uniform.

3. The display device according to claim 1, wherein, The plurality of center patterns include a first group of center patterns having the same shape and a second group of center patterns having a shape different from that of each center pattern in the first group.

4. The display device according to claim 3, wherein, The central patterns of the first group are all rhomboid in shape.

5. The display device according to claim 1, wherein, The plurality of first patterns includes a first group of first patterns having the same shape and a second group of first patterns having a shape different from the shape of each of the first patterns in the first group.

6. The display device according to claim 5, wherein, The first patterns in the first group all have a rectangular shape.

7. The display device according to claim 5, wherein, The plurality of second patterns includes a first group of second patterns having the same shape and a second group of second patterns having shapes different from those of the first group of second patterns. In this configuration, each first pattern in the first group extends in a direction intersecting the first direction and the second direction, and the first pattern in the first group and the second pattern in the first group extend in directions intersecting each other.

8. The display device according to claim 1, wherein, The plurality of first patterns and the plurality of second patterns are symmetrical with respect to the plurality of central patterns.

9. The display device according to claim 1, wherein, The plurality of first patterns form a plurality of first pattern rows arranged along the first direction, and The plurality of second patterns form a plurality of second pattern rows arranged along the first direction.

10. The display device according to claim 1, wherein, The bridging pattern includes a first bridging pattern. The second electrode comprises a first part and a second part that are separate from each other. Wherein, the first bridging pattern electrically connects the first portion and the second portion, and The plurality of central patterns, the plurality of first patterns, the plurality of second patterns, and the plurality of third patterns form the first part and the second part.

11. The display device according to claim 10, wherein, The first bridging pattern is located in the current path of the second electrode.

12. The display device according to claim 1, wherein, The bridging pattern includes a second bridging pattern. The first electrode comprises a first part and a second part that are separate from each other, and The second bridging pattern electrically connects the first portion and the second portion.

13. The display device according to claim 1, wherein, The input sensor also includes an insulating layer. The bridging pattern is located below the insulating layer, and The first electrode and the second electrode are located above the insulating layer.

14. The display device according to claim 1, wherein, The plurality of wire elements includes a plurality of first wire elements extending in a first crossing direction and a plurality of second wire elements extending in a second crossing direction. Wherein, the first opening region through which the corresponding third pattern of the plurality of third patterns passes is defined in the first line element of the plurality of first line elements, and Wherein, the second opening region through which the corresponding third pattern of the plurality of third patterns passes is defined in the second line element of the plurality of second line elements.

15. The display device according to claim 1, wherein, The plurality of wire elements includes a plurality of first wire elements extending in a first crossing direction and a plurality of second wire elements extending in a second crossing direction, and A portion of the plurality of first wire elements and a portion of the plurality of second wire elements have an integral shape in the intersection region of the first electrode and the second electrode.

16. The display device according to claim 1, wherein, The display panel includes multiple light-emitting areas and non-light-emitting areas adjacent to the multiple light-emitting areas, and The plurality of central patterns, the plurality of first patterns, the plurality of second patterns, and the plurality of line elements are superimposed on the non-light-emitting area.

17. The display device according to claim 16, wherein, The multiple light-emitting regions form multiple unit light-emitting regions. Each of the plurality of unit light-emitting regions includes a first light-emitting region for generating light of a first color, a second light-emitting region for generating light of a second color, a third light-emitting region for generating light of a third color, and a fourth light-emitting region for generating light of the third color. Among them, the corresponding unit light-emitting region among the plurality of unit light-emitting regions is located inside the first opening.

18. The display device according to claim 1, wherein, The area of ​​each of the second and third openings is larger than the area of ​​the first opening.

19. The display device according to claim 1, further comprising: The input device is configured to provide a drive signal to the input sensor. The input sensor is configured to sense user input in a first mode by means of a change in capacitance between the first electrode and the second electrode, and to sense input to the input device based on the drive signal in a second mode.

20. A display device, the display device comprising: The display panel is configured to display images; as well as An input sensor is located on the display panel and includes a sensing area having multiple unit sensing areas arranged in a matrix along a first and a second direction that intersect each other. In each of the plurality of unit sensing regions, the input sensor includes: Multiple central patterns are arranged along the second direction, and each has a first opening; Multiple first patterns are located on one side of the multiple central patterns in the first direction, arranged along the second direction, and each has a second opening; Multiple second patterns are located on the opposite side of the multiple central patterns in the first direction, arranged along the second direction, and each has a third opening; A plurality of third patterns are configured to electrically connect two adjacent patterns among the plurality of central patterns, the plurality of first patterns, and the plurality of second patterns; Multiple line elements are located between two adjacent patterns among the multiple center patterns, the multiple first patterns, and the multiple second patterns; and A bridging pattern is configured to connect at least one of a first opening region in a line element defined among the plurality of line elements and a second opening region in a third pattern defined among the plurality of third patterns.

21. The display device according to claim 20, further comprising: Multiple fourth patterns are located at the boundary of two adjacent unit sensing regions in the first direction among the multiple unit sensing regions, and each has a fourth opening.

22. The display device according to claim 21, wherein, Each of the plurality of fourth patterns is symmetrical with respect to the second direction.

23. The display device according to claim 20, wherein, The plurality of central patterns, the plurality of first patterns, the plurality of second patterns, and the plurality of third patterns are electrically connected to form a current path in one of the first and second directions. The plurality of wire elements are electrically connected to form a current path in another direction, either the first or the second direction. The plurality of line elements are electrically insulated from the plurality of center patterns.

24. A display device, the display device comprising: The display panel is configured to display images; as well as An input sensor, located on the display panel, includes a sensing area having multiple unit sensing areas arranged in a matrix along a first and a second direction that intersect each other. In each of the plurality of unit sensing regions, the input sensor includes: Multiple central patterns are arranged along the second direction, and each has a first opening; Multiple first patterns are located on one side of the multiple central patterns in the first direction, arranged along the second direction, and each has a second opening; Multiple second patterns are located on the opposite side of the multiple central patterns in the first direction, arranged along the second direction, and each has a third opening; A plurality of third patterns are configured to electrically connect two adjacent patterns among the plurality of central patterns, the plurality of first patterns, and the plurality of second patterns; Multiple line elements are located between two adjacent patterns among the multiple center patterns, the multiple first patterns, and the multiple second patterns; and A bridging pattern is configured to connect two adjacent first patterns among the plurality of first patterns or two adjacent second patterns among the plurality of second patterns.

Images