Analog-to-digital conversion circuit with improved linearity

Abstract

The present disclosure relates to analog-to-digital conversion circuits with improved linearity. An example analog-to-digital converter (ADC) and a method that can be performed by the ADC are disclosed herein. The ADC can derive a first code that approximates a combination of an analog input value of the ADC and a jitter value of the ADC sampled on a capacitor array. The ADC can further derive a second code that represents a residual of the combination relative to the first code applied to the capacitor array. The ADC can combine the value of the first code and the value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the value of the first code and the value of the second code in the digital domain can provide greater analog-to-digital (A / D) conversion linearity.

Description

Technical Field

[0001] The present disclosure relates generally to the field of analog-to-digital converters and, more particularly, but not exclusively, to precision analog-to-digital conversion circuits. Background Art

[0002] Analog signals and / or values ​​may be generated in various circuit components, such as signal generators, sensors, and antennas. However, there may be many situations where having digital signals or values ​​may be beneficial, such as for processing or storing signals or values. In order to take advantage of the advantages of having digital signals or values ​​when generating analog signals or values, analog-to-digital conversion circuits (ADCs) have been developed to convert analog signals or values ​​into digital signals or values.

[0003] A signal may be a sequence of values ​​based on time. A digital value may be represented by a code. The name of a code such as CODE1 may refer to a digital (number) value represented by the code. Some (but not all) digital values ​​may be represented by a code using a common binary weighted encoding. The resolution of a digital value or code represented by a plurality of bits (which may be an abbreviation of "numerical resolution") may refer to binary weighted encoding, regardless of the way in which it is physically encoded. Physical resolution may refer to the number of physical bits used to physically encode a digital value. For example, the digital value of the example code CODE1 may be encoded in 8 bits using thermometer encoding. The physical resolution of the example CODE1 may be 8 bits. The weight of each bit in the 8 bits may be 1 / 8, and a set of possible numerical values ​​that CODE1 may represent may be 0 / 8, 1 / 8, 2 / 8, 3 / 8, 4 / 8, 5 / 8, 6 / 8, 7 / 8, 8 / 8. The 9 possible numerical values ​​are evenly spaced, and the (numerical) resolution of CODE1 may be represented as log2(9)≈3.17 bits. In some cases, the resolution may be rounded to the nearest integer bit without loss of clarity. For example, the resolution of the example CODE1 may be "approximately 3 bits" or simply "3 bits".

[0004] In many electronic applications, analog input values ​​are converted to digital output values ​​(e.g., for further digital processing or storage). For example, in precision measurement systems, electronic devices are equipped with one or more sensors to perform measurements, and these sensors can generate analog values. The analog values ​​can be provided as input to an ADC to generate digital output values ​​for further processing or storage.

[0005] ADCs can be found in many places such as broadband communication systems, automatic test equipment, audio systems, vehicles, factory automation systems, etc. ADCs can convert analog electrical values ​​that represent real-world phenomena such as light, sound, temperature, flow, or pressure. Designing ADCs is a very important task because each application may have different requirements in terms of speed, performance, power consumption, cost, and size. As the number of applications that require ADCs grows, the need for accurate and reliable conversion performance also grows.

[0006] Some applications may require precise and accurate conversion of analog values, thus requiring a precision ADC (precision means accurate and / or accurate). Specifications required for a precision ADC may include small (ideally zero) nonlinearity errors. Nonlinearity error (sometimes referred to as integral nonlinearity or INL error) may characterize ADC deviation within a predetermined range that results from providing a linear relationship between an analog input value (VIN) and a digital output value (DOUT). The linear relationship may be DOUT = VIN / VSCALE + OFFSET, where VSCALE may be an analog scaling amount (e.g., VSCALE may be a nominal reference voltage), and OFFSET may be a constant. Capacitance ratio mismatches of capacitors in a capacitive digital-to-analog converter (CDAC) may significantly contribute to nonlinearity errors.

[0007] U.S. Patent Nos. 8,810,443, 9,054,727, 9,231,611, and 9,331,709 to Steensgaard-Madsen teach in part how to make a SAR ADC (successive approximation register ADC) substantially linear despite possible mismatches in the CDAC capacitance ratios. Steensgaard-Madsen writes (U.S. Patent No. 8,810,443; col. 21; lines 62-65) that the teachings may be combined with the teachings of U.S. Patent No. 8,232,905 (replacement publication US2011 / 0115661A1), also to Steensgaard-Madsen. One of ordinary skill in the art may envision a combination of U.S. Patent Nos. 8,232,905 (the '905 patent) and 8,810,443 (the '443 patent) to increase the maximum conversion rate and / or improve the power efficiency of the ADC. For example, one of ordinary skill in the art may envision a combination of features of a conventional sequentially configured analog-to-digital converter with a conventional analog-to-digital converter system, the combination having a sampling digital-to-analog converter to sample a combination of analog signal values ​​and analog dithering, and having a mismatch shaping encoder to increase the maximum conversion rate of the ADC and / or improve power efficiency. However, in such a combination, analog imperfections such as nonlinearity and / or deviations in the gain factor of a multi-bit quantizer (e.g., 214 in FIG. 4 of the `905 patent) may result in deviations from desired properties, including deviations from a set of desired statistical characteristics, described in the paragraph beginning at column 12, line 37 in the `443 patent with respect to FIG. 5. Therefore, the approximate assumptions described in column 13, lines 10-15 of the `443 patent may become too coarse, and the degree of nonlinearity due to the mismatch in the CDAC capacitance ratio may exceed the level required for the application. As described in US Pat. Nos. 8,232,905, 8,810,443, 9,054,727, 9,231,611, and 9,331,709, the use of overrange (also called redundancy) may also result in some deviation from the desired statistical characteristics and may lead to nonlinear errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure may be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, various features are not drawn to scale and are used for illustration purposes only. Where a scale is shown, either explicitly or implicitly, it is provided only as an illustrative example. In other embodiments, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 An example ADC according to various embodiments is shown.

[0010] Figure 2 It shows the various embodiments Figure 1 Example timing of ADC 100 in FIG.

[0011] Figure 3 shows a diagram similar to the diagram according to various embodiments Figure 1 An example fully differential implementation of the ADC of an ADC. Summary of the invention

[0012] An example analog-to-digital converter (ADC) and a method that can be performed by the ADC are disclosed herein. The ADC can derive a first code that approximates a combination of an analog input value of the ADC and a dither value of the ADC. The ADC can further derive a second code to represent a residual amount relative to the combination of the first code. The ADC can combine the value of the first code and the value of the second code to produce a combined code to be applied to a capacitor array. Combining the value of the first code and the value of the second code in the digital domain can provide greater linearity within the ADC.

[0013] A method for providing a digital output code to represent an analog input value is disclosed herein. The method may include the following steps: sampling a combination of the analog input value and a dither value at a node of a capacitor array, deriving a first code that approximates the combination of the analog input value and the dither value, and applying a first segment of the first code to the first segment of the capacitor array, and applying a second segment of the first code to the second segment of the capacitor array. The method may further include the following steps: deriving a second code to represent a first residual of the combination of the analog input value and the dither value, the first residual being related to the first code applied to the capacitor array, combining a numerical value of the first code and a numerical value of the second code to derive a combined code, and applying the first segment of the combined code to the first segment of the capacitor array, and applying the second segment of the combined code to the second segment of the capacitor array, wherein the first segment of the combined code and the second segment of the combined code are responsive to the second code. The method may further comprise the steps of deriving a third code to represent a second residual of the combination of the analog input value and the dither value, the second residual being related to the combined code applied to the capacitor array, and combining the third code with the combined code and the dither code representing the dither value to provide the digital output code.

[0014] An analog-to-digital converter (ADC) is disclosed herein. The ADC may include a capacitor array including a plurality of capacitors, and a control circuit coupled to the capacitor array. The control circuit may determine a first code based on an analog input value and a dither value of the ADC, the first code approximating a combination of the analog input value and the dither value, and determine a second code based on a residual of the combination of the analog input value and the dither value, the residual being related to the first code, and the second code representing the residual. The control circuit may further combine a numerical value of the first code and a numerical value of the second code to generate a combined code, and determine a digital output code based at least in part on the combined code and the dither code, the dither code representing the dither value. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific examples of parts and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. In addition, the present disclosure may repeat reference numerals and / or letters in various examples, or sometimes in different drawings. This repetition is for the purpose of simplicity and clarity, and does not itself specify the specific relationship between the various embodiments and / or configurations discussed. Different embodiments may have different advantages, and any embodiment does not require a specific advantage.

[0016] Figure 1 An example ADC 100 is shown in accordance with various embodiments. Several elements of ADC 100 may have similarities to those of Patent No. '443. Figure 2 200. For example, in Figure 1 In the ADC 100 of the '443 patent, the CDAC capacitor array 102 of the ADC 100 may include a first segment 102-1, which may include N1 nominally equal-sized (also referred to as unit-sized) capacitors. The N1 nominally equal-sized capacitors within the first segment 102-1 may include a plurality of capacitors, wherein the plurality of capacitors are nominally equal-sized (in other words, exhibit nominally equal capacitance). In the ADC 200 of the '443 patent, the first segment 201-1 (the '443 patent) Figure 2) may include N1=4 equal-sized capacitors each of nominal size C / 4. The CDAC capacitor array 102 may further include a second segment 102-2, which may include N2 nominally binary-weighted capacitors. The combined nominal capacitance of all capacitors in the second segment 102-2 may be substantially equal to the nominal capacitance of a unit-sized capacitor in the first segment 102-1. For example, the N2 nominally binary-weighted capacitors in the second segment 102-2 may include a plurality of capacitors, wherein the combined nominal capacitance of the capacitors within the second segment 102-2 may be substantially equal to the nominal capacitance of a single capacitor within the first segment 102-1. In the ADC 200 in the `443 patent, the second segment 201-2 may include N2=6 binary-weighted capacitors. The combined nominal capacitance of the second segment 201-2 in the `443 patent may be 63C / 256, which may converge to the nominal capacitance of the unit-sized capacitor C / 4 for expected larger N2 values. CDAC capacitor array 102 may further include a third segment 102-3. Third segment 102-3 of CDAC capacitor array 102 in ADC 100 may not be equivalent to any portion of ADC 200 in the '443 patent, but may be similar to capacitor 215, capacitor 216, and / or capacitor 217 of ADC 200 in FIG. 4 of the '905 patent. Each of first segment 102-1, second segment 102-2, and third segment 102-3 may have a first connection for coupling each capacitor in each segment to common node 104, and a second connection for coupling each capacitor in each segment to a corresponding plurality of switches for each capacitor in each segment. Figure 1 ADC 100 and Patent No. '443 Figure 2 ADC 200 of the present invention may include a circuit (circuit 107 of ADC 100 herein and circuit 207 of ADC 200 in Patent No. '443) for providing a plurality of reference potentials (such as VL=0 volts (V) and VH=5V), which may be referred to as a reference circuit. Figure 1In the ADC 100 of '443, the input voltage VIN(t) may be applied to one, more, or all capacitors in the first segment 102-1 during an acquisition phase, which may end at a sampling instant when the sampling switch 108 opens (becomes non-conductive) in response to a transition of the control signal CNV that may be applied as an input to the ADC 100. For example, the switch 110-1, which may be coupled to the connection of the capacitors within the first segment 102-1, may cause the input voltage VIN(t) of the ADC 100 to be applied to one or more capacitors within the first segment 102-1 during the acquisition phase. In the '443 patent, VIN(t) may be applied to all capacitors in the first segment 201-1, and the sampling switch 208 may be opened at the sampling instant in response to a transition of the control signal CNV. In addition, in the ADC 100, the N2-bit digital dither value DX may be applied to the second segment 102-2 via the multiplexer circuit 106-3. In Patent No. '443, the 6-bit (N2=6) jitter value DX (Patent No. '443) Figure 3 bits x5, x6, x7, x8, x9, x10) in the multiplexer circuit 206-3 (patent No. '443) Figure 3 ) and switch driver 206-5 (Patent No. '443 Figure 3 ) is applied to the second section 201-2 (Patent No. '443 Figure 2 ). Figure 1 Any switch drivers within the ADC 100 are not explicitly shown, but a person of ordinary skill in the art (PHOSITA) will understand that switch drivers may be implicitly included. PHOSITA will further recognize that the CDAC circuit may be implemented in a variety of ways, and that the inputs of the CDAC circuit may be characterized by equivalent capacitance or weights of the inputs (some examples described in the '443 patent and the '905 patent), which may not be equal to the physical capacitance. For example, it is well known that one or more coupling capacitors may be configured internally in the CDAC to effectively reduce the weight of its input terminals connected to the physical capacitors, which may be greater than what may otherwise be suggested.

[0017] In the ADC 200 of the '443 patent, the code M (the '443 patent) Figure 3 bits m1, m2, ..., m10) in the CDAC capacitor array 201 during a conversion operation (see Patent No. '443). Figure 2 During the conversion operation, the code M may be updated in multiple conversion steps including successive approximation. The first segment M1 of the code M (bits m1, m2, m3, m4) may be updated via the scrambler circuit 206-6 (patent No. '443). Figure 3) is provided, the scrambler circuit processing is provided by the control circuit 206-1 (Patent No. '443 Figure 3 ) provides code B1 (bits b1, b2, b3, b4). The second segment M2 of code M (bits m5, m6, ..., m10) can be transmitted via multiplexer circuit 206-3 (patent No. '443) Figure 3 ) is provided, the multiplexer circuit is from the control circuit 206-1 (Patent No. '443 Figure 3 ) receives the same code B2 (bits b5, b6, ..., b10). The first and second segments of code M can be applied to the first and second segments of CDAC capacitor array 201 (patent No. '443). Figure 2 The switch driver and the switch may be configured to selectively supply power to the CDAC capacitor array 201 (patent number '443) according to the corresponding bit of the code M. Figure 2 ) applies a reference potential (VH or VL) to each capacitor in the circuit. Figure 1The ADC 100 of the '443 patent can be configured to provide similar basic operations associated with the code M of the ADC 200 of the '443 patent. The control circuit 101 can provide a digital code B, which includes a first segment B1 and a second segment B2. The digital code B can include multiple bits, wherein the first segment B1 can include a first portion of the digital code B, and the second segment B2 can include a second portion of the digital code B. The code can represent a numerical value B=B1+B2. The first segment B1 of the digital code B can be processed by a scrambler circuit 106-6, which provides a code M1 having N1 physical bits to control switches to selectively apply a reference potential (VH or VL) to each of the N1 unit-sized capacitors in the first CDAC segment 102-1. For example, a first segment B1 of the digital code B may be applied to the scrambler circuit 106-6, and the output M1 of the scrambler circuit 106-6 may cause the switch 110-1 to couple each capacitor of the first segment 102-1 to the reference potential VH or the reference potential VL based on the code M1 derived from the first segment B1. A second segment B2 of the digital code B may be transmitted via the multiplexer circuit 106-3, which provides the code M2 ​​to the control switch 110-2 to selectively apply the reference potential (VH or VL) to each of the N2 nominally binary-weighted capacitors 102-2. For example, the second segment B2 of the digital code B may be applied to the multiplexer circuit 106-3, and each individual bit at the output of the multiplexer 106-3 may cause the switch 110-2 to couple each individual capacitor in the second segment 102-2 to the reference potential VH or the reference potential VL based on each individual bit of the second segment B2 (collectively representing the value B2). The physical resolution of the first segment B1 may be (but need not be) N1 bits, and the first segment B1 may be (but need not be) a thermometer type code. For example, the first CDAC segment 102-1 may include 32 capacitors, each of which has a nominal size of C / 32 (a nominal unit size capacitor may be 1 picofarad (pF), in other words, C=32pF). The value of B1 may be one of 33 possible values ​​(e.g., 0 / 32, 1 / 32, 2 / 32, 3 / 32, ..., 32 / 32), and the scrambler circuit 106-6 may output a code M1 encoded as 32 bits, with each bit having a weight of 1 / 32. The code M1 may be an equally weighted code. The value of the code M1 may be equal to the value of the code B1. The scrambler circuit 106-6 may be a tree type mismatch shaping encoder that receives code B1 encoded as 6 bits with 6 corresponding weights: 16 / 32, 8 / 32, 4 / 32, 2 / 32, 1 / 32 and 1 / 32. A tree type mismatch shaping encoder is described in U.S. Patent No. 5,684,482, which is incorporated herein by reference.For example, a tree-type mismatch shaping encoder may include one or more switching blocks, wherein the switching blocks may be separated into multiple layers, and the switching blocks within a single layer are coupled to the switching blocks in adjacent layers. The switching block may receive an input signal and may divide the signal into one or more n-bit output signals, where n is the number of bits, and the output signal is output by the switching block. The number of output signals and the number of bits in each output signal are different between the layers of the switching block. The tree-type mismatch shaping encoder may have an input applied to the first layer of the switching block, and may be propagated through the layers of the switching blocks divided at each layer to the final layer that produces the output of the tree-type mismatch shaping encoder. One or more number conservation rules may define the output of the switching block based on the input of the switching block. The resolution of code B1 and code M1 may be log2(33)≈5.05≈5 bits. In another embodiment, the scrambler circuit 106-6 may be implemented because the scrambler circuit 116 (FIG. 23 of U.S. Patent No. 6,348,884) is implemented as described in U.S. Patent No. 6,348,884, which is also incorporated herein by reference. In another embodiment, code B1 can be encoded as 32 bits using thermometer type encoding. Many variants of mismatch shaping encoders (also referred to as dynamic element matching-or DEM-encoders and / or scrambler circuits) are known to PHOSITA. Examples include switching encoders, rotary encoders, dual rotary encoders, tree encoders, counting and sorting encoders, etc. Mismatch shaping encoders can be configured to provide zero-order encoding (e.g., randomizing errors caused by mismatches), first-order encoding (e.g., suppressing errors caused by mismatches by first-order filtering), and even high-order encoding. Various types of encoders can respond to optional random, pseudo-random or basic random inputs (one or more bits, each bit can simulate a coin-tossing random event), which can be used to basically suppress element selection patterns that may cause idle tones.

[0018] A combination of an input voltage VIN(t) and an analog jitter value may be sampled on the CDAC capacitor array 102 of the ADC 100. In particular, the '443 patent is incorporated herein by reference to describe in part how a combination of an input voltage VIN(t) and an analog jitter value may be sampled on the CDAC capacitor array 102 of the ADC 100. For example, an analog input voltage VIN(t) may be applied to the capacitors of the first segment 102-1, and a substantially random analog jitter value may be applied to the capacitors of the second segment 102-2 via code DX, wherein the analog input voltage VIN(t) and the substantially random analog jitter value form a sampled value representing the combination. Thus, the CDAC 102 may sample a combination of an analog input voltage VIN(t) and an analog jitter value. The operation / configuration of the third CDAC segment 102-3 may be predefined and fixed for all conversion cycles. For example, during the acquisition phase, the capacitors 102-3 may be connected in a predefined configuration (e.g., all capacitors may be connected to VL). Whether to consider the third segment 102-3 as part of the CDAC structure may be a matter of personal preference. The third segment 102-3 may not be used for any portion of the digital-to-analog (D / A) conversion code B, code DX, or any other value or code that may change from one conversion cycle to the next.

[0019] Compared to Patent No. '443 Figure 2 The control circuit 206 of the embodiment of the present invention can derive the digital output code DOUT with relatively few successive approximation steps. For example, compared with the traditional control circuit implemented in the traditional successive approximation register (SAR) ADC, the control circuit 101 can derive the digital output code DOUT in relatively few successive approximation steps. Specifically, the control circuit 101 can be configured to derive the high-resolution code DOUT (for example, the resolution can be 16 bits or more) in only 3 conversion steps, and the code B can be derived in only 2 conversion steps. The conversion step can be a step of successive approximation, which can resolve one or more bits. The term "successive approximation" can be used in this article to characterize a circuit and / or method that can resolve one or more bits at each step of the conversion operation. For example, the successive approximation conversion method can be implemented by the ADC 200 described in Patent No. '905 (Figure 4).

[0020] In the `905 patent, ADC 200 (FIG. 4 of the `905 patent) can derive the conversion result d(k) as a weighted sum of three codes, for example, d(k)=d1(k)+d2(k) / 4+d3(k) / 16, see columns 7 and 8 of the `905 patent. FIG. 4 and FIG. 5 of the `905 patent show that the three codes can be derived sequentially by the quantizer 214 (FIG. 4 of the `905 patent), and they can be applied to the CDAC circuit continuously via different sections of the CDAC circuit. The residual at a given conversion step (such as a step where only d1(k) is known) can be amplified by an amplifier 218 (FIG. 4 of the `905 patent), which is configured with negative feedback to derive the next code, such as d2(k). The weighting factors may be included in the numerical values ​​of each code, and the conversion result may be represented as d(k)=CODE1+CODE2+CODE3, where CODE1 may be d1(k), CODE2 may be d2(k) / 4, and CODE3 may be d3(k) / 16. Column 7 of Patent No. '905 describes the benefits of using redundancy (also known as overlap or overrange) to provide robustness metrics for several analog defects. In one example, CODE1, CODE2, and CODE3 may be 3-bit binary weighted codes with a position offset of 2 bits (in other words, a relative scaling factor of 4). Therefore, CODE1, CODE2, and CODE3 do not necessarily correspond to different groups of bits of the binary weighted representation of d(k)=CODE1+CODE2+CODE3. A conventional digital adder circuit that provides a carry from a bit position to the next bit position may be used to add CODE1, CODE2, and CODE3 to derive a binary weighted code representing the conversion result d(k). A nominally equivalent analog addition operation can be provided by applying the three codes to different segments of the CDAC structure (see FIG. 4 in the '905 patent). Figure 1The ADC 100 of the '905 patent may have several aspects in common with the ADC 200 of the '905 patent. The ADC 100 may derive a conversion result of a successive approximation conversion method as a weighted sum of multiple codes. For example, the ADC 100 may derive a conversion result as a weighted sum of CODE1, CODE2, and CODE3. The ADC 100 may combine CODE1 and CODE2 in a digital / digital manner before the combined value B=CODE1+CODE2 may be applied to the CDAC, which is different from the ADC 200 of the '905 patent. Compared to conventional ADCs (including the ADC 200 of the '905 patent), this may improve the linearity of the ADC 100 if the matching of the capacitors in the CDAC capacitor arrangement 102 is not perfect. In other words, compared to the linear robustness of the ADC 200 of the '905 patent relative to potential capacitor mismatch errors, it may improve the robustness of the ADC 100 linearity relative to potential capacitor mismatch errors. ADC 100 may derive codes (especially CODE1, CODE2, and CODE3) sequentially via a quantizer circuit (such as quantizer circuit ADC 114-1 or quantizer circuit ADC2 114-2), and may apply several combinations of codes (such as CODE1 and CODE1+CODE2) to CDAC capacitor array 102 successively. The residual at the conversion step may be amplified by an amplifier circuit with negative feedback (such as amplifier circuit 118) for deriving the next code. A weighting factor may be included in the numerical value of each code, and the conversion result may be represented as DOUT=CODE1+CODE2+CODE3. In an example, CODE1, CODE2, and CODE3 may be 6-bit binary weighted codes with a position shift of 5 bits (in other words, a relative scaling factor of 32), and the resolution of DOUT may be 16 bits. Therefore, ADC 100 may include redundancy, and CODE1, CODE2, and CODE3 do not need to correspond to different bit groups of the binary weighted representation of DOUT=CODE1+CODE2+CODE3. In an example, the most significant bit (MSB) of CODE2 may overlap with the least significant bit (LSB) of CODE1 corresponding to system-level redundancy. However, after the digital addition operation B=CODE1+CODE2, the MSB of the second segment B2 may not overlap with the LSB of the first segment B1, where B=B1+B2=CODE1+CODE2. Improved linearity can be obtained by resolving the overlap between CODE1 and CODE2 in the digital domain (by numerically calculating CODE1+CODE2) rather than in the analog domain (by applying CODE1 to segment A of the CDAC and applying CODE2 to segment B of the CDAC (separate from segment A)).

[0021] Figure 2 Shows Figure 1 100. The combination of the input voltage VIN(n) and the analog jitter value derived from the jitter code DX(n) may be sampled at a sampling instant. The reference to the value or code may include an index of a conversion cycle as a first argument. For example, DX(n) may refer to the state or value of DX for the nth conversion cycle. Figure 2 DOUT(n) shown in the upper right corner can be expressed in Figure 2 The output code of the input voltage VIN(n) sampled at the sampling instant shown in the lower left corner. The delay from the sampling instant of VIN(n) to providing the corresponding digital value DOUT(n) can be the delay of ADC 100. The sampling instant can be after a sequence of 3 conversion steps, and 3 conversion codes are derived in sequence: CODE1(n), CODE2(n) and CODE3(n). These 3 conversion steps can be referred to as Step1, Step2 and Step3. The acquisition phase can be referred to as Step0. A reference to a value, code or step can include an index of the step as a second independent variable. For example, Step(n,3) can refer to Step3 of the nth conversion cycle. As another example, B2(n,2) can refer to the state or value of code B2 at Step(n,2), in other words the state or value of code B2 at Step2 of conversion cycle n.

[0022] A full conversion cycle of ADC 100 (including acquisition and digital processing) may be a sequence of five steps. Step 0 may be an acquisition phase or step. Step 1, Step 2, and Step 3 may be conversion steps or steps of a successive approximation method. Step 4 may be the last step of digital processing for deriving the result DOUT. Before describing each step in more detail, an overview of the five steps according to some embodiments will be provided.

[0023] Step 0: Collect and sample a combined value, where the combined value includes an analog input value VIN(n) and a jitter value.

[0024] Step 1: Export code CODE1 to represent the sampled combination value.

[0025] Step 2: Derive code CODE2 to represent the residual amount relative to the sampled combination value of CODE1.

[0026] Step 3: Derive code CODE3 to represent the residual amount relative to the sampled combined value of CODE1+CODE2.

[0027] Step 4: By combining the codes in Steps 0, 1, 2, and 3 with the optional mismatch information, derive the code DOUT(n) to represent the analog input value VIN(n).

[0028] Step 0 is described in detail in Patent No. '443. A summary / overview will be provided here (see Figure 1 and Figure 2 ). During the acquisition phase, the input voltage VIN(t) may be applied across one, several, or all N1 capacitors in the first segment of capacitors 102-1. The analog jitter value may be applied via the second segment of capacitor 102-2 by D / A conversion of the jitter code DX(n). The third segment of capacitor 102-3 may be configured to a predefined fixed “reset” state, which may be selected in part to provide a nominal offset (e.g., zero). Switch 108 may couple the connections of the first segment of capacitors 102-1, the connections of the second segment of capacitors 102-2, and the connections of the third segment of capacitors 102-3 to a predefined potential (such as ground) during the acquisition phase, wherein the connections coupled to the predefined potential are different from the connections to which the input voltage VIN(t), the analog jitter value, and the predefined fixed “reset” state are applied. When sampling switch 108 is opened at the sampling instant of VIN(n), a combination of the values ​​applied to CDAC capacitor array 102 (combined value) may be sampled and represented by a substantially isolated amount of charge on node 104. When the sampling switch 108 is opened at the sampling time, the charge portions of the first segment capacitor 102-1, the second segment capacitor 102-2, and the third segment capacitor 102-3 can be substantially isolated at the node 104. In preparation for Step 1, the nominally equivalent combined value can be sampled by the first quantizer circuit ADC1 114-1 at or about the sampling time. ADC1 114-1 can be configured to receive the input voltage VIN(t) and the dither code DX(n). In one embodiment, the dither code DX(n) provided to ADC1 114-1 can be truncated to obtain a coarser resolution than the dither code DX(n) provided to the CDAC capacitor array 102 via the multiplexer circuit 106-3.

[0029] Now consider Step 1 (deriving code CODE1 representing the sampled combined value). The quantizer circuit ADC1 114-1 can be any type of quantizer / ADC circuit that is configured to provide CODE1 to represent a sampled combined value that is nominally equivalent to the combined value sampled on the CDAC capacitor array 102 at the sampling time of VIN(n). The nominal value may be CODE1(n)=VIN(n) / VSCALE+DX(n)+OFFSET1, where VSCALE may be a scaling factor and OFFSET1 may be a constant. The resolution of CODE1 may be selected based on the degree of mismatch that can be expected between the combined value sampled by ADC1 114-1 and the combined value sampled by CDAC 102. In an example embodiment, the estimated worst-case mismatch error may be 1% of full scale, and the resolution of CODE1 may be selected to be 8 bits. At 8-bit resolution, ADC1 114-1 may be a flash quantizer, a two-step quantizer, a successive approximation register (SAR) ADC, a voltage controlled oscillator (VCO) based quantizer, a pipeline ADC, or any other type of quantizer deemed suitable for the application. Small circuit size, low power consumption, and fast operation may be desirable characteristics of ADC 114-1. In example embodiments where low power consumption may be targeted, ADC1 114-1 may be a SAR ADC that includes a CDAC capacitor array that is significantly smaller than CDAC capacitor array 102. For example, in these embodiments, the total capacitance of ADC1 114-1 implemented as a SAR ADC may be less than 10% of the total capacitance of CDAC capacitor array 102. For example, SAR ADC1 114-1 may include a CDAC capacitor array with a total capacitance of less than 1 pF. The right side of the first segment capacitor 102-1 may float during Step1 (in other words, all switches 110-1 may be open). The second and third segments of the CDAC capacitor array 102 may maintain their configuration during Step0. In another embodiment, ADC1 114-1 may be configured to sample VIN(t) and derive a code that is digitally combined with a dithered code DX(n) to provide CODE1. Thus, ADC1 114-1 need not (but may) include dithering in the analog quantity sampled by ADC1 114-1 to derive CODE1 to approximate the combined value sampled across the CDAC capacitor array 102.

[0030] Now consider Step 2 (deriving code CODE2 to represent the residual amount relative to the sampled combined value of CODE1). The amplifier circuit 118 may be configured with negative feedback provided by the third segment capacitor 102-3 via the switch 110-3. The gain factor GAIN2 (in other words, the amount of negative feedback) may be selected based in part on how well the combined value sampled on the CDAC capacitor array 102 can be expected (relied on) to approximate CODE1. The gain factor GAIN2 may be selected to provide redundancy with respect to the resolution and accuracy of CODE1. A relatively inaccurate value of CODE1 combined with a large gain factor GAIN2 may cause the amplifier 118 to saturate during Step 2. A relatively small gain factor GAIN2 may be selected to prevent saturation. In an example embodiment in which the resolution of CODE1 may be 8 bits, the gain factor may be GAIN2=64.

[0031] The control circuit 101 may be configured to receive CODE1 from ADC1 114-1 and apply it to the CDAC capacitor array 102 via a first segment B1 of code B and a second segment B2 of code B. The code may represent a numerical value of CODE1(n)=B(n,2)=B1(n,2)+B2(n,2). Therefore, the value corresponding to CODE1 may be applied to the CDAC capacitor array 102 via code segments B1 and B2 of B. In an example embodiment, the resolution of CODE1 may be less than or equal to the resolution of code segment B1. In this case, the assignment of CODE1 may be B1(n,2)=CODE1(n) and B2(n,2)=0. However, in another example embodiment, the 8-bit resolution of CODE1 may exceed the resolution of code segment B1. The first capacitor segment 102-1 may include N1=32 capacitors, and the code segment B1 may be encoded using 6 physical bits with 6 corresponding weights 16 / 32, 8 / 32, 4 / 32, 2 / 32, 1 / 32, and 1 / 32. The resolution of the code segment B1 may be (approximately) 5 bits. It may be advantageous to implement ADC1 114-1 to provide CODE1 in a format similar to that of code B. For example, ADC1 114-1 may be a SAR ADC including CDACs with nominal weights 16 / 32, 8 / 32, 4 / 32, 2 / 32, 1 / 32, 1 / 32, 1 / 64, 1 / 128, 1 / 256. CODE1 may be encoded by 9 physical bits, and the resolution of CODE1 may be (approximately) 8 bits. The first group of 6 physical bits of CODE1 with weights 16 / 32, 8 / 32, 4 / 32, 2 / 32, 1 / 32, 1 / 32 may be assigned to code B1(n,2). The second group of 3 physical bits of CODE1 with weights 1 / 64, 1 / 128, 1 / 256 may be assigned to code B2(n,2). Code B2 may be a binary weighted code with N2=15 physical bits having weights 1 / 64, 1 / 128, 1 / 256, 1 / 512, 1 / 1024, ..., 1 / 1048576. In an example embodiment, the control circuit 101 may not need to perform any non-trivial calculations to provide code segment B1 and code segment B2 to represent CODE1 in Step2. In another example embodiment, the control circuit 101 may be configured to derive code segment B1 and code segment B2 as non-trivial functions of CODE1. For example, B=B1+B2 may be linearly scaled relative to CODE1. The slope and / or offset of the linear scaling may be determined as part of a manufacturing process, for example as part of testing a semiconductor circuit.

[0032] The multiplexer circuit 106-3 can be configured to provide M2(n,2)=B2(n,2) to the second segment 102-2 of the CDAC. The scrambler circuit 106-6 can receive B1(n,2) and encode it into a representation M1(n,2) containing N1=32 physical bits. Each bit can have a weight of 1 / 32 and can retain the value of B1(n,2), in other words, M1(n,2)=B1(n,2). The code M1(n,2) can control the switch 110-1 to selectively apply the reference potential (VH or VL) to each capacitor in the first segment of the capacitor 102-1. The first code CODE1(n)=B1(n,2)+B2(n,2)=M1(n,2)+M2(n,2) can approximate the combination of the analog input value VIN(n) sampled at the node 104 of the capacitor array 102 in Step0 and the dither value. The first segment M1(n,2) of the first code may be applied to the first segment 102-1 of the capacitor array 102. The second segment M2(n,2) of the first code may be applied to the second segment 102-2 of the capacitor array 102.

[0033] During Step2, any capacitor in the third segment of capacitor 102-3 that is not configured to provide negative feedback to amplifier 118 may be configured to be in a predefined state (such as, connected to VL). The output of amplifier 118 may be substantially stable to a voltage that may be an amplified residual quantity relative to the sampled combined value of CODE1. The amplification factor may be a negative value (such as -64), but the polarity may be reasonably ignored in this description (e.g., GAIN2=absolute(-64)=64). The second quantizer circuit ADC2 114-2 may be configured to receive the amplified residual voltage and provide a code CODE2(n) representing the residual quantity. In an example embodiment, various parameters of ADC 100 (including, but not limited to, parameters of ADC2 114-2) may be selected so that the nominal value of CODE2(n) may be CODE2(n)=VIN(n) / VSCALE+DX(n)-CODE1(n)+OFFSET2, where VSCALE may be a scaling factor and OFFSET2 may be a constant. In some embodiments, CODE2(n) may further include a second scaling factor SCALE2, such that CODE2(n)=(VIN(n) / VSCALE+DX(n)-CODE1(n)) / SCALE2+OFFSET2, where SCALE2 may be responsive to the value of GAIN2 and the scaling factor of the second quantizer circuit 114-2. The gain factor GAIN2 may be included in the weighting factor for each physical bit representing CODE2(n) or canceled. The resolution of CODE2 may be selected based on the expected (dependent) accuracy of the amplifier circuit 118 including negative feedback and the quantizer circuit ADC2 114-2. ADC2114-2 may be a flash quantizer, a two-step quantizer, a SAR ADC, a VCO-based quantizer, a pipeline ADC, or any other type of quantizer deemed suitable for the application. Small circuit size, low power consumption, and fast operation may be desirable characteristics of ADC2 114-2. In an example embodiment, ADC2 114-2 may be a SAR ADC that includes a CDAC capacitor array that is significantly smaller than CDAC capacitor array 102. For example, SAR ADC2 114-2 may include a CDAC capacitor array with a total capacitance less than 1 pF, where CDAC capacitor array 102 may have a total capacitance greater than 1 pF (such as 40 pF). The resolution of CODE2 may be (approximately) 10 bits. CODE2 may be represented by more than 10 physical bits, and the bit weights may be based on characteristics of ADC2 that provide redundancy (e.g., nominal scaling of the CDAC capacitor array).For example, CODE2 can be represented by 12 physical bits having weights 1 / 128, 1 / 256, 1 / 512, 1 / 1024, 1 / 2048, 1 / 2048, 1 / 4096, 1 / 8192, 1 / 16384, 1 / 16384, 1 / 32768, 1 / 65536. The first quantizer ADC1 114-1 can be configured to provide an offset in CODE1(n) to set the desired average value of CODE2(n) and / or the desired average value of the amplified residual voltage. The average value of CODE2(n) can be close to the middle value of the range of possible values, such as approximately 1 / 128. The range of possible values ​​of CODE2 can be unipolar. In another example embodiment, the range of possible values ​​of CODE2 can be bipolar, and the nominal average value of CODE2(n) can be approximately 0.

[0034] If CODE1(n) has a desired set of characteristics, such as CODE1(n)≈VIN(n) / VSCALE+DX(n)+OFFSET1, then CODE2(n) may be the result of a substantially random process when DX(n) is derived from a substantially random process. For example, DX(n) may be provided by a circuit included in control circuit 101 that generates substantially random values. Specifically, if evaluated as a signal, CODE2(n) may be a substantially noise-like signal, and it may be substantially uncorrelated with VIN(n). However, if ADC1 114-1 is affected by analog imperfections (e.g., gain errors), CODE2(n) and VIN(n) may be somewhat correlated. The teachings of patent No. '443 (col. 12, lines 20-36) include that in some embodiments, to improve linearity, a goal may be to reduce the correlation of VIN(n) with any bit sequence that controls the capacitors in second capacitor segment 102-2 in Step(n,3). Thus, the goal may be to reduce (ideally avoid) the correlation of VIN(n) and M2(n,3), including the correlation of VIN(n) with any single physical bit of M2(n,3). The teachings of the '443 patent may also include the improvement goals described in column 14, lines 28-49. The linearity of ADC 100 may be improved by combining CODE1 and CODE2 in a digital / digital manner (in other words, in the digital domain) in Step 3, rather than by combining them in the analog domain (e.g., via different segments of the CDAC capacitor array, as shown in ADC 200 in FIG. 4 of the '905 patent).

[0035] CODE2(n) may be a second code representing a residual amount of a combination of an analog input value VIN(n) and a dither value sampled at node 104 of capacitor array 102 relative to a first code CODE1(n)=M1(n,2)+M2(n,2) applied to capacitor array 102 .

[0036] Now consider Step 3 (deriving code CODE3 to represent the residual amount relative to the sampled combined value of CODE1+CODE2). CODE1 and CODE2 can be digitally combined, and the combined value B=CODE1+CODE2 can be applied to the CDAC capacitor array 102 via the first segment B1 and the second segment B2 of B. For example, the control circuit 101 can digitally combine CODE1 and CODE2 to produce the combined value B, and apply the combined value B to the CDAC capacitor array 102 via the first segment B1 and the second segment B2 of the combined value B. The first segment B1 of B can be encoded by the scrambler circuit 106-6. The second segment B2 of B can have a range of possible values ​​that is substantially as wide as the minimum weighting factor of B1 (such as the least significant bit LSB). The second segment B2 of B may not need to provide redundancy, and this may be beneficial to the linearity of the ADC 100.

[0037] The control circuit 101 can be configured to calculate B(n,3)=CODE1(n)+CODE2(n). By selecting a set of bits from the binary weighted representation of B(n,3), a binary weighted representation of the second segment B2(n,3) of B(n,3) can be unambiguously derived. However, the value of B1(n,3)=B(n,3)-B2(n,3) can be encoded in a variety of ways because the physical format used to encode B1(n,3) can provide a certain degree of redundancy. The characteristics of the scrambler circuit 106-6 may determine whether a particular encoding type of B1 may be preferred in another embodiment. In one embodiment, if the scrambler circuit 106-6 is configured to derive a thermometer code from B1, all types of encodings of B1 may be equivalent, see, for example, U.S. Patent No. 6,348,884. Column 22 of Patent No. '443 describes several options for the scrambler circuit 106-6, including an option in which B1 can be arbitrarily encoded. The scrambler circuit 106-6 may include a rotary scrambler, a butterfly scrambler, a tree scrambler, or any other type of scrambler known to PHOSITA. In some embodiments, the scrambler circuit 106-6 may implement an encoding function, wherein the number of input terminals of the scrambler circuit 106-6 may be different from the number of output terminals of the scrambler circuit 106-6. The non-redundant (e.g., binary weighted) encoding of B2(n,3) may be advantageous for performing an approximation, such as described in Patent No. '443 (column 13, lines 10-15), which is better for all physical bits of M2(n,3). This may be advantageous for improving the linearity of the ADC 100. Figure 2 It is shown that the value of B1 can change from the value B1(n,2) in Step2 to another value B1(n,3) in Step3. Therefore, the code M1 provided by the scrambler circuit 106-6 can change from the value M1(n,2) in Step2 to another value M1(n,3) in Step3. In some conversion cycles, the code may not change from Step2 to Step3 (e.g., for some values ​​of n, B1(n,2)=B1(n,3)). In one embodiment, the range of possible values ​​of CODE2(n) can be unipolar, and / or the change in value B1(n,3)-B1(n,2) can correspond to at most one bit of the change in value of M1. This may be beneficial in reducing the switching of the CDAC capacitor 102-1 and the loading of the reference circuit 107.

[0038] The residual of the combined value sampled on the CDAC capacitor array 102 with respect to B(n,3) applied to the CDAC in Step3 may be relatively small and substantially independent of VIN(n). In an example embodiment, various parameters of the ADC 100 (including, but not limited to, parameters of ADC2 114-2) may be selected so that the nominal value of CODE3(n) representing the residual may be CODE3(n)=VIN(n) / VSCALE+DX(n)-B(n,3)+OFFSET3, where VSCALE may be a scaling factor and OFFSET3 may be a constant. The expression reflects that when B(n,3)=CODE1(n)+CODE2(n), the error contained in CODE1(n) (e.g., the mismatch of the value sampled by ADC1 114-1) may be compensated by CODE2(n).

[0039] CODE1(n)=M1(n,2)+M2(n,2) can be combined with CODE2(n) to derive a combined code B(n,3)=M1(n,3)+M2(n,3). The first segment of the combined code M1(n,3) can be applied to the first segment 102-1 of the capacitor array 102. The second segment of the combined code M2(n,3) can be applied to the second segment 102-2 of the capacitor array 102. Both segments M1(n,3) and M2(n,3) can respond to the second code CODE2(n).

[0040] The operation of the ADC 100 to derive CODE1(n) in Step 1 may be relatively unimportant compared to the operation during Step 2 and Step 3. The operation of the ADC 100 to derive CODE2(n) in Step 2 may substantially determine the characteristics of the residual represented by CODE3(n) in Step 3. The residual may be substantially independent of VIN(n), and the error contained in CODE3(n) may be relatively unimportant to the linearity of the ADC 100. The operation of the ADC 100 to derive CODE3(n) in Step 3 may affect the noise and offset specifications of the ADC 100.

[0041] In Step 3, amplifier circuit 118 may be configured with negative feedback provided by third segment capacitor 102-3. Gain factor GAIN3 may be selected based in part on the expected worst-case (maximum) magnitude of the residual represented by CODE3(n). In some embodiments, gain factor GAIN3 may have an absolute value of at least 250. In an example embodiment, the resolution of B(n,3)=CODE1(n)+CODE2(n) may be (approximately) 16 bits, and capacitor 102-3 may be configured for amplifier circuit 118 to provide gain factor GAIN3=2048.

[0042] The output of the amplifier circuit 118 can be substantially stable at a voltage that can be an amplified residual of the sampled combined value relative to B(n,3)=CODE1(n)+CODE2(n). The second quantizer circuit ADC2 114-2 can be configured to sample the amplified residual voltage and provide a code CODE3(n) representing the residual. The gain factor GAIN3 can be included in the weight of each physical bit representing CODE3(n) or be canceled. The resolution of CODE3(n) can be equal to the resolution of CODE2(n), which can be (approximately) 10 bits. CODE3(n) can be represented by more than 10 physical bits, and the bit weights can be based on characteristics of ADC2 114-2 that provide redundancy (e.g., nominal scaling of the CDAC capacitor array). For example, CODE3 can be represented by 12 physical bits with weights 1 / 4096, 1 / 8192, 1 / 16384, 1 / 32768, 1 / 65536, 1 / 65536, 1 / 131072, 1 / 262144, 1 / 524288, 1 / 524288, 1 / 1048576, 1 / 2097152.

[0043] CODE3(n) may be a third code representing a residual amount of a combination of an analog input value VIN(n) and a dither value sampled at a node 104 of the capacitor array 102 relative to a combined code B(n,3)=M1(n,3)+M2(n,3) applied to the capacitor array 102 .

[0044] In an example embodiment, various parameters of the ADC 100 may be selected such that the nominal value of DOUT(n) may be (VIN(n) / VSCALE)=CODE1(n)+CODE2(n)+CODE3(n)-DX(n). The resolution of the value DOUT(n) may be (approximately) 21 bits. In another embodiment, if GAIN3 is relatively reduced (e.g., from 2048 to 1024), the resolution may be relatively small (e.g., 20 bits). A large gain factor GAIN3 may be beneficial in suppressing noise components from ADC2 114-2 via CODE3(n). The resolution of ADC2 114-2 (such as the resolution of CODE2 and / or CODE3) and the gain factor GAIN3 may be selected based on a target noise specification for the ADC 100. It may be advantageous to select parameters for the ADC 100 such that the noise level and / or resolution of ADC2 has a relatively small impact on the noise specification of the ADC 100.

[0045] Any capacitor in the third segment of capacitors 102 - 3 that is not configured to provide negative feedback to amplifier 118 in Step 3 may be configured to be in a predefined state (eg, connected to VL).

[0046] PHOSITA will appreciate that amplifier 118 may include auto-zero circuitry (not shown) and / or other circuitry and methods to improve the offset specifications of ADC 100 .

[0047] PHOSITA will further recognize that once ADC2 samples the amplified residual voltage required to derive CODE3(n), amplifier 118 may be placed in a low power mode (eg, it may be turned off).

[0048] PHOSITA will further appreciate that ADC2 114-2 may be configured to provide CODE2 of a first resolution (such as 8 bits) in Step2, and to provide CODE3 of a second resolution (such as 10 bits) in Step3. Alternatively, a third quantizer circuit ADC3 (not shown) may be provided and configured to provide CODE3 in step3, and ADC2 114-2 may be configured to provide CODE2 in Step2 (and be inactive in Step3). In another embodiment, a single quantizer circuit may be configured to operate as ADC1 114-1 in Step1, and may be further configured to operate as ADC2 114-2 in Step2 and Step3.

[0049] Now consider Step 4 (deriving a code DOUT to represent the analog input value VIN(n) by combining the codes from steps 0, 1, 2, and 3 with optional mismatch information). The mismatch information may include multiple codes representing potential mismatches of capacitor ratios and / or other analog defects. In an example embodiment, the control circuit 101 may be configured to calculate DOUT(n)=CODE1(n)+CODE2(n)+CODE3(n)-DX(n). The potential mismatch of the capacitor ratios of the CDAC capacitor array 102 may not be considered, and the mismatch of the capacitor 102 may cause noise-like errors (mismatch-induced noise) in DOUT(n). The linearity of the ADC 100 may be substantially unaffected by the potential mismatch of the CDAC capacitor array 102. The reason for including the mismatch information in calculating DOUT may be to improve the signal-to-noise ratio (SNR) by reducing the mismatch-induced noise (e.g., to below the level characterized by thermal noise).

[0050] The scrambler circuit 106-6 and the jitter code DX(n) may be provided and configured so that the power spectral density of any mismatch-induced noise may be substantially uniform, as further described with respect to the scrambler circuit 206-6 of the '443 patent, particularly in FIG. 10b of the '443 patent. Specifically, in an example embodiment, the scrambler circuit 106-6 may be implemented as summarized in the '443 patent at column 11, lines 54-62. For example, the scrambler circuit 106-6 may be implemented as a zero-order mismatch shaping encoder that may nominally randomize the error caused by the first segment mismatch of the capacitor 102-1 into an error signal that is substantially similar to white noise. The jitter code DX(n) may be provided by the control circuit 101 as a substantially independent coin-tossing bit sequence of N2 (the '443 patent, including the '49-57 lines at column 12). The control circuit 101 may include a pseudo-random number generator for deriving DX(n), or may include other circuit systems (compared to the '443 patent) to provide a relatively more / better random bit sequence (e.g., a substantially non-repeating random sequence). A truly random bit sequence can be used, but truly random dithering is not required to achieve the objectives of the present teachings. It is sufficient that DX(n) is at least quasi-random, which is a relatively low standard that a pseudo-random number generator can meet. For example, the dithering code DX(n) may include multiple pseudo-random bits, where the multiple pseudo-random bits can be generated by a pseudo-random number generator, such as a linear feedback shift register (LFSR) generator or a generator based on a cellular automaton. For some embodiments, a substantially non-repeating substantially random sequence may be preferred.

[0051] Patent No. '443 further teaches a scrambler circuit that can be provided as scrambler circuit 106-6 in another embodiment. In particular, Patent No. '443 teaches that a scrambler circuit 206-6 (FIG. 7 of Patent No. '443) and a jitter code DX(n) can be provided so that the power spectral density of any mismatch-induced noise can be substantially non-uniform / shaped (FIG. 10c of Patent No. '443). Specifically, scrambler circuit 206-6 (FIG. 7 of Patent No. '443) can be a first-order or higher-order mismatch shaping encoder. (Patent No. '443, col. 11, line 62, front) In addition, as described in applicant's prior patent publications, to achieve first-order or higher-order shaping (adjustment) of errors caused by mismatch of capacitor 102-2, a dithering code DX(n) may be derived by a state machine that receives DX(n-1), B2(n-1,3), and optionally one or more substantially random bits as inputs to reduce possible patterns (e.g., idle tones) that may be embedded in the mismatch-induced errors. The state machine may be configured to effectively adjust the spectral characteristics of each individual bit in M2 driving capacitor 102-2.

[0052] In an embodiment, mismatch information (e.g., a code representing a potential mismatch of capacitor ratios and / or other analog defects) may be provided to the control circuit 101, which may be configured to include the mismatch information when deriving DOUT(n). The mismatch information may be derived as part of a manufacturing process, for example, as part of testing a semiconductor circuit. Alternatively, during normal operation of the ADC 100, the mismatch information may be derived in the field by foreground calibration (e.g., during power-up, idle periods, or interrupts) or by background calibration (e.g., using statistical methods). U.S. Patent No. 7,705,765 to Yang describes how to measure the weighting factors of the CDAC, and how to store digital codes representing the measured weighting factors and combine them with digital codes from an A / D conversion operation to derive a coded numerical value representing the value of an analog signal. U.S. Patent No. 7,705,765 is incorporated herein by reference.

[0053] The nominal value DOUT(n)=M1(n,3)+[M2(n,3)-DX(n)]+CODE3(n) can be a combination of the third code CODE3(n), the combined code M(n,3)=M1(n,3)+M2(n,3) and the dither code DX(n) representing the dither value sampled in Step0.

[0054] Mismatch information may be included in the calculation of DOUT(n) to account for potential deviations from the nominal weighting factors, where estimated (based on mismatch information correction) weighting factors may be applied to each individual bit in the calculation of DOUT(n), such as described in Patent No. '443 (particularly in Column 8, Lines 16-29). The calculation may be based on the acquisition state of CDAC (Step 0, dither code DX(n)) and the evaluation state of CDAC (Step 3, codes M1(n,3), M2(n,3) and CODE3(n)). Note that bits y1, y2, y3, y4 in Patent No. '443 may be bits representing M1(n,3); bits y5, y6, y7, y8, y9, y10 in Patent No. '443 may be bits representing M2(n,3), and bits x5, x6, x7, x8, x9, x10 in Patent No. '443 may be bits representing DX(n). Further note that DOUT=y1*w(T1)+y2*w(T2)+y3*w(T3)+y4*w(T4)+(y5-x5)*w(T5)+(y6-x6)*w(T6)+(y7-x7)*w(T7)+(y8-x8)*w(T8)+(y9-x9)*w(T9)+(y10-x10)*w(T10) from column 8, lines 24-26 of patent No. '443 can be DOUT(n)=M1(n,3)+[M2(n, 3)-DX(n)]+CODE3(n) is calculated bit by bit, corresponding to the estimated weights w(T1), w(T2), w(T3), w(T4) for each bit in M1(n,3) and the estimated weights w(T5), w(T6), w(T7), w(T8), w(T9), w(T10) for each bit in M2(n,3) and DX(n), where each bit is assigned an estimated (corrected) weighting factor, which can be the nominal weighting factor plus an adjustment / correction value based on the mismatch information.

[0055] The nominal weight value M1(n,3) of code M1(n,3) can be obtained by applying a nominal weight to each bit in the code (e.g., Figure 2The estimated weight value EW_M1(n,3) of the code M1(n,3) can be calculated by applying the estimated weight to each bit in the code. Nominally, EW_M1(n,3)=M1(n,3). For example, the nominal weight value of M1(n,3) represented by the bits [y1, y2, y3, y4] can be M1(n,3)=y1 / 4+y2 / 4+y3 / 4+y4 / 4, and the estimated weight value of M1(n,3) can be EW_M1(n,3)=y1*w(T1)+y2*w(T2)+y3*w(T3)+y4*w(T4), where w(T1), w(T2), w(T3), w(T4) can be estimates of the weight of each bit. Thus, the expression for DOUT (from column 8, lines 24-26 of patent No. '443) can be an estimated weighted evaluation of the nominal calculation DOUT(n) = M1(n,3) + [M2(n,3) - DX(n)] + CODE3(n), where w(T1), w(T2), w(T3), w(T4), w(T5), w(T6), w(T7), w(T8), w(T9), w(T10) can be the weighted evaluation of patent No. '443. Figure 2 24-26]] . In other words, the expression for DOUT (from column 8, lines 24-26 of patent No. '443) can alternatively be expressed as DOUT(n) = EW_M1(n,3) + [EW_M2(n,3) - EW_DX(n)]. As described in this paragraph, T* can refer to the input terminals of the capacitors within the CDAC capacitor array 102, and * represents a number (index) assigned to each capacitor, where the number is unique to each capacitor. w(T*) can be the weight (e.g., estimated weight) of the bit in the code applied to terminal T*. For example, y* can represent a bit of M1(n,3), where * is a number (index) representing the position of the bit within M1(n,3).

[0056] The value of a code may be assumed to be the nominal weighted value unless explicitly stated to be an estimated weighted value. The prefix "EW_" added to the code name CODENAME shall unambiguously reference the estimated weighted value EW_CODENAME for code CODENAME.

[0057] In an embodiment, mismatch information (e.g., a code representing a potential mismatch of capacitor ratios and / or other analog defects) may provide estimated weights for one or more bits of one or more of the codes M1(n,3), M2(n,3), DX(n), and CODE3(n) that may be combined to derive DOUT(n). The control circuit 101 may be configured to receive the mismatch information and derive and output a binary weighted code DOUT(n)=EW_M1(n,3)+EW_M2(n,3)-EW_DX(n)+EW_CODE3(n). For any bit of any code for which the mismatch information cannot provide an explicit estimate of the actual weight, a nominal weight may be used. In other words, the nominal weight may be a base (initial or default) estimate of the weight of any bit in any code.

[0058] In one embodiment, mismatch information may be provided and used to calculate an estimated weight value EW_M1(n,3) for code M1(n,3) applied to the first segment 102-1 of the CDAC capacitor array 102 in an evaluation state (e.g., Step 3). The mismatch information may provide an estimated weight for each bit in code M1(n,3). Nominal weight values ​​may be calculated for M2(n,3), DX(n), and CODE3(n), and these values ​​may be combined to provide an output value DOUT(n) representing the sampled input value VIN(n). DOUT(n)=EW_M1(n,3)+M2(n,3)+CODE3(n)-DX(n).

[0059] In another embodiment, mismatch information may be provided and used to calculate estimated weighted values ​​EW_M1(n,3) and EW_M2(n,3) of codes M1(n,3) and M2(n,3), which may be applied to the CDAC capacitor array 102 in an evaluation state (such as Step3). Mismatch information may also be provided and used to calculate an estimated weighted value EW_DX(n) of code DX(n) applied to the second segment 102-2 of the CDAC capacitor array 102 in an acquisition state (such as Step0). A nominal weighted value of CODE3(n) may be calculated. These values ​​may be combined to provide an output code DOUT(n) representing VIN(n). DOUT(n)=EW_M1(n,3)+EW_M2(n,3)−EW_DX(n)+CODE3(n). The estimated weights of the bits of M2(n,3) and DX(n) may be shared, and EW_M2(n,3)-EW_DX(n) may be calculated using the bit value differences, as described in Patent No. '443.

[0060] In another embodiment, mismatch information may be provided and used to calculate an estimated weighted value EW_CODE3(n) of CODE3(n). A single code may specify a ratio RATIO of an estimated weight and a nominal weight for each bit in CODE3(n) such that EW_CODE3(n)=RATIO*CODE3(n). Thus, mismatch information may be used to scale the nominal value CODE3(n) to derive its estimated weighted value EW_CODE3(n). Mismatch information may be provided and used to calculate estimated weighted values ​​EW_M1(n,3), EW_M2(n,3) and EW_DX(n) of codes M1(n,3), M2(n,3) and DX(n). These values ​​may be combined to provide an output value DOUT(n) representing a sampled input value VIN(n). DOUT(n)=EW_M1(n,3)+EW_M2(n,3)–EW_DX(n)+EW_CODE3(n).

[0061] In another embodiment, estimated weight values ​​may be calculated for one or more of codes M1(n,3), M2(n,3), DX(n), and CODE3(n). In each case, the estimated weight value may be calculated as the sum of a nominal value and an adjustment (bias) value. Mismatch information may be provided and used to calculate each adjustment (bias) value.

[0062] In another embodiment, a scrambler circuit 106-6 and a dither code DX(n) may be provided such that the power spectral density of any mismatch-induced noise may be substantially non-uniform / shaped (such as shown in FIG. 10c of the '443 patent). The control circuit 101 may be configured to receive and use the mismatch information to calculate estimated weighted values ​​of one or more codes M1(n,3), M2(n,3), DX(n), and CODE3(n) to derive an output code DOUT(n) representing a sampled input value VIN(n).

[0063] Figure 2 It is shown that the sampling switch 108 ( Figure 1 ). The sampling switch 108 may be opened at the sampling instant for VIN(n) at or near the end of the acquisition phase Step(n,0). The sampling switch 108 may remain open during the three conversion steps: Step1, Step2, and Step 3. The sampling switch 108 may be closed after ADC2 114-2 samples the amplified residual voltage to derive CODE3(n). For example, the switch 108 may be closed in the conversion from Step3 to Step4, and the switch 110-1( Figure 1) may be configured to apply VIN(t) across the first capacitor segment 102-1 during Step 4. Step (n, 4) may overlap with the acquisition phase of the next conversion cycle, Step (n+1, 0). In another embodiment, the code DX may transition from DX(n) to DX(n+1) at or before the closing of the sampling switch 108. More generally, in another embodiment, the ADC 100 other than the control circuit 101 may be reset at the end of Step 3. Certain portions of the ADC 100 (e.g., ADC 1114-1) may be reset more quickly. PHOSITA may recognize that the code may be modified Figure 2 An example timing of Figure 2 To best convey this teaching.

[0064] Many variations of the present teachings are envisioned. For example, Figure 3 Shows something like Figure 1 An example fully differential implementation of the ADC 300 of the ADC 100 of the ADC 100 is shown. The fully differential input voltage VIN(t) may be the voltage difference between the positive potential VINP(t) and the negative potential VINM(t). The fully differential first quantizer ADC1 314-1 may be configured to receive the differential voltage VIN(t) and provide a first code CODE1 to represent the VIN(t) sampled at the sampling instant combined with the analog jitter value derived from the jitter code DX. The CDAC may include a positive side capacitor array 301P and a negative side capacitor array 301M. Each capacitor array 301P and capacitor array 301M may include 3 segments and have a structure similar to Figure 1 The overall structure of the capacitor array 102. The combination of VIN(t) sampled at the sampling moment and the jitter value derived from the jitter code DX can be a differential charge amount substantially isolated at the node 304P and the node 304M. The sampling switch 308 can be a symmetrical device that connects each node 304P and the node 304M to a bias potential (such as ground) during the acquisition phase. The input of the fully differential residual amplifier 318 can be connected to the node 304P and the node 304M, and it can output a differential voltage representing the amplified residual amount. The fully differential second quantizer ADC2 314-2 can receive the amplified residual amount from the amplifier 318 and provide a code CODE2 to represent the residual amount of the combined sampled value relative to CODE1, and further provide a code CODE3 to represent the residual amount of the combined sampled value relative to the combination of CODE1 and CODE2. Switches 312P and 312M can configure the third segments of CDAC capacitor arrays 301P and 301M as negative feedback for amplifier 318 to provide a gain factor GAIN2 in Step 2 of the conversion cycle and further provide a gain factor GAIN3 in Step 3 of the conversion cycle. Control circuit 101 can be connected with Figure 1The control circuit 101 is similar to or the same as the control circuit 101. The control circuit 101 provides the configuration signal CFG to the switch 312P and the switch 312M according to the timing, and the timing can be Figure 2 The timing shown in is similar or identical to that shown in . Code M1 can configure switch 310P and switch 310M to drive the first segment of CDAC capacitor array 301P and CDAC capacitor array 301M. Code M2 ​​can configure switch 311P and switch 311M to drive the second segment of CDAC capacitor array 301P and CDAC capacitor array 301M. Reference voltage circuit 107 can be configured to provide reference potentials VH and VL to switch 310P and switch 311P in a first polarity and switch 310M and switch 311M in a second polarity opposite to the first polarity. Alternatively and / or equivalently, in another embodiment, code M1 and code M2 ​​can be applied to capacitor array 301P of a first polarity, and they can be applied to capacitor array 301M of an opposite second polarity. PHOSITA may be proficient in implementing and operating fully differential circuits, and they may recognize that Figure 3 The ADC 300 can be Figure 1 The functional equivalent of a single-ended ADC 100 is realized in a fully differential manner.

[0065] In another embodiment (not shown), the present teachings may be combined with the teachings of U.S. Patent No. 8,576,104, which is incorporated herein by reference. The purpose of such a combination may be to allow a wide common mode range for differential input signals, such as Figure 3 VINP(t) and VINM(t) in . The first quantizer circuit ADC1 can be implemented as a pair of quantizers (not shown) that generate a first polarity code CODE1P and a second polarity code CODE1M. The first polarity code CODE1P may represent a combination of VINP(t) sampled at a sampling moment and a first polarity jitter value that can be derived from the first polarity jitter code DXP. The second polarity code CODE1M may represent a combination of VINM(t) sampled at a sampling moment and a second polarity jitter value that can be derived from the second polarity jitter code DXM. Because VINP(t) and VINM(t) can be substantially different (for example, the common-mode component can vary significantly), CODE1P and CODE1M can be substantially different. The control circuit can be configured with a first half and a second half to process each single-ended conversion separately. For example, the control circuit can be substantially implemented as Figure 1 The jitter code DXP and the jitter code DXM may be, but need not be, independent of each other. One embodiment may be implemented as follows: Figure 1Two instances of ADC 100 in FIG. 1 are configured to process and convert VINP(t) and VINM(t) independently of each other except CODE3. A fully differential residual amplifier circuit (not shown, compared to Figure 3 The amplifier 318 and ADC2) can be replaced in Step 3 of the conversion cycle. Figure 1 Each of the two amplifier circuits 118 in. CODE3 can be derived on a fully differential basis. CODE3 can be provided to a first half control circuit for converting VINP(t) at a first polarity and to a second half control circuit for converting VINM(t) at an opposite second polarity. These codes can be combined, used, and output in various ways, as described in more detail in U.S. Pat. No. 8,576,104.

[0066] Example Implementations

[0067] The following examples are illustrated.

[0068] Example 1 may include a method for providing a digital output code to represent an analog input value, the method comprising the following steps: sampling a combination of an analog input value and a jitter value at a node of a capacitor array; deriving a first code that approximates the combination of the analog input value and the jitter value; applying a first segment of the first code to a first segment of the capacitor array and applying a second segment of the first code to a second segment of the capacitor array; deriving a second code to represent a first residual of the combination of the analog input value and the jitter value, the first residual being related to the first code applied to the capacitor array; combining a numerical value of the first code and a numerical value of the second code to derive a combined code; applying the first segment of the combined code to the first segment of the capacitor array and applying the second segment of the combined code to the second segment of the capacitor array, wherein the first segment of the combined code and the second segment of the combined code are responsive to the second code; deriving a third code to represent a second residual of the combination of the analog input value and the jitter value, the second residual being related to the combined code applied to the capacitor array; and combining the third code with the combined code and the jitter code representing the jitter value to provide a digital output code.

[0069] Example 2 may include the method of Example 1, wherein applying the first segment of the first code to the first segment of the capacitor array includes encoding the first segment of the first code with a mismatch shaping encoder.

[0070] Example 3 may include the method of Example 1, wherein combining the value of the first code and the value of the second code comprises adding the value of the first code and the value of the second code.

[0071] Example 4 may include the method of Example 1, wherein sampling the combination of the analog input value and the dithering value at the node of the capacitor array includes applying the dithering code to the second segment of the capacitor array.

[0072] Example 5 may include the method of Example 4, wherein the dithering code comprises a plurality of substantially quasi-random bits.

[0073] Example 6 may include the method of Example 4, further comprising the step of deriving a dithering code in response to a combined code applied to the second segment of the capacitor array in a previous conversion cycle.

[0074] Example 7 may include the method of Example 1, wherein deriving the second code includes amplifying the first residual.

[0075] Example 8 may include the method of Example 1, wherein deriving the third code comprises amplifying the second residue with a gain factor having an absolute value of at least 250.

[0076] Example 9 may include the method of Example 1, wherein the second segment of the combined code is a binary weighted code.

[0077] Example 10 may include the method of Example 1, wherein the first segment of the combined code is an equal weighted code.

[0078] Example 11 may include the method of Example 1, wherein a resolution of the first code is greater than a resolution of the first segment of the first code.

[0079] Example 12 may include the method of Example 1, wherein combining the third code with the combined code and the dithered code comprises calculating an estimated weighted value of at least one bit of the combined code using the mismatch information.

[0080] Example 13 may include the method of Example 1, wherein the second residual is substantially uncorrelated with the analog input value.

[0081] Example 14 may include the method of Example 1, wherein deriving the second code includes providing a successive approximation analog-to-digital converter.

[0082] Example 15 may include the method of Example 14, wherein a total capacitance of the successive approximation analog-to-digital converter is less than 10% of a total capacitance of the capacitor array.

[0083] Example 16 may include the method of Example 1, further comprising identifying mismatch information including a code representing a potential mismatch of a plurality of ratios of capacitors in the capacitor array.

[0084] Example 17 may include the method of Example 1, wherein deriving the first code comprises truncating the dithered code.

[0085] Example 18 may include the method of Example 1, wherein deriving the second code includes configuring a third segment of the capacitor array to provide negative feedback to the amplifier to provide the first gain factor.

[0086] Example 19 may include the method of Example 18, wherein deriving the third code comprises configuring a third segment of the capacitor array to provide negative feedback to the amplifier to provide a second gain factor, wherein an absolute value of the first gain factor is less than an absolute value of the second gain factor.

[0087] Example 20 may include the method of Example 1, wherein deriving the first code includes providing a flash quantizer.

[0088] Example 21 may include one or more computer-readable media having instructions stored thereon, wherein when the instructions are executed by a control circuit, the control circuit is caused to perform the method of any one of Examples 1 to 20.

[0089] Example 22 may include an analog-to-digital converter (ADC) for performing the method of any of Examples 1 to 20, wherein the ADC includes any components throughout the present disclosure for performing the method of any of Examples 1 to 20.

[0090] Example 23 may include an analog-to-digital converter (ADC) including a capacitor array including a plurality of capacitors and a control circuit coupled to the capacitor array. The control circuit determines a first code based on a combination of an analog input value and a dither value of the ADC, the first code approximating the combination of the analog input value and the dither value; applies a first segment of the first code to a first segment of the capacitor array; applies a second segment of the first code to a second segment of the capacitor array; determines a second code based on a first residual of the combination of the analog input value and the dither value, the first residual being related to the first code, the second code representing the first residual; combines a digital value of the first code with a digital value of the second code to generate a combined code; applies a first segment of the combined code to a first segment of the capacitor array, wherein the first segment of the combined code is responsive to the second code; applies a second segment of the combined code to a second segment of the capacitor array, wherein the second segment of the combined code is responsive to the second code; determines a third code to represent a second residual of the combination of the analog input value and the dither value, the second residual being related to the combined code applied to the capacitor array; and determines a digital output code based on the combined code and the dither code, the dither code representing the dither value.

[0091] Example 24 may include the ADC of Example 23, wherein the second segment of the combined code is a binary weighted code.

[0092] Example 25 may include the ADC of Example 23, wherein the first segment of the combined code is an equivalent weighted code.

[0093] Example 26 may include the ADC of Example 23, wherein a resolution of the first code is greater than a resolution of the first segment of the first code.

[0094] Example 27 may include the ADC of Example 23, wherein determining the digital output code comprises combining the third code with the combined code and the dithering code.

[0095] Example 28 may include the ADC of Example 27, wherein combining the third code with the combined code and the dithered code comprises determining an estimated weight value for at least one bit of the combined code using the mismatch information.

[0096] Example 29 may include the ADC of Example 27, wherein the second residual is substantially uncorrelated with the analog input value.

[0097] Example 30 may include the ADC of Example 23, wherein the control circuit further causes sampling of a combination of the analog input value and the dither value at a node of the capacitor array.

[0098] Example 31 may include the ADC of Example 23, further comprising a successive approximation register (SAR) ADC coupled to the control circuit, wherein the SAR ADC converts a combination of the analog input value and the dither value to digital and provides the converted combination as a first code to the control circuit.

[0099] Example 32 may include the ADC of Example 31, wherein a total capacitance of the SAR ADC is less than 10% of a total capacitance of the capacitor array.

[0100] Example 33 may include the ADC of Example 23, wherein determining the first code comprises truncating a dither code representing a dither value.

[0101] Example 34 may include an analog-to-digital converter (ADC) comprising a charging device, a device for applying a code to the charging device, and a device for controlling the operation of the ADC. The device is used to apply the code to perform the following steps: apply a first segment of a first code to the first segment of the charging device; apply a second segment of the first code to the second segment of the charging device; apply a first segment of a combined code to the first segment of the charging device, wherein the first segment of the combined code is responsive to the second code; and apply a second segment of the combined code to the second segment of the charging device, wherein the second segment of the combined code is responsive to the second code. The device for controlling the operation of the ADC performs the following steps: determine a first code that approximates a combination of an analog input value and a dithered value; determine a second code to represent a first residual of the combination of the analog input value and the dithered value, the first residual being related to the first code applied to the charging device; determine a third code to represent a residual of the combination of the analog input value and the dithered value relative to the combined code applied to the charging device; and generate a digital output code by combining the third code with the combined code and the dithered code representing the dithered value.

[0102] Example 35 may include the ADC of Example 34, wherein the means for controlling operation of the ADC further causes a combination of the analog input value and the dither value to be sampled at a node of the charging device.

[0103] Example 36 may include the ADC of Example 34, further comprising means for analog-to-digital conversion, the means being operable to convert the analog input value to a digital value, and provide the converted analog input value to means for controlling operation of the ADC to determine the first code.

[0104] Example 37 may include the ADC of Example 36, wherein a total capacitance of the means for analog-to-digital conversion is less than 10% of a total capacitance of the means for charging.

[0105] Example 38 may include the ADC of Example 34, wherein determining the first code includes truncating a dither code representing a dither value.

[0106] The foregoing summarizes the features of one or more embodiments of the subject matter disclosed herein. These embodiments are provided to enable a person of ordinary skill in the art (PHOSITA) to better understand the various aspects of the present disclosure. Certain well-understood terms and underlying technologies and / or standards may be referenced without detailed description. It is expected that PHOSITA will have or have access to background knowledge or information of those technologies and standards sufficient to practice the teachings of the present disclosure.

[0107] PHOSITA will understand that they can easily use this disclosure as a basis for designing or modifying other processes, structures or variations to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. PHOSITA will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications to this article without departing from the spirit and scope of the present disclosure.

[0108] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications to this article without departing from the spirit and scope of the present disclosure.

[0109] Certain embodiments of the present disclosure may readily include a system-on-chip (SoC) central processing unit (CPU) package. SoC represents an integrated circuit (IC) that integrates components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and radio frequency functions: all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM), where multiple chips are located within a single electronic package and are configured to interact closely with each other through the electronic package. Where appropriate, any module, function, or block element of an ASIC or SoC may be provided in a reusable "black box" intellectual property (IP) block that may be distributed separately without disclosing the logical details of the IP block. In various other embodiments, digital signal processing functions may be implemented in one or more silicon cores in application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and other semiconductor chips.

[0110] In some cases, the teachings of the present disclosure may be encoded into one or more tangible, non-transitory computer-readable media having executable instructions stored thereon, which, when executed, instruct a programmable device (such as a processor or DSP) to perform the methods or functions disclosed herein. Where the teachings herein are at least partially embodied in a hardware device (such as an ASIC, IP block, or SoC), the non-transitory medium may include a hardware device programmed with logic hardware to perform the methods or functions disclosed herein. The teachings may also be practiced in the form of register transfer level (RTL) or other hardware description languages ​​such as VHDL or Verilog, which may be used to program a manufacturing process to produce the disclosed hardware elements.

[0111] The computer program logic that implements all or part of the functions described herein is embodied in various forms, including but not limited to source code form, computer executable form, hardware description form, and various intermediate forms (e.g., mask work, or forms generated by assemblers, compilers, linkers, or locators). In an example, the source code includes a series of computer program instructions implemented in various programming languages, such as object code, assembly language, or high-level languages ​​such as OpenCL, RTL, Verilog, VHDL, Fortran, C, C++, JAVA, or HTML, for use with various operating systems or operating environments. The source code can define and use various data structures and communication messages. The source code can be in a computer executable form (e.g., via an interpreter), or the source code can be converted (e.g., via a converter, assembler, or compiler) to a computer executable form.

[0112] In an example embodiment, any number of circuits in the figure can be implemented on a board of an associated electronic device. The board can be a general circuit board that can accommodate various components of the internal electronic system of the electronic device and further provide connectors for other peripheral devices. More specifically, the board can provide an electrical connection through which other components of the system can communicate electrically. Any suitable processor (including a digital signal processor, a microprocessor, a support chipset, etc.), a memory element, etc. can be appropriately coupled to the circuit board based on specific configuration requirements, processing requirements, computer design, etc. Other components, such as external storage devices, additional sensors, controllers for audio / video display, and peripheral devices can be connected to the board as plug-in cards, via cables, or integrated onto the board. In another example embodiment, the circuit in the figure can be implemented as an independent module (e.g., a device with related components and circuit systems configured to perform a specific application or function), or as a plug-in module inserted into the specific application hardware of the electronic device.

[0113] Note that in many of the examples provided herein, interactions may be described using two, three, four or more electronic components. However, this is done for clarity and example purposes only. It should be understood that the system can be integrated in any suitable manner. Along similar design alternatives, any of the components, modules, and elements shown in the figures can be combined in various possible configurations, all of which are clearly within the broad scope of the present disclosure. In some cases, it may be easier to describe one or more functions of a given set of processes by only referencing a limited number of electrical components. It should be understood that the circuits in the figures and their teachings are easily expandable and can accommodate a large number of components and more complex / complex arrangements and configurations. Therefore, the examples provided should not limit the scope or inhibit the broad teachings of the circuits, as they may be applied to countless other architectures.

[0114] Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained by those skilled in the art, and the present disclosure is intended to cover all such changes, substitutions, variations, alterations, and modifications that fall within the scope of the appended claims. To assist the United States Patent and Trademark Office (USPTO) and any reader of any patent issued under this application in interpreting the claims appended hereto, applicants wish to note that applicants: (a) do not intend to invoke 35 U.S.C. § 112(f) as it exists on the date of filing this application unless “means” or “step” is specifically used in a particular claim; and (b) do not intend, by any statement in this disclosure, to limit the present disclosure in any manner not reflected in the appended claims.

Claims

1. A method for providing a digital output code to represent an analog input value, the method comprising the steps of: sampling a combination of the analog input value and the dither value at a node of the capacitor array; deriving a first code that approximates the combination of the analog input value and the dither value; applying a first segment of the first code to a first segment of the capacitor array and applying a second segment of the first code to a second segment of the capacitor array; deriving a second code to represent a first residual of the combination of the analog input value and the dither value, the first residual being related to the first code applied to the capacitor array; combining the value of the first code and the value of the second code to derive a combined code, wherein combining the value of the first code and the value of the second code comprises adding the value of the first code and the value of the second code; applying a first segment of the combined code to a first segment of the capacitor array and applying a second segment of the combined code to a second segment of the capacitor array, wherein the first segment of the combined code and the second segment of the combined code are responsive to the second code; deriving a third code to represent a second residual of the combination of the analog input value and the dither value, the second residual being related to the combined code applied to the capacitor array; as well as The third code is combined with the combined code and a dither code representing the dither value to provide the digital output code. 2 . The method of claim 1 , wherein applying the first segment of the first code to the first segment of the capacitor array comprises encoding the first segment of the first code by a mismatch shaping encoder. 3 . The method of claim 1 , wherein sampling the combination of the analog input value and the dither value at the node of the capacitor array comprises applying the dither code to a second segment of the capacitor array. The method of claim 3 , wherein the dithering code comprises a plurality of quasi-random bits.

5. The method of claim 3, further comprising the step of deriving the dithering code in response to a combined code applied to the second segment of the capacitor array in a previous conversion cycle. The method of claim 1 , wherein deriving the second code comprises upscaling the first residue.

7. The method of claim 1, wherein deriving the third code comprises amplifying the second residue by a gain factor having an absolute value of at least 250.

8. An analog-to-digital converter ADC, comprising: a capacitor array comprising a plurality of capacitors; and a control circuit coupled to the capacitor array, the control circuit being configured to: determining a first code based on a combination of an analog input value of the ADC and a dither value, the first code approximating the combination of the analog input value and the dither value; causing a first segment of the first code to be applied to a first segment of the capacitor array; causing a second segment of the first code to be applied to a second segment of the capacitor array; determining a second code based on a first residual of the combination of the analog input value and the dither value, the first residual being related to the first code and the second code being representative of the first residual; combining the value of the first code and the value of the second code to produce a combined code, wherein combining the value of the first code and the value of the second code comprises adding the value of the first code and the value of the second code; causing a first segment of the combined code to be applied to a first segment of the capacitor array, wherein the first segment of the combined code is responsive to the second code; causing a second segment of the combined code to be applied to a second segment of the capacitor array, wherein the second segment of the combined code is responsive to the second code; determining a third code to represent a second residual of the combination of the analog input value and the dither value, the second residual being related to the combination code applied to the capacitor array; as well as A digital output code is determined based on the combined code and a dither code, the dither code representing the dither value.

9. The analog-to-digital converter (ADC) of claim 8, wherein the second segment of the combined code is a binary weighted code.

10. The analog-to-digital converter (ADC) of claim 8, wherein the first segment of the combined code is an equally weighted code. 11 . The analog-to-digital converter (ADC) of claim 8 , wherein a resolution of the first code is greater than a resolution of the first segment of the first code. 12 . The analog-to-digital converter (ADC) of claim 8 , wherein determining the digital output code comprises combining the third code with the combined code and the dither code.

13. The analog-to-digital converter (ADC) of claim 12, wherein combining the third code with the combined code and the dithered code comprises using mismatch information to determine an estimated weight value of at least one bit of the combined code. 14 . The analog-to-digital converter (ADC) of claim 12 , wherein the second residual is substantially uncorrelated with the analog input value.

15. An analog-to-digital converter ADC, comprising: Charging device; Means for applying code to the charging device, the means for applying the code to perform the following steps: applying a first segment of a first code to a first segment of the charging device; applying a second segment of the first code to a second segment of the charging device; applying a first segment of a combined code to a first segment of the charging device, wherein the first segment of the combined code is responsive to a second code; as well as applying a second section of the combined code to a second section of the charging device, wherein the second section of the combined code is responsive to the second code; and Means for controlling the operation of the ADC, the means for performing the following steps: determining said first code that approximates a combination of an analog input value and a dither value; determining the second code to represent a first residual amount of the combination of the analog input value and the jitter value, the first residual amount being related to the first code applied to the charging device; determining a third code to represent a residual amount of the combination of the analog input value and the jitter value relative to the combined code applied to the charging device; and A digital output code is generated by combining the third code with the combination code and a dither code representing the dither value.

16. The analog-to-digital converter (ADC) according to claim 15, wherein the means for controlling the operation of the ADC is further configured to perform the following steps: The combination of the analog input value and the dither value is caused to be sampled at a node of the charging device.

17. The analog-to-digital converter (ADC) according to claim 15, further comprising a device for analog-to-digital conversion, the device being configured to perform the following operations: converting the analog input value to digital; and The converted analog input value is provided to means for controlling operation of the ADC to determine the first code.

18. The analog-to-digital converter (ADC) according to claim 17, wherein a total capacitance of the means for analog-to-digital conversion is less than 10% of a total capacitance of the charging means.

19. The analog-to-digital converter (ADC) of claim 15, wherein determining the first code comprises truncating the dither code representing the dither value.

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