Matrix multiplication method and device based on Winograd algorithm

Abstract

The present disclosure provides an operation device for generating a third matrix by multiplying a first matrix with a second matrix based on a Winograd algorithm, the operation device comprising: a second cumulative value output unit, the second cumulative value output unit having a plurality of second cumulative value operation units, wherein one of the second cumulative value operation units accumulates a second product value obtained by multiplying pairs of second matrix element values ​​with each other, selects the output value of the adjacent second cumulative value operation unit or the calculated second product value to output the second cumulative value; and one or more row element value operation units, wherein one row element value operation unit accumulates a first matrix element product value obtained by multiplying pairs of first matrix element values ​​with each other, and the element value operation unit calculates the element value of the third matrix by using the accumulated first matrix element product value and the second cumulative value. In addition, a method for designing an operation device is provided, which enables the performance of low-precision operations to be enhanced when multiple precisions are provided, and enables the hardware area to be saved when supporting high-precision operations.

Description

Technical Field

[0001] In some embodiments, the present disclosure relates to a matrix multiplication method and a matrix multiplication device based on the Winograd algorithm. Background Art

[0002] The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

[0003] Matrix multiplication is a core operation widely used in many fields such as artificial intelligence, signal processing, and graphics. In order to efficiently process matrix multiplication in different application-specific integrated circuit (ASIC) products, dedicated hardware operators are used for matrix multiplication. For example, NVIDIA provides the latest graphics processing units (GPUs) with built-in tensor cores for processing matrix multiplication.

[0004] There are various algorithms for reducing the operation cost required when performing matrix multiplication in an operator for matrix multiplication. Among them, a matrix multiplication algorithm based on the Winograd algorithm reduces the number of multiplication operations by half compared to ordinary matrix multiplication.

[0005] Over the currently available basic hardware designs utilizing the Winograd algorithm, matrix multiplication designs based on advanced Winograd algorithms need to provide improvements in various aspects such as reduced hardware design footprint, high-speed operations, and double-precision support. Summary of the invention

[0006] Technical issues

[0007] In some embodiments, an object of the present disclosure is to provide a matrix multiplication apparatus based on the Winograd algorithm for reduced hardware footprint, improved operation speed, and double precision of operation.

[0008] Technical Solution

[0009] According to at least one embodiment of the present disclosure, a computing device for multiplying a first matrix by a second matrix to generate a third matrix based on a Winograd algorithm includes: a second cumulative value output unit, the second cumulative value output unit having a plurality of second cumulative value calculation units, one of the plurality of second cumulative value calculation units being configured to accumulate second product values ​​obtained by multiplying each of the paired element values ​​of the second matrix, selecting output values ​​of adjacent second cumulative value calculation units and one of the accumulated second product values ​​as a second cumulative value, and outputting the second cumulative value; a third cumulative value output unit, the third cumulative value output unit having a plurality of third cumulative value calculation units, one of the plurality of third cumulative value calculation units being configured to generate a second product value obtained by multiplying one of the paired element values ​​of the first matrix by the paired element values ​​of the second matrix. a first value obtained by adding one element value of the prime values ​​of the first matrix, generating a second value obtained by adding another element value of the paired element values ​​of the first matrix to another element value of the paired element values ​​of the second matrix, accumulating a third product value obtained by multiplying the first value by the second value, selecting one of the output values ​​of the adjacent third cumulative value calculation units and the accumulated third product value as the third accumulated value, and outputting the third accumulated value; and an element value calculation unit, the element value calculation unit having one or more row element value calculation units, one of the one or more row element value calculation units being configured to accumulate the element product values ​​of the first matrix obtained by multiplying each of the paired element values ​​of the first matrix, and calculating the element values ​​of the third matrix by respectively subtracting the accumulated element product values ​​of the first matrix and the second accumulated value from the third accumulated value.

[0010] Another embodiment of the present disclosure provides a computing device, which includes an input partitioning unit, a first adding unit, a second adding unit, a multiplication unit, and an accumulator, and performs operations based on a Winograd algorithm to multiply a first matrix by a second matrix to generate a third matrix, wherein the input partitioning unit is configured to partition each of a bitmap representing an element value of the first matrix, a bitmap representing an element value of the second matrix, a bitmap representing another element value of the first matrix, and a bitmap representing another element value of the second matrix into a high partitioning bitmap and a low partitioning bitmap in units of N bits, wherein N bits are the bit length at the input terminal of the first adding unit, and the first adding unit The method further comprises: configuring to add an element value of the first matrix and an element value of the second matrix to each other for each of the selected partition bitmaps having equal rank between the high partition bitmap and the low partition bitmap, the second adding unit being configured to selectively add another element value of the first matrix and another element value of the second matrix to each other for each of the selected partition bitmaps having equal rank between the high partition bitmap and the low partition bitmap, the multiplication unit being configured to calculate a product value by multiplying an addition result of the first adding unit and an addition result of the second adding unit, and the accumulator being configured to accumulate the product value calculated by the multiplication unit.

[0011] Another embodiment of the present disclosure provides a computing device, which includes four preprocessors, a first adding unit, a second adding unit, a multiplying unit, a third adding unit and an accumulator, and performs operations based on the Winograd algorithm to multiply a first matrix by a second matrix to generate a third matrix, wherein each of the four preprocessors is configured to receive a pair of matrix element values ​​with a length of N bits (where N is a natural number), place one element value of the pair of matrix element values ​​in a high bitmap on a bitmap with a preset length, place the other element value of the pair of matrix element values ​​in a low bitmap on the bitmap with a preset length, and extend the sign of the element value located in the low bitmap by copying the sign bit of the other element value to the (N+1)th bit on the bitmap with a preset length to generate bitmap data with a (2N+1)-bit length, wherein the first adding unit The element is configured to add data generated on the bitmap having a preset length and by two preprocessors among the four preprocessors to each other to generate a first result value, the second adding unit is configured to add data generated on the bitmap having the preset length and by the other two preprocessors among the four preprocessors to each other to generate a second result value, the multiplying unit is configured to multiply a value corresponding to the upper bitmap of the first result value and a value corresponding to the upper bitmap of the second result value to each other to generate an eleventh product value, and multiply a value corresponding to the lower bitmap of the first result value and a value corresponding to the lower bitmap of the second result value to each other to generate a twelfth product value, the third adding unit is configured to add the eleventh product value and the twelfth product value to each other to generate a multiplication result value, and the accumulator is configured to accumulate the multiplication result values.

[0012] Another embodiment of the present disclosure provides a method for multiplying a first matrix by a second matrix to generate a third matrix, which is performed by a computing device having a plurality of second cumulative value calculation units, a plurality of third cumulative value calculation units, and one or more row element value calculation units, the method comprising i) outputting the second cumulative value by accumulating second product values ​​obtained by multiplying each of the paired element values ​​of the second matrix to select one of the output values ​​of the adjacent second cumulative value calculation units and the accumulated second product values ​​as the second cumulative value and outputting the second cumulative value, and ii) causing a third cumulative value calculation unit corresponding to the second cumulative value calculation unit in position to generate a third cumulative value obtained by adding one element value of the paired element values ​​of the first matrix to one element value of the paired element values ​​of the second matrix. a value, and generates a second value obtained by adding another element value in the paired element values ​​of the first matrix to another element value in the paired element values ​​of the second matrix, iii) causing a third cumulative value calculation unit to accumulate a third product value obtained by multiplying the first value and the second value, selecting one of the output value of an adjacent third cumulative value calculation unit adjacent to the one third cumulative value calculation unit and the accumulated third product value as a third accumulated value and outputting the third accumulated value, and iv) causing a row element value calculation unit corresponding in position to the one third cumulative value calculation unit to accumulate the first matrix element product value obtained by multiplying each of the paired element values ​​of the first matrix, and calculate the element value of the third matrix by subtracting the accumulated first matrix element product value and the second accumulated value from the third accumulated value, respectively.

[0013] Another embodiment of the present disclosure provides a method for performing operations based on a Winograd algorithm to multiply a first matrix by a second matrix to generate a third matrix, which is performed by a computing device having an input partitioning unit, a first adding unit, a second adding unit, a multiplication unit, and an accumulator. The method includes i) causing the input partitioning unit to partition each of a bitmap representing an element value of the first matrix, a bitmap representing an element value of the second matrix, a bitmap representing another element value of the first matrix, and a bitmap representing another element value of the second matrix into a high partitioning bitmap and a low partitioning bitmap in units of N bits, wherein N bits are the bit length at the input terminal of the first adding unit, and ii) causing the second adding unit to perform operations based on a Winograd algorithm to multiply a first matrix by a second matrix to generate a third matrix. an adding unit to add an element value of the first matrix and an element value of the second matrix to each other for each of the selected partition bitmaps having equal rank between the high partition bitmap and the low partition bitmap, iii) causing the second adding unit to selectively add another element value of the first matrix and another element value of the second matrix to each of the selected partition bitmaps having equal rank between the high partition bitmap and the low partition bitmap, iv) causing the multiplication unit to calculate a product value by multiplying the addition result of the first adding unit and the addition result of the second adding unit, and v) causing the accumulator to accumulate the product value calculated by the multiplication unit.

[0014] Another embodiment of the present disclosure provides a method for performing operations based on the Winograd algorithm to multiply a first matrix by a second matrix to generate a third matrix by executing a computing device having four preprocessors, a first adding unit, a second adding unit, a multiplying unit, a third adding unit, and an accumulator. The method comprises i) causing each of the four preprocessors to receive a pair of matrix element values ​​of length N bits (where N is a natural number), placing one element value of the pair of matrix element values ​​in a high bitmap on a bitmap having a preset length, placing the other element value of the pair of matrix element values ​​in a low bitmap on the bitmap having a preset length, and extending the sign of the element value in the low bitmap by copying the sign bit of the other element value to the (N+1)th bit on the bitmap having the preset length, so as to generate bitmap data of (2N+1) bit length, ii) causing the The first adding unit adds the data generated on the bitmap with a preset length and by two of the four preprocessors to generate a first result value, iii) causes the second adding unit to add the data generated on the bitmap with a preset length and by the other two of the four preprocessors to generate a second result value, iv) causes the multiplication unit to multiply the value corresponding to the high bitmap of the first result value and the value corresponding to the high bitmap of the second result value to generate an eleventh product value, and multiply the value corresponding to the low bitmap of the first result value and the value corresponding to the low bitmap of the second result value to generate a twelfth product value, v) causes the third adding unit to add the eleventh product value and the twelfth product value to generate a multiplication result value, and vi) causes the accumulator to accumulate the multiplication result value.

[0015] Beneficial Effects

[0016] The present disclosure, in some embodiments, provides a computing device in the form of a systolic array having core units whose functions are separated to provide additional units responsible for the separated functions arranged one-dimensionally across the systolic array, thereby improving a conventional operating device having a single type of unit arranged two-dimensionally across the systolic array by significantly reducing the hardware footprint.

[0017] In addition, the present disclosure provides a computing device that allows its core hardware units to receive data obtained from operations performed by coplanar adjacent core units, thereby improving conventional computing devices by significantly reducing the number of paths used to transmit computing data generated by the core hardware units to other units, thereby achieving high-speed computing of the computing device.

[0018] In addition, the present disclosure implements operations on matrix data of various precisions, thereby providing an efficient matrix multiplication device designed when processing multiple matrix data of various precisions. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Matrix multiplication is shown in which matrix Z is obtained by multiplying matrix X by Y.

[0020] Figure 2 is a diagram of a configuration of a conventional matrix multiplication device in a systolic array form for matrix multiplication based on the Winograd algorithm.

[0021] Figure 3 yes Figure 2 2 is a diagram showing the internal configuration of a first X-element processing unit, a first Y-element processing unit, and a first Z-element processing unit in FIG.

[0022] Figure 4 is a diagram of a configuration of a systolic array type operation device for matrix multiplication based on a Winograd algorithm according to at least one embodiment of the present disclosure.

[0023] Figure 5 : is a diagram of the internal configuration of the first-row element value calculation unit, the leftmost second cumulative value calculation unit, and the upper-left third cumulative value calculation unit.

[0024] Figure 6 is a diagram illustrating in detail the configuration of the second cumulative value calculation unit and the uppermost third cumulative value calculation unit, in which reference numerals indicate only some components essential for the description and the other remaining components are not numbered.

[0025] Figure 7 is a data flow diagram of a sum-product operation method (specifically, the function of a third cumulative value calculation unit but not including the function of a third selection unit) according to at least one embodiment of the present disclosure.

[0026] Figure 8 is an implementation according to at least one embodiment Figure 7 Schematic diagram of a data flow diagram of a sum-product computing device.

[0027] Fig. 9 is a replacement Figure 5 A diagram showing a configuration of a multiplication device of a first multiplication unit or a second multiplication unit for performing multiplication on two 16-bit input data items after division in 8-bit units.

[0028] Fig.10 is a diagram of a sum-product operation device according to at least one embodiment as a device required to calculate matrix multiplication by combining a plurality of matrix element values ​​into a single data.

[0029] Fig.11is a diagram of an arithmetic device that can be used for a first multiplication unit of a row element value calculation unit and a second multiplication unit of each second cumulative value calculation unit. DETAILED DESCRIPTION

[0030] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, similar reference numerals preferably designate similar elements, although these elements are shown in different drawings. In the following description of some embodiments, for the sake of clarity and brevity, no further description related to known parts and functions is provided.

[0031] Figure 1 Matrix multiplication is shown in which matrix Z is obtained by multiplying matrix X by Y.

[0032] like Figure 1 As shown in , when the size of matrix X is n×p and the size of matrix Y is p×m, the size of matrix Z becomes n×m, and each element z of matrix Z can be calculated as in Formula 1 ij The value of .

[0033]

[0034] The multiplication expression of Formula 1 can be expressed as a multiplication expression by using the Winograd algorithm as in Formula 2.

[0035]

[0036] In Formula 2, the calculation formula of the second ∑ term is commonly applied to each row element of the matrix Z, and the calculation formula of the third ∑ term is commonly applied to each column element of the matrix Z, so the second ∑ term in Formula 2 can be calculated only once for each row of elements of Z, and the third ∑ term in Formula 2 can be calculated only once for each column of elements of Z to obtain all constituent element values ​​of the matrix Z. In addition, when the elements of the matrix X or Y always have constant values, the calculation formula of the second or third ∑ term in Formula 2 can use pre-calculated values.

[0037] This way of performing matrix multiplication as in Formula 2 by using the characteristics of the Winograd algorithm reduces the total number of multiplications compared to the matrix multiplication of Formula 1. The larger the matrix Z is, the more the number of matrix multiplication operations decreases, almost reaching 1 / 2 times the number of matrix multiplications in Formula 1.

[0038] In the Winograd algorithm, in addition to computing the multiplication expression, the additional cost involved in the first ∑ term of Equation 2 is the addition operation for input multiplication and the accompanying use of the multiplication unit for processing inputs greater than 1 bit. It is typical in operations on integer inputs that the cost of the multiplication operator is greater than the addition operator, and the operation cost of the integer multiplication unit is proportional to the square of the input bit length. For this reason, the longer the input bit length, the lower the relative additional cost caused by those large 1-bit multiplication inputs.

[0039] Therefore, despite the further addition operations occurring in the first ∑ term of Equation 2 and those multiplication inputs greater than 1 bit occurring, the total operation cost required for the matrix multiplication of Equation 2 is significantly reduced compared to the matrix multiplication of Equation 1.

[0040] Figure 2 is a diagram of a configuration of a conventional matrix multiplication device 200 in a systolic array form for matrix multiplication based on the Winograd algorithm.

[0041] Figure 2 The matrix multiplication device 200 is an example of a matrix multiplier that multiplies 4×4 matrices X and Y to calculate and generate respective elements of a 4×4 matrix Z, and includes a first operation unit 210 , a second operation unit 220 , and a third operation unit 230 .

[0042] The first operation unit 210 includes a plurality of X element processing units 211, 212, 213 and 214 having the same number as the maximum allowable number of rows of the matrix X that can be processed at one time. A matrix larger than the maximum allowable number of rows of the matrix X can be processed by the first operation unit 210 by division. Since the matrix division process is mathematically self-evident, no further description is provided. For convenience, the present disclosure focuses on matrices that match the maximum matrix size that can be processed by the operator at the same time. The X element processing units 211, 212, 213, 214 each receive paired matrix X element values ​​to calculate and generate multiplication operation values, and store paired X element values ​​and multiplication operation values.

[0043] The second operation unit 220 includes a plurality of Y element processing units 221, 222, 223 and 224, the number of which is equal to the number of columns of the matrix Y that can be processed simultaneously. The Y element processing units 221, 222, 223, 224 each receive a pair of matrix Y element values ​​to calculate and generate a multiplication operation value, and store the pair of Y element values ​​and the multiplication operation value respectively.

[0044] The third operation unit 230 receives the pairs of X element values ​​and their multiplication values ​​stored in the first operation unit 210 and receives the pairs of Y element values ​​and their multiplication values ​​stored in the second operation unit 220 to calculate and generate matrix Z element values.

[0045] The third operation unit 230 includes a plurality of Z-element processing units 231, 232, ..., 246, the number of which is equal to the maximum allowable number of rows of the matrix X that can be processed simultaneously multiplied by the maximum allowable number of columns of the matrix Y that can be processed simultaneously.

[0046] Figure 3 yes Figure 2 2 is a diagram showing the internal configuration of the first X-element processing unit 211, the first Y-element processing unit 221, and the first Z-element processing unit 231 in FIG.

[0047] The first X-element processing unit 211 includes a first multiplication unit 314 .

[0048] The first multiplication unit 314 multiplies the first matrix X element and the second matrix X element by each other to generate a first product value.

[0049] The first Y-element processing unit 221 includes a second multiplication unit 324 .

[0050] The second multiplication unit 324 multiplies the first matrix Y element and the second matrix Y element by each other to generate a second product value.

[0051] The first Z element processing unit 231 includes an eleventh storage unit 311, a twelfth storage unit 312, a thirteenth storage unit 313, a twenty-first storage unit 321, a twenty-second storage unit 322, a twenty-third storage unit 323, a first adding unit 331, a second adding unit 332, a third multiplication unit 333 and an accumulation operation unit 334.

[0052] The eleventh storage unit 311 and the twelfth storage unit 312 receive and store the first matrix X element and the second matrix X element, respectively.

[0053] The thirteenth storage unit 313 stores the first product value generated by the first multiplication unit 314 .

[0054] The twenty-first storage unit 321 and the twenty-second storage unit 322 receive and store the first matrix Y element and the second matrix Y element, respectively.

[0055] The twenty-third storage unit 323 stores the second product value generated by the second multiplication unit 324 .

[0056] The first adding unit 331 receives the first matrix X element and the first matrix Y element respectively stored in the eleventh storage unit 311 and the twenty-first storage unit 321 , and it performs addition on the received elements to generate a first added value.

[0057] The second adding unit 332 receives the second matrix X element and the second matrix Y element respectively stored in the twelfth storage unit 312 and the twenty-second storage unit 322, and it performs addition on the received elements to generate a second added value.

[0058] The third multiplication unit 333 receives the first added value and the second added value and multiplies them to generate a third product value.

[0059] After receiving the first product value, the second product value and the third product value from the first multiplication unit 314, the second multiplication unit 324 and the third multiplication unit 333 respectively, the accumulation operation unit 334 subtracts the first product value and the second product value from the third product value to generate an accumulation value. The accumulation value calculated here becomes a Z element value of the matrix Z.

[0060] exist Figure 2 , 246 receives the first X element value, the second X element value and the product value thereof from the left end X element processing unit 211, 212, 213, 214 thereof, and receives the first Y element value, the second Y element value and the product value thereof from the top end Y element processing unit 221, 222, 223, 224 thereof, to calculate the Z element value corresponding to the relevant Z element processing unit 231, 232, 246. For example, the Z element processing unit 236 receives the element values ​​necessary for its operation from the left end X element processing unit 212 thereof in the same row and from the top end Y element processing unit 222 thereof in the same column.

[0061] Furthermore, the six storage units 311 , 312 , 313 , 321 , 322 , and 323 may each be implemented as a flip-flop, the operation of which is obvious to those skilled in the art and will not be described herein.

[0062] exist Figure 2 , the computing device 200 has more Z element processing units 231, 232, ..., 246 of the third computing unit 230 than each of the number of X element processing units 211, 212, 213, 214 and the number of Y element processing units 221, 222, 223, 224 of the first computing unit 210. For this reason, improving the performance of the computing device 200 requires optimizing the third computing unit 230.

[0063] like Figure 2 and Figure 3 As shown in , the first Z-element processing unit 231 in the third operation unit 230 receives data for subtraction operation from the first operation unit 210 and the second operation unit 220 respectively.

[0064] Not only the first Z-element processing unit 231 but also the remaining Z-element processing units 232 , . . . , 246 receive data for subtraction operations from the first operation unit 210 and the second operation unit 220 , respectively.

[0065] Therefore, the Z-element processing units 231 , 232 , . . . , 246 require a two-dimensionally arranged path for transmitting data required for the subtraction operation.

[0066] Figure 4 is a diagram of a configuration of a systolic array type operation device 400 for matrix multiplication based on a Winograd algorithm according to at least one embodiment of the present disclosure.

[0067] The operation device 400 according to at least one embodiment of the present disclosure is exemplified as a matrix multiplication device, which multiplies each of the first matrix X and the second matrix Y, each of which has a size of 4×4, to generate corresponding element values ​​of the third matrix Z, which has a size of 4×4. The operation device 400 includes an element value calculation unit 410, a second cumulative value output unit 420, and a third cumulative value output unit 430.

[0068] The element value calculation unit 410 includes a plurality of row element value calculation units 411, 412, 413, and 414. The number of row element value calculation units 411, 412, 413, and 414 is n, and n is a natural number equal to or greater than 1. Here, n may be equal to each of the number of rows of the third matrix Z that can be processed simultaneously and the maximum number of rows of the matrix X. This embodiment illustrates an example case where n=4.

[0069] The second cumulative value output unit 420 includes a plurality of second cumulative value calculation units 421, 422, 423, and 424. The number of the second cumulative value calculation units 421, 422, 423, and 424 is m, and m is a natural number equal to or greater than 1. Here, m may be equal to each of the number of columns of the matrix Z that can be processed simultaneously and the maximum number of columns of the matrix Y. This embodiment illustrates an example case where m=4.

[0070] The third cumulative value output unit 430 includes a plurality of third cumulative value calculation units 431, 432, ..., 446. Here, the number of the third cumulative value calculation units 431, 432, ..., 446 is n×m, that is, 16.

[0071] like Figure 4 As shown in , a plurality of row element value calculation units 411, 412, 413, 414, a plurality of second cumulative value calculation units 421, 422, 423, 424 and a plurality of third cumulative value calculation units 431, 432, ..., 446 are formed as a whole in the entire two-dimensional systolic array.

[0072] When Figure 4When the entire two-dimensional systolic array is specifically classified by type, its components include a plurality of row element value calculation units 411, 412, 413, 414 formed as a one-dimensional systolic array, a plurality of second cumulative value calculation units 421, 422, 423, 424 formed as a one-dimensional systolic array, and a plurality of third cumulative value calculation units 431, 432, ..., 446 formed as a two-dimensional systolic array.

[0073] However, when n=1 or m=1, the third cumulative value calculation units 431, 432, ..., 446 are formed as a one-dimensional systolic array.

[0074] The second accumulated value output unit 420 is formed above the third accumulated value output unit 430 , and the element value calculation unit 410 is formed on the side of the third accumulated value output unit 430 . Figure 4 The element value calculation unit 410 is illustrated as being formed on the left side of the third cumulative value output unit 430 , although it may be formed on the right side of the third cumulative value output unit 430 according to an embodiment.

[0075] The second cumulative value calculation units 421, 422, 423, 424 accumulate the second product values ​​obtained by multiplying each of the paired element values ​​of the second matrix. In addition, among the second cumulative value calculation units 421, 422, 423, 424, those units 421, 422, 423 except the rightmost unit 424 select and output one of the outputs of the adjacent second cumulative value calculation units 422, 423, 424 and the second multiplication cumulative value as the second cumulative value.

[0076] In addition, the rightmost second cumulative value calculation unit 424 outputs the second multiplication cumulative value to the second cumulative value calculation unit 423 on the left side thereof.

[0077] In addition, the third cumulative value calculation units 431, 432, ..., 446 each generate a first value obtained by adding one element value of the paired element values ​​of the first matrix to one element value of the paired element values ​​of the second matrix, generate a second value obtained by adding the other element value of the paired element values ​​of the first matrix to the other element value of the paired element values ​​of the second matrix, and accumulate a third product value obtained by multiplying the generated first value by the generated second value.

[0078] The third cumulative value calculation units 431, 432, ..., 446 except the rightmost third cumulative value calculation units 434, 438, 442, 446, that is, the remaining third cumulative value calculation units 431, 432, ..., 445 each select one of the output values ​​of their adjacent third cumulative value calculation units 43, 432, ..., 446 and the third multiplication cumulative values ​​to generate the selected one as the third cumulative value.

[0079] The third cumulative value calculating units 434 , 438 , 442 , 446 on the rightmost side output the third multiplication cumulative values ​​to the third cumulative value calculating units 433 , 437 , 441 , 445 on their left sides, respectively.

[0080] The row element value calculation units 411, 412, 413, 414 each accumulate first matrix element product values ​​obtained by multiplying pairs of element values ​​of the first matrix by each other, and respectively subtract the first matrix element multiplication cumulative value and the second cumulative value from the third cumulative value to generate a third matrix element value.

[0081] Figure 5 4 is a diagram of the internal configuration of the first-row element value calculation unit 411 , the leftmost second cumulative value calculation unit 421 , and the upper-left third cumulative value calculation unit 431 .

[0082] Reference Figure 4 and Figure 5 , the operations of the first row element value calculation unit 411, the leftmost second cumulative value calculation unit 421, and the upper left third cumulative value calculation unit 431 are described below.

[0083] The element value calculation unit 411 includes a second cumulative value storage unit 501 , a first multiplication unit 511 , a first accumulator 512 , an eleventh storage unit 513 , and a first summing unit 517 .

[0084] The element value calculation unit 411 accumulates first matrix element product values ​​obtained by multiplying pairs of element values ​​of the first matrix with each other, and subtracts the first matrix element product value and the second accumulated value accumulated by the first row element value calculation unit 411 from the third accumulated value generated by the third accumulated value calculation unit 431 corresponding in position to the first row element value calculation unit 411, respectively, to generate a third matrix element value.

[0085] The second accumulated value storage unit 501 stores the second accumulated value received from the second accumulated value output unit 420 .

[0086] The first multiplication unit 511 has its input terminal i 11 and i 12 The first element value x is received at 11 and the second element value x 12 The first multiplication unit 511 converts the input x 11 and x 12 are multiplied with each other to generate the first matrix element product value a1. 11 and i 12 The third element value x is received 13 and the fourth element value x14 After the first multiplication unit 511 adds the input x 13 and x 14 multiplied with each other to generate another first matrix element product value a2. Note that in the present disclosure, the subscripts of the matrix element values ​​may be such as in x ij With x i,j The two are used interchangeably to convey the same meaning, only the subscript is expressed differently.

[0087] The first accumulator 512 sequentially accumulates the first matrix element product values ​​a1 and a2 generated by the first multiplication unit 511 to generate a first matrix element multiplication cumulative value.

[0088] If the number of columns of the matrix X is 6, as in the case where the size of the matrix X is 4×6, 6×6, and 8×6, then the input terminals i and i of the first multiplication unit 511 are respectively input. 11 and i 12 The fifth element value x 15 and the sixth element value x 16 The first accumulator 512 performs multiplication on another pair of matrix X element values ​​to generate another first matrix element product value a3. In this case, the first accumulator 512 sequentially accumulates the first matrix element product values ​​a1, a2 and a3 generated by the first multiplication unit 511 to generate a first matrix element multiplication accumulation value.

[0089] The eleventh storage unit 513 stores the first matrix element multiplication accumulated value generated by the first accumulator 512. The first matrix element multiplication accumulated value stored in the eleventh storage unit 513 is used by the first summing unit 517 to calculate the element value of each row of the matrix Z.

[0090] The first summing unit 517 respectively subtracts the first matrix element multiplication cumulative value stored in the eleventh storage unit 513 and the second cumulative value stored in the second cumulative value storage unit 501 from the third cumulative value stored in the fourteenth storage unit 516 to generate a third matrix Z element value.

[0091] On the other hand, in order to allow the second accumulated value in the second accumulated value storage unit 501 to be transmitted to the second row element value calculation unit 412, a connecting line extends from the connecting cable between the second accumulated value storage unit 501 and the first summation unit 517 to the second accumulated value storage unit (not shown) of the second row element value calculation unit 412 located below the first row element value calculation unit 411.

[0092] The second row element value calculation unit 412 has the same components as those of the first row element value calculation unit 411. After receiving the matrix X element values ​​required to calculate the element values ​​of the second row of the Z matrix, the second row element value calculation unit 412 generates the element values ​​of the second row of the Z matrix using the second accumulated value stored in the second accumulated value storage unit (not shown) in the second row element value calculation unit 412 and the third accumulated value received from the adjacent third accumulated value calculation unit 435.

[0093] Although not shown here, there are continuous additional connection cables (not shown) formed in order to sequentially transmit the second accumulated value to the third row element value calculation unit 413 and the fourth row element value calculation unit 414 .

[0094] The configuration and operation of the second row element value calculation unit 412 , the third row element value calculation unit 413 , and the fourth row element value calculation unit 414 are similar to those of the first row element value calculation unit 411 , and no further description is provided.

[0095] The leftmost second accumulated value calculation unit 421 includes a second multiplication unit 521 , a second accumulator 522 , and a second selection unit 523 .

[0096] The leftmost second cumulative value calculation unit 421 accumulates second product values ​​obtained by multiplying each of the input pairs of element values ​​of the second matrix, and selects and outputs one of the output value of the adjacent second cumulative value calculation unit 422 and the accumulated second product value as the second cumulative value.

[0097] The second multiplication unit 521 has its input terminal i 21 and i 22 The first element value y is received at 11 and the second element value y 21 The paired matrix Y element value of the input y 11 and 21 multiplied to generate the second matrix element product value b1. 21 and i 22 The third element value y is received 31 and the fourth element value y 41 After the second multiplication unit 521 adds the input y 31 and 41 Multiply them to generate another second matrix element product value b2.

[0098] The second accumulator 522 sequentially accumulates the second matrix element product values ​​b1 and b2 generated by the second multiplication unit 521 to generate a second matrix element multiplication cumulative value.

[0099] If the number of rows of the matrix Y is 6, as in the case where the size of the matrix Y is 6×4, 6×6, and 6×8, then the input terminals i and i of the second multiplication unit 521 are respectively input. 21 and i 22 The fifth element value y 51 and the sixth element value y 61 The second accumulator 522 sequentially accumulates the second matrix element product values ​​b1, b2 and b3 generated by the second multiplication unit 521 to generate a second matrix element multiplication accumulation value.

[0100] The second selection unit 523 receives the second matrix element multiplication accumulation value generated by the second accumulator 522 and the multiplication accumulation value from the adjacent second accumulation value calculation unit 422, respectively, and selects and outputs one of the second matrix element multiplication accumulation value from the second accumulator 522 and the multiplication accumulation value received from the adjacent second accumulation value calculation unit 422 according to the value of the control input c0 to the second selection unit 523 as the second accumulation value stored in the second accumulation value storage unit 501.

[0101] It should be noted that when the value of the control input c0 is 0, the selected one is the second matrix element multiplication accumulation value generated by the second accumulator 522, and when the value of the control input c0 is 1, the selected one is the multiplication accumulation value received from the adjacent second accumulation value calculation unit 422.

[0102] The upper left third cumulative value calculation unit 431 includes a twelfth storage unit 514, a thirteenth storage unit 515, a fourteenth storage unit 516, a twenty-first storage unit 524, a twenty-second storage unit 525, a thirty-first adding unit 531, a thirty-second adding unit 532, a third multiplication unit 533, a third accumulator 534 and a third selecting unit 535.

[0103] The upper left third cumulative value calculation unit 431 is suitable for generating a first value by adding one element value of the pair of element values ​​of the input first matrix to one element value of the pair of element values ​​of the input second matrix, generating a second value by adding the other element value of the pair of element values ​​of the input first matrix to the other element value of the pair of element values ​​of the input second matrix, accumulating a third product value obtained by multiplying the first value and the second value, and selecting and generating one of the output value of the adjacent third cumulative value calculation unit 432 and the third multiplication cumulative value as the third cumulative value.

[0104] The twelfth storage unit 514 stores one of the paired matrix X element values, and the thirteenth storage unit 515 stores the other of the paired matrix X element values. 11 and x 12 As pairs of matrix X element values ​​are input to their input terminals i 11 and i 12 When , the twelfth storage unit 514 stores an element value x 11 , and the thirteenth storage unit 515 stores another element value x 12 .

[0105] The fourteenth storage unit 516 receives and stores the third cumulative value from the third selection unit 535. Here, the third cumulative value is selected by any one of the third selection units (not shown) of the third cumulative value calculation units 432, 433, and 434 existing in the same row as the upper left third cumulative value calculation unit 431 and the third selection unit 535 of the upper left cumulative value calculation unit 431, and is sequentially transmitted to the left until the third selection unit 535 outputs it to be stored in the fourteenth storage unit 516.

[0106] The twenty-first storage unit 524 stores one of the paired matrix Y element values, and the twenty-second storage unit 525 stores the other of the paired matrix Y element values. 11 and 21 When the matrix Y element values ​​are input as pairs, the twenty-first storage unit 524 stores an element value y 11 , and the twenty-second storage unit 525 stores another element value y 21 .

[0107] Furthermore, the data respectively stored in the twenty-first storage unit 524 and the twenty-second storage unit 525 are respectively output downward to the third cumulative value calculation unit 435 adjacent below at the twenty-first storage unit (not shown) and the twenty-second storage unit (not shown) thereof.

[0108] The thirty-first adding unit 531 receives one matrix X element value from the twelfth storage unit 514 and one matrix Y element value from the twenty-first storage unit 524 , and adds the one matrix X element value and the one matrix Y element to each other to generate a first value.

[0109] The thirty-second adding unit 532 receives another matrix X element value from the thirteenth storage unit 515 and another matrix Y element value from the twenty-second storage unit 525 , and adds the another matrix X element value and the another matrix Y element value to each other to generate a second value.

[0110] The third multiplication unit 533 multiplies the first value generated by the thirty-first addition unit 531 and the second value generated by the thirty-second addition unit 532 by each other to generate a third product value.

[0111] The third accumulator 534 accumulates the third product value generated by the third multiplication unit 533 .

[0112] The third selection unit 535 receives the third multiplication-accumulation value generated by the third accumulator 534 and the multiplication-accumulation value from the adjacent third accumulation-value calculation unit 432, respectively, and selects and outputs one of the third matrix element multiplication-accumulation value from the third accumulator 534 and the multiplication-accumulation value received from the adjacent third accumulation-value calculation unit 432 as the third accumulation value according to the value of the control input c0 to the third selection unit 535. The third accumulation value output from the third selection unit 535 is stored in the fourteenth storage unit 516.

[0113] In addition, the third selection unit 535 makes its selection to output the third accumulated value, which is subjected to the same control input c0 as the control input c0 input to the second selection unit 523 of the upper left third accumulated value calculation unit 431 present on the systolic array, which is located in the same column as the leftmost second accumulated value calculation unit 421.

[0114] Figure 6 is a diagram illustrating in detail the configuration of the second cumulative value calculation units 421 , 422 , 423 , 424 and the uppermost third cumulative value calculation units 431 , 432 , 433 , 434 , in which reference numerals indicate only some components essential for description and the remaining components are not numbered.

[0115] In view of the above description of the operation of the leftmost second cumulative value calculation unit 421 and the upper left third cumulative value calculation unit 431, no further description is provided of the operation of the remaining second cumulative value calculation units 422, 423, 424 and the remaining third cumulative value calculation units 432, 433 and 434. Instead, the data selection operation of the second selection units 523, 623, 624 and the third selection units 535, 635 and 636 is mainly described.

[0116] exist Figure 6 , when the control input c0 is 0, this causes the second selection unit 523 to select and output the multiplication accumulation value generated by the second accumulator 522 of the second accumulation value calculation unit 421 to the second accumulation value storage unit 501. The control input also causes the third selection unit 535 to select and output the multiplication accumulation value generated by the third accumulator 534 of the third accumulation value calculation unit 431 to the fourteenth storage unit 516.

[0117] When the value of c0 is 1, this causes the second selection unit 523 to select and output the multiplication accumulation value output from the second selection unit 623 of the second accumulation value calculation unit 422 to the second accumulation value storage unit 501. The control input also causes the third selection unit 535 to select and output the multiplication accumulation value generated by the third accumulator S21 of the third accumulation value calculation unit 432 to the fourteenth storage unit 516.

[0118] When the value of c1 is 0, this causes the second selection unit 623 to select and input the multiplication accumulation value generated by the second accumulator S11 of the second cumulative value calculation unit 422 to the second cumulative value calculation unit 421 at the second selection unit 523. This c1 value causes the third selection unit 635 of the third cumulative value calculation unit 432 to select and input the multiplication accumulation value generated by the third accumulator S21 of the third cumulative value calculation unit 432 to the third cumulative value calculation unit 431 at the third selection unit 535.

[0119] When the c1 value is 1, this causes the second selection unit 623 of the second cumulative value calculation unit 422 to select and input the multiplication accumulation value output from the second selection unit 624 of the second cumulative value calculation unit 423 to the second cumulative value calculation unit 421 at the second selection unit 523, and this causes the third selection unit 635 to select and input the multiplication accumulation value generated by the third accumulator S22 of the third cumulative value calculation unit 433 to the third cumulative value calculation unit 431 at the third selection unit 535.

[0120] When the c2 value is 0, this causes the second selection unit 624 to select and input the multiplication accumulation value generated by the second accumulator S12 of the second cumulative value calculation unit 423 to the second cumulative value calculation unit 422 at the second selection unit 623, and this causes the third selection unit 636 to select and input the multiplication accumulation value generated by the third accumulator S22 of the third cumulative value calculation unit 433 to the third cumulative value calculation unit 432 at the third selection unit 635.

[0121] When the c2 value is 1, this causes the second selection unit 624 to select and input the multiplication accumulation value generated by the second accumulator S13 of the second cumulative value calculation unit 424 to the second cumulative value calculation unit 422 at the second selection unit 623, and this causes the third selection unit 636 to select and input the multiplication accumulation value generated by the third accumulator S23 of the third cumulative value calculation unit 434 to the third cumulative value calculation unit 432 at the third selection unit 635.

[0122] Table 1 shows reference numbers of components that undergo a selection operation based on control input values ​​c0, c1, c2 to output accumulated values ​​for the first row element value calculation unit 411 to generate matrix Z element values.

[0123]

Table 1

[0124]

[0125] As shown in Table 1, when c0=0, without referring to the values ​​of c1 and c2, the multiplication accumulation value generated by the second accumulator 522 of the second cumulative value calculation unit 421 is selected by the second selection unit 523 and output to the second cumulative value storage unit 501, and the multiplication accumulation value generated by the third accumulator 534 of the third cumulative value calculation unit 431 is selected by the third selection unit 535 and output to the fourteenth storage unit 516.

[0126] When c0=1 and c1=0, without referring to the c2 value, the multiplication accumulation value generated by the second accumulator S11 of the second cumulative value calculation unit 422 is sequentially selected by the second selection unit 623 and the second selection unit 523 and output to the second cumulative value storage unit 501, and the multiplication accumulation value generated by the third accumulator S21 of the third cumulative value calculation unit 432 is sequentially selected by the third selection unit 635 and the third selection unit 535 and output to the fourteenth storage unit 516.

[0127] When c0=c1=1 and c2=0, the multiplication accumulation value generated by the second accumulator S12 of the second cumulative value calculation unit 423 is sequentially selected and output by the second selection unit 624, the second selection unit 623 and the second selection unit 523, and the multiplication accumulation value generated by the third accumulator S22 of the third cumulative value calculation unit 433 is sequentially selected and output to the fourteenth storage unit 516 by the third selection unit 636, the third selection unit 635 and the third selection unit 535.

[0128] When c0=c1=c2=1, the multiplication accumulation value generated by the second accumulator S13 of the second cumulative value calculation unit 424 is sequentially selected and output to the second cumulative value storage unit 501 by the second selection unit 624, the second selection unit 623 and the second selection unit 523, and the multiplication accumulation value generated by the third accumulator S23 of the third cumulative value calculation unit 434 is sequentially selected and output to the fourteenth storage unit 516 by the third selection unit 636, the third selection unit 635 and the third selection unit 535.

[0129] Therefore, the first row element value calculation unit 411 sequentially receives the corresponding third cumulative value and second cumulative value in response to the control input values ​​c0, c1, c2, thereby sequentially generating the matrix Z element value z 11 、z 12 、z 13 and z 14 .

[0130] Since the operation of the first row element value calculation unit 411 is similar to the operations of the remaining row element value calculation units 412, 413 and 414, no further description is provided about the processing performed by the remaining row element value calculation units 412, 413 and 414 to generate matrix Z element values.

[0131] In addition, Figure 5 In the embodiment, the seven storage units 501, 513, 514, 515, 516, 524, 525 can be implemented as, but not limited to, flip-flops, respectively, and the second selection unit 523 and the third selection unit 535 can be implemented as, but not limited to, multiplexers. In addition, since the operations of the flip-flops and the multiplexers are obvious to those skilled in the art, no further description is provided.

[0132] As described above, the computing device 400 according to at least one embodiment of the present disclosure is implemented such that the third cumulative value calculation units 431, 432, ..., 446 having a two-dimensional systolic array do not involve the subtraction operation required for calculating the element values ​​of the matrix Z. Instead, the subtraction operation circuit for calculating the element values ​​of the matrix Z is designed to be in each of the row element value calculation units 411, 412, 413, 414 like the first summing unit 517.

[0133] The third cumulative value calculation units 431, 432, ..., 446 arranged in a two-dimensional array are each provided with a single hardware element for performing a selection operation to replace the typical hardware necessary for performing two (-) operations, and instead, a (-) operation circuit is provided for each of the row element value calculation units 411, 412, 413, 414 having a one-dimensional structure, resulting in Figure 2 Compared to the conventional overall hardware design area in Figure 4 The overall hardware design area of ​​the computing device of the present disclosure is reduced.

[0134] In addition, there is no data path for transmitting the second accumulated value, which is the minuend generated by the second accumulated value output unit 420, between the second accumulated value output unit 420 and the third accumulated value output unit 430. Instead, an additional data path is formed in the second accumulated value output unit 420 from the right side toward the left side thereof and in the element value calculation unit 410 from the upper side toward the lower side thereof.

[0135] In this manner, the present disclosure allows the second cumulative value as the minuend generated by the second cumulative value output unit 420 to proceed along a route by means of the second cumulative value output unit 420 and the element value calculation unit 410 having a one-dimensional systolic array, which is similar to Figure 2 The number of transmission paths of the second accumulated value of the minuend is significantly reduced compared to the computing device 200. Therefore, when performing matrix multiplication by using the Winograd algorithm, Figure 4 The computing device 400 can be compared with Figure 2 The conventional computing device 200 is executed at a high speed.

[0136] Therefore, the present disclosure has a significant effect in terms of economy due to reduced hardware footprint, and also has a significant effect in terms of agility due to increased operation speed.

[0137] When designing the computing device 400 according to at least one embodiment of the present disclosure, this can be implemented to support multiple precisions, that is, multiple bit lengths.

[0138] The operation device 400 is designed to support multiple precisions by allowing the thirty-first adding unit 531 , the thirty-second adding unit 532 , the third multiplying unit 533 , and the third accumulator 534 in the third accumulated value calculating unit 431 to each work together on inputs of different bit lengths.

[0139] When matrix multiplication is performed with multiple precisions, hardware cost can be significantly reduced by an operation device for matrix multiplication when the operation device is implemented to support operations on input data of different precisions in addition to one precision of the input data.

[0140] Although this embodiment describes the case of supporting both 8-bit precision and 16-bit precision input data, it is applicable to various cases such as supporting both 16-bit precision and 32-bit precision input data.

[0141] There are two possible approaches to hardware design of a matrix multiplication device supporting multiple precisions: one is to process high-precision data in multiple cycles based on a hardware operator supporting low precision, and the other is to process multiple low-precision data in one cycle based on a hardware operator supporting high precision.

[0142] First, a method of processing multiple high-precision data in multiple cycles based on a hardware operator supporting low precision is described.

[0143] With the Winograd algorithm, 8-bit integer matrix data requires 9-bit integer multiplication when input, and 16-bit integer matrix data requires 17-bit integer multiplication when input. The 17-bit integer multiplication can be performed by using the 9-bit integer multiplication unit 4 times.

[0144] Figure 7 is a data flow diagram of a sum-product operation method (particularly, functions of a thirty-first adding unit 531 , a thirty-second adding unit 532 , a third multiplying unit 533 , and a third accumulator 534 of a third cumulative value calculating unit 431 ) according to at least one embodiment.

[0145] Please note, Figure 7The carry indication indicates whether a rounded bit occurs in the most significant digit when performing an addition operation. For example, the present disclosure may be implemented such that the carry value is set to 1 when rounding occurs in the most significant digit, and the carry value is set to 0 when rounding does not occur in the most significant digit.

[0146] Figure 8 According to at least one embodiment and implemented Figure 7 8 is a diagram of a data flow diagram of a sum-product operation device 800.

[0147] exist Figure 8 , the sum-product operation device 800 according to at least one embodiment includes an input division unit 810, a first addition unit 820, a second addition unit 830, a multiplication unit 840, and an accumulator 850. The third cumulative value calculation units 431, 432, 433, and 434 can be implemented by including the sum-product operation device 800 according to at least one embodiment.

[0148] As illustrated, the sum-product operation device 800 according to at least one embodiment of the present disclosure has a first addition unit 820 and a second addition unit 830 that are extended to process the sum operation of the matrix element input in units of 2N bits, and the first addition unit 820 and the second addition unit 830 are originally limited to provide the sum operation of the matrix element input in units of up to N bits instead of 2N bits. The case of N=8 is illustrated below.

[0149] The input division unit 810 includes an eleventh processor (unit) 811 , a twelfth processor 812 , a twenty-first processor 813 , and a twenty-second processor 814 .

[0150] The first adding unit 820 includes an eleventh selecting unit 821 , a twelfth selecting unit 822 , an eleventh adding unit 823 , a first carry storing unit 824 , and a first carry input unit 825 .

[0151] The second adding unit 830 includes a twenty-first selecting unit 831 , a twenty-second selecting unit 832 , a twenty-first adding unit 833 , a second carry storing unit 834 , and a second carry input unit 835 .

[0152] The multiplication unit 840 includes an addition and multiplication unit 841 , a multiplier selection unit 842 , and a multiplier multiplication unit 843 .

[0153] exist Figure 8 , the eleventh processing unit 811 receives the first input x as a 2N-bit (ie, 16-bit) long X matrix element. i,2k-1 Partition into high-order or high-N-bit partition bitmap and the low-order or low-N bits of the partition bitmap x i,2k-1 mod28 and outputs it to the eleventh selection unit 821.

[0154] The twelfth processing unit 812 converts the second input y as a 2N-bit length Y matrix element 2k,j Divide into high N bits partition bitmap and the lower N bits of the partition bitmap y 2k,j mod2 8 and outputs it to the twelfth selection unit 822.

[0155] The eleventh selection unit 821 receives and selectively outputs x according to the value of S0. i,2k-1 High-resolution bitmap and low partition bitmap x i,2k-1 mod2 8 For example, the eleventh selection unit 821 outputs the lower partition bitmap x in response to S0=0. i,2k-1 mod2 8 , and in response to S0=1, the high partition bitmap is output And it inputs the output to the eleventh adding unit 823.

[0156] The twelfth selection unit 822 selects a first matrix element value and a second matrix element value respectively through each of the selected partition bitmaps having equal ranks between the high partition bitmap and the low partition bitmap. In particular, the twelfth selection unit 822 receives and selectively outputs y respectively according to the value of S0. 2k,j High-resolution bitmap and low partition bitmap y 2k,j mod2 8 For example, the twelfth selection unit 822 outputs the lower partition bitmap y in response to S0=0. 2k, j mod2 8 , and in response to S0=1, the high partition bitmap is output And it inputs the output to the eleventh adding unit 823.

[0157] The eleventh adding unit 823 receives the output of the eleventh selecting unit 821 and the output of the twelfth selecting unit 822 and adds them to generate their added value. Here, the eleventh adding unit 823 receives the selection value of each partition bitmap having an equal rank between the high partition bitmap and the low partition bitmap from the eleventh selecting unit 821 and the twelfth selecting unit 822.

[0158] The twenty-first processing unit 813 converts the third input x as the other X matrix element of 2N bits in length into i,2k Divide into high N bits partition bitmap and the lower N bits of the partition bitmap x i,2kmod2 8 and outputs it to the twenty-first selection unit 831.

[0159] The twenty-second processing unit 814 converts the fourth input y as the other Y matrix element of 2N bits in length into 2k-1,j Divide into high N bits partition bitmap and the lower N bits of the partition bitmap y 2k-1,j mod2 8 and outputs it to the twenty-second selection unit 832.

[0160] The twenty-first selection unit 831 receives and selectively outputs x according to the value of S1. i,2k High-resolution bitmap and low partition bitmap x i,2k mod2 8 For example, the twenty-first selection unit 831 outputs the lower partition bitmap x in response to S1=0. i,2k mod2 8 , and in response to S1=1, the high partition bitmap is output And it inputs the output to the twenty-first adding unit 833.

[0161] The twenty-second selection unit 832 receives and selectively outputs y according to the value of S1. 2k-1,j High-resolution bitmap and low partition bitmap y 2k-1,j mod2 8 For example, the twenty-second selection unit 832 outputs the lower partition bitmap y in response to S1=0. 2k-1,j mod2 8 , and in response to S1=1, the high partition bitmap is output And it inputs the output to the twenty-first adding unit 833.

[0162] The twenty-first adding unit 833 receives the output of the twenty-first selecting unit 831 and the output of the twenty-second selecting unit 832 and adds them to generate their added value. Here, the twenty-first adding unit 833 receives the selection value of each partition bitmap having an equal rank between the high partition bitmap and the low partition bitmap from the twenty-first selecting unit 831 and the twenty-second selecting unit 832, respectively.

[0163] The addition and multiplication unit 841 multiplies the addition result from the eleventh addition unit 823 by the addition result from the twenty-first addition unit 833 to generate a multiplication result.

[0164] The multiplier selection unit 842 selects a multiplier corresponding to the addition result of the eleventh adding unit 823 and the addition result of the twenty-first adding unit 833 .

[0165] The multiplier multiplying unit 843 multiplies a product generated by multiplying the addition result of the eleventh adding unit 823 and the addition result of the twenty-first adding unit 833 by the multiplier selected from the multiplier selecting unit 842 to generate a second product value.

[0166] The accumulator 850 accumulates the second product value generated by the multiplier multiplication unit 843 .

[0167] The M0 / M1 value is determined according to whether the corresponding addition unit (e.g., the eleventh addition unit 823 and the twenty-first addition unit 833) operates as an (N+1)-bit integer addition unit or as an N-bit positive addition unit. For example, when the corresponding addition unit (e.g., the eleventh addition unit 823 and the twenty-first addition unit 833) needs to operate as an (N+1)-bit integer addition unit, that is, in the (N+1)-bit integer addition unit mode, the M0 / M1 value is set to 0, and when the corresponding addition unit (e.g., the eleventh addition unit 823 and the twenty-first addition unit 833) needs to operate as an N-bit positive addition unit, the M0 / M1 value is set to 1.

[0168] In the case where the M0 / M1 value is 0, which means that the corresponding adding units (e.g., the eleventh adding unit 823 and the twenty-first adding unit 833) operate in the (N+1)-bit integer adding unit mode, they generate an N-bit output value and a carry obtained from the sum of the N-bit input values, and input the generated N-bit output value and the sign value F to the addition and multiplication unit 841. Here, the sign value input to the addition and multiplication unit 841 refers to a result value obtained by performing an XOR operation on three input values ​​by an XOR (exclusive OR) operator, which is generated in the form of a sign value F of an (N+1)-bit output, as shown in the following Table 2. Here, the three input values ​​refer to the signs A and B of the two input values ​​for any related one adding unit (e.g., the eleventh adding unit 823 and the twenty-first adding unit 833) and the carry C generated as a result of the 8-bit addition operation of the related this adding unit (e.g., the eleventh adding unit 823 and the twenty-first adding unit 833).

[0169]

Table 2

[0170] A B C F 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1

[0171] In the case where the M0 / M1 value is 1, which means that the corresponding adding units (eg, the eleventh adding unit 823 and the twenty-first adding unit 833) operate in the N-bit positive adding unit mode, they generate an N-bit output value and a carry obtained from the sum of the N-bit input values.

[0172] In the case where the corresponding addition units (for example, the eleventh addition unit 823 and the twenty-first addition unit 833) which means that the U0 / U1 value is 1 perform addition of the lower N bits, they store the carries thus generated in memories such as triggers, respectively, and then use the carries as carry inputs for the addition units themselves when they experience S0 / S1=1.

[0173] Figure 8 The flag values ​​such as S0 / S1, M0 / M1, and U0 / U1 determined according to the precision and multiplication processing cycle of the corresponding adding units (e.g., the eleventh adding unit 823 and the twenty-first adding unit 833) are shown. The flag values ​​S0 / S1, M0 / M1, and U0 / U1 may be set as shown in Table 3.

[0174] The settings of S0 / S1, M0 / M1, and U0 / U1 values ​​are not limited to those shown in Table 3, and may be variously set according to the embodiment.

[0175]

Table 3

[0176]

[0177] Fig. 9 is a replacement Figure 5 1 is a diagram of a configuration of a multiplication device of a first multiplication unit 511 or a second multiplication unit 521 for performing multiplication on two 2N-bit input data items after division into N-bit units.

[0178] like Fig. 9 As shown in , the multiplication device 900 according to the first embodiment includes a first input division unit 911, a second input division unit 912, a first selection unit 913, a second selection unit 914, a first sign extension unit 915, a second sign extension unit 916, a first multiplication unit 917, a multiplier selection unit 918 and a multiplier multiplication unit 919.

[0179] The following describes a case where the multiplication device 900 according to the first embodiment is employed as the first multiplication unit 511 .

[0180] As illustrated, the multiplication device 900 according to this embodiment has a first multiplication unit 917 that is extended to process multiplication of matrix element inputs in units of 2N bits, and the first multiplication unit 917 is originally limited to provide multiplication operations for matrix element inputs in units of up to N bits instead of 2N bits. The case of N=8 is illustrated below.

[0181] In the following, reference will be made to Figure 5 and Fig. 9 The operation of the multiplication device 900 according to the first embodiment will be described together.

[0182] The first input division unit 911 divides the first input x as a 2N-bit length X matrix element. i,2k-1 Divide into high N bits partition bitmap and the lower N bits of the partition bitmap x i,2k-1 mod2 8 and outputs it to the first selection unit 913.

[0183] The second input division unit 912 converts the second input x as another 2N-bit-long X matrix element i,2k Divide into high N bits partition bitmap and the lower N bits of the partition bitmap x i,2k mod2 8 and outputs it to the second selection unit 914.

[0184] The first selection unit 913 receives and selectively outputs x from the first input division unit 911 according to the value of S0. i,2k-1 For example, in case of S0=0, the first selection unit 913 outputs the low partitioning bitmap, and in case of S0=1, it outputs the high partitioning bitmap, and it inputs the output to the first symbol extension unit 915.

[0185] After receiving the control input of S1 value, the second selection unit 914 receives and selectively outputs x i,2kj For example, in case of S1=0, the second selection unit 914 outputs the low partitioning bitmap, and in case of S1=1, it outputs the high partitioning bitmap, and it inputs the output to the second symbol extension unit 916.

[0186] In the case of M0=0, the first sign extension unit 915 adds the sign value of the N-bit high partitioning bitmap input to the first sign extension unit 915 to the front of the N-bit high partitioning bitmap, thereby generating and inputting (N+1)-bit data in the form of [high partitioning bitmap sign value, N-bit high partitioning bitmap] to the first multiplication unit 917. In the case of M0=1, the first sign extension unit 915 generates and inputs (N+1)-bit data in the form of [0, N-bit high partitioning bitmap] to the first multiplication unit 917.

[0187] In the case of M1=0, the second sign extension unit 916 adds the sign value of the N-bit high division bitmap input to the second sign extension unit 916 to the front of the N-bit high division bitmap, thereby generating and inputting (N+1)-bit data in the form of [high division bitmap sign value, N-bit high division bitmap] to the first multiplication unit 917. In the case of M1=1, the second sign extension unit 916 generates and inputs (N+1)-bit data in the form of [0, N-bit high division bitmap] to the first multiplication unit 917.

[0188] The first multiplication unit 917 multiplies the (N+1)-bit data received from the first sign extension unit 915 and the (N+1)-bit data received from the second sign extension unit 916 to generate a multiplication result.

[0189] The multiplier selection unit 918 selects a multiplier corresponding to the (N+1)-bit data received from the first sign extension unit 915 and the (N+1)-bit data received from the second sign extension unit 916. For example, the multiplier selection unit 918 selects 1 as the multiplier in the case of {S0, S1} = {0, 0} and selects 2 as the multiplier in the case of {S0, S1} = {0, 1}. 8 As the multiplier, select 2 when {S0, S1} = {1, 0} 8 As the multiplier, and in the case of {S0, S1} = {1, 1}, select 2 16 As a multiplier.

[0190] The multiplier multiplication unit 919 multiplies the multiplication result obtained by multiplying the (N+1)-bit data received from the first sign extension unit 915 by the (N+1)-bit data received from the second sign extension unit 916 by the multiplier selected by the multiplier selection unit 918 to generate and send a first product value to the second accumulator 522.

[0191] In addition, the multiplication device 900 according to the first embodiment is adopted as the second multiplication unit 521, wherein the input matrix Y element values ​​input to the first input division unit 911 and the second input division unit 912 can imitate the operation process after the input matrix X element values ​​are input to the first input division unit 911 and the second input division unit 912, so no further description is provided.

[0192] Fig.10 is a diagram of a sum-product operation device 1000 according to at least one embodiment, which is a device required to calculate matrix multiplication by combining a plurality of matrix element values ​​into a single data. Fig.10 It is another embodiment that realizes the functions of the thirty-first adding unit 531 , the thirty-second adding unit 532 , the third multiplying unit 533 , and the third accumulator 534 of the third cumulative value calculating unit 431 .

[0193] Refer to the following Fig.10 and Fig.11 Another approach to designing a matrix multiplication apparatus that supports multiple precisions based on hardware operators that support high precision processing multiple low precision data items in one cycle is described. This embodiment describes a design method for processing 4 pairs of N-bit matrix elements at a time by extending a hardware unit that processes 2 pairs of 2N-bit matrix elements at a time using a Winograd algorithm.

[0194] exist Fig.10 , the sum-product operation device 1000 according to at least one embodiment includes a plurality of pre-processing units (devices) 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, a plurality of selection units 1021, 1022, 1023, 1024, 1025, a first adding unit 1031, a second adding unit 1032, a third adding unit 1033, a multiplication unit 1040, and an accumulator 1050. The third cumulative value calculation units 431, 432, 433, 434 can each be implemented by including this embodiment of the sum-product operation device 1000.

[0195] Note that the sum-product operation device 1000 according to this embodiment of the present disclosure exemplifies a configuration for providing a sum-product operation performed on inputs in units of N bits. The following exemplifies a case where N=16.

[0196] The first preprocessor 1011 receives an N-bit-long input matrix Y element value Y 2k,j and store it in the first bitmap, and convert the N-bit matrix element value y 2k,j The sign bit of the first bitmap is copied to the (N+1)th bit of the first bitmap to generate a sign-extended first bitmap of (N+1) bits in length {SignExt(y 2k,j )}. Here, when N is 16, the length of the first bitmap of the sign-extended (N+1)-bit length becomes 17 bits.

[0197] The second pre-processor 1012 receives two N / 2-bit-long input matrix Y element values ​​y 4k,j and 4k-2,j and store it in the second bitmap, and convert the N / 2-bit matrix element value y 4k-2,j The sign bit of the bitmap is copied and inserted into the (N / 2+1)th bit of the second bitmap to generate a (N / 2+1)-bit length SignExt(y 4k-2,j ), thereby generating a second bitmap {y 4k,j ,SignExt(y 4k-2,j )}. Here, {y4 k,j ,SignExt(y 4k-2,j )} is the y entered 4k,j and y as sign-extended 4k-2,j {SignExt(y 4k-2,j )} in the order of the bitmap.

[0198] The third pre-processor 1013 receives an N-bit-long input matrix X element value x i,2k-1 and store it in the third bitmap, and convert the N-bit matrix element value x i,2k-1The sign bit of the third bitmap is copied to the (N+1)th bit of the third bitmap to generate a sign-extended third bitmap {SignExt(x i,2k-1 )}.

[0199] The fourth pre-processor 1014 receives two N / 2-bit-long input matrix X element values ​​x i,4k-1 and x i,4k-3 and store it in the fourth bitmap, and convert the N / 2-bit matrix element value x i,4k-3 The sign bit of the bitmap is copied and inserted into the (N / 2+1)th bit of the fourth bitmap to generate a (N / 2+1)-bit length SignExt(x i,4k-3 ), thereby generating a fourth bitmap {x i,4k-1 ,SignExt(x i,4k-3 )}. Here, {x i,4k-1 ,SignExt(x i,4k-3 )} is the x entered i,4k-1 and x as sign extension i,4k-3 {SignExt(x i,4k-3 )} in the order of the bitmap.

[0200] The fifth pre-processor 1015 receives an N-bit-long input matrix Y element value y 2k-1,j and store it in the fifth bitmap, and the N-bit matrix element value y 2k-1,j The sign bit of the fifth bitmap is copied to the (N+1)th bit of the fifth bitmap to generate a sign-extended fifth bitmap {SignExt(y 2k-1,j )}.

[0201] The sixth pre-processor 1016 receives two N / 2-bit-long input matrix Y element values ​​y 4k-1,j and 4k-3,j and store it in the sixth bitmap, and convert the N / 2-bit matrix element value y 4k-3,j The sign bit of the y is copied and inserted into the (N / 2+1)th bit of the sixth bitmap to generate a (N / 2+1)-bit length SignExt(y 4k-3,j ), thereby generating a sixth bitmap {y 4k-1,j ,SignExt(y 4k-3,j )}. Here, {y 4k-1,j ,SignExt(y 4k-3,j )} is to press y 4k-1,j and y as sign-extended 4k-3,j {SignExt(y 4k-3,j )} in the order of the bitmap.

[0202] The seventh preprocessor 1017 receives the input element value x of the N-bit matrix Xi,2k and store it in the seventh bitmap, and convert the N-bit matrix element value x i,2k The sign bit of the seventh bitmap is copied to the (N+1)th bit of the seventh bitmap to generate a sign-extended seventh bitmap {SignExt(x i,2k )}.

[0203] The eighth pre-processor 1018 receives two N / 2-bit-long input matrix X element values ​​x i,4k and x i,4k-2 and store it in the eighth bitmap, and convert the N / 2-bit matrix element value x i,4k-2 The sign bit of the digit is copied and inserted into the (N / 2+1)th bit of the eighth bitmap to generate a (N / 2+1)-bit length SignExt(x i,4k-2 ), thereby generating the eighth bitmap {x i,4k ,SignExt(x i,4k-2 )}. Here, {x i,4k ,SignExt(x i,4k-2 )} is to press x i,4k and x as sign extension i,4k-2 {SignExt(x i,4k-2 )} in the order of the bitmap.

[0204] Here, when N is 16, the lengths of the first to eighth bitmaps are all (N+1) equal to 17 bits.

[0205] It should be noted that regarding the input of the matrix element value in the N / 2 bit mode, for example, the fourth pre-processor 1014 receives the matrix element value in the form of {x i,1 , x i,3}、{x i,5 , x i,7}、{x i,9 , x i,11}, and the eighth pre-processor 1018 receives the matrix element values ​​input in the order of {x i,2 , x i,4}、{x i,6 , x i,8}、{x i,10 , x i,12}The matrix element values ​​entered in order.

[0206] The first selection unit 1021 , the second selection unit 1022 , the third selection unit 1023 , the fourth selection unit 1024 , and the fifth selection unit 1025 operate differently according to each input S value.

[0207] In response to the S value being input as 0, the first selection unit 1021 selects the first bitmap {SignExt(y 2k,j)} and the second bitmap {y 4k,j ,SignExt(y 4k-2,j )} select the first bitmap {SignExt(y 2k,j )} and input it to the first addition unit 1031.

[0208] In response to the S value being input as 0, the second selection unit 1022 selects the third bit map {SignExt(x i,2k-1 )} and the fourth bitmap {x i,4k-1 ,SignExt(x i,4k-3 )} select the third bitmap {SignExt(x i,2k-1 )} and input it to the first addition unit 1031.

[0209] In response to the S value being input as 0, the third selection unit 1022 selects the fifth bitmap {SignExt(y 2k-1,j )} and the sixth bitmap {y 4k-1,j ,SignExt(y 4k-3),j )} input selects the fifth bitmap of input {SignExt(y 2k-1,j )} and input it to the second adding unit 1032.

[0210] In response to the S value being input as 0, the fourth selection unit 1022 selects the seventh bitmap {SignExt(x i,2k )} and the eighth bitmap {x i,4k ,SignExt(x i,4k-2 )} select the seventh bitmap {SignExt(x i,2k )} and input it to the second adding unit 1032.

[0211] On the other hand, when the S value is 1, the first selection unit 1021 and the second selection unit 1022 respectively select and input the second bitmap {y 4k,j ,SignExt(y 4k-2,j )} and the fourth bitmap {x i,4k-1 ,SignExt(x i,4k-3 )}.

[0212] On the other hand, when the S value is 1, the third selection unit 1023 and the fourth selection unit 1024 respectively select and input the sixth bitmap {y 4k-1,j ,SignExt(y 4k-3,j )} and the eighth bitmap {x i,4k ,SignExt(x i,4k-2 )}.

[0213] The first adding unit 1031 and the second adding unit 1032 to be described below may each be implemented as a duplex adding unit, and detailed configurations thereof are obvious to those skilled in the art, and thus no further description related to the configuration is provided.

[0214] When the S value is 0, the first adding unit 1031 adds the first bitmap {SignExt(y 2k,j )} and the third bitmap {SignExt(x i,2k-1 )} are added together and input into the multiplication unit 1040.

[0215] When the S value is 0, the second adding unit 1032 adds the fifth bitmap {SignExt(y 2k-1,j )} and the seventh bitmap {SignExt(x i,2k )} are added and input to the multiplication unit 1040.

[0216] In the case where the S value is 0, the first adding unit 1031 and the second adding unit 1032 perform (N+2)-bit addition.

[0217] When the S value is 1, the first adding unit 1031 adds the second bitmap {y 4k,j ,SignExt(y 4k-2,j )} and the fourth bitmap {x i,4k-1 ,SignExt(x i,4k-3 )} are added and input to the multiplication unit 1040.

[0218] When the S value is 1, the second adding unit 1032 adds the sixth bitmap {y 4k-1,j ,SignExt(y 4k-3,j )} and the eighth bitmap {x i,4k ,SignExt(x i,4k-2 )} are added and input to the multiplication unit 1040.

[0219] In the case where the S value is 1, the first addition unit 1031 and the second addition unit 1032 divide each of the two input bitmaps into half and perform (N / 2+1)-bit addition twice. For example, the first addition unit 1031 adds y as the corresponding high-order data item of the second bitmap and the fourth bitmap. 4k,j and x i,4k-1 Add to provide the high-order addition result, which will be used as the SignExt(y 4k-2,j ) and SignExt(x i,4k-3) are added to provide a low-order addition result, and the high-order addition result and the low-order addition result are input to the multiplication unit 1040. In addition, the second addition unit 1032 generates y by adding the corresponding high-order data items of the sixth bitmap and the eighth bitmap. 4k-1,j and x i,4k The high-order addition result obtained by adding the high-order addition result is used as the SignExt(y 4k-3,j ) and SignExt(x i,4k-2 ) are added to provide a low-order addition result, and the high-order addition result and the low-order addition result are input to the multiplication unit 1040.

[0220] Hereinafter, the multiplication unit 1040 to be described may be implemented as a duplex multiplication unit, and its detailed configuration is obvious to those skilled in the art, so further description on the configuration is not provided.

[0221] In the case where the S value is 0, the multiplication unit 1040 performs 18-bit multiplication to output a 36-bit multiplication result, and inputs the result to the fifth selection unit 1025. Specifically, the multiplication unit 1040 multiplies the addition result of the first addition unit 1031 when the S value is 0 and the addition result of the second addition unit 1032 when the S value is 0 by each other to input the multiplication result to the fifth selection unit 1025.

[0222] In the case where the S value is 1, the multiplication unit 1040 performs two 9-bit multiplications, outputs two 18-bit multiplication results, and inputs them to the third addition unit 1033. For example, when the S value is 1, the multiplication unit 1040 multiplies the high-bit addition result from the first addition unit 1031 and the high-bit addition result from the second addition unit 1032 to output an 18-bit output as a first multiplication result, multiplies the low-bit addition result from the first addition unit 1031 and the low-bit addition result from the second addition unit 1032 to output another 18-bit output as a second multiplication result, and inputs the first multiplication result and the second multiplication result to the third addition unit 1033.

[0223] The third adding unit 1033 inputs a result of adding the first multiplication result and the second multiplication result from the multiplication unit 1040 to the fifth selecting unit 1025 .

[0224] In the case where the S value is 0, the fifth selection unit 1025 outputs the 36-bit multiplication result input from the multiplication unit 1040 to the accumulator 1050 .

[0225] In the case where the S value is 1, the fifth selection unit 1025 outputs the result input from the third addition unit 1033 to the accumulator 1050 .

[0226] It should be noted that although the third cumulative value calculation unit 431 can be implemented to include the sum-product operation device 1000 according to this embodiment, its first preprocessor 1011, second preprocessor 1012, fifth preprocessor 1015, sixth preprocessor 1016, first selection unit 1021 and third selection unit 1023 components can be implemented to be located in the first cumulative value calculation unit 421.

[0227] In addition, the third preprocessor 1013 , the fourth preprocessor 1014 , the seventh preprocessor 1017 , the eighth preprocessor 1018 , the second selection unit 1022 , and the fourth selection unit 1024 may be implemented to be located in the first row element value calculation unit 411 .

[0228] Fig.11 . . of the row element value calculation units 411 , 412 , 413 , 414 and the second multiplication units 521 , . . . of the corresponding second cumulative value calculation units 421 , 422 , 423 , 424 according to the second embodiment.

[0229] The following describes an example case in which the multiplication device 1100 according to the second embodiment is employed as the first multiplication units 511 , . . . of the row element value calculation units 411 , 412 , 413 , 414 .

[0230] The multiplication device 1100 according to the second embodiment includes a plurality of preprocessors 1111 , 1112 , 1113 , 1114 , a plurality of selection units 1121 , 1122 , 1123 , a multiplication unit 1130 , and an addition unit 1140 .

[0231] The first preprocessor 1111 receives an N-bit-long input matrix X element value x i,2k-1 and store it in the first bitmap, and replace the element value x i,2k-1 The sign bit of the first bitmap is copied to the (N+1)th bit of the first bitmap, thereby generating a (N+1)-bit length sign-extended first bitmap {SignExt(x i,2k-1 )}.

[0232] The second preprocessor 1112 receives two N / 2-bit-long input matrix X element values ​​x i,4k-1 and x i,4k-3 and store it in the second bitmap, and convert an N / 2-bit matrix element value x i,4k-3 The sign bit of the bitmap is copied and inserted into the (N / 2+1)th bit of the second bitmap to generate a (N / 2+1)-bit length SignExt(x i,4k-3 ), thereby generating a second bitmap {x i,4k-1 ,SignExt(xi,4k-3 )}.

[0233] The third preprocessor 1113 receives an N-bit-long input matrix X element value x i,2k and store it in the third bitmap, and convert the N-bit matrix element value x i,2k The sign bit of the third bitmap is copied to the (N+1)th bit of the third bitmap to generate a sign-extended third bitmap {SignExt(x i,2k )}.

[0234] The fourth preprocessor 1114 receives two N / 2-bit-long input matrix X element values ​​x i,4k and x i,4k-2 and stores it in the fourth bitmap, and converts an N / 2-bit matrix element value x i,4k-2 The sign bit of the bitmap is copied and inserted into the (N / 2+1)th bit of the fourth bitmap to generate a (N / 2+1)-bit length SignExt(x i,4k-2 ), thereby generating a fourth bitmap {x i,4k ,SignExt(x i,4k-2 )}.

[0235] The first selection unit 1121 , the second selection unit 1122 , and the third selection unit 1023 operate differently according to each input S value.

[0236] When the S value is 0, the first selection unit 1121 selects the first bitmap {SignExt(x i,2k-1 )} and the second bitmap {x i,4k-1 ,SignExt(x i,4k-3 )} select the first bitmap {SignExt(x i,2k-1 )} and input it to the multiplication unit 1130.

[0237] When the S value is 0, the second selection unit 1122 selects the third bitmap {SignExt(x i,2k )} and the fourth bitmap {x i,4k ,SignExt(x i,4k-2 )} select the third bitmap {SignExt(x i,2k )} and input it to the multiplication unit 1130.

[0238] On the other hand, when the S value is 1, the first selection unit 1121 and the second selection unit 1122 respectively select and input the second bitmap {x i,4k-1 ,SignExt(x i,4k-3 )} and the fourth bitmap {x i,4k ,SignExt(xi,4k-2 )}.

[0239] The multiplication unit 1130 described below may be implemented as a duplex multiplication unit.

[0240] The multiplication unit 1130 may be implemented as a duplex multiplication unit, and its detailed configuration will be apparent to those skilled in the art, so no further description is provided.

[0241] When the S value is 0, the multiplication unit 1130 multiplies the selection result from the first selection unit 1121 and the selection result from the second selection unit 1122 , and inputs the multiplication result to the selection unit 1123 .

[0242] In the case where the S value is 1, the multiplication unit 1130 performs two 9-bit multiplications, outputs two 18-bit multiplication results, and inputs them to the addition unit 1140. Specifically, when the S value is 1, the multiplication unit 1130 adds the second bitmap {x i,4k-1 ,SignExt(x i,4k-3 )} high data x i,4k and the fourth bitmap {x i,4k ,SignExt(x i,4k-2 )} high data x i,4k multiply each other to provide a first multiplication result. In addition, the multiplication unit 1130 adds the second bitmap {x i,4k-1 ,SignExt(x i,4k-3 )}'s low-order data SignExt(x i,4k-3 ) and the fourth bitmap {x i,4k ,SignExt(x i,4k-2 )}'s low-order data SignExt(x i,4k-2 ) are multiplied with each other to provide a second multiplication result. The multiplication unit 1130 inputs the generated first multiplication result and the second multiplication result to the addition unit 1140.

[0243] The adding unit 1140 inputs a result of adding the first multiplication result and the second multiplication result from the multiplication unit 1130 to the third selecting unit 1123 .

[0244] In the case where the S value is 0, the third selection unit 1123 outputs the multiplication result input from the multiplication unit 1130 to the accumulator 512 .

[0245] In the case where the S value is 1, the third selection unit 1123 outputs the result input from the addition unit 1140 to the accumulator 512 .

[0246] In the case where the multiplication device 1100 according to the second embodiment is used as the second multiplication units 521, ... of the corresponding second cumulative value calculation units 421, 422, 423 and 424, the first preprocessor 1111, the second preprocessor 1112, the third preprocessor 1113 and the fourth preprocessor 1114 receive inputs of other matrix Y element values ​​as follows.

[0247] For example, the first preprocessor 1111 receives an N-bit-long input matrix Y element value y 2k,j And generate the first bit map of the sign extension of (N+1) bits in length {SignExt(y 2k,j )}.

[0248] The second preprocessor 1112 receives two N / 2-bit-long input matrix Y element values ​​y 4k,j and 4k-2,j , and generate a second bitmap {y 4k,j ,SignExt(y 4k-2,j )}.

[0249] The third preprocessor 1113 receives the N-bit-long input matrix Y element value y 2k-1,j And generate a (N+1)-bit length sign-extended third bitmap {SignExt(y 2k-1,j )}.

[0250] The fourth pre-processor 1114 receives two N / 2-bit-long input matrix Y element values ​​y 4k-1,j and 4k-3,j And generate a fourth bitmap {y 4k-1,j ,SignExt(y 4k-3,j )}.

[0251] In addition, the multiplication device 1100 according to the second embodiment is used as the second multiplication units 521, ... of the corresponding second cumulative value calculation units 421, 422, 423, 424, wherein the input matrix Y element values ​​input to the first preprocessor 1111, the second preprocessor 1112, the third preprocessor 1113 and the fourth preprocessor 1114 can follow the operation process after the input matrix X element values ​​are input to the first preprocessor 1111, the second preprocessor 1112, the third preprocessor 1113 and the fourth preprocessor 1114, and therefore no further description is provided.

[0252] Although the exemplary embodiments of the present disclosure have been described for illustrative purposes, it will be appreciated by those skilled in the art that various modifications, additions and substitutions may be made without departing from the concept and scope of the claimed invention. Therefore, for the sake of brevity, the exemplary embodiments of the present disclosure have been described. The scope of the technical concept of these embodiments is not limited by the examples. Therefore, it will be understood by those of ordinary skill that the scope of the claimed invention is not limited by the embodiments explicitly described above, but by the claims and their equivalents.

[0253] Reference Number

[0254] 200: Matrix multiplication device

[0255] 210: first computing unit 211, 212, 213, 214: X element processing units

[0256] 220: second operation unit 221, 222, 223, 224: Y element processing unit

[0257] 230: third operation unit 231, 232, ..., 246: Z element processing unit

[0258] 311: eleventh storage unit 312: twelfth storage unit

[0259] 313: thirteenth storage unit 314: first multiplication unit

[0260] 321: 21st storage unit 322: 22nd storage unit

[0261] 323: 23rd storage unit 324: 2nd multiplication unit

[0262] 331: first adding unit 332: second adding unit

[0263] 333: Third multiplication unit 334: Accumulation operation unit

[0264] 400: Computing equipment

[0265] 410: element value calculation unit 411, 412, 413, 414: row element value calculation unit

[0266] 420: second cumulative value output unit 421, 422, 423, 424: second cumulative value calculation unit

[0267] 430: third cumulative value output unit 431, 432, ..., 446: third cumulative value calculation unit

[0268] 501: Second accumulated value storage unit

[0269] 511: first multiplication unit 512: first accumulator

[0270] 513: eleventh storage unit 514: twelfth storage unit

[0271] 515: 13th storage unit 516: 14th storage unit

[0272] 517: First summing unit 521: Second multiplication unit

[0273] 522: second accumulator 523, 623, 624: second selection unit

[0274] 524: 21st storage unit 525: 22nd storage unit

[0275] 531: thirty-first adding unit 532: thirty-second adding unit

[0276] 533: third multiplication unit 534: third accumulator

[0277] 535, 635, 636: third selection unit 800, 1000: sum-product computing device

[0278] 810: Input division unit 820: First addition unit

[0279] 830: second adding unit 840: multiplying unit

[0280] 850: Accumulator 900: Multiplication device

[0281] 911: first input division unit 912: second input division unit

[0282] 913: first selection unit 914: second selection unit

[0283] 915: first symbol extension unit 916: second symbol extension unit

[0284] 917: First multiplication unit 918: Multiplier selection unit

[0285] 919: Multiplier multiplication unit

[0286] 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018: Preprocessor

[0287] 1021, 1022, 1023, 1024, 1025: Select unit

[0288] 1031: first addition unit 1032: second addition unit

[0289] 1033: third adding unit 1040: multiplying unit

[0290] 1050: accumulator 1100: multiplication device

[0291] 1111, 1112, 1113, 1014: Preprocessor

[0292] 1121, 1122, 1123: Select unit

[0293] 1130: Multiplication unit 1140: Addition unit

[0294] S11, S12, S13, S21, S22, S23, S23: Accumulator

[0295] CROSS-REFERENCE TO RELATED APPLICATIONS

[0296] This application claims priority under U.S. patent law to Patent Application No. 10-2019-0077200 filed in Korea on June 27, 2019, the entire contents of which are incorporated herein by reference. In addition, this non-provisional application claims priority in countries other than the United States for the same reasons as the above Korean Patent Application, the entire contents of which are hereby incorporated by reference.

Claims

1. A computing device for performing operations based on a Winograd algorithm for multiplying a first matrix by a second matrix to generate a third matrix, the computing device comprising: a second cumulative value output unit having a plurality of second cumulative value calculation units, one of the plurality of second cumulative value calculation units being configured to accumulate second product values ​​obtained by multiplying each of the paired element values ​​of the second matrix, select one of the output value of the adjacent second cumulative value calculation unit and the accumulated second product value as the second cumulative value, and output the second cumulative value; a third cumulative value output unit, the third cumulative value output unit having a plurality of third cumulative value calculation units, one of the plurality of third cumulative value calculation units being configured to generate a first value obtained by adding one element value of a pair of element values ​​of the first matrix to one element value of a pair of element values ​​of the second matrix, generate a second value obtained by adding the other element value of the pair of element values ​​of the first matrix to the other element value of the pair of element values ​​of the second matrix, accumulate a third product value obtained by multiplying the first value by the second value, select one of an output value of an adjacent third cumulative value calculation unit and the accumulated third product value as a third cumulative value, and output the third cumulative value; as well as An element value calculation unit, the element value calculation unit having one or more row element value calculation units, one of the one or more row element value calculation units being configured to accumulate element product values ​​of the first matrix obtained by multiplying each of the pair of element values ​​of the first matrix, and calculate element values ​​of the third matrix by respectively subtracting the accumulated element product values ​​of the first matrix and the second accumulated value from the third accumulated value.

2. The computing device according to claim 1, wherein: The one third cumulative value calculating unit corresponds in position to the one second cumulative value calculating unit and the one row element value calculating unit.

3. The computing device according to claim 2, wherein: The plurality of third cumulative value calculation units are formed in a two-dimensional systolic array, and the plurality of second cumulative value calculation units and the one or more row element value calculation units are each formed in a one-dimensional systolic array.

4. The computing device according to claim 3, wherein: The plurality of second cumulative value calculation units are formed above the plurality of third cumulative value calculation units, and the one or more row element value calculation units are formed on the sides of the plurality of third cumulative value calculation units.

5. The computing device according to claim 1, further comprising: A second cumulative value storage unit is configured to store the second cumulative value output from the second cumulative value output unit.

6. The computing device according to claim 5, wherein: The second accumulated value storage unit is located between the second accumulated value output unit and the one or more row element value calculation units.

7. The computing device according to claim 5, wherein: The one row element value calculation unit is configured to calculate an element value of the third matrix by using the second accumulated value stored in the second accumulated value storage unit.

8. The computing device according to claim 1, wherein: The one row element value calculation unit is configured to sequentially generate element values ​​of rows among the rows of the third matrix and corresponding to positions of the one or more row element value calculation units.

9. The computing device according to claim 8, wherein: The one row element value calculation unit is configured to receive the third accumulated value transferred from the adjacent third accumulated value calculation unit in order to calculate the element value of the third matrix.

10. The computing device according to claim 2, wherein: The third cumulative value calculation unit includes: an input division unit, a first addition unit, a second addition unit, a multiplication unit, and an accumulator, and wherein the input partitioning unit is configured to partition each of a bitmap representing an element value of the first matrix, a bitmap representing an element value of the second matrix, a bitmap representing another element value of the first matrix, and a bitmap representing another element value of the second matrix into a high partitioning bitmap and a low partitioning bitmap in units of N bits, wherein the N bits are a bit length at an input terminal of the first adding unit, The first adding unit is configured to add the one element value of the first matrix and the one element value of the second matrix to each other for each of the selected partition bitmaps having an equal rank between the high partition bitmap and the low partition bitmap, The second adding unit is configured to selectively add the other element value of the first matrix and the other element value of the second matrix to each other for each of the selected partition bitmaps having an equal rank between the high partition bitmap and the low partition bitmap, The multiplication unit is configured to calculate the third product value by multiplying the addition result of the first addition unit and the addition result of the second addition unit, and The accumulator is configured to generate the third accumulated value by accumulating the third product values ​​calculated by the multiplication unit.

11. The computing device according to claim 2, wherein: The third cumulative value calculation unit includes: four preprocessors, a first adding unit, a second adding unit, a multiplication unit, a third adding unit and an accumulator, and The preprocessors are each configured to receive a pair of matrix element values ​​having a length of N bits, place one element value of the pair of matrix element values ​​in a high bitmap on a bitmap having a preset length, place the other element value of the pair of matrix element values ​​in a low bitmap on a bitmap having a preset length, and extend the sign of the element value located in the low bitmap by copying the sign bit of the other element value to the (N+1)th bit on the bitmap having the preset length, so as to generate bitmap data having a length of (2N+1) bits, wherein N is a natural number, The first adding unit is configured to add data generated by two preprocessors among the four preprocessors on the bitmap having a preset length to each other to generate a first result value, The second adding unit is configured to add the data generated on the bitmap having the preset length and by the other two preprocessors among the four preprocessors to each other to generate a second result value, The multiplication unit is configured to multiply a value corresponding to the upper bitmap of the first result value and a value corresponding to the upper bitmap of the second result value by each other to generate an eleventh product value, and to multiply a value corresponding to the lower bitmap of the first result value and a value corresponding to the lower bitmap of the second result value by each other to generate a twelfth product value, The third adding unit is configured to add the eleventh product value and the twelfth product value to each other to generate the third product value, and The accumulator is configured to accumulate the third product value.

12. The computing device according to claim 1, wherein: The one or more row element value calculation units each include: A multiplication unit configured to divide the paired element values ​​of the first matrix into high bit groups and low bit groups, respectively, to sequentially select one bit group of the paired element values ​​of the first matrix and another bit group of the paired element values ​​of the first matrix in combination, and multiply the two bit groups with each other to generate a combined product value, and sequentially multiply the combined product value with a multiplier corresponding to the selected combination to generate the element product value of the first matrix.

13. The computing device according to claim 1, wherein: The one or more row element value calculation units each include: a first preprocessor configured to form the first bitmap by copying the first element of the first matrix to a high bit group of a first bitmap and copying the sign of the second element of the first matrix and the second element to a low bit group of the first bitmap, respectively; a second preprocessor configured to form a second bitmap by copying a third element of the first matrix to a high bit group of a second bitmap and copying a sign of a fourth element of the first matrix and the fourth element to a low bit group of the second bitmap, respectively; a multiplication unit configured to multiply the upper bit group of the first bitmap and the upper bit group of the second bitmap by each other to generate a first multiplication result, and to multiply the lower bit group of the first bitmap and the lower bit group of the second bitmap by each other to generate a second multiplication result; and An adding unit is configured to add the first multiplication result and the second multiplication result to each other to generate a first matrix element product value.

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