Integrated assembly having vertically spaced channel material segments and method of forming an integrated assembly

Abstract

Some embodiments include a vertically stacked NAND memory array having alternating insulating levels and conductive levels. The conductive levels include terminal regions and include non-terminal regions adjacent to the terminal regions. The terminal regions are thicker in a vertical direction than the non-terminal regions and are configured as segments that are vertically stacked on top of and vertically spaced from each other. Blocks are adjacent to the segments and have an approximately the same vertical thickness as the segments. The blocks include a high dielectric constant material, a charge blocking material, and a charge storage material. A channel material extends vertically along the stack and is adjacent to the blocks. Some examples include an integrated assembly. Some embodiments include a method of forming the integrated assembly.

Description

[0001] Relevant patent data

[0002] This application claims priority to U.S. Patent Application No. 16 / 548,471, filed on August 22, 2019, entitled "Integrated Assemblies Having Vertically-Spaced Channel Material Segments, and Methods of Forming Integrated Assemblies", the entire disclosure of which is incorporated herein by reference. Field of the Invention

[0003] Integrated assemblies (e.g., integrated NAND memories) having vertically-spaced channel material segments, and methods of forming integrated assemblies. Background of the Invention

[0004] Memory provides data storage for electronic systems. Flash memory is a type of memory and has many uses in modern computers and devices. For example, a modern personal computer may have a BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to use flash memory in solid state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and provides the ability to remotely upgrade the device to improve features.

[0005] NAND can be the basic architecture of flash memory and can be configured to include vertically stacked memory cells.

[0006] Before specifically describing NAND, it may be helpful to more generally describe the relationship of the memory array within an integrated arrangement. FIG. 1 shows a block diagram of a prior art device 1000 that includes a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns, access lines 1004 (e.g., word lines WL0 to WLm that conduct signals), and first data lines 1006 (e.g., bit lines BL0 to BLn that conduct signals). The access lines 1004 and the first data lines 1006 can be used to transfer information to and from the memory cells 1003. A row decoder 1007 and a column decoder 1008 decode address signals A0 to AX on an address line 1009 to determine which memory cells 1003 are to be accessed. A sense amplifier circuit 1015 operates to determine the value of the information read from the memory cells 1003. An I / O circuit 1017 transfers the value of the information between the memory array 1002 and input / output (I / O) lines 1005. Signals DQ0 to DQN on the I / O lines 1005 can represent the value of the information read from or written to the memory cells 1003. Other devices can communicate with the device 1000 via the I / O lines 1005, the address line 1009, or control lines 1020. A memory control unit 1018 is used to control memory operations performed on the memory cells 1003 and utilizes signals on the control lines 1020. The device 1000 can receive supply voltage signals Vcc and Vss on a first supply line 1030 and a second supply line 1032, respectively. The device 1000 includes a selection circuit 1040 and an input / output (I / O) circuit 1017. The selection circuit 1040 can select signals on the first data lines 1006 and second data lines 1013 that can represent the value of the information read from or programmed into the memory cells 1003 in response to signals CSEL1 to CSELn via the I / O circuit 1017. The column decoder 1008 can selectively activate the CSEL1 to CSELn signals based on the A0 to AX address signals on the address line 1009. During read and program operations, the selection circuit 1040 can select signals on the first data lines 1006 and second data lines 1013 to provide communication between the memory array 1002 and the I / O circuit 1017.

[0007] The memory array 1002 of FIG. 1 can be a NAND memory array, and FIG. 2 shows a schematic diagram of a three-dimensional NAND memory device 200 that can be used for the memory array 1002 of FIG. 1. The device 200 includes a plurality of strings of charge storage devices. In a first direction (Z-Z'), each string of charge storage devices can include, for example, 32 charge storage devices stacked on top of each other, where each charge storage device corresponds to one of, for example, 32 layers (e.g., layer 0 to layer 31). The charge storage devices of a corresponding string can share a common channel region, such as a region formed in a corresponding pillar of a semiconductor material (e.g., polysilicon), and the strings of charge storage devices are formed around the pillar. In a second direction (X-X'), each of a plurality of first groups (e.g., 16 first groups) of strings can include, for example, 8 strings that share a plurality of (e.g., 32) access lines (i.e., "global control gate (CG) lines", also referred to as word lines (WL)). Each of the access lines can be coupled to charge storage devices within a layer. When each charge storage device includes a cell capable of storing two information bits, the charge storage devices logically grouped by the same access line (and thus corresponding to the same layer) can be grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. In a third direction (Y-Y'), each of a plurality of second groups (e.g., 8 second groups) of strings can include 16 strings coupled to corresponding ones of 8 data lines. The size of a memory block can include 1,024 pages and a total of approximately 16 MB (e.g., 16 WL x 32 layers x 2 bits = 1,024 pages / block, block size = 1,024 pages x 16 KB / page = 16 MB). The number of strings, layers, access lines, data lines, first groups, second groups, and / or pages can be greater than or less than the numbers shown in FIG. 2.

[0008] FIG. 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of FIG. 2 in the X-X' direction, and the memory block 300 includes 15 strings of charge storage devices in one of the 16 first groups of strings described with reference to FIG. 2. The plurality of strings of the memory block 300 can be grouped into a plurality of subsets 310, 320, 330 (e.g., strip columns) (e.g., strip column I , strip column J and strip column K), where each subset (e.g., a block column) includes a "partial block" of the memory block 300. The global source - side select gate (SGD) line 340 can be coupled to the SGDs of multiple strings. For example, the global SGD line 340 can be coupled to multiple (e.g., 3) sub - SGD lines 342, 344, 346 via corresponding ones of multiple (e.g., 3) sub - SGD drivers 332, 334, 336, where each sub - SGD line corresponds to a respective subset (e.g., a block column). Each of the sub - SGD drivers 332, 334, 336 can simultaneously couple or disconnect the SGDs of the strings of the corresponding partial block (e.g., a block column) independently of the SGDs of the strings of other partial blocks. The global source - side select gate (SGS) line 360 can be coupled to the SGSs of multiple strings. For example, the global SGS line 360 can be coupled to multiple sub - SGS lines 362, 364, 366 via corresponding ones of multiple sub - SGS drivers 322, 324, 326, where each sub - SGS line corresponds to a respective subset (e.g., a block column). Each of the sub - SGS drivers 322, 324, 326 can simultaneously couple or disconnect the SGSs of the strings of the corresponding partial block (e.g., a block column) independently of the SGSs of the strings of other partial blocks. The global access line (e.g., the global CG line) 350 can be coupled to the charge storage devices of the corresponding layers of each of the multiple strings. Each global CG line (e.g., the global CG line 350) can be coupled to multiple sub - access lines (e.g., sub - CG lines) 352, 354, 356 via corresponding ones of multiple sub - string drivers 312, 314, and 316. Each of the sub - string drivers can simultaneously couple or disconnect the charge storage devices corresponding to the respective partial block and / or layer independently of the charge storage devices of other partial blocks and / or other layers. The charge storage devices corresponding to the respective subset (e.g., partial block) and the respective layer can include a "partial layer" of the charge storage devices (e.g., a single "block"). The strings corresponding to the respective subset (e.g., partial block) can be coupled to corresponding ones of the sub - sources 372, 374, and 376 (e.g., "block sources"), where each sub - source is coupled to a respective power supply.

[0009] Alternatively, the NAND memory device 200 is described with reference to the schematic diagram of FIG. 4.

[0010] The memory array 200 includes word lines 2021 to 202 N and bit lines 2281 to 228 M .

[0011] The memory array 200 also includes NAND strings 2061 to 206 M . Each NAND string includes charge storage transistors 2081 to 208 N。A charge storage transistor can store charge using a floating gate material (e.g., polysilicon), or can store charge using a charge trapping material (e.g., silicon nitride, metal nanodots, etc.).

[0012] The charge storage transistor 208 (e.g., charge storage transistors 2081 to 280 N ) is located at the intersection of the word line 202 (e.g., word lines 2021 to 202 N ) and the string 206 (e.g., NAND strings 2061 to 206 M ). The charge storage transistor 208 represents a non-volatile memory cell for data storage. The charge storage transistor 208 of each NAND string 206 is connected in series from source to drain between a source selection device (e.g., a source side select gate (SGS)) 210 (e.g., source selection devices 2101 to 210 M ) and a drain selection device (e.g., a drain side select gate (SGD)) 212 (e.g., drain selection devices 2121 to 212 M ). Each source selection device 210 is located at the intersection of the string 206 and the source selection line 214, and each drain selection device 212 is located at the intersection of the string 206 and the drain selection line 215. The selection devices 210 and 212 can be any suitable access devices, and are generally illustrated by boxes in FIG. 4.

[0013] The source of each source selection device 210 is connected to the common source line 216. The drain of each source selection device 210 is connected to the source of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the drain of the source selection device 2101 is connected to the source of the charge storage transistor 2081 of the corresponding NAND string 2061. The source selection device 210 is connected to the source selection line 214.

[0014] The drain of each drain selection device 212 is connected to a bit line (i.e., a digital line) 228 (e.g., bit lines 2281 to 228 M ) at a drain contact. For example, the drain of the drain selection device 2121 is connected to the bit line 2281. The source of each drain selection device 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the source of the drain selection device 2121 is connected to the drain of the charge storage transistor 208 N of the corresponding NAND string 2061.

[0015] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The charge storage transistor 208 couples its control gate 236 to the word line 202. The columns of the charge storage transistors 208 are the transistors within the NAND string 206 that are coupled to a given bit line 228. The rows of the charge storage transistors 208 are the transistors that are commonly coupled to a given word line 202.

[0016] There is a desire to develop an improved NAND architecture and an improved method for manufacturing the NAND architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1 shows a block diagram of a prior art memory device having a memory array with memory cells.

[0018] FIG. 2 shows a schematic diagram of the prior art memory array of FIG. 1 in the form of a 3D NAND memory device.

[0019] FIG. 3 shows a cross-sectional view of the prior art 3D NAND memory device of FIG. 2 in the X-X' direction.

[0020] FIG. 4 is a schematic diagram of a prior art NAND memory array.

[0021] Figure 5 and 6 is a diagrammatic cross-sectional side view of a region of an integrated assembly shown in example sequential process stages of an example method for forming an example NAND memory array.

[0022] Figure 6A is Figure 6 a diagrammatic top view of a portion of the integrated assembly.

[0023] Figures 7 to 14 is a Figure 5 diagrammatic cross-sectional side view of a region of an integrated assembly shown in example sequential process stages of an example method for forming an example NAND memory array. Figure 7 The process stage of Figure 6 is after the process stage of

[0024] Figure 14A is a Figure 14 diagrammatic cross-sectional top view along line A-A of

[0025] Figure 15 is an alternative Figure 14 diagrammatic cross-sectional side view of a region of an integrated assembly shown in example process stages.

[0026] Figure 16 is an alternative Figure 14 diagrammatic cross-sectional side view of a region of an integrated assembly shown in example process stages. Detailed implementation manners

[0027] The operation of a NAND memory cell includes the movement of charges between a channel material and a charge storage material. For example, the programming of a NAND memory cell may include causing charges (i.e., electrons) to move from the channel material into the charge storage material and then storing the charges within the charge storage material. The erasure of a NAND memory cell may include causing holes to move into the charge storage material to recombine with the electrons stored in the charge storage material and thereby releasing the charges from the charge storage material. The charge storage material may include a charge trapping material (e.g., silicon nitride, metal dots, etc.). A problem with conventional NANDs may be that the charge trapping material extends across multiple memory cells of a memory array, and this may lead to charge migration from one memory cell to another. Charge migration may cause data retention problems. Some embodiments include a NAND architecture having breaks in the charge trapping material in the regions between memory cells; and such breaks may advantageously impede the migration of charges between memory cells. Refer to Figures 5 to 16 Describe exemplary embodiments.

[0028] Refer to Figure 5 , the structure (integrated assembly, integrated structure) 10 includes a vertical stack 12 of alternating first tier 14 and second tier 16. The first tier 14 includes a first material 60, and the second tier 16 includes a second material 62. The first and second materials may include any suitable compositions and have different compositions from each other. In some embodiments, the first material 60 may include silicon dioxide, consist essentially of silicon dioxide, or consist of silicon dioxide; and the second material 62 may include silicon nitride, consist essentially of silicon nitride, or consist of silicon nitride. The tiers 14 and 16 may have any suitable thickness; and may be the same thickness as each other or may be different thicknesses from each other. In some embodiments, the tiers 14 and 16 may have a vertical thickness in the range from about 10 nanometers (nm) to about 400 nm. In some embodiments, the tiers 14 and 16 may have a thickness in the range from about 10 nm to about 50 nm.

[0029] Stack 12 is shown as being supported above substrate 18. Substrate 18 may include semiconductor material; and may include, for example, single-crystalline silicon, consist essentially of single-crystalline silicon, or consist of single-crystalline silicon. Substrate 18 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any structure including a semiconductive material, including (but not limited to) bulk semiconductive material such as a semiconductive wafer (alone or in an assembly including other materials) and a layer of semiconductive material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including (but not limited to) the semiconductor substrates described above. In some applications, substrate 18 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

[0030] A gap is provided between stack 12 and substrate 18 to indicate that other components and materials may be provided between stack 12 and substrate 18. Such other components and materials may include additional levels of the stack, source line levels, source-side select gates (SGS), etc.

[0031] Reference Figure 6 , an opening 64 is formed to extend through stack 12. Opening 64 has sidewalls 65 that extend along first material 60 and second material 62. When viewed from above (as Figure 6A shown), opening 64 may have a closed shape (circular, oval, polygonal, etc.), and Figure 6 the sidewalls 65 shown in the cross-section of Figure 6A may be part of a single continuous sidewall that extends around the closed shape of opening 64 (as Figure 6 shown). Opening 64 may represent a large number of substantially identical openings that are formed at a process stage of

[0032] Reference Figure 7 , a third material 66 is formed along sidewalls 65 of opening 64. Third material 66 lines opening 64 and narrows the opening. Third material 66 may include any suitable composition; and in some embodiments may include one or more of boron, germanium, and silicon (e.g., polysilicon), consist essentially of one or more of them, or consist of one or more of them. In embodiments where the third material includes polysilicon, carbon (and / or other materials) may be incorporated into the polysilicon to improve the polysilicon's resistance to etching utilized in subsequent process steps.

[0033] The dielectric barrier material 28, the charge blocking material 34, the charge storage material 38, the charge path material (gate dielectric material) 42, the channel material 44, and the insulating material 46 are formed within the narrowed opening 64. In some embodiments, the materials 28, 34, 38, 42, 44, and 46 may be considered to be formed adjacent to each other and extending perpendicularly through the stack 12.

[0034] The dielectric barrier material 28 may be a high-k material. The term "high-k" means a dielectric constant greater than that of silicon dioxide. In some embodiments, the dielectric barrier material 28 may include one or more of aluminum oxide (AlO), hafnium oxide (HfO), hafnium silicate (HfSiO), zirconium oxide (ZrO), and zirconium silicate (ZrSiO), consist essentially of one or more of them, or consist of one or more of them; where the chemical formula indicates the main component rather than a specific stoichiometry.

[0035] The charge blocking material 34 may include any suitable composition; and in some embodiments, may include one or both of silicon oxynitride (SiON) and silicon dioxide (SiO2), consist essentially of one or both of them, or consist of one or both of them.

[0036] The charge storage material 38 may include any suitable composition. In some embodiments, the charge storage material 38 may include a charge trapping material; such as, for example, silicon nitride, silicon oxynitride, conductive nanodots, etc. For example, in some embodiments, the charge storage material 38 may include silicon nitride, consist essentially of silicon nitride, or consist of silicon nitride. In alternative embodiments, the charge storage material 38 may be configured to include a floating gate material (such as, for example, polysilicon).

[0037] The charge path material (gate dielectric material, tunneling material) 42 may include any suitable composition. In some embodiments, the charge path material 42 may include one or more of, for example, silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, etc. The charge path material 42 may be bandgap engineered to achieve the desired electrical properties; and thus, may include a combination of two or more different materials.

[0038] The channel material 44 includes a semiconductor material; and may include any suitable composition or combination of compositions. For example, the channel material 44 may include one or more of silicon, germanium, III / V semiconductor materials (such as, for example, gallium phosphide), semiconductor oxides, etc.; where the term III / V semiconductor material refers to a semiconductor material including elements selected from Group III and Group V of the periodic table (where Group III and Group V are the old nomenclature and are now referred to as Group 13 and Group 15). In some embodiments, the channel material 44 may include silicon, consist essentially of silicon, or consist of silicon.

[0039] The insulating material 46 may include any suitable composition; and in some embodiments may include silica, consist essentially of silica, or consist of silica.

[0040] In Figure 7 the illustrated embodiment, the channel material 44 is configured to surround an annular ring of the insulating material 46. This configuration of the channel material may be considered to include a hollow channel configuration, where the insulating material 46 is provided within the "hollow" of the annular-ring-shaped channel configuration. In other embodiments (not shown), the channel material may be configured as a solid strut configuration.

[0041] Referring Figure 8 , a second material 62 ( Figure 7 ) is removed to leave a void 68. The void 68 may be referred to as a first void to distinguish it from other voids formed at a later process stage.

[0042] A region (portion) 72 of the material 66 along the second tier 16 is exposed through the void 68. Other regions (portions) 70 of the material 66 along the first tier 14 are not exposed through the void 68. In some embodiments, the regions 70 and 72 may be referred to as a first region and a second region, respectively.

[0043] Referring Figure 9 , an exposed region 72 of the third material 66 (i.e., the portion of the third material along the second tier 16) is converted to a conductive fourth material 74. In the illustrated embodiment, some of the third material 66 along the first tier 14 (i.e., some portions 70 of the third material 66) is also converted to the fourth material 74. The remaining region of the third material 66 is a plug 76, which is approximately vertically centered along the first tier 14. The fourth material 74 may have any suitable horizontal dimension D1 along the Figure 9 cross-section of ; and in some embodiments may have a horizontal dimension D1 in the range from about 1 nm to about 10 nm.

[0044] The conductive material 74 may include any suitable composition; and in some embodiments, may include one or more metals (e.g., one or more of cobalt, molybdenum, nickel, ruthenium, tantalum, titanium, and tungsten), consist essentially of the one or more metals, or consist of the one or more metals.

[0045] One or more metal precursors flowing into void 68 can be utilized to form conductive material 74. The metal precursor can be a metal halide material and / or a metal organic material. In some embodiments, conductive material 74 can include tungsten, consist essentially of tungsten, or consist of tungsten; and can be formed using a precursor including a tungsten halide (e.g., tungsten hexafluoride (WF6)). As another example, conductive material 74 can include titanium, consist essentially of titanium, or consist of titanium; and can be formed using a precursor including a titanium halide (e.g., titanium tetrachloride (TiCl4)). The metal precursor can be utilized under any suitable reaction conditions; and in some embodiments, the metal precursor can be utilized at a temperature of at least about 300 °C and a pressure of about atmospheric pressure. In some embodiments, the third material 66 can include silicon (e.g., polysilicon), consist essentially of silicon, or consist of silicon, and the metal precursor can react with this silicon to form conductive material 74.

[0046] Conductive material 74 can be a pure metal or can include one or more non-metal components. In some embodiments, conductive material 74 can include a metal and can additionally include one or more of boron, carbon, nitrogen, oxygen, and silicon. Thus, the one or more metals within conductive material 74 can exist as metal borides, metal carbides, metal nitrides, metal silicides, and / or metal oxides. Metal nitrides can be formed by incorporating a nitriding (nitrogen doping) species (e.g., NH3) during the formation of material 74, along with the metal precursor; and / or by including nitrogen within material 66. Metal oxides can be formed by incorporating an oxidizing species (e.g., O2 and / or O3) during the formation of material 74, along with the metal precursor and / or by including oxygen within material 66. Metal carbides can be formed by incorporating a carbon-containing species (e.g., a carbon halide) during the formation of material 74, along with the metal precursor and / or by including carbon within material 66. Metal borides can be formed by incorporating a boron-containing species (e.g., B2H6) with the metal precursor during the formation of material 74 and / or by including boron within material 66. Metal silicides can be formed by incorporating a silicon-containing species (e.g., silane) during the formation of material 74, along with the metal precursor and / or by including silicon within material 66.

[0047] In some embodiments, conductive material 74 can include one or more of TiSi, TiSiN, W, WSiN, and WN, consist essentially of one or more of them, or consist of one or more of them; where the chemical formula indicates the main component rather than a specific stoichiometry.

[0048] Reference Figure 10 , a conductive structure 22 is formed in void 68 ( Figure 9) Inside. The conductive structure 22 includes conductive materials 24 and 26. The conductive materials 24 and 26 can include any suitable conductive composition; for example (by way of example), one or more of various metals (such as, titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (such as, metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (such as, conductively doped silicon, conductively doped germanium, etc.). The conductive materials 24 and 26 are different from each other in composition. In some embodiments, the core material 24 can include one or more metals (such as, can include tungsten), and the outer conductive material 26 can include one or more metal nitrides (such as, can include titanium nitride). Although the conductive structure 22 is shown as including two materials, in other embodiments, the conductive structure can include more than two materials or only include a single material.

[0049] The conductive structure 22 directly contacts the conductive material 74; and in the illustrated embodiment, the outer conductive material 26 (such as, titanium nitride) directly contacts the conductive material 74.

[0050] Reference Figure 11 , the first material 60 ( Figure 10 ) is removed to form a second void 78.

[0051] Reference Figure 12 , the remaining region of the third material 66 ( Figure 11 ) is removed to form a gap 80. The conductive fourth material 74 can be considered configured as segments 82, where such segments are vertically stacked on top of each other and are vertically spaced from each other by the intervening gap 80. In some embodiments, the gap 80 can be considered an access port extending through the conductive material 74.

[0052] The gap 80 can have any suitable vertical thickness (vertical dimension) T1; and in some embodiments, this vertical thickness can be in the range from about 1 nm to about 20 nm.

[0053] The conductive structure 22 and the conductive segments 74 directly adjacent to such conductive structures can be considered a conductive layer (i.e., Figure 12 the layer 16 can be a conductive layer including the structure 22 and the segments 74). In some embodiments, the conductive layer can be considered a NAND word line layer.

[0054] Each of the conductive layers 16 includes a terminal region 84 and a non-terminal region 86 adjacent to the terminal region. The terminal region 84 corresponds to the conductive segments 82, and the non-terminal region 86 corresponds to the conductive structure 22.

[0055] The terminal region 84 is thicker in the vertical direction than the non-terminal region 86. In the illustrated embodiment, the terminal region 84 has a vertical thickness (vertical dimension) T2, and the non-terminal region 86 has a vertical thickness T3. In some embodiments, the vertical thickness T2 will be greater than the vertical thickness T3 by an amount in the range of from about 10% to about 90% of T3.

[0056] In some embodiments, the terminal region 84 may include the same composition as the region of the conductive structure 22 that is directly adjacent to such terminal region. For example, in some embodiments, the conductive material 74 of the terminal region 84 may include titanium nitride, and the conductive material 26 of the non-terminal region 86 may also include titanium nitride. In other embodiments, the terminal region 84 may include a composition different from the region of the conductive structure 22 that is directly adjacent to such terminal region. For example, in some embodiments, the conductive material 26 of the non-terminal region 86 may include titanium nitride, consist essentially of titanium nitride or consist of titanium nitride; and the conductive material 74 of the terminal region 84 may include one or more of TiSi, TiSiN, W, WSiN, and WN, consist essentially of one or more of them or consist of one or more of them; where the chemical formula indicates the main component rather than a specific stoichiometry.

[0057] In Figure 12 the illustrated embodiment, the non-terminal region 86 is substantially vertically centered relative to the terminal region 84 along each of the conductive levels 16. The term "substantially vertically centered" means vertically centered within reasonable manufacturing and measurement tolerances.

[0058] Reference Figure 13 , the gap 80 extends through the dielectric barrier material 28, the charge blocking material 34, and the charge storage material 38 to form blocks 88 that include the materials 28, 34, and 38. The blocks 88 are vertically spaced from each other by the intervening gap 80. The blocks have a vertical thickness that is substantially the same as the vertical thickness T2 of the segments 82 of the conductive material 74; where the term "substantially the same" means the same within reasonable manufacturing and measurement tolerances.

[0059] In the illustrated embodiment, each of the blocks 88 has a substantially horizontal top surface 83 and a substantially horizontal bottom surface 85 (where the term "substantially horizontal" means horizontal within reasonable manufacturing and measurement tolerances). Figure 13 The cross-sectional view of

[0060] In some embodiments, the dielectric barrier material 28 within block 88 may be considered configured as the first segment 20, the charge blocking material 34 within block 88 may be considered configured as the second segment 36, and the charge storage material within block 88 may be considered configured as the third segment 40. The first segment 20, the second segment 36, and the third segment 40 may be considered to have first, second, and third vertical thicknesses, respectively; where such first, second, and third vertical thicknesses are approximately the same as each other and approximately the same as the vertical thickness T2 of the terminal region 84 (where the term "approximately the same" means the same within reasonable manufacturing and measurement tolerances).

[0061] In Figure 13 the illustrated embodiment, the gap 80 does not penetrate the tunneling material 42. Thus, the tunneling material 42 and the channel material 44 remain as linear structures that vertically extend through the alternating layers 14 and 16. In other embodiments (described below with respect to Figure 16 ), the gap 80 may extend through the tunneling material 42.

[0062] Referring to Figure 14 , an insulating material 90 is formed within the void 78 ( Figure 13 ). The insulating material 90 may include any suitable composition; and in some embodiments may include silicon dioxide, consist essentially of silicon dioxide, or consist of silicon dioxide. The insulating material 90 may be referred to as the fifth material to distinguish it from the first, second, third, and fourth materials 60, 62, 66, and 74 described above.

[0063] Figure 14 The layers 14 and 16 of

[0064] may be considered alternating insulating and conductive layers (e.g., NAND word line layers), respectively.

[0064] The NAND memory cell 52 includes a dielectric barrier material 28, a charge blocking material 34, a charge storage material 38, a gate dielectric material 42, and a channel material 44. The illustrated NAND memory cell 52 forms part of a vertically extending string of memory cells. This string may represent a large number of substantially identical NAND strings formed during the fabrication of a NAND memory array (where the term "substantially identical" means the same within reasonable manufacturing and measurement tolerances).

[0065] Each of the NAND memory cells 52 includes a control gate region 54 adjacent to the dielectric barrier material 28; where the control gate region includes a terminal region 84 of the conductive layer 16. The control gate region 54 includes a control gate similar to the control gates described above with respect to FIGS. 1 - 4. The conductive layer 16 includes a region 58 adjacent to (near) the control gate region 54. The region 58 may be referred to as the second region or the word line region; and includes a non - terminal region 86 of the conductive layer.

[0066] In Figure 14In an embodiment, the control gate region 54 can be considered to include a front surface 57 facing the dielectric barrier material 28. Such a front surface has approximately the same vertical thickness as materials 28, 34, and 38. Thus, the entire charge storage material 38 of the memory cell 52 can be along the front surface 57 of the control gate region 54 associated with this memory cell. This enables the charge in the charge storage region to be well controlled through the associated control gate region 54. Similarly, the vertical extension 82 of the control gate region (i.e., the terminal segment 84) enables the control gate region to be wider (thicker) in the vertical direction than the word line region 58 adjacent to such a control gate region. Compared with what can be achieved when the control gate region is maintained at the same vertical thickness as the word line region 58, a wider control gate region in the vertical direction and a narrower word line region in the vertical direction may be able to couple a larger amount of the charge storage material 38 to the control gate region, such that the word line region 58 can be vertically spaced apart by a greater distance compared with what can be achieved when the word line region is maintained at the same vertical thickness as the control gate region 54. The relatively large vertical spacing between the word line regions 58 can advantageously reduce the capacitive coupling between vertically adjacent word line regions.

[0067] Figure 14A Shows a cross-section along Figure 14 line A-A, and shows a representative segment 82 of the conductive material 74 extending completely around the materials 28, 34, 38, 42, 44, and 46 of the memory cell 52. Similarly, Figure 14A The view shows that the block 88 of materials 28, 34, and 38 is an annular ring (toroidal shape) that extends around the channel material 44 (and in the illustrated embodiment, also around the tunneling material 42).

[0068] Figure 14 and 14A An advantage of the configuration of

[0069] In Figure 14 the embodiment, the void 78 ( Figure 13 ) is completely filled with the insulating material 90. In other embodiments, the void may be only partially filled with this insulating material.

[0070] Figure 15 Shows a configuration similar to Figure 14 the configuration, but in which the void 78 is only partially filled with the insulating material 90. Thus, a portion of the void 78 remains within the insulating layer 14. The remaining portion of the void 78 is covered by the insulating material 90. The void 78 can be filled with air or any other suitable gas.

[0071] Figure 15The configuration (i.e., the configuration having voids within the insulating layer 14) has the advantage that this can mitigate capacitive coupling when capacitive coupling between vertically adjacent materials is found to be a problem.

[0072] As discussed above with respect to Figure 13 In some embodiments, the gap 80 may extend through the tunneling material 42 in addition to extending through the materials 28, 34, and 38. Thus, the tunneling material 42 may be incorporated into the block 88. Figure 16 Shows an embodiment similar to Figure 14 but where the block 88 also includes the tunneling material (charge access material, gate dielectric material) 42.

[0073] The channel material 44 is "flat" (i.e., has a substantially continuous thickness and is substantially vertically straight) in the Figures 14 to 16 configuration, rather than undulating. A flat channel material can positively affect the string current as compared to a non-flat configuration. In some embodiments, the configuration of the channel material 44 may be referred to as a "flat configuration". It is noted that the segments 40 of the charge storage material 38 are also "flat"; and can be considered to be in a "flat configuration" each (marked as segments 40 in Figure 13 ). A flat segment 40 may have a favorable charge distribution as compared to non-flat segments of the charge storage material.

[0074] In operation, the charge storage material 38 may be configured to store information in the NAND memory cells 52 of the various embodiments described herein. The value of the information stored in an individual memory cell (where the term "value" represents one or more bits) may be based on the amount of charge (e.g., number of electrons) stored in the charge storage region of the memory cell. The amount of charge in an individual charge storage region may be controlled (e.g., increased or decreased) based at least in part on the value of the voltage applied to the associated gate 54 and / or based on the value of the voltage applied to the channel material 44.

[0075] The charge access material (tunneling material, gate dielectric material) 42 forms the tunneling region of the memory cell 52. Such a tunneling region may be configured to allow the desired charge (e.g., electrons) to migrate (e.g., transport, transfer) between the charge storage material 38 and the channel material 44. The tunneling region may be configured (i.e., designed) to achieve a selected criterion, such as (by way of example) (but not limited to) an equivalent oxide thickness (EOT). The EOT quantifies the electrical properties (e.g., capacitance) of the tunneling region in terms of a representative physical thickness. For example, the EOT may be defined as the thickness of a theoretical silicon dioxide layer that would be required to have the same capacitance density as a given dielectric, ignoring leakage current and reliability considerations.

[0076] The charge blocking material 34 adjacent to the charge storage material 38 may provide a mechanism to block the flow of charge from the charge storage material 38 to the associated gate 54.

[0077] A dielectric barrier material (high dielectric constant material) 28 provided between the charge blocking material 34 and the associated gate 54 can be used to inhibit back tunneling of charge carriers from the gate 54 towards the charge storage material 38. In some embodiments, the dielectric barrier material 28 can be considered to form a dielectric barrier region within the memory cell 52.

[0078] The embodiments described herein advantageously provide a methodology that can be used to tailor the gate length (i.e., control the vertical thickness of the terminal region of the gate 54), where such gate length is approximately the length of the storage node (i.e., segment 40 of the charge storage material 38) within a NAND memory cell (i.e., memory cell 52). In some embodiments, the conductive structure 22 can have a very small amount of titanium nitride 26 therein, which can improve the resistance along the word line region 58 of the conductive structure. Titanium nitride 26 can primarily be used as a nucleation material for growing tungsten 24 within the conductive structure 22 because the conductive material 74 can be selected to have the desired work function, desired conductivity, desired adhesion to adjacent materials, etc. within the NAND memory cell 52.

[0079] The assemblies and structures discussed above can be used within an integrated circuit (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and can be incorporated into an electronic system. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems, such as (by way of example) cameras, wireless devices, displays, chip sets, set-top boxes, games, lighting, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, airplanes, etc.

[0080] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed using any suitable methodology now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0081] The terms "dielectric" and "insulating" can be used to describe materials having insulating electrical properties. The terms are considered synonymous within this disclosure. The use of the term "dielectric" in some instances and the term "insulating" (or "electrically insulating") in other instances can provide a variation in language within this disclosure to simplify the underlying basis within the following claims and is not used to indicate any significant chemical or electrical differences.

[0082] The terms "electrically connected" and "electrically coupled" may both be used in this disclosure. The terms are considered synonymous. Utilizing one term in some examples and the other term in other examples may provide a variation in language within this disclosure to simplify the underlying basis in the following claims.

[0083] The specific orientation of the various embodiments in the figures is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientation in some applications. The description provided herein and the following claims are directed to any structure having the described relationships between the various features, regardless of whether the structure is in the specific orientation of the figures or rotated relative to that orientation.

[0084] The cross-sectional views of the accompanying figures show only the features in the plane of the cross-section and do not show the material behind the plane of the cross-section (unless otherwise indicated) in order to simplify the figures.

[0085] When a structure is referred to above as being "on", "adjacent", or "against" another structure, it may be directly on the other structure or there may also be an intervening structure. In contrast, when a structure is referred to as being "directly on", "directly adjacent", or "directly against" another structure, there is no intervening structure. The terms "directly below", "directly above", etc. do not indicate direct physical contact (unless otherwise explicitly stated), but rather indicate vertical alignment.

[0086] A structure (e.g., a layer, material, etc.) may be referred to as "vertically extending" to indicate that the structure extends generally upward from a lower underlying substrate (e.g., a substrate). A vertically extending structure may extend substantially orthogonally to the upper surface of the substrate, or not.

[0087] Some embodiments include an integrated structure having a vertical stack of alternating insulating layers and conductive layers. The conductive layers have terminal regions and have non-terminal regions adjacent to the terminal regions. The terminal regions are thicker in the vertical direction than the non-terminal regions and have a first vertical thickness. A dielectric barrier material is adjacent to the terminal regions. The dielectric barrier material is configured as a first segment that is vertically stacked and vertically spaced from each other. The first segment has a second vertical thickness. A charge blocking material is adjacent to the dielectric barrier material. The charge blocking material is configured as a second segment that is vertically stacked and vertically spaced from each other. The second segment has a third vertical thickness. A charge storage material is adjacent to the charge blocking material. The charge storage material is configured as a third segment that is vertically stacked and vertically spaced from each other. The third segment has a fourth vertical thickness. The first, second, third, and fourth vertical thicknesses are approximately the same as each other. A charge passage material is adjacent to the charge storage material. A channel material is adjacent to the charge passage material.

[0088] Some embodiments include a NAND memory array having a vertical stack of alternating insulating levels and conductive (word line) levels. The conductive levels include terminal regions and non-terminal regions adjacent to the terminal regions. The terminal regions are thicker than the non-terminal regions in a vertical direction and are configured as segments that are vertically stacked on top of and vertically spaced from each other. A block is adjacent to the segments and has an approximately the same vertical thickness as the segments. The block includes a high dielectric constant material, a charge blocking material, and a charge storage material. A channel material extends vertically along the stack and is adjacent to the block.

[0089] Some embodiments include a method of forming an integrated structure. A vertical stack of alternating first and second levels is formed. The first level includes a first material and the second level includes a second material. An opening is formed that extends through the stack. A third material is formed within the opening to narrow the opening. A dielectric barrier material, a charge blocking material, a charge storage material, a charge path material, and a channel material are formed within the narrowed opening. The second material is removed to leave a first void and to expose regions of the third material along the second level. The exposed regions of the third material along the second level are converted to a conductive fourth material. The conversion also converts some of the third material along the first level to the conductive fourth material. A conductive structure is formed within the first void and directly abutting the conductive fourth material. The first material is removed to form a second void. A remaining region of the third material is exposed at an end of the second void. The remaining region of the third material is removed to form a gap. The gap is between segments of the conductive fourth material. The gap is extended through the dielectric barrier material, the charge blocking material, and the charge storage material to form blocks including the dielectric barrier material, the charge blocking material, and the charge storage material. The blocks are vertically spaced from each other.

Claims

1. An integrated structure, comprising: Vertical stack of alternating insulating and conductive layers; The conductive layer has a terminal region and a non-terminal region adjacent to the terminal region; the terminal region is thicker in the vertical direction than the non-terminal region and has a first vertical thickness; A dielectric barrier material adjacent to the terminal region, the dielectric barrier material configured as a first segment stacked vertically and spaced vertically from each other, the first segment having a second vertical thickness; A charge blocking material adjacent to the dielectric barrier material; The charge blocking material is configured as a second segment stacked vertically and spaced vertically from each other, the second segment having a third vertical thickness; A charge storage material adjacent to the charge blocking material; The charge storage material is configured as a third segment stacked vertically and spaced vertically from each other, the third segment having a fourth vertical thickness; the first, second, third, and fourth vertical thicknesses are approximately the same as each other; A charge conduction material adjacent to the charge storage material; and A channel material adjacent to the charge conduction material.

2. The integrated structure according to claim 1, wherein the terminal region is thicker than the non-terminal region in the vertical direction by an amount in the range of about 10% to about 90% of the vertical thickness of the non-terminal region.

3. The integrated structure according to claim 1, wherein the terminal region comprises the same composition as the non-terminal region.

4. The integrated structure according to claim 1, wherein the terminal region comprises a composition different from that of the non-terminal region.

5. The integrated structure according to claim 1, wherein the terminal region contains one or more metals.

6. The integrated structure according to claim 5, wherein the one or more metals comprise one or more of cobalt, molybdenum, nickel, ruthenium, tantalum, titanium, and tungsten.

7. The integrated structure according to claim 6, wherein the terminal region further comprises one or more of boron, carbon, nitrogen, oxygen, and silicon.

8. The integrated structure according to claim 1, wherein the non-terminal region comprises a metal nitride layer surrounding a metal-containing conductive core; wherein the metal nitride layer comprises titanium nitride; and wherein the metal-containing conductive core is composed of tungsten.

9. The integrated structure according to claim 8, wherein the terminal region contains one or more of TiSi, TiSiN, W, WSiN, and WN; wherein the chemical formula indicates the main component rather than a specific stoichiometry.

10. The integrated structure according to claim 1, wherein the non-terminal region is substantially vertically centered relative to the terminal region along each of the conductive levels.

11. A NAND memory array, comprising: Vertical stack of alternating insulating and conductive layers; The conductive layer includes a terminal region and a non-terminal region adjacent to the terminal region; the terminal region is thicker in the vertical direction than the non-terminal region and is configured as segments stacked vertically and spaced vertically from each other; A block adjacent to the segments and having a vertical thickness substantially the same as the segments, the block including a high dielectric constant material, a charge blocking material, and a charge storage material; and A channel material extending vertically along the stack and adjacent to the block.

12. The NAND memory array according to claim 11, wherein the block has a substantially horizontal top surface and a bottom surface.

13. The NAND memory array according to claim 11, wherein each of the blocks has a pair of opposite substantially vertical sidewall surfaces extending from one of the substantially horizontal top surfaces to one of the substantially horizontal bottom surfaces along a cross-section.

14. The NAND memory array according to claim 11, wherein the blocks are vertically spaced from each other by an intervening gap having a vertical thickness in the range from about 1 nm to about 20 nm.

15. The NAND memory array according to claim 11, wherein the segment has the same composition as a portion of the non-terminal region directly adjacent to the segment.

16. The NAND memory array according to claim 11, wherein the segment has a composition different from a portion of the non-terminal region directly adjacent to the segment.

17. The NAND memory array according to claim 11, wherein the segment comprises one or more metals.

18. The NAND memory array according to claim 17, wherein the segment further comprises one or more of boron, carbon, nitrogen, oxygen, and silicon.

19. The NAND memory array according to claim 11, wherein the segment comprises one or more of TiSi, TiSiN, W, WSiN, and WN; wherein the chemical formula indicates the main component rather than a specific stoichiometry.

20. The NAND memory array according to claim 19, wherein the non-terminal region of the conductive layer comprises titanium nitride directly abutting the segment.

21. The NAND memory array according to claim 11, wherein the block comprises a charge path material.

22. The NAND memory array according to claim 11, wherein the charge path material extends vertically along the stack and is between the block and the channel material.

23. A method of forming an integrated structure, comprising: Form a vertical stack of alternating first and second layers; The first layer includes a first material and the second layer includes a second material; Form an opening extending through the stack; Form a third material within the opening to narrow the opening; Form a dielectric barrier material, a charge blocking material, a charge storage material, a charge conduction material, and a channel material within the narrowed opening; Remove the second material to leave a first void and expose a region of the third material along the second layer; Convert the exposed region of the third material along the second layer to a conductive fourth material, the conversion also converting some of the third material along the first layer; Form a conductive structure within the first void and directly against the conductive fourth material; Remove the first material to leave a second void, with the remaining region of the third material exposed at the end of the second void; Remove the remaining region of the third material to form a gap; the gap is between segments of the conductive fourth material; and Extend the gap through the dielectric barrier material, the charge blocking material, and the charge storage material to form a block including the dielectric barrier material, the charge blocking material, and the charge storage material; the blocks are vertically spaced from each other.

24. The method according to claim 23, further comprising, after forming the block, filling at least a portion of the second void with an insulating fifth material.

25. The method according to claim 24, wherein the second void is completely filled with the insulating fifth material.

26. The method according to claim 24, wherein the second void is only partially filled with the insulating fifth material.

27. The method according to claim 23, wherein the gap extends through the charge path material to form the block including the charge path material.

28. The method according to claim 23, wherein the third material includes one or more of boron, germanium, and silicon.

29. The method according to claim 23, wherein the third material includes polysilicon.

30. The method according to claim 29, wherein the third material further includes carbon.

31. The method according to claim 23, wherein the third material includes polysilicon, and wherein converting the third material to the conductive fourth material includes: Expose the third material to one or more metal precursors to form the conductive fourth material including one or more metals.

32. The method according to claim 31, wherein the conductive fourth material further includes one or more of boron, carbon, nitrogen, oxygen, and silicon.

33. The method according to claim 23, wherein the third material includes silicon, and wherein the conductive fourth material includes one or more of TiSi, TiSiN, W, WSiN, and WN; wherein the chemical formula indicates the main component rather than a specific stoichiometry.

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