Processors, computer systems, and methods for hierarchical cache flush

Abstract

A processor, computer system, and method for hierarchical cache flush. The processor includes a first core and a last level cache. The first core includes a decoder, a memory order buffer, and a first core internal cache. The decoder, in response to an instruction of an instruction set architecture specifying a key identification code and an address for a hierarchical cache flush, generates at least one microinstruction. According to the at least one microinstruction, a flush request with the specified key identification code and the specified address is supplied through the memory order buffer to the first core internal cache, and then from the first core internal cache to the last level cache, so that the last level cache flushes a matching cache line matching the specified key identification code and the specified address.

Description

Technical Field

[0001] This application relates to processor hierarchical cache management techniques, specifically to processors, computer systems, and methods for performing hierarchical cache clearing by specifying a key identification code and a specified address. Background Technology

[0002] In computer architecture, memory can be stratified. Higher-level memory offers higher speed, lower latency, but smaller capacity. Most computers have the following four memory strata (ordered from fastest to slowest access): registers; cache memory; system memory (main memory, such as DRAM); and hard disks (SSD or HDD).

[0003] Caches can also be designed hierarchically, arranged from fastest to slowest access, including: Level 1 cache (L1 cache), Level 2 cache (L2 cache), and Level 3 cache (L3 cache, also known as the last level cache, or LLC). The management of hierarchical caches will significantly affect system performance.

[0004] To protect confidential and / or sensitive data, existing technologies have developed transparent total memory encryption (TMC) functions that use multiple keys to encrypt memory, enabling memory management at the key-level granularity. However, existing hierarchical caches lack corresponding key-level granular management functions, which prevents the operating system (OS) from managing hierarchical caches at the key-level granularity. Summary of the Invention

[0005] This application proposes a technique for managing hierarchical caches at the key level.

[0006] A processor implemented according to one embodiment of this application includes a first core and a last-level cache. The first core includes a decoder, a memory ordering buffer (MOB), and a first-core cache. When the decoder responds to an instruction in an instruction set architecture that specifies a key identification code and performs hierarchical cache clearing at a specified address, it translates at least one microinstruction. Based on the at least one microinstruction, a clearing request carrying a specified key identification code and a specified address is supplied to the first-core cache through the memory ordering buffer, and then passed from the first-core cache to the last-level cache, causing the last-level cache to clear a matching cache line that matches the specified key identification code and the specified address.

[0007] In one embodiment, the processor further includes a snoop filter. The last-level cache issues a snoop request, which is passed to the first core cache through the snoop filter. The snoop request carries a matching cache line flag; in both the first core cache and the last-level cache, cache lines that match the specified key identifier and the specified address all contain the matching cache line flag. Based on the matching cache line flag carried in the snoop request, the first core cache finds its own cache line that matches the specified key identifier and the specified address, and clears it.

[0008] In one embodiment, the processor further includes a second core. The second core includes a second-core cache. The snooping filter also transmits the snooping request to the second-core cache. The second-core cache, based on the matching cache line flag carried in the snooping request, finds the cache line that matches the specified key identification code and the specified address, and clears it.

[0009] Furthermore, this application also implements a computer system that, in addition to the aforementioned processor design, can also be designed as a multi-chip processor architecture.

[0010] In one embodiment, a computer system includes a first processor fabricated on a first die and a second processor fabricated on a second die. The first processor may be designed as described above, wherein the last-level cache and the snoop filter are respectively referred to as a first last-level cache and a first snoop filter. The second processor includes a third core, a second last-level cache, and a second snoop filter. The third core includes a third-core cache. The first last-level cache also transmits the purge request from the first-core cache to the second last-level cache via a channel between the first die and the second die. Based on the purge request, the second last-level cache purges cache lines that match the specified key identification code and the specified address. The second last-level cache issues a second snoop request, which is transmitted to the third-core cache via the second snoop filter. The second snoop request carries a matching cache line flag. The third core cache, based on the matching cache line flag contained in the second snooping request, finds the cache line that matches the specified key identification code and the specified address, and clears it.

[0011] Another implementation method, based on the aforementioned concept, proposes a method for hierarchical cache clearing by specifying a key identification code and a specified address.

[0012] According to the technology of this application, the hierarchical cache is equipped with corresponding key-based management functions; when the transparent full memory encryption function is enabled, the operating system can manage the hierarchical cache at the key-based granularity.

[0013] The following detailed description of the invention is illustrated with specific examples and accompanying drawings. Attached Figure Description

[0014] Figure 1 This is an instruction architecture for the ISA instruction CFLUSHKEYID in this application;

[0015] Figure 2 According to one embodiment of this application, the format 200 of a cache line in a hierarchical cache is illustrated.

[0016] Figure 3 This is a block diagram illustrating a processor 300 and a core core_1 thereon, according to one embodiment of the present invention; and

[0017] Figure 4 The diagram illustrates a computer system 400 implemented according to one embodiment of this application.

[0018] [Symbol Explanation]

[0019] 102: Opcode;

[0020] 104, 106: Indicates operands for a specified key identification code (Key_ID_S) and a specified address (Addr_S);

[0021] 108, 110, 112: Instruction schema for instruction CFLUSHKEYID;

[0022] 200: The format of a cache line in a tiered cache;

[0023] 202: Valid bit (VALID);

[0024] 204: Key ID;

[0025] 206: Tags;

[0026] 300: Processor;

[0027] 302: System memory;

[0028] 304: Instruction cache;

[0029] 306: Decoder;

[0030] 308: Instruction Buffer (XIB);

[0031] 310: Instruction Translator (XLATE);

[0032] 312: Register Alias ​​Table (RAT);

[0033] 314: Reserved Station (RS);

[0034] 316: Sequential Memory Buffer (MOB);

[0035] 318: Micro-opcode

[0036] 320, 322: operands;

[0037] 324: Removal Requirement;

[0038] 326: Eavesdropping Filter;

[0039] 328: Request for eavesdropping;

[0040] 400: Computer System;

[0041] 402: Removal Requirement;

[0042] 404: Kernel cache;

[0043] 406, 410: Requests for eavesdropping;

[0044] 408: Channel;

[0045] CFLUSHKEYID:ISA instruction;

[0046] core_1, core_i, core_N: Cores;

[0047] Die_1, Die_2: First and second grains;

[0048] imm16: Immediate number;

[0049] L1, L2, L3: Level 1, Level 2, and Level 3 caches;

[0050] LLC_1, LLC_2: Last-level cache;

[0051] MOB: Sequential Memory Cache;

[0052] Processor_1, Processor_2: Processors;

[0053] reg, Reg: registers;

[0054] r / m: Register label or system memory address;

[0055] snoop_1, snoop_2: eavesdropping filters;

[0056] Sys_Mem: System memory;

[0057] ucode: microcode. Detailed Implementation

[0058] The following description illustrates various embodiments of the present invention. This description introduces the basic concepts of the invention and is not intended to limit its scope. The actual scope of the invention should be defined in accordance with the claims.

[0059] Modern computer technology often incorporates transparent total memory encryption (TMI) designs, using multiple keys to encrypt system memory to enhance system security. Each key can be represented by a key ID. The computer system may contain a key table to store the mapping between keys and key IDs. During encryption operations, the key corresponding to the key ID can be retrieved by querying the key table.

[0060] In the corresponding system memory multi-key encryption processing, this application enables the processor to list the key ID as one of the management parameters of the hierarchical cache (e.g., including L1 cache, L2 cache, and L3 cache). In this way, the use of the hierarchical cache can be combined with the application of transparent full-memory encryption to clear cache lines with specific key IDs.

[0061] In one embodiment, the present invention discloses a processor in which an instruction set architecture (ISA) instruction (hereinafter referred to as CFLUSHKEYID) is provided to clear a cache line of a hierarchical cache by matching a specified key identification code (Key_ID_S) and a specified address (Addr_S).

[0062] Generally, modern operating systems commonly employ virtual memory management mechanisms, and the Memory Management Unit (MMU) of the Central Processing Unit supports the translation from virtual address (VA) to physical address (PA). The specified address (Addr_S) of the instruction CFLUSHKEYID in this application can be either a physical address (PA) or a virtual address (VA). If the specified address is a virtual address, it can first be translated into a physical address using the memory management unit (such as a sequential memory cache) before the cache line is cleared. If there are updated contents in the matching cache line that have not yet been written back to system memory, the updated contents will be written to system memory before the matching cache line is cleared. The processor supports various instruction set architectures, including x86, Advanced RISC Machine (ARM), MIPS (Microprocessor without Interlocked Pipeline Stages), RISC-V (RISC-Five), SPARC, IBM Power, and others.

[0063] Figure 1This application's ISA instruction CFLUSHKEYID uses an instruction architecture that, in addition to the opcode 102 for instruction identification, employs two operands 104 and 106. Operand 104 indicates the specified key identification code (Key_ID_S), and operand 106 indicates the specified address (Addr_S). The processor compares the specified key identification code (Key_ID_S) with the key identifier (Key_ID) in the cache line indicated by the specified address (Addr_S) in the hierarchical cache. If the comparison is successful, a clearing operation is performed. Operands 104 and 106 can have various forms. In instruction architecture 108, the instruction CFLUSHKEYID shows that operand 104 carries a register label or system memory address, and operand 106 carries a register (reg) label, to retrieve the specified key identification code (Key_ID_S) and the specified address (Addr_S) from the register or system memory (r / m) and the register (reg), respectively. In instruction architecture 110, the operand 104 of the instruction CFLUSHKEYID is a register (reg) label, and the operand 106 is a register label or a system memory address, to retrieve the specified key identification code (Key_ID_S) and the specified address (Addr_S) from the register (reg), register, or system memory (r / m), respectively. In instruction architecture 112, the operand 104 of the instruction CFLUSHKEYID is a register label or a system memory address, and the operand 106 is an immediate value (imm16), to retrieve the specified key identification code (Key_ID_S) and the specified address (Addr_S) from the register or system memory (r / m) and the immediate value (imm16), respectively. In another embodiment, the ISA instruction CFLUSHKEYID uses only one operand, in addition to the opcode 102 used for instruction identification. This operand indicates the specified key identification code (Key_ID_S) and the specified address (Addr_S). The operand can be a register label, a system memory address, or an immediate value, to obtain the specified key identification code (Key_ID_S) and the specified address (Addr_S) from a register (reg), system memory (m), or an immediate value. In program writing, the CFLUSHKEYID instruction can be preceded by other instructions to fill in registers / memory / immediate values, preparing the specified key identification code (Key_ID_S) and the specified address (Addr_S) for the CFLUSHKEYID instruction to obtain using these operands 104 and 106.

[0064] Figure 2According to one embodiment of this application, the format 200 of a cache line in a tiered cache is illustrated. Referring to the format 200 of cache lines in a tiered cache, field 202 is the validity bit (VALID), where a value of 0 indicates that the cache line is invalid, and a value of 1 indicates that the cache line is valid. Field 204 records the key identification code (Key_ID), and field 206 records the tag (TAG). The tiered cache can use a cache line search method to search for matching cache lines based on a specified key identification code (Key_ID_S) and physical address (PA).

[0065] The cache line search method includes the following steps: First, the hierarchical cache obtains the corresponding tag and index based on the physical address (PA). Specifically, since the physical address contains the tag and index fields used to search the hierarchical cache, the hierarchical cache can directly read the corresponding tag and index from the physical address. Second, the hierarchical cache finds the cache line information that matches the specified key ID (Key_ID_S), tag, and index based on the specified key ID (Key_ID_S), the tag, and the index corresponding to the physical address (PA). Specifically, the hierarchical cache first obtains at least one valid cache line based on the index (INDEX). Then, it compares the specified key identification code (Key_ID_S) and tag (TAG) with the key identification code (Key_ID, field 204) and tag (TAG, field 206) in each obtained cache line. If they match, the corresponding cache line is a matching cache line; otherwise, the corresponding cache line is a non-matching cache line. How to obtain at least one cache line based on the index (INDEX) is common knowledge to those skilled in the art and will not be elaborated here.

[0066] In this invention, by adding a key identification code (Key_ID) field to the cache line and modifying the hierarchical cache accordingly, a hierarchical cache is managed at the key level.

[0067] In one embodiment, the present invention has a corresponding instruction CFLUSHKEYID designed in the processor's microcode, and can also be modified accordingly in the processor hardware.

[0068] Figure 3This diagram illustrates a processor 300 and a core core_1 thereon, according to one embodiment of the present invention. The illustrated hierarchical cache includes first, second, and third level caches L1, L2, and L3. The first and second level caches L1 and L2 are the in-core caches of core_1. The third level cache L3 is the last level cache (LLC) that can be shared by other cores.

[0069] An instruction is loaded from system memory 302 into an instruction cache 304 and then passed to a decoder 306 for decoding. The decoder 306 includes an instruction buffer (XIB) 308 and an instruction translator (XLATE) 310. The instruction buffer (XIB) 308 identifies and segments the instruction CFLUSHKEYID proposed in this application, while the instruction translator (XLATE) 310 translates the instruction CFLUSHKEYID into at least one microinstruction recognizable by the pipeline hardware according to the opcode 102 of the instruction CFLUSHKEYID. This microinstruction drives subsequent hardware to flush the cache lines in the first, second, and third level caches L1, L2, and L3 that match the specified key identification code (Key_ID_S) and specified address (Addr_S) in the instruction CFLUSHKEYID. In one embodiment, the instruction translator (XLATE) 310, based on microcode (stored in a microcode memory), translates the instruction CFLUSHKEYID into at least one microinstruction recognizable by the pipeline hardware according to the opcode 102 of the instruction CFLUSHKEYID. This at least one microinstruction is stored in the corresponding reservation station (RS) 314 via a register alias table (RAT) 312 before being applied; one of the microinstructions is a clear microinstruction, which triggers a memory order buffer (MOB) 316 to drive the hierarchical cache to perform a clear operation. In one embodiment, the at least one microinstruction also includes microinstructions for exception checking (such as privilege level checking), memory address jumping (i.e., jumping to the instruction following CFLUSHKEYID), and other functions.

[0070] The sequential memory buffer (MOB) 316 is generally used as a communication interface between core_1 and memory space (register Reg, first, second and third level caches L1, L2 and L3, and system memory 302). Figure 3 Specifically, this application's microinstruction design explains how the sequential memory buffer (MOB) 316 clears cache lines at specified key identification codes (Key_ID_S) and specified addresses (Addr_S) from the first, second, and third level caches L1, L2, and L3.

[0071] As shown in the figure, the reservation station (RS) 314 transmits the clear microinstruction (including micro-opcode 318, operands 320 and 322) to the memory sequential buffer (MOB) 316. After identifying the micro-opcode 318, the specified key identification code (Key_ID_S) and the specified address (Addr_S) can be obtained from register Reg or system memory 302 according to operand instructions 320 and 322 through the communication interface implemented by the memory sequential buffer (MOB) 316. In other embodiments (instruction architecture 112), the specified address (Addr_S) can be obtained by interpreting the immediate value (imm16). As previously described, in another embodiment, the instruction CFLUSHKEYID contains only one operand, which has two fields: one indicating the specified key identification code (Key_ID_S) and the other indicating the specified address (Addr_S). This operand can be a register label, a system memory address, or an immediate value, to obtain the specified key identification code (Key_ID_S) and the specified address (Addr_S) from a register (reg), system memory (m), or an immediate value. It should be noted that if the specified address (Addr_S) is a virtual address, the memory sequential buffer (MOB) 316 will translate it to a physical address (PA). Then, the memory sequential buffer (MOB) 316 will pass a clear request 324 through the first-level cache L1 and the second-level cache L2 to the third-level cache L3.

[0072] The clearing request 324 includes a specified key identification code (Key_ID_S) and the physical address (PA) corresponding to the specified address (Addr_S). Based on the specified key identification code (Key_ID_S) and the physical address (PA) corresponding to the specified address (Addr_S) indicated by the clearing request 324, the Level 3 cache L3 finds matching cache lines and clears them according to the cache line search method described above. Specifically, matching cache lines that have not yet been written back to system memory 302 are cleared only after being written back to system memory 302. One implementation method is to invalidate a valid bit (VALID) of the matching cache line to perform the clearing operation. In one embodiment, if the Level 3 cache L3 cannot find a matching cache line according to the cache line search method described above, no operation is performed, and the CFLUSHKEYID instruction completes.

[0073] The flag of a matching cache line found in the Level 3 cache (L3) (hereinafter referred to as the matching cache line flag) will be used to find matching cache lines in the Level 2 cache (L2) and the Level 1 cache (L1). In general hierarchical cache designs, cache lines are marked with flags; cache lines matching the same key ID and address at different levels use the same flag. In one embodiment, the matching cache line flag includes the key ID (Key_ID), tag (TAG), and index (INDEX). In another embodiment, the matching cache line flag includes the physical address (PA).

[0074] The third-level cache L3 sends a snoop request 328, containing a matching cache line flag, to the snoop filter 326. This snoop request with the matching cache line flag is then supplied by the snoop filter 326 to the second-level cache L2. The second-level cache L2 evicts cache lines that match the matching cache line flag and then passes this snoop request to the first-level cache L1. The first-level cache L1 evicts cache lines that match the matching cache line flag. Thus, cache lines matching the specified key ID (Key_ID_S) and the specified address (Addr_S) are consistently evicted across all hierarchical caches L1, L2, and L3.

[0075] Figure 4The diagram illustrates a computer system 400 implemented according to one embodiment of this application. Die_1 and Die_2 each include a processor_1 and a processor_2. Each processor_1 / Processor_2 includes multiple cores core_1 to core_N. Each core includes an in-core cache (e.g., L1 and L2 level caches). Processor_1 allows its multiple cores core_1 to core_N to share a last-level cache (e.g., L3 level cache) LLC_1; and in conjunction with the last-level cache LLC_1, processor_1 sets up a snoop filter Snoop_1. Processor_2's multiple cores core_1 to core_N share a last-level cache LLC_2; and in conjunction with the last-level cache LLC_2, processor_2 sets up a snoop filter Snoop_2. Die_1 and Die_2 provide two processors, Processor_1 and Processor_2, which share a single system memory, Sys_Mem. The diagram shows the core_i of Processor_1 in Die_1 executing the instruction CFLUSHKEYID, which indicates the specified key identification code (Key_ID_S) and the specified address (Addr_S).

[0076] Core_i, through the communication interface formed by its sequential memory cache (MOB), transmits a clear request 402, indicating a specified key identification code (Key_ID_S) and the physical address corresponding to a specified address (Addr_S), to the core cache 404, and then to the last-level cache LLC_1. Based on the specified key identification code (Key_ID_S) and specified address (Addr_S) indicated by the clear request 402, the last-level cache LLC_1 finds matching cache lines and clears them. The flag of the matching cache line found by the last-level cache LLC_1 (matching cache line flag) can be carried in a snoop request 406 and given to the snoop filter snoop_1. The snoop filter snoop_1 then passes the request to the core caches of each core (core_1 to core_N) in Processor_1, clearing the cache lines that match the matching cache line flag. In this way, within the processor Processor_1, the cache lines matching the specified key identification code (Key_ID_S) and the specified address (Addr_S) in the core cache of all cores core_1 to core_N, as well as the last-level cache LLC_1 shared by all cores core_1 to core_N, are consistently cleared.

[0077] Specifically, through channel 408 between die_1 and die_2 (in one embodiment, channel 408 is an internal bus), the last-level cache LLC_1 transmits the purge request 402 (with a specified key identification code (Key_ID_S) and a physical address (PA) corresponding to a specified address (Addr_S)) from the core cache 404 to the last-level cache LLC_2. Based on the specified key identification code (Key_ID_S) and specified address (Addr_S) indicated by the purge request 402, the last-level cache LLC_2 identifies and purges matching cache lines. The flag of the matching cache line found by the last-level cache LLC_2 (matching cache line flag), which is of course the same as the flag found by the last-level cache LLC_1, is also carried in snoop request 410 and delivered to the snoop filter snoop_2. The snoop request 410 is passed by the snoop filter snoop_2 to the core caches of each core (core_1 to core_N) in processor_2, causing cache lines matching the specified cache line flag to be cleared. In this way, within processor_2, cache lines matching the specified key identification code (Key_ID_S) and the specified address (Addr_S) are consistently cleared in the core caches of all cores (core_1 to core_N) and the lowest-level cache LLC_2 shared by all cores (core_1 to core_N).

[0078] This application's technology enables the complete and thorough clearing of all tiered caches in the entire computer system 400 that match a specified key identification code (Key_ID_S) and a specified address (Addr_S). Any application that uses an ISA instruction to perform tiered cache clearing of a specified key identification code (Key_ID_S) and a specified address (Addr_S) falls under the scope of this application's technology.

[0079] The following is based on Figure 1 Taking the instruction set architecture 108 as an example, combined with Figure 1-4 This explains how the instruction CFLUSHKEYID in this invention is executed. Assume the sequence of instructions to be executed is as follows:

[0080] MOV EAX, KeyID (1)

[0081] MOV EBX, ProcessMemory_VA (2)

[0082] CFLUSHKEYID EAX, EBX (3)

[0083] Instructions (1), (2), and (3), after being compiled, will be loaded into... Figure 3 The processor 300 reads and executes instructions (1) and (2) sequentially from the system memory 302. The value of register EAX is set to the key identification code KeyID, and the value of register EBX is set to the virtual address ProcessMemory_VA. Then, the processor 300 executes instruction (3).

[0084] Please refer to Figure 3 The processor 300 loads instruction (3) from system memory 320 into instruction cache 304 and then passes it to decoder 306. Decoder 306 then... Figure 1 The opcode 102 shown translates instruction (3) into at least one microinstruction, and then stores the at least one microinstruction into the corresponding reservation station (RS) 314 via register alias table (RAT) 312. When the clear microinstruction in the at least one microinstruction meets the execution conditions, the reservation station (RS) 314 sends it to the memory sequential buffer (MOB) 316 for execution. After identifying the micro-opcode (opcode) 318, the memory sequential buffer (MOB) 316 obtains the key identification code KeyID and the virtual address ProcessMemory_VA from registers EAX and EBX according to operand instructions 320 and 322. The memory sequential buffer (MOB) 316 converts the virtual address ProcessMemory_VA to the physical address ProcessMemory_PA. Then, the memory sequential buffer (MOB) 316 generates a clear request 324 based on the key identification code KeyID and the physical address ProcessMemory_PA, and passes the clear request 324 to the third-level cache L3 through the first-level cache L1 and the second-level cache L2.

[0085] Please also refer to Figure 2 , 3The third-level cache (L3) obtains the corresponding tag (ProcessMemory_TAG) and index (ProcessMemory_INDEX) based on the physical address (ProcessMemory_PA). If a match is found, L3 first obtains at least one valid cache line based on the index (ProcessMemory_INDEX), and compares the key ID (KeyID) and tag (ProcessMemory_TAG) with the key ID (Key_ID, field 204) and tag (TAG, field 206) in each obtained cache line to find the matching cache line, and then clears it. Then, L3 sends a snoop request (Snoop request) 328 to snoop filter 326, which includes a matching cache line flag (containing key ID, tag (ProcessMemory_TAG), index (ProcessMemory_INDEX), etc.). This snoop request with the matching cache line flag is then supplied to the second-level cache (L2) by snoop filter 326. The second-level cache (L2) clears cache lines that match the cache line flag and then passes such snooping requests with the matching cache line flag to the first-level cache (L1). The first-level cache (L1) clears cache lines that match the cache line flag. Thus, cache lines matching the key identifier KeyID and the virtual address ProcessMemory_VA are consistently cleared across all tiered caches (L1, L2, L3).

[0086] Please refer to the following: Figure 4Assume that processor_1's core_i in computer system 400 executes the aforementioned instruction sequence (1), (2), and (3). Core_i, through the communication interface formed by its sequential memory cache (MOB), transmits a clear request 402, containing a key identification code KeyID and the physical address ProcessMemory_PA corresponding to the virtual address ProcessMemory_VA, to the core cache 404, and then to the lowest-level cache LLC_1. Based on the key identification code KeyID and the physical address ProcessMemory_PA indicated by the clear request 402, the lowest-level cache LLC_1 finds the matching cache line and clears it. The flag for the matching cache line found in the lowest-level cache LLC_1 (the matching cache line flag, which includes the key identification code KeyID, the tag ProcessMemory_TAG, the index ProcessMemory_INDEX, etc.) can be carried in snoop request 406 and given to the snoop filter snoop_1. Snoop_1 then passes the flag to the core caches of each core (core_1 to core_N) in Processor_1, causing the cache lines matching the matching cache line flag to be cleared. In this way, within Processor_1, the cache lines matching the key identification code KeyID and the virtual address ProcessMemory_VA in the core caches of all cores (core_1 to core_N) and the lowest-level cache LLC_1 shared by all cores (core_1 to core_N) are consistently cleared.

[0087] Additionally, through channel 408 between die_1 and die_2 (in one embodiment, channel 408 is an internal bus), the last-level cache LLC_1 transmits the purge request 402 (specifying the key identification code KeyID and the physical address ProcessMemory_PA corresponding to the virtual address ProcessMemory_VA) from the core cache 404 to the last-level cache LLC_2. Based on the key identification code KeyID and physical address ProcessMemory_PA indicated by the purge request 402, the last-level cache LLC_2 finds and purges the matching cache line. The flag of the matching cache line found by the last-level cache LLC_2 (the matching cache line flag, containing the key identification code KeyID, the tag ProcessMemory_TAG, the index ProcessMemory_INDEX, etc.) will naturally be the same as the flag found by the last-level cache LLC_1, and will also be carried in snoop request 410 and delivered to the snoop filter snoop_2. The snoop request 410 is passed by the snoop filter snoop_2 to the core caches of each core (core_1 to core_N) in processor_2, causing cache lines matching the cache line flag to be cleared. In this way, within processor_2, the cache lines matching the key identification code KeyID and the virtual address ProcessMemory_VA in the core caches of all cores (core_1 to core_N) and the lowest-level cache LLC_2 shared by all cores (core_1 to core_N) are consistently cleared.

[0088] According to the technology of this application, the hierarchical cache is equipped with corresponding key-based management functions; when the transparent full memory encryption function is enabled, the operating system can manage the hierarchical cache at the key-based granularity.

[0089] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is defined by the claims.

Claims

1. A processor for performing hierarchical cache flush with a specified key recognition code and a specified address, comprising: a first core including a decoder, a memory order buffer, and a first in-core cache; and a last level cache; wherein: the decoder, in response to an instruction set architecture instruction for performing hierarchical cache flush with a specified key recognition code and a specified address, generates at least one microinstruction; the at least one microinstruction, with a flush request with the specified key recognition code and the specified address, is supplied to the first in-core cache through the memory order buffer, and is further supplied to the last level cache by the first in-core cache, so that the last level cache flushes a matching cache line matching the specified key recognition code and the specified address.

2. The processor for performing hierarchical cache flush with a specified key recognition code and a specified address as recited in claim 1, further comprising: a snoop filter; wherein: the last level cache issues a snoop request to the first in-core cache through the snoop filter; the snoop request carries a matching cache line flag; the cache line matching the specified key recognition code and the specified address in the first in-core cache and the last level cache both use the matching cache line flag; and the first in-core cache finds the cache line matching the specified key recognition code and the specified address according to the matching cache line flag carried by the snoop request, and flushes the cache line.

3. The processor for performing hierarchical cache flush with a specified key recognition code and a specified address as recited in claim 2, wherein: the first in-core cache includes a first level cache and a second level cache, and the last level cache is a third level cache; the snoop request is received by the second level cache from the snoop filter, and is further transmitted by the second level cache to the first level cache.

4. The processor for performing hierarchical cache flush with a specified key recognition code and a specified address as recited in claim 3, wherein: the second level cache finds the cache line matching the specified key recognition code and the specified address according to the matching cache line flag carried by the snoop request, and flushes the cache line; and the first level cache finds the cache line matching the specified key recognition code and the specified address according to the matching cache line flag carried by the snoop request, and flushes the cache line.

5. The processor for performing hierarchical cache flush with a specified key recognition code and a specified address as recited in claim 2, further comprising: a second core including a second in-core cache, wherein: the snoop filter also transmits the snoop request to the second in-core cache; the second in-core cache finds the cache line matching the specified key recognition code and the specified address according to the matching cache line flag carried by the snoop request, and flushes the cache line.

6. The processor for performing hierarchical cache flush with a specified key recognition code and a specified address as recited in claim 1, wherein: the first in-core cache includes a first level cache and a second level cache; and the first level cache flushes the cache line matching the specified key recognition code and the specified address according to the matching cache line flag carried by the snoop request. ​ The last level cache is a third level cache.

7. The processor of claim 6, wherein: The flush request is passed from the first level cache to the second level cache, and from the second level cache to the third level cache.

8. The processor of claim 1, wherein: The last level cache obtains a tag and an index from a physical address corresponding to the specified address; and The last level cache, among cache lines matching the specified key recognition code, the tag, and the index, is a matching cache line.

9. A computer system for performing a hierarchical cache flush with a specified key recognition code and a specified address, comprising: A first processor fabricated on a first die, including a first core, and the first core including a decoder, a memory order buffer, and a first in-core cache; and A first last level cache fabricated on the first processor; wherein: The decoder, in response to an instruction set architecture instruction for performing a hierarchical cache flush with a specified key recognition code and a specified address, converts at least one microinstruction; According to the at least one microinstruction, a flush request with the specified key recognition code and the specified address is supplied to the first in-core cache through the memory order buffer, and is passed from the first in-core cache to the first last level cache, so that the first last level cache flushes a cache line matching the specified key recognition code and the specified address.

10. The computer system of claim 9, further comprising: A first snoop filter fabricated on the first processor; wherein: The first last level cache issues a first snoop request to the first in-core cache through the first snoop filter; The first snoop request carries a matching cache line flag; The matching cache line matching the specified key recognition code and the specified address in the first in-core cache and the first last level cache uses the matching cache line flag; and The first in-core cache, according to the matching cache line flag carried by the first snoop request, finds a cache line matching the specified key recognition code and the specified address, and flushes it.

11. The computer system of claim 10, wherein: The first processor further includes a second core, and the second core includes a second in-core cache; The first snoop filter also passes the first snoop request to the second in-core cache; The second in-core cache, according to the matching cache line flag carried by the first snoop request, finds a cache line matching the specified key recognition code and the specified address, and flushes it.

12. The computer system of claim 9, wherein: The first L1 cache obtains a tag and an index according to a physical address corresponding to the specified address; and In the first L1 cache, a cache line matching the specified key identification code, the tag and the index, i.e., matching the specified key identification code and the specified address.

13. The computer system of claim 9, further comprising: a second processor fabricated on a second die, including a third core, and the third core including a third L1 cache; and a second L1 cache fabricated on the second processor; wherein: The first L1 cache further transmits the flush request from the first L1 cache to the second L1 cache via a channel between the first die and the second die; According to the flush request, the second L1 cache flushes a cache line matching the specified key identification code and the specified address.

14. The computer system of claim 13, further comprising: a second snoop filter fabricated on the second processor; wherein: The second L1 cache issues a second snoop request to the third L1 cache via the second snoop filter; The second snoop request carries a matching cache line flag; In the third L1 cache and the second L1 cache, a cache line matching the specified key identification code and the specified address uses the matching cache line flag; and The third L1 cache finds a cache line matching the specified key identification code and the specified address according to the matching cache line flag carried by the second snoop request, and flushes the cache line.

15. A method of performing hierarchical cache flush with a specified key identification code and a specified address, comprising: In response to an instruction set architecture (ISA) instruction of performing hierarchical cache flush with a specified key identification code and a specified address, a decoder belonging to a first core of a first processor on a first die converts at least one microinstruction, and the first core further includes a memory order buffer (MOB) and a first L1 cache; and According to the at least one microinstruction, a flush request with the specified key identification code and the specified address is supplied to the first L1 cache via the MOB, and the first L1 cache transmits the flush request to a first L1 cache shared by a plurality of cores on the first processor, so that the first L1 cache flushes a matching cache line matching the specified key identification code and the specified address.

16. The method of claim 15, further comprising: causing the first last level cache to issue a first snoop request to a first snoop filter on the first processor, the first snoop request carrying a matching cache line tag, and causing the first in-core cache to flush a cache line matching the specified key identification code and the specified address according to the matching cache line tag carried by the first snoop request.

17. The method of claim 16, further comprising: causing the first snoop request to be received by a second level cache in the first in-core cache from the first snoop filter and to be passed by the second level cache to a first level cache in the first in-core cache.

18. The method of claim 17, further comprising: causing the second level cache to flush a cache line matching the specified key identification code and the specified address according to the matching cache line tag carried by the first snoop request; and causing the first level cache to flush a cache line matching the specified key identification code and the specified address according to the matching cache line tag carried by the first snoop request.

19. The method of claim 16, further comprising: causing the first snoop filter to also pass the first snoop request to a second in-core cache, the first processor further comprising a second core, the second core comprising the second in-core cache; causing the second in-core cache to flush a cache line matching the specified key identification code and the specified address according to the matching cache line tag carried by the first snoop request.

20. The method of claim 15, wherein: the first in-core cache comprises a first level cache and a second level cache; the first last level cache is a third level cache; and the flush request is passed by the first level cache to the second level cache and by the second level cache to the third level cache.

21. The method of claim 15, wherein: the first last level cache derives a tag and an index from a physical address corresponding to the specified address; and the cache line in the first last level cache matching the specified key identification code, the tag, and the index is the matching cache line.

22. The method of claim 15, further comprising: The first L2 cache is further configured to pass the flush request to a second L2 cache shared by a plurality of cores of a second processor on a second die through a channel between the first die and the second die; and The second L2 cache is configured to flush cache lines matching the specified key identification and the specified address according to the flush request.

23. The method of claim 22, further comprising: The second L2 cache is further configured to issue a second snoop request to a second snoop filter on the second processor to pass to a third in-core cache of a third core in the second processor, wherein the second snoop request carries a matching cache line flag, and the matching cache line flag is used by cache lines matching the specified key identification and the specified address in the third in-core cache and the second L2 cache; and The third in-core cache is configured to flush cache lines matching the specified key identification and the specified address according to the matching cache line flag carried by the second snoop request.

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