Memory system, memory controller, and method of operating a memory system

Abstract

The present application discloses a memory system, a memory controller and a method for operating the memory system. The memory system can configure a plurality of mapping cache pools for caching different types of mapping data in a mapping cache for caching mapping data, configure a timer in a first mapping cache pool among the plurality of mapping cache pools, and write the mapping data cached in the first mapping cache pool into a memory device based on the timer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2020-0106077, filed on August 24, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the disclosed technology relate to a memory system, a memory controller, and a method of operating a memory system. Background Art

[0004] A memory system may include a storage device that stores data. Such a memory system may operate based on a request from a host such as a computer, a mobile device (e.g., a smart phone or tablet), or other similar electronic device. Examples of memory systems may span from traditional hard disk drives (HDDs) to semiconductor-based data storage devices such as solid-state drives (SSDs), universal flash memory devices (UFS), or embedded MMC (eMMC) devices.

[0005] The memory system may further include a memory controller for controlling the memory device. The memory controller may receive a command from the host and execute the command or control a read / write / erase operation of the memory device included in the memory system. The memory controller may also be used to run firmware to perform logic operations for controlling such operations.

[0006] In conventional technology, a memory system manages mapping data for performing operations of reading, writing, and erasing data in a memory device. The memory system uses a mapping cache to cache the mapping data so as to quickly access the mapping data. After updating the mapping data cached in the mapping cache, the memory system flushes the mapping data cached in the mapping cache to the memory device when a specific condition is met. Summary of the invention

[0007] Embodiments of the disclosed technology may provide a memory system, a memory controller, and a method of operating the memory system, which can alleviate degradation in performance of a read operation and a write operation caused by densely clearing mapping data into a memory device.

[0008] Furthermore, embodiments of the disclosed technology may provide a memory system, a memory controller, and a method of operating the memory system, which are capable of satisfying QoS of a read operation and a write operation requested by a host.

[0009] According to one aspect, an embodiment of the disclosed technology may provide a memory system including a memory device operable to store data and a memory controller communicating with the memory device and configured to control the memory device.

[0010] The memory controller may configure a plurality of mapping cache pools that respectively cache different types of mapping data within the mapping cache that caches the mapping data.

[0011] The memory controller may configure a timer in a first mapping cache pool among the plurality of mapping cache pools.

[0012] The memory controller may write the mapping data cached in the first mapping cache pool into the memory device based on the timer.

[0013] On the other hand, an embodiment of the disclosed technology may provide a memory controller including a memory interface configured to communicate with a memory device operable to store data and a processor configured to communicate with the memory device through the memory interface and control the memory device.

[0014] The processor may configure a plurality of mapping cache pools for respectively caching different types of mapping data in the mapping cache for caching the mapping data.

[0015] The processor may configure a timer in a first mapping cache pool among the plurality of mapping cache pools.

[0016] The processor may write the mapping data cached in the first mapping cache pool to the memory device based on the timer.

[0017] In another aspect, embodiments of the disclosed technology may provide a method of operating a memory system.

[0018] A method of operating a memory system may include configuring a plurality of mapping cache pools for respectively caching different types of mapping data within a mapping cache provided to cache mapping data.

[0019] A method of operating a memory system may include configuring a timer in a first mapping cache pool among a plurality of mapping cache pools.

[0020] A method of operating a memory system may include writing mapping data cached in a first mapping cache pool to a memory device based on a timer.

[0021] In some embodiments of the disclosed technology, temporary degradation in performance of read and write operations due to intensive flushing of mapping data into a memory device may be mitigated.

[0022] Furthermore, in some embodiments of the disclosed technology, QoS of read operations and write operations requested by the host may be met. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other aspects, features and advantages of the disclosed technology will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0024] Figure 1 is a schematic diagram showing a configuration of a memory system according to an embodiment of the disclosed technology.

[0025] Figure 2 is a block diagram schematically illustrating a memory device according to an embodiment of the disclosed technology.

[0026] Figure 3 is a diagram illustrating a structure of word lines and bit lines of a memory device according to an embodiment of the disclosed technology.

[0027] Figure 4 is a block diagram schematically illustrating a memory system according to an embodiment of the disclosed technology.

[0028] Figure 5 Operation of a timer corresponding to each of a plurality of mapping cache pools according to an embodiment of the disclosed technology is shown.

[0029] Figure 6 An example of a method in which a memory system configures a region of each mapped cache pool according to an embodiment of the disclosed technology is shown.

[0030] Figure 7 Examples of the types of mapping data cached in various mapping cache pools according to embodiments of the disclosed technology are shown.

[0031] Figure 8 An example of a write size per update according to the type of map data is shown.

[0032] Fig. 9 Shown according to the reference Figure 8 An example of configuration of a timer of a type of mapping data is described.

[0033] Fig.10 is a flowchart illustrating an example of an operation in which a memory system according to an embodiment of the disclosed technology determines whether to stop a timer.

[0034] Fig.11 An example of a time point at which a memory system runs a timer according to an embodiment of the disclosed technology is shown.

[0035] Fig.12A method of operating a memory system according to an embodiment of the disclosed technology is shown.

[0036] Fig.13 is a diagram illustrating a configuration of a computing system according to an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings.

[0038] Figure 1 is a diagram showing a schematic configuration of a memory system 100 according to an embodiment of the disclosed technology.

[0039] Reference Figure 1 , the memory system 100 may include a memory device 110 configured to store data, and a memory controller 120 configured to control the memory device 110 .

[0040] The memory device 110 may include a plurality of memory blocks, each memory block including a predetermined number of memory cells for storing data. The memory device 110 may be configured to operate in response to a control signal received from the memory controller 120. The operation of the memory device 110 may include, for example, a read operation, a program operation (also referred to as a "write operation"), an erase operation, etc.

[0041] The memory cells in the memory device 110 are used to store data and may be arranged in a memory cell array. In some embodiments where the memory device 110 is a flash memory device, the memory cell array may be divided into memory blocks of memory cells, and each block includes a different page of memory cells. In some embodiments of a NAND flash memory device, a page of cells is the smallest storage unit that can be programmed (or written) and read, and data stored in the memory cells may be erased in units of memory blocks.

[0042] In some embodiments, the memory device 110 can be implemented as various types, such as double data rate synchronous dynamic random access memory (DDR SDRAM), fourth generation low power double data rate (LPDDR4) SDRAM, graphic double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin transfer torque random access memory (STT-RAM).

[0043] The memory device 110 may be implemented in a three-dimensional array structure. Embodiments of the disclosed technology may be applied to any type of flash memory device having a charge storage layer. In an embodiment, the charge storage layer may be formed of a conductive material, and such a charge storage layer may be referred to as a floating gate. In other embodiments, the charge storage layer may be formed of an insulating material, and such a flash memory device may be referred to as a charge capture flash memory (CTF).

[0044] The memory device 110 may be configured to receive a command and an address from the memory controller 120 and access a region of the memory cell array selected using the address. That is, the memory device 110 may perform an operation corresponding to the received command on a memory region in the memory device having a physical address corresponding to the address received from the memory controller 120.

[0045] In some embodiments, memory device 110 may perform, among other operations, programming operations, read operations, and erase operations. During a programming operation, memory device 110 may write ("program") data to an area selected by an address. During a read operation, memory device 110 may read data from a memory area selected by an address. During an erase operation, memory device 110 may erase data stored in a memory area selected by an address.

[0046] The memory controller 120 may control write (program) operations, read operations, erase operations, and background operations to be performed on the memory device 110. The background operations may include operations implemented to optimize the overall performance of the memory device 110, such as garbage collection (GC) operations, wear leveling (WL) operations, and bad block management (BBM) operations.

[0047] The memory controller 120 may control the operation of the memory device 110 at the request of the host. Alternatively, when the memory controller 120 performs such background operation of the memory device, it may control the operation of the memory device 110 even without a request from the host.

[0048] The memory controller 120 and the host may be separate devices. In some embodiments, the memory controller 120 and the host may be integrated and implemented as a single device. In the following description, as an example, the memory controller 120 and the host are separate devices.

[0049] Reference Figure 1 , the memory controller 120 may include a memory interface 122 , a control circuit 123 , and a host interface 121 .

[0050] The host interface 121 may be configured to provide an interface for communicating with a host.

[0051] When receiving a command from the host HOST, the control circuit 123 may receive the command through the host interface 121 and may perform an operation of processing the received command.

[0052] The memory interface 122 may be directly or indirectly connected to the memory device 110 to provide an interface for communicating with the memory device 110. That is, the memory interface 122 may be configured to provide the memory device 110 and the memory controller 120 with an interface for the memory controller 120 to perform a memory operation on the memory device 110 based on control signals and instructions from the control circuit 123.

[0053] The control circuit 123 may be configured to control the operation of the memory device 110 through the memory controller 120. For example, the control circuit 123 may include a processor 124 and a working memory 125. The control circuit 123 may further include an error detection / correction circuit (ECC circuit) 126 and the like.

[0054] The processor 124 may control the overall operation of the memory controller 120 . The processor 124 may perform logic operations. The processor 124 may communicate with the host HOST through the host interface 121 . The processor 124 may communicate with the memory device 110 through the memory interface 122 .

[0055] The processor 124 may be used to run a flash translation layer (FTL) to effectively manage memory operations on the memory system 100. For example, the processor 124 may convert a logical block address (LBA) provided by the host into a physical block address (PBA) through the FTL. The FTL may receive the LBA and convert the LBA into the PBA by using a mapping table.

[0056] Based on the mapping unit, FTL can adopt various address mapping methods. Typical address mapping methods may include page mapping method, block mapping method and hybrid mapping method.

[0057] The processor 124 may be configured to randomize the data received from the host to write the randomized data to the memory cell array. For example, the processor 124 may randomize the data received from the host by using a randomization seed. The randomized data is provided to the memory device 110 and written to the memory cell array.

[0058] The processor 124 may be configured to derandomize data received from the memory device 110 during a read operation. For example, the processor 124 may derandomize data received from the memory device 110 by using a derandomization seed. The derandomized data may be output to the host HOST.

[0059] The processor 124 may execute firmware (FW) to control the operation of the memory controller 120. In other words, the processor 124 may control the overall operation of the memory controller 120, and may execute (drive) the firmware loaded into the working memory 125 during booting in order to perform logical operations.

[0060] Firmware refers to a program or software stored on a specific non-volatile memory and runs inside the memory system 100 .

[0061] In some embodiments, the firmware may include various functional layers. For example, the firmware may include at least one of a flash translation layer (FTL) configured to translate a logical address in a host HOST request into a physical address of the memory device 110, a host interface layer (HIL) configured to interpret a command issued by the host HOST to a data storage device such as the memory system 100 and pass the command to the FTL, and a flash interface layer (FIL) configured to pass the command issued by the FTL to the memory device 110.

[0062] For example, the firmware may be stored in the memory device 110 and then loaded into the working memory 125 .

[0063] The working memory 125 may store firmware, program codes, commands or data necessary to drive the memory controller 120. The working memory 125 may include, for example, at least one of static RAM (SRAM), dynamic RAM (DRAM) and synchronous RAM (SDRAM) as a volatile memory.

[0064] Error detection / correction circuit 126 may be configured to detect and correct one or more erroneous bits in data by using error detection and correction codes. In some embodiments, the data subject to error detection and correction may include data stored in working memory 125 and data retrieved from memory device 110 .

[0065] The error detection / correction circuit 126 can be implemented to decode the data by using an error correction code. The error detection / correction circuit 126 can be implemented by using various decoding schemes. For example, a decoder that performs non-systematic code decoding or a decoder that performs systematic code decoding can be used.

[0066] In some embodiments, the error detection / correction circuit 126 can detect one or more error bits on a sector-by-sector basis. Each read data may include multiple sectors. As used herein, a "sector" may refer to a data unit that is smaller than the minimum unit (e.g., page) of a read operation of a flash memory. The sectors that constitute each read data may be mapped based on an address.

[0067] In some embodiments, the error detection / correction circuit 126 may calculate the bit error rate (BER) on a sector-by-sector basis and determine whether the number of error bits in the data is within the error correction capability. For example, if the BER is higher than a reference value, the error detection / correction circuit 126 may determine that the error bits in the corresponding sector are uncorrectable and mark the corresponding sector as "failed". If the BER is lower than or equal to the reference value, the error detection / correction circuit 126 may determine that the corresponding sector is correctable and may mark the corresponding sector as "passed".

[0068] The error detection / correction circuit 126 may sequentially perform error detection and correction operations on all read data. When a sector included in the read data is correctable, the error detection / correction circuit 126 may proceed to the next sector to check whether an error correction operation is required for the next sector. After completing the error detection and correction operations on all read data in this manner, the error detection / correction circuit 126 may identify which sector of the read data is considered uncorrectable. The error detection / correction circuit 126 may provide information (e.g., address information) about the sector considered uncorrectable to the processor 124.

[0069] The memory system 100 may further include a bus 127 to provide a channel between constituent elements 121, 122, 124, 125, and 126 of the memory controller 120. The bus 127 may include, for example, a control bus for transferring various types of control signals and commands, and a data bus for transferring various types of data.

[0070] Figure 1 120 by way of example. Note that some of the above constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 may be omitted, or some of the above constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 may be integrated into a single element. In some embodiments, one or more other constituent elements may be added to the above constituent elements of the memory controller 120.

[0071] In the following, reference will be made to Figure 2 The memory device 110 is described in more detail.

[0072] Figure 2 is a block diagram schematically illustrating a memory device 110 according to an embodiment of the disclosed technology.

[0073] In some implementations, a memory device 110 based on an embodiment of the disclosed technology may include a memory cell array 210 , an address decoder 220 , a read / write circuit 230 , a control logic 240 , and a voltage generation circuit 250 .

[0074] The memory cell array 210 may include a plurality of memory blocks BLK1 -BLKz, where z is a natural number equal to or greater than 2.

[0075] In the plurality of memory blocks BLK1 -BLKz, a plurality of word lines WL and a plurality of bit lines BL may be arranged in rows and columns, and a plurality of memory cells MC may be arranged.

[0076] The plurality of memory blocks BLK1-BLKz may be connected to the address decoder 220 through a plurality of word lines WL. The plurality of memory blocks BLK1-BLKz may be connected to the read / write circuit 230 through a plurality of bit lines BL.

[0077] Each of the plurality of memory blocks BLK1-BLKz may include a plurality of memory cells. For example, the plurality of memory cells are nonvolatile memory cells. In some embodiments, the nonvolatile memory cells may be arranged in a vertical channel structure.

[0078] The memory cell array 210 may be configured as a memory cell array having a two-dimensional structure. In some embodiments, the memory cell array 210 may be configured as a memory cell array having a three-dimensional structure.

[0079] Each of the plurality of memory cells included in the memory cell array 210 may store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 may be a single-layer cell (SLC) configured to store one bit of data per memory cell. For another example, each of the plurality of memory cells included in the memory cell array 210 may be a multi-layer cell (MLC) configured to store two bits of data per memory cell. For another example, each of the plurality of memory cells included in the memory cell array 210 may be a triple-layer cell (TLC) configured to store three bits of data per memory cell. For another example, each of the plurality of memory cells included in the memory cell array 210 may be a quad-layer cell (QLC) configured to store four bits of data per memory cell. For another example, the memory cell array 210 may include a plurality of memory cells, each of which may be configured to store at least five bits of data per memory cell.

[0080] Reference Figure 2 , the address decoder 220 , the read / write circuit 230 , the control logic 240 , and the voltage generation circuit 250 may operate as a peripheral circuit configured to drive the memory cell array 210 .

[0081] The address decoder 220 may be connected to the memory cell array 210 through a plurality of word lines WL.

[0082] The address decoder 220 may be configured to operate in response to commands and control signals from the control logic 240 .

[0083] The address decoder 220 may receive an address through an input / output buffer inside the memory device 110. The address decoder 220 may be configured to decode a block address among the received addresses. The address decoder 220 may select at least one memory block based on the decoded block address.

[0084] The address decoder 220 may receive a read voltage Vread and a pass voltage Vpass from the voltage generating circuit 250 .

[0085] When a read voltage is applied during a read operation, the address decoder 220 may apply the read voltage Vread to a selected word line WL inside a selected memory block, and may apply a pass voltage Vpass to remaining unselected word lines WL.

[0086] During a program verification operation, the address decoder 220 may apply a verification voltage generated by the voltage generation circuit 250 to a selected word line WL inside a selected memory block, and may apply a pass voltage Vpass to remaining unselected word lines WL.

[0087] The address decoder 220 may be configured to decode a column address among the received addresses. The address decoder 220 may transmit the decoded column address to the read / write circuit 230.

[0088] The memory device 110 may perform a read operation and a program operation on a page-by-page basis. An address received when requesting a read operation and a program operation may include at least one of a block address, a row address, and a column address.

[0089] The address decoder 220 may select a memory block and a word line based on the block address and the row address. The column address may be decoded by the address decoder 220 and provided to the read / write circuit 230.

[0090] The address decoder 220 may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

[0091] The read / write circuit 230 may include a plurality of page buffers PB. The read / write circuit 230 may operate as a “read circuit” when the memory cell array 210 performs a read operation, and may operate as a “write circuit” when the memory cell array 210 performs a write operation.

[0092] The above-mentioned read / write circuit 230 is also called a page buffer circuit including a plurality of page buffers PB, or a data register circuit. The read / write circuit 230 may include a data buffer capable of storing data for data processing, and in some embodiments, may further include a cache buffer for data caching.

[0093] The plurality of page buffers PB may be connected to the memory cell array 210 through the plurality of bit lines BL, respectively. In order to detect or sense the threshold voltage Vth of the memory cell during a read operation and a program verification operation, the plurality of page buffers PB may continuously supply a sensing current to the bit lines BL connected to the memory cell to detect a change in the amount of current flowing based on the programming state of the corresponding memory cell at the sensing node, and may save or latch the corresponding voltage as sensing data.

[0094] The read / write circuit 230 may operate in response to a page buffer control signal output from the control logic 240 .

[0095] During a read operation, the read / write circuit 230 senses a voltage value of a memory cell, and the voltage value is read out as data. The read / write circuit 230 temporarily stores the retrieved data and outputs the data DATA to an input / output buffer of the memory device 110. In an embodiment, the read / write circuit 230 may include a column selection circuit in addition to the page buffer PB or the page register.

[0096] The control logic 240 may be connected to the address decoder 220, the read / write circuit 230, and the voltage generating circuit 250. The control logic 240 may receive a command CMD and a control signal CTRL through an input / output buffer of the memory device 110.

[0097] The control logic 240 may be configured to control the overall operation of the memory device 110 in response to the control signal CTRL. The control logic 240 may output a control signal for adjusting a voltage level at a sensing node of the plurality of page buffers PB.

[0098] Control logic 240 may control read / write circuit 230 to perform a read operation on memory cells in memory cell array 210. Voltage generation circuit 250 may generate a read voltage Vread and a pass voltage Vpass used during a read operation in response to a voltage generation circuit control signal output from control logic 240.

[0099] The memory block BLK included in the memory device 110 may be composed of a plurality of pages PG, each of which includes a plurality of memory cells. In some embodiments, the plurality of memory cells may be arranged in a plurality of strings. The plurality of pages PG may be mapped to a plurality of word lines WL, and the plurality of strings STR may be mapped to a plurality of bit lines BL.

[0100] In the memory block BLK, a plurality of word lines WL and a plurality of bit lines BL may be arranged in rows and columns. For example, each of the plurality of word lines WL may be arranged in a row direction, and each of the plurality of bit lines BL may be arranged in a column direction. For another example, each of the plurality of word lines WL may be arranged in a column direction, and each of the plurality of bit lines BL may be arranged in a row direction.

[0101] A plurality of word lines WL and a plurality of bit lines BL may cross each other, thereby defining a memory cell array including a plurality of memory cells MC. Each memory cell MC may have a transistor TR disposed therein.

[0102] For example, the transistor TR arranged in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of the transistor TR may be connected to the corresponding bit line BL directly or via another transistor TR. The source (or drain) of the transistor TR may be connected to the source line (which may be grounded) directly or via another transistor TR. The gate of the transistor TR may include a floating gate (FG) surrounded by an insulator and a control gate (CG) to which a gate voltage is applied from the word line WL.

[0103] In each of the multiple storage blocks BLK1-BLKz, a first selection line (also called a source selection line or a drain selection line) may be additionally arranged on the outside of a first outermost word line that is closer to the read / write circuit 230 among the two outermost word lines, and a second selection line (also called a drain selection line or a source selection line) may be additionally arranged on the outside of the remaining second outermost word line.

[0104] In some cases, at least one dummy word line may be additionally arranged between the first outermost word line and the first selection line. In addition, at least one dummy word line may be additionally arranged between the second outermost word line and the second selection line.

[0105] A read operation and a program operation (write operation) of a memory block may be performed page by page, and an erase operation may be performed memory block by memory block.

[0106] Figure 3 is a diagram illustrating a structure of word lines WL and bit lines BL of a memory device 110 according to an embodiment of the disclosed technology.

[0107] Reference Figure 3 The memory device 110 has a core region where memory cells MC are concentrated, and an auxiliary region corresponding to the remaining region outside the core region. The auxiliary region includes circuits for supporting the operation of the memory cell array 210.

[0108] The core region may include a page PG and a string STR. In some embodiments, a plurality of word lines WL1 to WL9 and a plurality of bit lines BL are arranged to cross.

[0109] The word lines WL1 to WL9 may be connected to the row decoder 310. The bit lines BL may be connected to the column decoder 320. Figure 2 The data register 330 of the read / write circuit 230 may exist between the plurality of bit lines BL and the column decoder 320 .

[0110] The plurality of word lines WL1 to WL9 may correspond to a plurality of pages PG.

[0111] For example, each of the plurality of word lines WL1 to WL9 may correspond to one page PG. Figure 3 As shown. When each of the plurality of word lines WL1 to WL9 has a large size, each of the plurality of word lines WL1 to WL9 may correspond to at least two (e.g., two or four) pages PG. Each page PG is a minimum unit associated with performing a programming operation and a reading operation, and when performing a programming operation and a reading operation, all memory cells MC within the same page PG may perform the operation simultaneously.

[0112] A plurality of bit lines BL may be connected to the column decoder 320. In some embodiments, the plurality of bit lines BL may be divided into odd-numbered bit lines BL and even-numbered bit lines BL such that a pair of odd-numbered bit lines BL and even-numbered bit lines BL are commonly coupled to the column decoder 320.

[0113] The address can be used to access one or more memory cells MC in the core area. The address can be provided to the row decoder 310 and the column decoder 320 through the input / output terminal to select the corresponding target memory cell. As used herein, "target memory cell" can refer to one of the memory cells MC that is accessed as a target by the memory controller or user to program data therein or read programmed data therefrom, and in some embodiments, the memory cell MC may be located at the intersection between the word lines WL1 to WL9 connected to the row decoder 310 and the bit lines BL connected to the column decoder 320.

[0114] In some implementations, the data register 330 plays a role because all data processing by the memory device 110, including programming and reading operations, occurs through the data register 330. If the data processing of the data register 330 is delayed, all other regions need to wait until the data processing is completed by the data register 330. In addition, performance degradation of the data register 330 may degrade the overall performance of the memory device 110.

[0115] Reference Figure 3 In the example shown, in one string STR, a plurality of transistors TR1 to TR9 may be connected to a plurality of word lines WL1 to WL9, respectively. In some embodiments, the plurality of transistors TR1 to TR9 correspond to memory cells MC. In this example, the plurality of transistors TR1 to TR9 include a control gate CG and a floating gate FG.

[0116] The plurality of word lines WL1 to WL9 include two outermost word lines WL1 and WL9. A first selection line DSL may be additionally arranged outside the first outermost word line WL1, which is closer to the data register 330 and has a shorter signal path than the remaining outermost word lines WL9. A second selection line SSL may be additionally arranged outside the remaining second outermost word line WL9.

[0117] The first selection transistor D-TR whose on / off is controlled by the first selection line DSL has a gate electrode connected to the first selection line DSL but does not include a floating gate FG. The second selection transistor S-TR whose on / off is controlled by the second selection line SSL has a gate electrode connected to the second selection line SSL but does not include a floating gate FG.

[0118] The first selection transistor D-TR is used as a switch circuit that selectively connects the corresponding string STR to the data register 330. The second selection transistor S-TR is used as a switch circuit that selectively connects the corresponding string STR to the source line SL. The first selection transistor D-TR and the second selection transistor S-TR can be used to enable or disable the corresponding string STR.

[0119] During a programming operation, the memory system 100 fills the target memory cell MC to be programmed with electrons. Therefore, the memory system 100 applies a predetermined on-voltage Vcc to the gate electrode of the first selection transistor D-TR, thereby turning on the first selection transistor D-TR, and applies a predetermined off-voltage (e.g., 0V) to the gate electrode of the second selection transistor S-TR, thereby turning off the second selection transistor S-TR.

[0120] The memory system 100 turns on both the first selection transistor D-TR and the second selection transistor S-TR during a read operation or a verification operation. Therefore, during a read operation or a verification operation, a current may flow through the corresponding string STR and to the source line SL corresponding to the ground voltage, so that the voltage level of the bit line BL may be measured. However, during a read operation, there may be a time difference in on / off timing between the first selection transistor D-TR and the second selection transistor S-TR.

[0121] During the erase operation, the memory system 100 may apply a predetermined voltage (e.g., +20V) to the substrate through the source line SL. During the erase operation, the memory system 100 applies a specific voltage to allow both the first selection transistor D-TR and the second selection transistor S-TR to float, thereby generating an infinite resistance. As a result, the applied erase voltage may remove charge from the floating gate FG of the memory cell in the selected memory block.

[0122] When the operation of clearing the mapped data into the memory device and the read operation or write operation requested by the host are performed simultaneously, the performance of the read operation or write operation requested by the host may be affected, and thus the QoS may not be satisfied. Recognizing the above problems, some embodiments of the disclosed technology provide a memory system that can avoid a large amount of mapped data being intensively cleared into the memory device. Some embodiments of the disclosed technology can improve the QoS of operations requested from the host.

[0123] Figure 4 is a block diagram schematically illustrating a memory system according to an embodiment of the disclosed technology.

[0124] Reference Figure 4, the memory controller 120 of the memory system 100 may include a mapping cache (MAP_CACHE) in which mapping data is cached. When accessing the mapping data, the memory controller 120 may identify whether the mapping data that the memory controller 120 desires to access is cached in the mapping cache (MAP_CACHE). When the mapping data is cached in the mapping cache (MAP_CACHE), the memory controller 120 may access the mapping data in the mapping cache (MAP_CACHE). When the mapping data is not cached in the mapping cache (MAP_CACHE), the memory controller 120 may read the mapping data from the memory device 110 and then cache the mapping data from the memory device 110 into the mapping cache (MAP_CACHE).

[0125] The mapping cache (MAP_CACHE) may be located inside or outside the memory controller 120. For example, the mapping cache (MAP_CACHE) may be located in the working memory 125 within the memory controller 120. In another example, the mapping cache (MAP_CACHE) may be located in a separate volatile memory device (e.g., SRAM, DRAM) outside the memory controller 120.

[0126] In some embodiments of the disclosed technology, the memory controller 120 may configure multiple mapping cache pools (MC_POOL) within the mapping cache (MAP_CACHE). At this time, each of the multiple mapping cache pools (MC_POOL) may cache different types of mapping data. The multiple mapping cache pools (MC_POOL) may be divided based on the type of cached mapping data.

[0127] exist Figure 4 In the embodiment, the plurality of mapping cache pools (MC_POOL) may include a mapping cache pool for mapping data of cache type 1, a mapping cache pool for mapping data of cache type 2, a mapping cache pool for mapping data of cache type 3, and a mapping cache pool for mapping data of cache type 4. In this patent document, reference will be made later to Figure 7 Let's discuss the types of data further.

[0128] The memory controller 120 may configure a timer in at least one mapping cache pool among a plurality of mapping cache pools (MC_POOL).

[0129] At this time, a timer corresponding to the mapping cache pool may be used to determine a time point at which the mapping data cached in the corresponding mapping cache pool is cleared to the memory device 110. The clearing may correspond to writing the mapping data cached in the corresponding mapping cache pool to the memory device 110. In some embodiments, the memory controller 120 may configure a timer for all of the multiple mapping cache pools (MC_POOL). In some other embodiments, the memory controller 120 may configure a timer for only a portion of the multiple mapping cache pools (MC_POOL). Figure 4 In the example of , the memory controller 120 configures a timer for a mapping cache pool for caching mapping data of type 1, type 2, and type 3, but does not configure a timer for a mapping cache pool for caching mapping data of type 4.

[0130] Mapping data cached in a mapping cache pool for which no timer is configured may be cleared to the memory device 110 when a specific condition is met (e.g., when the size of the cached mapping data is greater than or equal to a threshold) rather than when a timer expiration condition is met.

[0131] The memory controller 120 may clear mapping data cached in the first mapping cache pool (MC_POOL_1) among the plurality of mapping cache pools (MC_POOL) to the memory device 110 based on a timer corresponding to the first mapping cache pool (MC_POOL_1).

[0132] Figure 5 The operation of a timer corresponding to each of a plurality of mapping cache pools (MC_POOL) according to an embodiment of the disclosed technology is shown.

[0133] Reference Figure 5 , the memory controller 120 may configure respective timers corresponding to a plurality of mapping cache pools (MC_POOL). For example, in each mapping cache pool, the timer may be configured differently by using different time interval settings.

[0134] For example, the memory controller 120 may configure a timer for a mapping cache pool so that mapping data cached in the corresponding mapping cache pool is cleared to the memory device 110 at time intervals T1.

[0135] The memory controller 120 may configure a timer for another mapping cache pool so that mapping data cached in the corresponding mapping cache pool is cleared to the memory device 110 at a time interval T2 different from T1.

[0136] The memory controller 120 may configure a timer for yet another mapping cache pool so that mapping data cached in the corresponding mapping cache pool is cleared to the memory device 110 at a time interval T3 different from T1 and T2 .

[0137] By configuring timers differently in the mapping cache pool (MC_POOL), the memory controller 120 may disperse the time points at which corresponding mapping data cached in the mapping cache (MAP_CACHE) is flushed to the memory device 110 .

[0138] Therefore, the memory controller 120 can prevent a problem that occurs because map data cached in the map cache (MAP_CACHE) is intensively flushed into the memory device 110 .

[0139] Generally, read requests and write requests from the host are constantly input to the memory controller 120. When the memory controller 120 uses a large amount of resources (e.g., space in the working memory 125) to flush mapping data cached in the mapping cache (MAP_CACHE) into the memory device 110, processing performance may be reduced due to a lack of resources available for processing the read request or the write request received from the host, and thus the QoS of the read operation and the write operation requested by the host may not be satisfied.

[0140] Therefore, in order to avoid this problem, the memory controller 120 can disperse the time points at which the mapping data cached in the mapping cache (MAP_CACHE) is cleared to the memory device 110 through a timer, so as to prevent a large amount of mapping data from being intensively cleared to the memory device. Therefore, the memory system 100 can alleviate the degradation of the performance of the read operation and the write operation that occurs due to the mapping data being intensively cleared to the memory device, thereby satisfying the QoS of the read operation and the write operation requested by the host.

[0141] The reason why the mapping data is distributed to each mapping cache pool and the mapping data is cleared in each mapping cache pool by configuring the plurality of mapping cache pools (MC_POOL) within the mapping cache (MAP_CACHE) has been described above.

[0142] In the following, reference will be made to Figure 6 An example of a method of configuring multiple map cache pools (MC_POOL) within a map cache (MAP_CACHE) is described.

[0143] Figure 6 An example of a method in which the memory system 100 configures a region of each mapped cache pool according to an embodiment of the disclosed technology is shown.

[0144] Reference Figure 6 , the memory controller 120 of the memory system 100 may configure a value of a register (REG) indicating an area of ​​a plurality of mapping cache pools (MC_POOL) in order to configure the plurality of mapping cache pools (MC_POOL) within a mapping cache (MAP_CACHE).

[0145] Here, the method of configuring the values ​​stored in the register (REG) may be determined in various ways. For example, each register (REG) may store the values ​​of the start address and the end address of the corresponding mapping cache pool. For another example, each register (REG) may store the values ​​of the start address and the size of the corresponding mapping cache pool.

[0146] Hereinafter, a detailed embodiment in which the memory controller 120 configures a timer corresponding to each of a plurality of mapping cache pools (MC_POOL) is described.

[0147] For example, the memory controller 120 may configure the timer corresponding to each of the plurality of mapping cache pools (MC_POOL) differently according to the type of mapping data cached in each mapping cache pool. That is, for the first mapping cache pool (MC_POOL_1) among the plurality of mapping cache pools (MC_POOL), the memory controller 120 may configure the timer corresponding to the first mapping cache pool (MC_POOL_1) according to the type of mapping data cached in the first mapping cache pool (MC_POOL_1).

[0148] In an embodiment of the disclosed technology, for example, types of mapping data may be divided as follows.

[0149] 1. L2V data types

[0150] The mapping data of the L2V data type is data indicating a mapping relationship between a logical address (LA) for transmission from the host and a virtual physical address (virtual address (VA)) of the memory device 110. The virtual physical address corresponds to a physical address of the virtual flash memory, which can be associated with the physical address of the memory device 110 through the virtual flash layer.

[0151] 2. VPT data type

[0152] The mapping data of the VPT data type is data indicating whether the area indicated by the mapping data is valid. In an embodiment, the area indicated by the mapping data may be a page located in the address indicated by the mapping data.

[0153] 3. Log data type

[0154] The mapping data of the log data type is data indicating a change in the mapping data, and can be used to track the change history of the mapping data.

[0155] 4. Other data types

[0156] The mapping data of other data types is data indicating remaining information (eg, a read count or an erase count of each memory block) other than the L2V data, the VPT data, and the log data.

[0157] Figure 7 Examples of the types of mapping data cached in various mapping cache pools according to embodiments of the disclosed technology are shown.

[0158] A plurality of map cache pools (MC_POOL) included in a map cache (MAP_CACHE) can cache different types of map data. Figure 7 In the example, multiple mapping cache pools (MC_POOL) can cache mapping data of L2V data types, VPT data types, and log data types respectively.

[0159] The memory controller 120 may configure a first timer (TIMER_1) for a mapping cache pool for caching mapping data of an L2V data type among a plurality of mapping cache pools (MC_POOL).

[0160] The memory controller 120 may configure a second timer (TIMER_2) for a mapping cache pool for caching mapping data of a VPT data type among the plurality of mapping cache pools (MC_POOL).

[0161] The memory controller 120 may configure a third timer (TIMER_3) for a mapping cache pool for caching mapping data of a log data type among the plurality of mapping cache pools (MC_POOL).

[0162] It has been described above that the memory controller 120 configures the timer according to the type of mapping data cached in the mapping cache pool.

[0163] Hereinafter, a detailed embodiment in which the memory controller 120 configures the timer value according to the type of mapping data cached in the mapping cache pool will be described.

[0164] For example, the memory controller 120 may configure a timer corresponding to a first mapping cache pool (MC_POOL_1) among the plurality of mapping cache pools (MC_POOL) based on at least one of a size of a cache line of the first mapping cache pool (MC_POOL_1), a number of stripes of mapping data cached in the first mapping cache pool (MC_POOL_1), and a configured target performance value. Figures 8 to 9 This is described in detail.

[0165] Figure 8 An example of a write size per update according to the type of map data is shown.

[0166] Reference Figure 8 , among the mapping data, L2V data has a size of 4B, VPT data has a size of 4B, and log data has a size of 12B.

[0167] When the L2V data is updated, the memory controller 120 reads a piece of L2V data, and for a piece of the read L2V data, updates the mapping information between the logical address and the virtual physical address stored in the corresponding L2V data, and then writes the L2V data. Therefore, when the L2V data is updated, the number of times the L2V data is written is once. When the L2V data is updated, the total size of the written L2V data is (4B*1)=4B.

[0168] When VPT data is updated, valid data is written to a new page, and the page storing the data of the previous version of the corresponding data is no longer valid. Therefore, the memory controller 120 updates a piece of VPT data that previously indicated a valid page to indicate an invalid page, and updates another piece of VPT data to indicate a new valid page. When VPT data is updated, the number of times the VPT data is written is two times. Therefore, when the VPT data is updated, the total size of the VPT data written is (4B*2)=8B.

[0169] When log data is updated, a new log data indicating the change information is written, and the regular log data is not changed, so the number of times the log data is written is once. Therefore, when the log data is updated, the total size of the written log data is (12B*1)=12B.

[0170] Fig. 9 Shown according to the reference Figure 8 An example of configuration of a timer of a type of mapping data is described.

[0171] As described above, when data is updated, the size of the written L2V data is 4B, the size of the written VPT data is 8B, and the size of the written log data is 12B.

[0172] The size of the cache line for caching mapping data in a mapping cache pool can be different for each mapping cache pool. Fig. 9 In the figure, it is assumed that the size of the cache line of the mapping cache pool that caches L2V data is 64B, the size of the cache line of the mapping cache pool that caches VPT data is 64B, and the size of the cache line of the mapping cache pool that caches log data is 128B.

[0173] In this case, when L2V data is updated, 4B of the cache line out of 64B is updated each time, so the dirty rate is 4B / 64B=1 / 16, which is the ratio of the cache line entering the dirty state each time it is updated.

[0174] In addition, when the VPT data is updated, 8B of the cache line out of 64B is updated at each update, so the dirty rate is 8B / 64B=1 / 8.

[0175] When the log data is updated, 12B of the cache line out of 128B is updated each time, so the dirty rate is 12B / 128B=3 / 32.

[0176] At this time, it is assumed that the number of stripes of the mapping data is 64, and the target performance is 1M IOPS (input / output operations per second). The 64 stripes of the mapping data means that the FTL stripes and processes a unit of one mapping data into 64. In this case, in order to meet 1M IOPS, 64 striped mapping data should be written every 1μs (= (1 / 1M)s).

[0177] Since the dirty rate of L2V data is 1 / 16, when 64 striped mapping data are updated, the number of cache lines in the dirty state is 64 / 16 = 4. Therefore, 4 cache lines should be cleared every 1 μs, and the timer value is therefore configured to 1 / 4 μs.

[0178] Since the dirty rate of VPT data is 1 / 8, when 64 striped mapping data are updated, the number of cache lines in the dirty state is 64 / 8 = 8. Therefore, 8 cache lines should be cleared every 1 μs, and the timer value is therefore configured to 1 / 8 μs.

[0179] Since the dirty rate of log data is 3 / 32, when 64 striped map data are updated, the number of cache lines in the dirty state is 64 / (32 / 3) = 6. Therefore, 6 cache lines should be cleared every 1 μs, and the timer value is therefore configured to 1 / 6 μs.

[0180] A method of configuring a timer in each mapping cache pool has been described.

[0181] Hereinafter, a time point at which a timer configured in each mapping cache pool stops is described.

[0182] Fig.10 is a flowchart illustrating an example of an operation in which the memory system 100 determines whether to stop a timer based on an embodiment of the disclosed technology.

[0183] Reference Fig.10 , in S1010 , the memory controller 120 of the memory system 100 may configure a timer corresponding to a first mapping cache pool ( MC_POOL_1 ) among a plurality of mapping cache pools (MC_POOL).

[0184] In step S1020 , the memory controller 120 may clear the mapping data cached on one cache line among the plurality of cache lines included in the first mapping cache pool ( MC_POOL_1 ) to the memory device 110 by running the timer configured in step S1010 .

[0185] In S1030, the memory controller 120 may determine whether the number of cache lines in a clean state among the plurality of cache lines included in the first mapping cache pool (MC_POOL_1) is greater than or equal to a preset threshold. The clean state corresponds to a state of the cache line in which any changes to the mapping data cached in the corresponding cache line are stored in the memory device 110.

[0186] When the number of cache lines in the clean state is greater than or equal to the preset threshold (S1030-Yes), the memory controller 120 may stop the timer corresponding to the first mapping cache pool (MC_POOL_1) in S1040. This is because the mapping data cached in the first mapping cache pool (MC_POOL_1) does not need to be cleared to the memory device 110 because the first mapping cache pool (MC_POOL_1) has enough extra space to store additional cache mapping data.

[0187] When the number of cache lines in the clean state is less than the preset threshold (S1030-No), the memory controller 120 may execute step S1010 again and reconfigure the timer corresponding to the first mapping cache pool (MC_POOL_1) to additionally clear the mapping data cached in the first mapping cache pool (MC_POOL_1).

[0188] A case has been described where there is no restriction on the point in time when the memory controller 120 runs the timer of the first mapping cache pool (MC_POOL_1).

[0189] Hereinafter, a case where the memory controller 120 operates the timer of the first mapping cache pool (MC_POOL_1) only at a point in time when a specific condition is satisfied will be described.

[0190] Fig.11 An example of a time point at which the memory system 100 runs a timer according to an embodiment of the disclosed technology is shown.

[0191] Reference Fig.11 , the memory controller 120 of the memory system 100 may run a timer corresponding to the first mapping cache pool in an idle state. The idle state may correspond to a state in which the memory system 100 does not process any request corresponding to a command received from the host or the memory system 100 does not process background operations (e.g., garbage collection or read reclamation).

[0192] The memory controller 120 may operate a timer corresponding to the first mapping cache pool (MC_POOL_1) only in an idle state, and may flush mapping data cached in the first mapping cache pool (MC_POOL_1) to the memory device 110 according to the timer.

[0193] When the memory controller 120 is in a busy state of processing a read operation or a write operation requested by the host or processing a background operation (e.g., garbage collection or read reclamation), the memory controller 120 does not run the timer corresponding to the first mapping cache pool (MC_POOL_1) to prevent performance degradation caused by clearing the mapping data into the memory device 110.

[0194] Fig.12 A method of operating the memory system 100 based on an embodiment of the disclosed technology is shown.

[0195] Reference Fig.12The method of operating the memory system 100 may include step S1210 of configuring a plurality of mapping cache pools (MC_POOL) for caching different types of mapping data in a mapping cache (MAP_CACHE) for caching mapping data.

[0196] The method of operating the memory system 100 may include step S1220 of configuring a timer in at least one mapping cache pool among the plurality of mapping cache pools (MC_POOL) configured in step S1210.

[0197] The method of operating the memory system 100 may include step S1230 of clearing mapping data cached in a first mapping cache pool (MC_POOL_1) among a plurality of mapping cache pools (MC_POOL) to the memory device 110 according to a timer corresponding to the first mapping cache pool (MC_POOL_1).

[0198] A timer corresponding to the first mapping cache pool (MC_POOL_1) may be configured according to the type of mapping data cached in the first mapping cache pool (MC_POOL_1).

[0199] For example, a timer corresponding to the first mapping cache pool (MC_POOL_1) may be configured based on the size of its cache lines, the number of stripes of mapping data cached in the first mapping cache pool (MC_POOL_1), and the configured target performance.

[0200] Meanwhile, the operation of the above-mentioned memory controller 120 may be controlled by the control circuit 123 , and the processor 124 may execute (drive) firmware that programs the general operation of the memory controller 120 .

[0201] Fig.13 is a diagram showing a configuration of a computing system 1300 based on an embodiment of the disclosed technology.

[0202] Reference Fig.13 , a computing system 1300 based on an embodiment of the disclosed technology may include: a memory system 100 electrically connected to a system bus 1360; a CPU 1310 configured to control the overall operation of the computing system 1300; a RAM 1320 configured to store data and information related to the operation of the computing system 1300; a user interface / user experience (UI / UX) module 1330 configured to provide a user environment to a user; a communication module 1340 configured to communicate with an external device of a wired and / or wireless type; and a power management module 1350 configured to manage the power used by the computing system 1300.

[0203] The computing system 1300 may be a personal computer (PC), or may include a mobile terminal such as a smart phone, a tablet computer, or various electronic devices.

[0204] The computing system 1300 may further include a battery for supplying an operating voltage, and may further include an application chipset, a graphic-related module, a camera image processor, and a DRAM. Other elements will be apparent to those skilled in the art.

[0205] The memory system 100 may include not only a device configured to store data in a disk, such as a hard disk drive (HDD), but also a device configured to store data in a non-volatile memory, such as a solid state drive (SSD), a universal flash memory device, or an embedded MMC (eMMC) device. The non-volatile memory may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. In addition, the memory system 100 may be implemented as various types of storage devices and installed in various electronic devices.

[0206] Based on the embodiments of the disclosed technology described above, the operation delay time of the memory system can be reduced or minimized. In addition, according to the embodiments of the disclosed technology, the overhead generated in the process of calling a specific function can be minimized. Although various embodiments of the disclosed technology have been described for illustrative purposes, it will be understood by those skilled in the art that various modifications, additions and substitutions may be made based on the contents described and illustrated in this patent document.

Claims

1. A memory system, comprising: a memory device operable to store data; as well as A memory controller that communicates with the memory device and controls the memory device by performing operations including: A plurality of mapping cache pools for caching different types of mapping data are configured in a mapping cache for caching mapping data. configuring a timer in a first mapping cache pool among the plurality of mapping cache pools, and Map data cached in the first mapping cache pool is written to the memory device based on the timer. 2 . The memory system of claim 1 , wherein the memory controller further configures registers that indicate regions of the plurality of mapping cache pools within the mapping cache. 3 . The memory system of claim 1 , wherein the memory controller further configures the timer based on a type of mapping data cached in the first mapping cache pool.

4. The memory system of claim 1 , wherein the different types include an L2V data type indicating a mapping relationship between a logical address and a virtual address, a VPT data type indicating validity of an area indicated by the mapping data, or a log data type indicating a change of the mapping data.

5. The memory system of claim 1 , wherein the memory controller further configures a timer corresponding to the first mapping cache pool based on at least one of a size of a cache line of the first mapping cache pool, a number of stripes of mapping data cached in the first mapping cache pool, and a target performance.

6. The memory system of claim 5 , wherein the memory controller stops a timer corresponding to the first mapping cache pool when detecting that the number of cache lines included in the first mapping cache pool and in a state in which changes in corresponding mapping data are stored in the memory device is greater than or equal to a preset threshold. 7 . The memory system of claim 1 , wherein when the memory controller is in an idle state, the memory controller runs a timer corresponding to the first mapping cache pool.

8. A memory controller comprising: a memory interface in communication with a memory device operable to store data; as well as a processor, communicating with the memory device through the memory interface and controlling the memory device, Wherein, the processor further 1) configures a plurality of mapping cache pools for respectively caching different types of mapping data within a mapping cache for caching mapping data, 2) configures a timer in a first mapping cache pool among the plurality of mapping cache pools, and 3) writes the mapping data cached in the first mapping cache pool to the memory device based on the timer.

9. The memory controller of claim 8, wherein the processor further configures registers that indicate regions of the plurality of mapping cache pools within the mapping cache.

10. The memory controller of claim 8, wherein the processor further configures the timer based on a type of mapping data cached in the first mapping cache pool.

11. The memory controller of claim 10, wherein the different types include an L2V data type indicating a mapping relationship between a logical address and a virtual address, a VPT data type indicating validity of an area indicated by the mapping data, or a log data type indicating a change of the mapping data.

12. The memory controller of claim 10 , wherein the processor further configures a timer corresponding to the first mapping cache pool based on at least one of a size of a cache line of the first mapping cache pool, a number of stripes of mapping data cached in the first mapping cache pool, and a target performance.

13. The memory controller of claim 12 , wherein the processor further stops a timer corresponding to the first mapping cache pool when the number of cache lines included in the first mapping cache pool and in a state in which changes in corresponding mapping data are stored in the memory device is greater than or equal to a preset threshold.

14. The memory controller of claim 8, wherein when the processor is in an idle state, the processor runs a timer corresponding to the first mapping cache pool.

15. A method of operating a memory system, the method comprising: configuring a plurality of mapping cache pools for caching different types of mapping data respectively in a mapping cache provided with caching mapping data; configuring a timer in a first mapping cache pool among the plurality of mapping cache pools; and Mapping data cached in the first mapping cache pool is written to a memory device of the memory system based on the timer.

16. The method of claim 15, wherein a timer corresponding to the first mapping cache pool is configured based on a type of mapping data cached in the first mapping cache pool.

17. The method of claim 16, wherein a timer corresponding to the first mapping cache pool is configured based on at least one of a size of a cache line of the first mapping cache pool, a number of stripes of mapping data cached in the first mapping cache pool, and a target performance.

18. The method according to claim 15, further comprising: configuring a timer in a second mapping cache pool among the plurality of mapping cache pools; as well as Based on a timer in the second mapping cache pool, mapping data cached in the second mapping cache pool is flushed to the memory device.

19. The method of claim 18, wherein a timer in the second mapping cache pool has a different time interval setting than a timer in the first mapping cache pool.

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