A high-speed data SGMII interface verification module and method

Abstract

The present invention relates to a high-speed data SGMII interface verification module and method, and the high-speed data SGMII interface verification method mainly comprises a high-speed data SGMII interface control module, a PCS module, a clock conversion module, a data conversion module and a PMA module. The high-speed data SGMII interface control module mainly loads and parses the high-speed data protocol, the PCS module is a physical coding sublayer, the PCS mainly includes line coding and CRC check coding, the clock conversion module in the high-speed data SGMII interface is to multiply and divide the clock according to the difference of the data bit width, the data conversion module is to convert the data into mutually matching bit widths, and the PMA module is mainly used for serialization and deserialization. The present invention solves the problem of mismatch between the clock and data bit widths of the controller and the physical media layer IP in the high-speed data SGMII interface by using adaptive matching of data and clock, and improves the multiplexing rate of IP and chip verification efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chip verification, and further to an FPGA prototype verification technology for reusing IP in chip verification, and in particular to a high-speed data SGMII interface verification module and method. Background Art

[0002] In the chip design process, chip verification is an important part of chip design, and FPGA prototype verification is an indispensable part of chip verification.

[0003] FPGA prototyping is a mature technology used to verify the functionality and performance of application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), and systems-on-chip (SoCs) by porting RTL to field-programmable gate arrays (FPGAs). It is used more extensively today due to the increasing complexity of hardware and the increasing amount of associated software that needs to be verified.

[0004] FPGAs have been used to verify relatively mature RTL because they can represent a nearly exact replica of a design running at high speeds. These replicas are also often portable enough to be used for field testing. On the pure hardware side, FPGA prototyping has become easier and more powerful as FPGA vendors move to the most advanced manufacturing process nodes as quickly as possible.

[0005] Since software typically accounts for more than half of the design effort, the FPGA implementation of the SOC RTL can also be used as the basis for software development, hardware / software co-verification, and software validation, all before the final silicon is available.

[0006] All of these factors help reduce design costs and time to market with less risk of re-spinning. For example, software that has been extensively validated on an FPGA prototype should be easier to combine with the first silicon from the fab. The FPGA prototype can also be used to set up any possible post-silicon debug paths.

[0007] When verifying the FPGA of a chip, such as SGMII, RapidIO and other high-speed interfaces, when using certain FPGA IP to replace the physical layer of the high-speed interface in the project, the controller data bit width and the optional bit width of the IP in the physical layer of the FPGA cannot match. The mismatch in bit width will also lead to clock inconsistency, resulting in the need to design or purchase IP separately. In order to solve this problem, a new verification method is proposed for FPGA verification of high-speed interfaces. This method solves the problem of bit width mismatch, optimizes the matching of clock matching, improves the reuse rate of IP verification, and reduces the verification cost. Summary of the invention

[0008] To this end, the purpose of the present invention is to provide a high-speed data SGMII interface verification method to solve the problem that the controller data bit width cannot match the IP selectable bit width of the physical layer in the FPGA when using certain FPGA IPs to replace the physical layer of the high-speed interface in the project, and to solve the problem of clock inconsistency caused by bit width mismatch, thereby reducing costs and increasing efficiency, and reducing the cost of designing or purchasing IP separately.

[0009] In order to solve the above technical problems, a high-speed data SGMII interface novel verification module of the present invention includes a high-speed data SGMII interface control module, a PCS module, a clock conversion module, a data conversion module and a PMA module;

[0010] The high-speed data SGMII interface control module mainly loads and parses the high-speed data protocol, and is connected to the PCS module for data exchange. In the sending path, the data of the high-speed data SGMII interface control module loading the protocol and the sending clock are transmitted to the PCS module for encoding and clock synchronization. The PCS transmits the encoded data and the synchronous sending clock to the data conversion module and the clock conversion module respectively. The clock conversion and data conversion modules convert the data bit width and clock frequency according to the data bit width ratio of the PCS module and the PMA module, transmit the synchronously converted data and clock to the PMA module for data serialization, and transmit the serialized data to the Serdes sending TX differential path of the PMA.

[0011] Optionally, on the receiving path, the Serdes of the PMA module receives the data received on the RX differential path, and transmits the deserialized data and the receiving clock of the PMA to the clock conversion module and the data conversion module through the PMA deserialization. The clock conversion and data conversion modules convert the data bit width and clock frequency according to the data bit width ratio between the PMA module and the PCS module. The PCS module decodes the converted data according to the received data and clock, and transmits it to the control end of the high-speed data SGMII interface.

[0012] Optionally, the high-speed data SGMII interface control module mainly loads and parses the high-speed data protocol, the PCS module is the physical coding sublayer, the PCS mainly includes line coding and CRC check coding, the clock conversion module in the high-speed data SGMII interface multiplies and divides the clock according to the difference in data bit width, the data conversion module converts data into mutually matching bit widths, and the PMA module is mainly used for serialization and deserialization.

[0013] Optionally, the clock conversion module divides or multiplies the synchronous transmission clock and the reception clock according to an integer ratio of the data bit width between the PCS module and the PMA module.

[0014] Optionally, the data conversion module converts data based on an integer ratio of data bit widths between the PCS module and the PMA module under a synchronous clock converted by a clock conversion module.

[0015] Another aspect of the present application further provides a high-speed data SGMII interface verification method, the verification method is based on the design and construction of a new verification module for the high-speed data SGMII interface, and comprises the following steps:

[0016] Step S1: the data conversion module includes a transmission path conversion clock data synchronization and a receiving path conversion clock data synchronization, wherein the transmission path conversion clock data synchronization converts every two consecutive 10-bit data into a 20-bit data in every two transmission clock cycles of the PCS module;

[0017] Step S2: The sending clock of the PMA module is obtained by dividing the PCS module clock by two, and the converted 20-bit data is synchronously transmitted to the PMA module under the sending clock of the PMA module;

[0018] Step S3: The receiving path converts the clock data synchronization to receive each 20-bit data in one receiving clock cycle of the PMA module;

[0019] Step S4: The PCS module receiving clock is obtained at twice the PMA module receiving clock. At every two PCS module receiving clocks, each 20-bit data is converted into two 10-bit data, and the data is transmitted to the PCS module in sequence at the PCS module receiving clock.

[0020] The above technical solution of the present invention has the following advantages over the prior art: a high-speed data SGMII interface verification module and method of the present invention realizes adaptive matching of data and clock, and solves the problem of mismatch between the clock and data bit width between the controller and the physical media layer IP in the high-speed data SGMII interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0022] Figure 1 It is a principle block diagram of the high-speed data SGMII interface verification method provided by the present invention;

[0023] Figure 2 The figure is the original block diagram of the clock conversion module and the data conversion module of the present invention;

[0024] Figure 3 This is a structural diagram of data and clock synchronization between the sending path and the receiving path in the data conversion module. DETAILED DESCRIPTION

[0025] like Figure 1 As shown, this embodiment provides a high-speed data SGMII interface verification module, including a high-speed data SGMII interface control module, a PCS (physical coding) module, a clock conversion module, a data conversion module and a PMA (physical medium access) module;

[0026] Further, Figure 1 The high-speed data SGMII interface novel verification method described in the original block diagram, the high-speed data SGMII interface control module mainly loads and parses the high-speed data protocol, it interacts with the PCS module for data, sends the RegisterWR / RD and TX / RXControl control signals to the PCS module to configure the PCS module and control the sending and receiving. In the sending path, the data TX_DATA and the sending clock TX_CLK_PCS loaded by the high-speed data SGMII interface control module are transmitted to the PCS module for encoding and clock synchronization. The PCS transmits the encoded data TX_DATA_PCS and the synchronous sending clock TX_CLK_PCS to the data conversion module and the clock conversion module respectively. The clock conversion and data conversion modules convert the data bit width and clock frequency according to the data bit width ratio of the PCS module and the PMA module, transmit the synchronously converted data TX_DATA_PMA and the clock TX_CLK_PMA to the PMA module for data serialization, and transmit the serialized data to the Serdes sending TX differential path of the PMA. On the receiving path, the Serdes of the PMA module receives the data received on the RX differential path, and transmits the deserialized data RX_DATA_PMA and the PMA receiving clock RX_CLK_PMA to the clock conversion module and the data conversion module through the PMA deserialization. The clock conversion and data conversion modules convert the data bit width and clock frequency according to the data bit width ratio of the PMA module and the PCS module to obtain the data RX_DATA_PCS and the clock RX_CLK_PCS. The PCS module decodes the received data RX_DATA_PCS to obtain RX_DATA, and transmits RX_DATA and the synchronous receiving clock RX_CLK_PCS to the control end of the high-speed data SGMII interface.

[0027] The high-speed data SGMII interface control module mainly loads and parses the high-speed data protocol, the PCS module is the physical coding sublayer, the PCS mainly includes line coding and CRC check coding, the clock conversion module in the high-speed data SGMII interface is to multiply and divide the clock according to the difference in data bit width, the data conversion module is to convert the data into mutually matching bit widths, and the PMA module is mainly used for serialization and deserialization.

[0028] Further, Figure 2 As shown in the original block diagram of the clock conversion module and the data conversion module, the clock conversion module divides or multiplies the synchronous transmission clock TX_CLK_PCS and the receiving clock RX_CLK_PMA according to the data bit width integer ratio between the PCS module and the PMA module to obtain the half-frequency TX_CLK_PMA of TX_CLK_PCS and the double-frequency TX_CLK_PCS of RX_CLK_PMA.

[0029] Figure 2 As shown in the original block diagram of the clock conversion module and the data conversion module, the data conversion module includes a sending path conversion clock data synchronization and a receiving path conversion clock data synchronization. The data conversion module is based on the data bit width integer ratio between the PCS module and the PMA module. Under the synchronous clock converted by the clock conversion module, the data is converted to convert two consecutive 10-bit wide TX_DATA_PCS into a 20-bit wide TX_DATA_PMA, and each 20-bit wide PMA receive data RX_DATA_PMA is converted into two 10-bit wide RX_DATA_PCS data.

[0030] The following is combined with Figure 3 The high-speed data SGMII interface verification module is shown in detail to introduce a high-speed data SGMII interface verification method provided by an embodiment of the present application, including the following steps:

[0031] Step S1: the data conversion module includes a transmission path conversion clock data synchronization and a receiving path conversion clock data synchronization, wherein the transmission path conversion clock data synchronization converts every two consecutive 10-bit data into a 20-bit data in every two transmission clock cycles of the PCS module;

[0032] Step S2: The sending clock of the PMA module is obtained by dividing the PCS module clock by two, and the converted 20-bit data is synchronously transmitted to the PMA module under the sending clock of the PMA module;

[0033] That is, in the odd-numbered PCS transmit clock cycle TX_CLK_PCS0, the received odd-numbered 10-bit data is cached in Buffer0, and in the next PCS transmit clock cycle TX_CLK_PCS1, the data is cached in Buffer1. Since TX_CLK_PMA is obtained by dividing TX_CLK_PCS, the two clocks are synchronized. In the odd-numbered PMA clock cycle TX_CLK_PMA0, the data of Buffer0 and Buffer1 are arranged and combined according to the high and low bits, that is, Buffer3

[19] , Buffer3

[18] , Buffer3

[17] , Buffer3

[16] , Buffer3

[15] , Buffer3

[14] , Buffer3

[13] , Buffer3

[12] , Buffer3

[11] , Buffer3

[10] , Buffer3[9], Buffer3[8], B uffer3[7], Buffer3[6], Buffer3[5], Buffer3[4], Buffer3[3], Buffer3[2], Buffer3[1], and Buffer3[0] correspond to Buffer2[0], Buffer2[1], Buffer2[2], Buffer2[3], Buffer2[4], Buffer2[5], Buffer2[6], Buffer2[7], Buffer2[8], Buffer2[9], Buffer1[0], Buffer1[1], Buffer1[2], Buffer1[3], Buffer1[4], Buffer1[5], Buffer1[6], Buffer1[7], Buffer1[8], and Buffer1[9] respectively, and the converted data and TX_CLK_PMA are transmitted to the PMA module at the same time.

[0034] Step S3: The receiving path converts the clock data synchronization to receive each 20-bit data in one receiving clock cycle of the PMA module;

[0035] Step S4: The PCS module receiving clock is obtained at twice the PMA module receiving clock. At every two PCS module receiving clocks, each 20-bit data is converted into two 10-bit data, and the data is transmitted to the PCS module in sequence at the PCS module receiving clock.

[0036] Furthermore, the receiving path conversion clock data synchronization will receive each 20-bit data under one receiving clock cycle RX_CLK_PMA of the PMA module. The receiving clock RX_CLK_PCS of the PCS module is obtained at twice the frequency of the receiving clock RX_CLK_PMA of the PMA module. Under each receiving clock RX_CLK_PMA0 of the PMA module, each 20-bit data RX_DATA_PMA is converted into two 10-bit data Buffer0 and Buffer1. That is, under one RX_CLK_PAM clock, Buffer1 and Buffer2[0], Buffer2[1], Buffer2[2], Buffer2[3], Buffer2[4], Buffer2[5], Buffer2[6], Buffer2[7], Buffer2[8], Buffer2[9], Buffer1[0], Buffer1[1], Buffer1[2], Buffer1[3], Buffer1[4], Buffer1[5], Buffer1[6], Buffer1[7], Buffer1[8], Buffer1[9] in Buffer1 and Buffer2 are respectively The RX_DATA_PMA

[19] , RX_DATA_PMA

[18] , RX_DATA_PMA

[17] , RX_DATA_PMA

[16] , RX_DATA_PMA

[15] , RX_DATA_PMA

[14] , RX_DATA_PMA

[13] , RX_DATA_PMA

[12] , RX_DATA_PMA

[11] , RX_DATA_PMA

[10] , RX_DATA_PMA[9], RX_DATA_PMA[8], RX_DATA_PMA[ 7], RX_DATA_PMA[6], RX_DATA_PMA[5], RX_DATA_PMA[4], RX_DATA_PMA[3], RX_DATA_PMA[2], RX_DATA_PMA[1], RX_DATA_PMA[0], in the odd RX_CLK_PCS0 clock cycle, the data of Buffer1 is transferred to Buffer3 and sent to the PCS module, and in the next RX_CLK_PCS1 clock cycle, the data of Buffer2 is transferred to Buffer3 and sent to the PCS module. In this way, the adaptive matching of data and clock is achieved, and the problem of mismatch between the clock and data bit width between the controller and the physical media layer IP in the high-speed data SGMII interface is solved.

[0037] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A high-speed data SGMII interface verification module, characterized in that: Including high-speed data SGMII interface control module, PCS module, clock conversion module, data conversion module and PMA module; The high-speed data SGMII interface control module mainly loads and parses the high-speed data protocol, and is connected to the PCS module for data exchange. In the sending path, the data loaded by the high-speed data SGMII interface control module and the sending clock are transmitted to the PCS module for encoding and clock synchronization. The PCS transmits the encoded data and the synchronous sending clock to the data conversion module and the clock conversion module respectively. The clock conversion and data conversion modules convert the data bit width and clock frequency according to the data bit width ratio of the PCS module and the PMA module, transmit the synchronously converted data and clock to the PMA module for data serialization, and transmit the serialized data to the Serdes sending TX differential path of the PMA; On the receiving path, the Serdes of the PMA module receives the data received on the RX differential path, and transmits the deserialized data and the PMA receiving clock to the clock conversion module and the data conversion module through the PMA deserialization. The clock conversion and data conversion modules convert the data bit width and clock frequency according to the data bit width ratio between the PMA module and the PCS module. The PCS module decodes the converted data according to the received data and clock, and transmits it to the control end of the high-speed data SGMII interface.

2. A high-speed data SGMII interface verification module according to claim 1, characterized in that: The high-speed data SGMII interface control module mainly loads and parses the high-speed data protocol, the PCS module is the physical coding sublayer, the PCS mainly includes line coding and CRC check coding, the clock conversion module in the high-speed data SGMII interface is to multiply and divide the clock according to the difference in data bit width, the data conversion module is to convert the data into mutually matching bit widths, and the PMA module is mainly used for serialization and deserialization.

3. A high-speed data SGMII interface verification module according to claim 1, characterized in that: The clock conversion module divides or multiplies the synchronous transmission clock and the reception clock according to the data bit width integer ratio between the PCS module and the PMA module.

4. A high-speed data SGMII interface verification module according to claim 1, characterized in that: The data conversion module converts data based on the data bit width integer ratio between the PCS module and the PMA module under the synchronous clock converted by the clock conversion module.

5. A high-speed data SGMII interface verification method, the verification method is based on the design and construction of the high-speed data SGMII interface new verification module according to claims 1-4, characterized in that: The steps include: Step S1: the data conversion module includes a transmission path conversion clock data synchronization and a receiving path conversion clock data synchronization, wherein the transmission path conversion clock data synchronization converts every two consecutive 10-bit data into a 20-bit data in every two transmission clock cycles of the PCS module; Step S2: The sending clock of the PMA module is obtained by dividing the PCS module clock by two, and the converted 20-bit data is synchronously transmitted to the PMA module under the sending clock of the PMA module; Step S3: The receiving path converts the clock data synchronization to receive each 20-bit data in one receiving clock cycle of the PMA module; Step S4: The PCS module receiving clock is obtained at twice the PMA module receiving clock. At every two PCS module receiving clocks, each 20-bit data is converted into two 10-bit data, and the data is transmitted to the PCS module in sequence at the PCS module receiving clock.

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