Chip verification method, device, equipment and storage medium

Abstract

The application provides a chip verification method, device and equipment and a storage medium. The method comprises the following steps: obtaining a configuration file of a chip system management network to be tested; extracting configuration information of the chip system management network from the configuration file, and generating a verification file suitable for a verification environment according to the configuration information; and referencing the verification file in the verification environment to perform simulation verification, and generating verification result information of the chip system management network. The application can accelerate the construction and later iteration of the chip system management network verification environment, and greatly improves the verification efficiency of the chip system management network.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip testing technical field, in particular to a chip verification method, device, equipment and storage medium. BACKGROUND

[0002] SOC (System on Chip) is a system or product formed by combining multiple integrated circuits with specific functions on a chip, which contains a complete hardware system and embedded software carried thereby. Chip verification is to verify whether the chip design meets the requirements of the chip definition, whether the risk has been completely released, and whether all defects have been found and corrected by using a corresponding verification language, verification tool and verification method before the chip is produced.

[0003] With the rapid development of integrated circuit technology, the design scheme of the chip becomes more and more complex. In order to meet the more complex functional requirements, the SOC chip has a very high degree of integration. And the chip system management network, as a network for transmitting control information between various chip modules, also becomes very large with the rapid increase of integrated modules. This also puts forward higher requirements for the rapid establishment and iterative maintenance of the verification environment of the system management network.

[0004] In the existing system management network verification environment, the number of chip modules in the system is increasing, and the number of data paths of control signals between modules is also increasing. The verification of the system control network needs to be manually built by the verification personnel, and the corresponding verification environment needs to be configured to complete the data monitoring comparison of each node of the signal transmission. If the system has new modules or routing nodes, the verification module needs to be manually added to adapt to the new verification requirements. When the chip scale is very large, the design is often changed in the early stage, and the information of each data path needs to be frequently modified. If the corresponding configuration of the iterative verification environment is manually modified, it may take several days or even a week to complete a change, which is extremely low in efficiency and far from meeting the verification requirements of the complex chip system. SUMMARY

[0005] The purpose of the embodiments of the present application is to provide a chip verification method, device, equipment and storage medium, which can accelerate the establishment and later iteration of the chip system management network verification environment, and greatly improve the verification efficiency of the chip system management network.

[0006] The first aspect of the embodiments of the present application provides a chip verification method, comprising: acquiring a configuration file of a chip system management network to be tested; extracting configuration information of the chip system management network from the configuration file, and generating a verification file suitable for a verification environment according to the configuration information; and referencing the verification file in the verification environment for simulation verification to generate verification result information of the chip system management network.

[0007] In one embodiment, the chip system management network comprises a plurality of interface nodes and a plurality of routing nodes.

[0008] In one embodiment, the extracting the configuration information of the chip system management network from the configuration file and generating a verification file applicable to a verification environment according to the configuration information comprises: extracting interface configuration information, routing configuration information and data path configuration information of the chip system management network from the configuration file; and generating the verification file applicable to the verification environment according to the interface configuration information, the routing configuration information and the data path configuration information.

[0009] In one embodiment, the interface configuration information comprises a size of an input buffer area and a size of an output buffer area of each interface node.

[0010] In one embodiment, the routing configuration information comprises bandwidth information and broadcast information of each port of each routing node.

[0011] In one embodiment, the data path configuration information comprises destination interface node information of each data path and routing node information via which the destination interface node is reached.

[0012] In one embodiment, the generating the verification file applicable to the verification environment according to the interface configuration information, the routing configuration information and the data path configuration information comprises: generating a check function of each of the plurality of interface nodes, the plurality of routing nodes and each data path according to the interface configuration information, the routing configuration information and the data path configuration information; and writing the check function, the interface configuration information, the routing configuration information and the data path configuration information into corresponding files of the verification environment to generate the verification file of the chip system management network.

[0013] In one embodiment, the method further comprises: upon receiving an updated configuration file of the chip system management network, updating a verification file applicable to the verification environment according to the updated configuration file.

[0014] A second aspect of the embodiments of the present application provides a chip verification device, comprising: a file acquisition module configured to acquire a configuration file of a chip system management network to be tested; a file generation module configured to extract configuration information of the chip system management network from the configuration file and generate a verification file applicable to a verification environment according to the configuration information; and a simulation module configured to perform simulation verification in the verification environment by referencing the verification file to generate verification result information of the chip system management network.

[0015] In an embodiment, the chip system management network comprises a plurality of interface nodes and a plurality of routing nodes.

[0016] In an embodiment, the file generation module is configured to extract interface configuration information, routing configuration information and data path configuration information of the chip system management network from the configuration file, and generate the verification file applicable to the verification environment according to the interface configuration information, the routing configuration information and the data path configuration information.

[0017] In an embodiment, the interface configuration information comprises a size of an input buffer and a size of an output buffer of each interface node.

[0018] In an embodiment, the routing configuration information comprises bandwidth information and broadcast information of each port of each routing node.

[0019] In an embodiment, the data path configuration information comprises destination interface node information of each data path and routing node information via which the destination interface node is reached.

[0020] In an embodiment, the file generation module is configured to generate a check function of each interface node, a check function of each routing node and a check function of each data path according to the interface configuration information, the routing configuration information and the data path configuration information, and write the check functions, the interface configuration information, the routing configuration information and the data path configuration information into corresponding files of the verification environment to generate the verification file of the chip system management network.

[0021] In an embodiment, the method further comprises: updating a verification file applicable to the verification environment according to an updated configuration file of the chip system management network when the updated configuration file is received.

[0022] A third aspect of embodiments of the present application provides an electronic device, comprising: a memory configured to store a computer program; and a processor configured to execute the computer program to implement the method of the first aspect of embodiments of the present application and any one of the embodiments thereof.

[0023] A fourth aspect of embodiments of the present application provides a non-transitory electronic device readable storage medium, comprising: a program, when executed by an electronic device, causing the electronic device to perform the method of the first aspect of embodiments of the present application and any one of the embodiments thereof.

[0024] The chip verification method, device, equipment, and storage medium provided by this application first obtains the configuration information file containing all the system management network configuration information provided by the designer, then automatically extracts the configuration information through a script and generates a verification file in the format required by the verification environment. The generated verification file is then integrated into the verification environment, and the verification file can be referenced in the verification environment for simulation verification. This reduces manual intervention in the verification process and greatly shortens the verification cycle, thereby accelerating the construction and iteration of the chip system management network verification environment and improving verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A schematic diagram of an electronic device according to an embodiment of the present application;

[0027] Figure 2 A schematic diagram of a chip system management network according to an embodiment of the present application;

[0028] Figure 3 This is a flowchart of a chip verification method according to an embodiment of the present application;

[0029] Figure 4A This is a flowchart of a chip verification method according to an embodiment of the present application;

[0030] Figure 4B This is a schematic diagram of a Python script according to an embodiment of the present application;

[0031] Figure 5 FIG. 1 is a schematic diagram of a chip verification device according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings. In the description of the present application, the terms "first", "second", etc. are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0033] In order to clearly describe the solution of this embodiment, the terms involved are defined as follows:

[0034] SOC: System-on-a-Chip, SoC is called system-level chip, also known as system on chip, which means it is a product, is a dedicated target integrated circuit, which contains a complete system and all embedded software.

[0035] Python: A computer language designed by Guido van Rossum of the Netherlands Mathematical and Computer Science Research Institute in the early 1990s, with strong simplicity, readability and scalability, which can use C or C++ to extend new functions and data types.

[0036] UVM: Universal Verification Methodology, a verification platform development framework based on SystemVerilog class library, which can be used by verification engineers to build a verification environment with standardized hierarchy and interface functions.

[0037] System Management Network: Chip system management network, used to control the data path between chip modules.

[0038] As shown in Figure 1 The embodiment provides an electronic device 1, comprising at least one processor 11 and a memory 12, Figure 1 The processor 11 and the memory 12 are connected through the bus 10. The memory 12 stores instructions executable by the processor 11, and the instructions are executed by the processor 11 to make the electronic device 1 execute all or part of the processes of the method in the following embodiments, to accelerate the building and later iteration of the chip system management network verification environment, and improve the verification efficiency of the chip system management network.

[0039] In an embodiment, the electronic device 1 can be a handheld device, a notebook computer, a desktop computer or a large-scale computing system composed of multiple computers supporting the running of a simulation program.

[0040] With the rapid development of integrated circuit technology, the design scheme of the chip becomes more and more complex. In order to meet the more complex functional requirements, the SOC chip has a very high degree of integration. And the chip system management network, as a network for transmitting control information between various chip modules, also becomes very large with the rapid increase of integrated modules. This also puts forward higher requirements for the rapid building and iteration maintenance of the verification environment of the system management network. With the existing system management network verification environment, the number of chip modules in the system is increasing, and the number of data paths of control signals between modules is also increasing.

[0041] Please refer to Figure 2Fig. 1 is a schematic diagram of an application scenario of a chip system management network according to an embodiment of the present application. The chip system management network can include a plurality of interface nodes and a plurality of routing nodes. Each interface node includes an input node and an output node.

[0042] In actual use, if a chip has 60 chip modules, each chip module has a bidirectional control signal communication requirement, and a full permutation has 3600 data paths in total. A complete data path first needs each chip module to access the chip system management network through an interface node, and then reaches another interface node to be accessed through a plurality of routing nodes, thereby accessing another chip module. A data path thus needs to set the interface nodes at both ends and a plurality of intermediate routing nodes, and configure the address routing, bandwidth allocation, and other information of each node. If all 3600 data paths are considered, the configuration information required is in the tens of thousands to one hundred thousand or more.

[0043] Current verification of a chip system control network often needs a verification personnel to manually build and configure a corresponding verification environment, to complete data monitoring and comparison of each node of a data path. If a chip module or a routing node is added to the chip system, a verification module needs to be manually added to adapt to the new verification requirement. Taking the above chip scale (60 chip modules) as an example, and considering that the design is often changed in the early stage, the information of each data path needs to be frequently modified. If the corresponding configuration of the iterative verification environment is manually modified, it can take several days or even a week to complete a change, which is extremely low in efficiency and far from meeting the verification requirement of a complex chip system.

[0044] Fig. 1 is a schematic diagram of an application scenario of a chip system management network according to an embodiment of the present application. The chip system management network can include a plurality of interface nodes and a plurality of routing nodes. Each interface node includes an input node and an output node. Figure 3 Fig. 2 is a chip verification method according to an embodiment of the present application. The method can be executed by the electronic device 1 shown in Fig. 1, and can be applied to a verification scenario of the chip system management network in Fig. 1, to accelerate the building and later iteration of a chip system management network verification environment, and improve the verification efficiency of the chip system management network. The method includes the following steps. Figure 1 Figure 2

[0045] Step 301: Obtain a configuration file of a chip system management network to be tested.

[0046] ​​In this step, a chip often includes multiple chip modules that can realize independent functions, and the respective chip modules complete corresponding chip functions through establishing data paths. The chip system management network is a network architecture for controlling data transmission between the respective chip modules, and the completeness of its functions determines the overall quality of the chip. Therefore, the chip system management network also needs to be verified when the chip is verified. The chip system management network generally includes multiple interface nodes and multiple routing nodes. The respective chip modules complete corresponding data path functions by accessing the chip system management network. The configuration file of the chip system management network can be a file containing configuration information of each data path, which can be entered by a chip designer to obtain, or the configuration file can be read from a corresponding database.

[0047] Step 302: Extracting configuration information of the chip system management network from the configuration file, and generating a verification file suitable for the verification environment according to the configuration information.

[0048] In this step, the configuration file can be a json format file or other format file, which is not limited here. Taking the json format configuration file as an example, a python script can be written to automatically extract the configuration information of the chip system management network from the configuration file, and convert the configuration information into a format required by the verification environment. Here, the verification environment can be a verification environment based on the UVM platform, and the converted verification file can be an SV (System Verilog) format file.

[0049] Step 303: Referencing the verification file in the verification environment for simulation verification to generate verification result information of the chip system management network.

[0050] In this step, the above-mentioned SV format verification file can be integrated into the verification environment based on the UVM platform, that is, the target verification environment for the chip system management network can be obtained. Then, the verification file is referenced in the target verification environment for simulation verification to generate the verification result information of the chip system management network. In this way, the entire environment building and verification process is automatically completed, improving the chip verification efficiency.

[0051] The above-mentioned chip verification method first obtains the configuration information file provided by the designer and containing all the configuration information of the system management network, then automatically extracts the configuration information through a script, generates a verification file in a format required by the verification environment, and integrates the above-mentioned generated verification file into the verification environment, so that the verification file can be referenced in the verification environment for simulation verification. In this way, manual intervention in the verification process is reduced, the verification period is greatly shortened, and the building and iteration of the chip system management network verification environment are accelerated, thereby improving the verification efficiency.

[0052] Please refer toFigure 4A which is a chip verification method of an embodiment of the present application. The method can be executed by the electronic device 1 shown in Figure 1 and can be applied to the verification scenario of the chip system management network in the above-mentioned Figure 2 to accelerate the establishment and later iteration of the chip system management network verification environment and improve the verification efficiency of the chip system management network. The method includes the following steps:

[0053] Step 401: Obtain the configuration file of the chip system management network to be tested. For details, see the description of step 301 in the above-mentioned embodiments.

[0054] Step 402: Extract the interface configuration information, routing configuration information, and data path configuration information of the chip system management network from the configuration file.

[0055] In this step, the configuration file contains all the configuration information files of the system management network, such as complete routing information of each interface node, routing node, and data path. The interface configuration information, routing configuration information, and data path configuration information of the chip system management network can be extracted from the configuration file through a python script.

[0056] In an embodiment, the interface configuration information includes but is not limited to the size of the input buffer area and the size of the output buffer area of each interface node.

[0057] In an embodiment, the routing configuration information includes but is not limited to the bandwidth information and broadcast information of each port of each routing node.

[0058] In an embodiment, the data path configuration information includes but is not limited to the destination interface node information of each data path and the routing node information to be passed through to reach the destination interface node.

[0059] The chip shown in Figure 2 includes 60 chip modules, a total of 3600 data paths, for example, a total of 100,000 rows of configuration information are generated. The specific configuration information includes interface node configuration information, such as the size of the input and output buffer area. Routing node configuration information mainly includes routing node port bandwidth information and broadcast information, etc. Complete data path configuration information mainly includes the complete routing table of all data paths, such as which routing nodes need to be passed through to reach the destination interface node, and which port of each routing node to take, etc.

[0060] Step 403: Generate a verification file suitable for the verification environment according to the interface configuration information, routing configuration information, and data path configuration information.

[0061] In this step, the extracted relevant configuration information can be automatically converted into a verification file in a format required by a UVM platform-based verification environment by using a python script, such as an SV format verification file.

[0062] As shown in Figure 4B , the python script can specifically include a processing interface node configuration information module 201, a processing routing node configuration information module 202, and a processing complete routing path configuration information module 203, where the specific functions of the modules are as follows:

[0063] (1) Processing interface node configuration information module 201

[0064] used to extract all configuration information of the interface node and generate a verification file in a format required by the verification environment.

[0065] (2) Processing routing node configuration information module 202

[0066] used to extract all configuration information of the routing node and generate a verification file in a format required by the verification environment.

[0067] (3) Processing complete routing path configuration information module 203

[0068] used to extract all data paths required by the interface node, the routing node, and the routing relationship between the nodes, and the above information constitutes a complete routing table of all data paths, and the routing table is converted into a verification file suitable for the verification environment.

[0069] In an embodiment, step 403 can include generating a plurality of interface nodes, a plurality of routing nodes, and a check function for each data path according to the interface configuration information, the routing configuration information, and the data path configuration information. The check function, the interface configuration information, the routing configuration information, and the data path configuration information are written into corresponding files of the verification environment to generate a verification file of the chip system management network.

[0070] In this step, the verification of each function requires a corresponding check function for checking whether each function meets the expectation. Here, a python script can be used to generate the corresponding check function. As shown in Figure 4B , the python script can further include a corresponding check function generation module 204 for generating a check function for all nodes and data paths in the verification environment according to the configuration information of the system management network, thereby implementing different checking methods for different nodes and paths. The specific working process of the check function can be to extract the actual value of each node signal in the simulation result of the system management network, and compare the actual value with the expected value in the configuration information to perform corresponding function checking.

[0071] After the configuration information and the checking function are prepared, the generated configuration information and the checking function are written into a format file suitable for a verification environment, and a verification file of the chip system management network is obtained. For example, the configuration information and the checking function in the above configuration file in the json format are written into an SV format file, and finally an SV format verification file is generated. The verification file can be called in the verification environment based on the UVM platform. Thus, the construction and later maintenance of the verification environment of the system management network are accelerated.

[0072] Step 404: In the verification environment, the verification file is referenced for simulation verification, and verification result information of the chip system management network is generated.

[0073] In this step, the above SV format verification file can be integrated into the verification environment based on the UVM platform, and a target verification environment for the chip system management network is obtained. Then, the verification file is referenced for compilation and simulation verification in the target verification environment, and verification result information of the chip system management network is generated. The verification result information can include the checking result of each checking function, that is, the comparison result of the actual value simulated by each node function and the expected value. Thus, the entire environment construction and verification process is automatically completed, and the chip verification efficiency is improved.

[0074] In an embodiment, in an actual scenario, if simulation fails and the configuration information is extracted incorrectly, the configuration information in the configuration file can be extracted again by modifying the above python script, and the verification file is generated, that is, steps 402 to 404 are repeated, and simulation is performed again until simulation is successful. It takes about ten to several tens of minutes to modify the python script, but after several iterations of the script are stable, the python script does not need to be modified again, and the verification file can be directly generated by using the python script, and the generation process only takes a few seconds. Compared with the manual modification which takes several days or even a week, the efficiency of the verification environment construction and iteration is greatly improved.

[0075] In an embodiment, after step 404, the method can further include:

[0076] Step 405: When the updated configuration file of the chip system management network is received, the verification file suitable for the verification environment is updated according to the updated configuration file.

[0077] In this step, if the designer modifies the information in the configuration file of the chip system management network, that is, updates the configuration file, the updated chip system management network still needs to be functionally simulated and verified. At this time, the updated configuration file can be reconfigured by a stable python script to extract the configuration information and generate an updated verification file suitable for the verification environment, that is, repeat the contents of steps 402 to 404 above. The chip system management network is simulated and verified based on the updated configuration file again, and the updated verification result information is obtained for the designer to refer to.

[0078] The chip verification method extracts all configuration information of the chip system management network through a python script, generates a corresponding verification file of the verification environment, and then integrates the generated configuration information into the verification environment. This method accelerates the construction of the chip system management network verification environment. Correspondingly, if a chip module requires a large amount of configuration information and has a similar format, the configuration information can also be extracted by this method to generate a format file required by the verification environment, thereby realizing the rapid construction and iteration of the verification environment. Compared with the manual modification of the corresponding configuration of the verification environment in the prior art, which may take several days or even a week to complete, this method can shorten the process to a few seconds, greatly reducing the probability of human error and improving the accuracy of verification. Moreover, for later project inheritance modification, the verification environment has better compatibility and inheritance. Thus, the construction and maintenance of the system management network verification environment are greatly accelerated.

[0079] Please refer to Figure 5 , which is a chip verification device 500 of an embodiment of the present application. The device can be applied to Figure 1 The electronic device 1 shown in the figure, and can be applied to the verification scenario of the chip system management network in the above Figure 2 to accelerate the construction and later iteration of the chip system management network verification environment and improve the verification efficiency of the chip system management network. The device includes a file acquisition module 501, a file generation module 502, and a simulation module 503. The principle relationship of each module is as follows:

[0080] The file acquisition module 501 is configured to acquire the configuration file of the chip system management network to be tested.

[0081] The file generation module 502 is configured to extract the configuration information of the chip system management network from the configuration file and generate a verification file suitable for the verification environment according to the configuration information.

[0082] The simulation module 503 is configured to reference the verification file in the verification environment for simulation verification and generate verification result information of the chip system management network.

[0083] In an embodiment, the chip system management network comprises a plurality of interface nodes and a plurality of routing nodes.

[0084] In an embodiment, the file generation module 502 is configured to extract interface configuration information, routing configuration information and data path configuration information of the chip system management network from the configuration file, and generate a verification file applicable to the verification environment according to the interface configuration information, the routing configuration information and the data path configuration information.

[0085] In an embodiment, the interface configuration information comprises a size of an input buffer area and a size of an output buffer area of each interface node.

[0086] In an embodiment, the routing configuration information comprises bandwidth information and broadcast information of each port of each routing node.

[0087] In an embodiment, the data path configuration information comprises destination interface node information of each data path and routing node information to be passed through to reach the destination interface node.

[0088] In an embodiment, the file generation module 502 is configured to generate a plurality of interface nodes, a plurality of routing nodes and a check function of each data path according to the interface configuration information, the routing configuration information and the data path configuration information, respectively, and write the check function, the interface configuration information, the routing configuration information and the data path configuration information into corresponding files of the verification environment to generate a verification file of the chip system management network.

[0089] In an embodiment, the chip verification device 500 further comprises an update module 504 configured to, when receiving an updated configuration file of the chip system management network, update the verification file applicable to the verification environment according to the updated configuration file.

[0090] The detailed description of the chip verification device 500 is described in the above-mentioned method steps.

[0091] The embodiment of the present application further provides a non-transitory electronic device readable storage medium, comprising a program, when the program is executed on an electronic device, the program causes the electronic device to execute all or part of the processes of the above-mentioned method. The storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD), etc. The storage medium can also comprise a combination of the above-mentioned types of memories.

[0092] While embodiments of the application have been described in connection with the preferred embodiments of the various figures, those of ordinary skill in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the application, and that such modifications and changes fall within the scope of the appended claims.

Claims

1. A chip verification method, characterized in that: include: Obtain the configuration file of the chip system management network to be tested; The chip system management network includes: multiple interface nodes and multiple routing nodes; Extracting configuration information of the chip system management network from the configuration file, and generating a verification file suitable for a verification environment based on the configuration information, wherein the configuration information includes information of the multiple interface nodes and the multiple routing nodes of the chip system management network, and the verification file includes a check function for the configuration information; The verification file is referenced in the verification environment to perform simulation verification, and verification result information of the chip system management network is generated, where the verification result information includes a check result of a check function.

2. The chip verification method according to claim 1, characterized in that: The extracting the configuration information of the chip system management network from the configuration file and generating a verification file suitable for the verification environment according to the configuration information includes: Extracting interface configuration information, routing configuration information and data path configuration information of the chip system management network from the configuration file; The verification file suitable for the verification environment is generated according to the interface configuration information, the routing configuration information and the data path configuration information.

3. The chip verification method according to claim 2, characterized in that: The interface configuration information includes: the size of the input buffer area and the size of the output buffer area of ​​each interface node.

4. The chip verification method according to claim 2, characterized in that: The routing configuration information includes: bandwidth information and broadcast information of each port of each routing node.

5. The chip verification method according to claim 2, characterized in that: The data path configuration information includes: destination interface node information of each data path and routing node information to be passed through to reach the destination interface node.

6. The chip verification method according to claim 2, characterized in that: Generating the verification file applicable to the verification environment according to the interface configuration information, the routing configuration information, and the data path configuration information includes: generating, according to the interface configuration information, the routing configuration information, and the data path configuration information, a check function for each of the plurality of interface nodes, the plurality of routing nodes, and each data path; The check function, the interface configuration information, the routing configuration information and the data path configuration information are written into corresponding files of the verification environment to generate the verification file of the chip system management network.

7. The chip verification method according to claim 1, characterized in that: Also includes: When the updated configuration file of the chip system management network is received, the verification file applicable to the verification environment is updated according to the updated configuration file.

8. A chip verification device, characterized in that: include: A file acquisition module is used to obtain the configuration file of the chip system management network to be tested; The chip system management network includes: multiple interface nodes and multiple routing nodes; a file generation module, configured to extract configuration information of the chip system management network from the configuration file, and generate a verification file suitable for a verification environment based on the configuration information, wherein the configuration information includes information of the multiple interface nodes and the multiple routing nodes of the chip system management network, and the verification file includes a check function for the configuration information; An integration module is used to integrate the verification file into the verification environment to obtain a target verification environment for the chip system management network, and the verification result information includes the inspection result of the inspection function.

9. The chip authentication device according to claim 8, characterized in that: The file generation module is used to: extract the interface configuration information, routing configuration information and data path configuration information of the chip system management network from the configuration file; and generate the verification file suitable for the verification environment based on the interface configuration information, the routing configuration information and the data path configuration information.

10. The chip authentication device according to claim 9, characterized in that: The interface configuration information includes: the size of the input buffer area and the size of the output buffer area of ​​each interface node; The routing configuration information includes: bandwidth information and broadcast information of each port of each routing node; The data path configuration information includes: destination interface node information of each data path and routing node information to be passed through to reach the destination interface node.

11. The chip authentication device according to claim 9, wherein: The file generation module is used to: generate the check functions of the multiple interface nodes, the multiple routing nodes and each data path respectively according to the interface configuration information, the routing configuration information and the data path configuration information; write the check function, the interface configuration information, the routing configuration information and the data path configuration information into the corresponding files of the verification environment to generate the verification file of the chip system management network.

12. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the method according to any one of claims 1 to 7.

13. A non-transitory electronic device readable storage medium, characterized in that: The invention comprises: a program, which, when executed by an electronic device, causes the electronic device to execute the method according to any one of claims 1 to 7.

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