Memory device, memory system having the same and write method thereof

Abstract

A memory device, a memory system having the same, and a write method thereof are provided. A memory device includes a first memory block defined in a first wafer, and a second memory block defined in a second wafer disposed in a perpendicular direction with respect to the first wafer. A size of the first memory block is smaller than a size of the second memory block.

Description

Technical Field

[0001] The various implementations generally relate to semiconductor technology, and more specifically, to a memory device, a memory system having the memory device, and a method of writing thereto. Background Technology

[0002] With the increasing demand for portable phones, mobile storage devices, and digital cameras, the demand for non-volatile memory devices, primarily used in these products, is also increasing. Among non-volatile memory devices, flash memory is widely used as data storage. Recently, to improve the integration of memory devices, three-dimensional non-volatile memory devices in which memory cells are stacked in three dimensions have been actively researched. Summary of the Invention

[0003] Various implementation methods involve measures that can improve the efficiency of memory usage.

[0004] In addition, various implementation methods involve measures that can improve the performance of the memory.

[0005] In one embodiment, a memory device may include: a first memory block defined in a first wafer; and a second memory block defined in a second wafer disposed in a vertical direction relative to the first wafer. The size of the first memory block may be smaller than the size of the second memory block.

[0006] In one embodiment, a memory device may include: a first wafer including a first substrate and a plurality of first electrode layers and a plurality of first interlayer dielectric layers, the plurality of first electrode layers and the plurality of first interlayer dielectric layers being alternately stacked on a top surface of the first substrate along a first vertical channel projecting in a vertical direction; and a second wafer disposed on the first wafer and including a second substrate and a plurality of second electrode layers and a plurality of second interlayer dielectric layers, the plurality of second electrode layers and the plurality of second interlayer dielectric layers being alternately stacked on a bottom surface of the second substrate along a second vertical channel projecting in a vertical direction. Each second electrode layer may include a pad portion. The first wafer may include a dielectric stack that overlaps with the pad portions of the second electrode layers in a vertical direction and is configured by the alternately stacked plurality of dielectric layers and the plurality of first interlayer dielectric layers.

[0007] In one embodiment, a memory system may include: a memory device; and a memory controller. The memory device may include: a small block defined in a first wafer; and a large block defined in a second wafer, the second wafer being disposed in a vertical direction relative to the first wafer. The memory controller may store data in the small block or the large block by referring to the size of the data to be written.

[0008] In one embodiment, a data writing method for a memory device including small blocks and large blocks may include the following steps: receiving a write request; detecting the size of the data to be written; and storing the data in the small block or the large block according to the detection result. Attached Figure Description

[0009] Figure 1 This is a block diagram schematically illustrating an example of a memory device according to an embodiment of the present disclosure.

[0010] Figure 2 It is shown Figure 1 A schematic perspective view representing an example of a memory device.

[0011] Figure 3 It is shown Figure 2 A diagram illustrating an example of a schematic arrangement of the first and second wafers.

[0012] Figure 4 It is shown Figure 3 A cross-sectional view illustrating an example of the detailed structure of the first and second wafers shown.

[0013] Figure 5 It is shown Figure 3 The circuit diagrams representing examples of the first and second memory blocks are shown.

[0014] Figure 6 It is shown Figure 2 A diagram illustrating another example of a schematic arrangement of the first and second wafers.

[0015] Figure 7 It is shown Figure 6 A cross-sectional view illustrating an example of the detailed structure of the first and second wafers shown.

[0016] Figure 8 It is shown Figure 6 The circuit diagrams representing examples of the first and second memory blocks are shown.

[0017] Figure 9 It is shown Figure 2 A diagram illustrating another example of a schematic arrangement of the first and second wafers.

[0018] Figure 10 It is shown Figure 9 A cross-sectional view illustrating an example of the detailed structure of the first and second wafers shown.

[0019] Figure 11 It is shown Figure 9 The circuit diagrams representing examples of the first and second memory blocks are shown.

[0020] Figure 12 It is shown Figure 2 A diagram illustrating another example of a schematic arrangement of the first and second wafers.

[0021] Figure 13 It is shown Figure 12 A cross-sectional view illustrating an example of the detailed structure of the first and second wafers shown.

[0022] Figure 14 It is shown Figure 12 The circuit diagrams representing examples of the first and second memory blocks are shown.

[0023] Figure 15 It is shown Figure 2 A diagram illustrating another example of a schematic arrangement of the first and second wafers.

[0024] Figure 16 It is shown Figure 15 A cross-sectional view illustrating an example of the detailed structure of the first and second wafers shown.

[0025] Figure 17 It is shown Figure 15 The circuit diagrams representing examples of the first and second memory blocks are shown.

[0026] Figure 18 It is shown Figure 2 A diagram illustrating another example of a schematic arrangement of the first and second wafers.

[0027] Figure 19 It is shown Figure 18 A cross-sectional view showing an example of the detailed structure of the first and second wafers.

[0028] Figure 20 It is shown Figure 18 The circuit diagram represents an example of the first memory block and the second memory block.

[0029] Figure 21 This is a cross-sectional view illustrating an example of the connection structure between the bit lines and page buffer circuitry of a memory device according to an embodiment of the present disclosure.

[0030] Figure 22 This is a cross-sectional view illustrating an example of the connection structure between the row lines and the row decoder of a memory device according to an embodiment of the present disclosure.

[0031] Figure 23 It is shown Figure 22 A top view showing an example of the main components of the first connection area.

[0032] Figures 24A to 24E This is a cross-sectional view illustrating an example of the steps for manufacturing a memory structure of a first wafer according to an embodiment of the present disclosure.

[0033] Figure 25 This is a cross-sectional view illustrating an example of another connection structure between a row line and a row decoder of a memory device according to an embodiment of the present disclosure.

[0034] Figure 26A and Figure 26B This is a diagram illustrating an example of bias conditions during an erase operation of a memory device according to an embodiment of the present disclosure.

[0035] Figure 27 This is a schematic block diagram illustrating an example of a memory system according to an embodiment of the present disclosure.

[0036] Figure 28 This is an example representation of a flowchart that helps explain the writing method according to embodiments of this disclosure.

[0037] Figures 29A to 29D This is an example representation of a diagram that helps explain the memory block management method according to embodiments of the present disclosure.

[0038] Figure 30 This is a block diagram schematically illustrating an example of a computing system including a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0039] The advantages and features of this disclosure, and methods of implementing them, will become apparent from the following description of exemplary embodiments thereof with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. The exemplary embodiments of this disclosure convey the scope of this disclosure to those skilled in the art.

[0040] Because the numerical values, dimensions, ratios, angles, and quantities of the elements illustrating embodiments of this disclosure given in the accompanying drawings are merely illustrative, this disclosure is not limited to what is shown. Throughout the specification, the same reference numerals denote the same parts. In describing this disclosure, detailed descriptions of related technologies will be omitted where it is determined that such detailed descriptions might obscure the essential points or clarity of this disclosure. It should be noted or understood that the terms “comprising,” “having,” “including,” etc., used in the specification and claims should not be construed as limited to the means listed thereafter, unless specifically stated otherwise. When referring to a singular noun, the use of an indefinite or definite article (e.g., “a,” “an,” or “the”) may include a plurality of that noun, unless specifically stated otherwise.

[0041] When interpreting elements in embodiments of this disclosure, they should be interpreted as including tolerances, even if not explicitly described.

[0042] Furthermore, in describing the components of this disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are used only for the purpose of distinguishing one component from another and do not limit the substance, order, sequence, or quantity of the components. Moreover, the components in embodiments of this disclosure are limited by these terms. These terms are used only to distinguish one component from another. Therefore, as used herein, within the technical spirit of this disclosure, a first component may be a second component.

[0043] If a component is described as "connected," "linked," or "attached" to another component, this may mean that the component can be "connected," "linked," or "attached" not only directly, but also indirectly via a third component. When describing positional relationships, such as "component A on component B," "component A above component B," "component A below component B," and "component A next to component B," another component C may be positioned between component A and component B, unless the terms "directly" or "exactly" are explicitly used.

[0044] Features of the various exemplary embodiments of this disclosure may be partially or completely coupled, combined, or separated. Various technical interactions and operations are possible. The various exemplary embodiments may be implemented individually or in combination.

[0045] In the following, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0046] Figure 1 This is a block diagram schematically illustrating an example of a memory device 100 according to an embodiment of the present disclosure.

[0047] Reference Figure 1 The memory device 100 according to embodiments of the present disclosure may include a memory cell array 110 and logic circuitry 120. Logic circuitry 120 may include a row decoder (X-DEC) 121, a page buffer circuitry 122, and peripheral circuitry (PERI circuitry) 123.

[0048] The memory cell array 110 may include multiple memory blocks BLK. Each memory block BLK may include multiple memory cells. Each memory block BLK may be connected to the row decoder 121 via multiple row lines RL. The memory cell array 110 may be connected to the page buffer circuit 122 via multiple bit lines BL.

[0049] In response to the row address X_A provided from the peripheral circuitry 123, the row decoder 121 can select any one of the plurality of memory blocks BLK included in the memory cell array 110. The row decoder 121 can transmit the operating voltage X_V provided from the peripheral circuitry 123 to the row line RL connected to the selected memory block BLK from the plurality of memory blocks BLK included in the memory cell array 110.

[0050] Page buffer circuit 122 may include a plurality of page buffers PB, each connected to a bit line BL. Page buffer circuit 122 may receive a page buffer control signal PB_C from peripheral circuit 123, and may send and receive a data signal DATA from peripheral circuit 123. Page buffer circuit 122 may control the bit line BL arranged in memory cell array 110 in response to page buffer control signal PB_C. For example, page buffer circuit 122 may detect data stored in memory cells of memory cell array 110 by sensing a signal on bit line BL of memory cell array 110 in response to page buffer control signal PB_C, and may send a data signal DATA to peripheral circuit 123 based on the detected data. Page buffer circuit 122 may apply a signal to bit line BL based on the data signal DATA received from peripheral circuit 123 in response to page buffer control signal PB_C, thereby writing data to memory cells of memory cell array 110. Page buffer circuit 122 may write data to or read data from memory cells connected to active word lines.

[0051] Peripheral circuitry 123 can receive command signals CMD, address signals ADD, and control signals CTRL from outside the memory device 100, and can send data signals DATA to and receive data signals DATA from external devices (e.g., memory controllers). Peripheral circuitry 123 can output signals (e.g., row address X_A and page buffer control signals PB_C, etc.) for writing data to or reading data from the memory cell array 110 based on the command signals CMD, ADD, and CTRL. Peripheral circuitry 123 can generate various voltages required by the memory device 100, including the operating voltage X_V.

[0052] In the following description, and in the accompanying drawings, two directions parallel to the top surface of the substrate and intersecting each other are defined as the first direction FD and the second direction SD, respectively, and the direction protruding vertically from the top surface of the substrate is defined as the vertical direction VD. For example, the first direction FD may correspond to the extension direction of a bit line, and the second direction SD may correspond to the extension direction of a row line. The first direction FD and the second direction SD may intersect each other substantially perpendicularly. The vertical direction VD may correspond to a direction perpendicular to the first direction FD and the second direction SD. In the accompanying drawings, the direction indicated by the arrow and the direction opposite to it represent the same direction.

[0053] Figure 2 It is shown Figure 1 A schematic perspective view representing an example of a memory device.

[0054] Reference Figure 2 The memory device 100 according to embodiments of the present disclosure may include a first wafer W1 and a second wafer W2 disposed on a vertical direction VD and bonded to each other. For ease of understanding, Figure 2 The first wafer W1 and the second wafer W2 are shown to be separated from each other in the vertical direction VD, but it should be understood that the top surface of the first wafer W1 and the bottom surface of the second wafer W2 are in contact with each other.

[0055] The first chip W1 may include a logic structure P and a memory structure C stacked on the logic structure P. The logic structure P may include... Figure 1 The memory structure C may include at least one of the following: a line decoder 121, a page buffer circuit 122, and a peripheral circuit 123. The memory structure C may include multiple first memory blocks (not shown).

[0056] The second wafer W2 may include multiple second memory blocks (not shown). The first memory block of the first wafer W1 and the second memory block of the second wafer W2 can constitute a... Figure 1 The memory cell array 110.

[0057] Multiple first bit lines BLa extending in the first direction FD and multiple first row lines RLa extending in the second direction SD can be configured in the first chip W1. A first memory block defined in the first chip W1 can be accessed via the multiple first bit lines BLa and the multiple first row lines RLa. For simplicity of illustration, Figure 2 The diagram shows only one first bit line BLa and only one first row line RLa, but it should be understood that multiple first bit lines BLa and multiple first row lines RLa are limited to the first chip W1.

[0058] Multiple second bit lines BLb extending in the first direction FD and multiple second row lines RLb extending in the second direction SD can be configured in the second chip W2. The second memory block defined in the second chip W2 can be accessed via the multiple second bit lines BLb and the multiple second row lines RLb. For simplicity of illustration, Figure 2 Only one second bit line BLb and only one second row line RLb are shown, but it should be understood that multiple second bit lines BLb and multiple second row lines RLb are limited to the second chip W2.

[0059] Although not shown, the first bit line BLa and the second bit line BLb, as well as the first row line RLa and the second row line RLb, can be electrically connected to the logic circuit defined in the logic structure P. (See reference...) Figures 21 to 25 The following description will make the connection structure between the first bit line BLa and the second bit line BLb, as well as the first row line RLa and the second row line RLb, and the logic circuit obvious.

[0060] Figure 3 It is shown Figure 2 The diagram illustrates an example of a schematic arrangement of the first and second wafers.

[0061] Reference Figure 3 The memory structure C of the first chip W1 may include a plurality of first memory blocks BLK1 arranged on a first direction FD, which is the extension direction of a plurality of first bit lines BLa. The plurality of first memory blocks BLK1 may be jointly connected to each of the plurality of first bit lines BLa. Although not shown, each first memory block BLK1 may include a plurality of cell strings connected to the plurality of first bit lines BLa.

[0062] Each of the multiple first memory blocks BLK1 can have the same size. The size of a first memory block BLK1 can be defined as the number of memory cells included in the first memory block BLK1. The number of memory cells included in the first memory block BLK1 can be proportional to the physical size of the first memory block BLK1. The physical size of the first memory block BLK1 can be defined by its width in the first direction FD, its length in the second direction SD, and its height in the vertical direction VD. Alternatively, the size of the first memory block BLK1 can be defined as its physical size. The size of the first memory block BLK1 can be defined as proportional to its physical size.

[0063] The second chip W2 may include a plurality of second memory blocks BLK2 arranged on a first direction FD, which is the extension direction of the plurality of second bit lines BLb. The plurality of second memory blocks BLK2 may be jointly connected to each of the plurality of second bit lines BLb. Although not shown, each second memory block BLK2 may include a plurality of cell strings connected to the plurality of second bit lines BLb.

[0064] Each of the multiple second memory blocks BLK2 can have the same size. The size of the second memory block BLK2 can be defined in the same way as the size of the first memory block BLK1 described above.

[0065] The width of the first memory block BLK1 in the first direction FD can be A1. The width of the second memory block BLK2 in the first direction FD can be A2, where A2 is greater than A1. The lengths of the first memory block BLK1 and the second memory block BLK2 in the second direction SD can be substantially the same. The heights of the first memory block BLK1 and the second memory block BLK2 in the vertical direction VD can also be substantially the same. Therefore, the number of second memory blocks BLK2 included in the second wafer W2 can be less than the number of first memory blocks BLK1 included in the first wafer W1.

[0066] The physical size of the first memory block BLK1 can be smaller than the physical size of the second memory block BLK2. The first memory block BLK1 can be a small block, and the second memory block BLK2 can be a large block.

[0067] Figure 4 It is shown Figure 3 A cross-sectional view illustrating an example of the detailed structure of the first and second wafers shown.

[0068] Reference Figure 4 The logic structure P may include a substrate 10 and a plurality of transistors TR defined on the substrate 10. Although not shown, the logic structure P may also include elements such as inductors, capacitors, and resistors. The transistors TR, inductors, capacitors, and resistors can constitute a logic circuit (e.g., Figure 1 (of 120).

[0069] The memory structure C may include a substrate 12a and a plurality of electrode layers 20a and a plurality of interlayer dielectric layers 22a alternately stacked on the substrate 12a. The substrate 12a may be defined on a logic structure P. The electrode layers 20a may include a conductive material. For example, the electrode layers 20a may include at least one selected from doped semiconductors (e.g., doped silicon), metals (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and transition metals (e.g., titanium or tantalum). Among the electrode layers 20a, at least one electrode layer 20a starting from the bottommost electrode layer 20a may be configured with a source select line SSLa. Among the electrode layers 20a, at least one electrode layer 20a starting from the topmost electrode layer 20a may be configured with a drain select line DSLa. The electrode layers 20a between the source select line SSLa and the drain select line DSLa may be configured with word lines WLa. The interlayer dielectric layers 22a may include silicon oxide.

[0070] Multiple vertical channels Cha, passing through multiple electrode layers 20a and multiple interlayer dielectric layers 22a in the vertical direction VD, can be defined in the first wafer W1. Although not shown in detail, each vertical channel Cha may include a channel layer and a gate dielectric layer. The channel layer may include polysilicon or monocrystalline silicon and may include P-type impurities such as boron (B) in some regions therein. The gate dielectric layer may have a straw or cylindrical shell shape surrounding the outer wall of the channel layer. The gate dielectric layer may include a tunnel dielectric layer, a charge storage layer, and a barrier layer sequentially stacked from the outer wall of the channel layer. In some embodiments, the gate dielectric layer may have an oxide-nitride-oxide (ONO) stack structure, wherein oxide layers, nitride layers, and oxide layers are sequentially stacked. A source select transistor may be configured around the vertical channel Cha via a source select line SSLa. A memory cell may be configured around the vertical channel Cha via a word line WLa. A drain select transistor may be configured around the vertical channel Cha via a drain select line DSLa. A cell string CSTRa can be configured by a source selection transistor, multiple memory cells, and a drain selection transistor arranged along a vertical channel CHa. The memory structure C can include multiple cell strings CSTRa.

[0071] Each of a plurality of first slits SLT1 is defined through a plurality of electrode layers 20a and a plurality of interlayer dielectric layers 22a. The plurality of first slits SLT1 divide the alternately stacked plurality of electrode layers 20a and the plurality of interlayer dielectric layers 22a into a first memory block cell. The first slits SLT1 may extend in a second direction SD and a vertical direction VD. The plurality of electrode layers 20a, the plurality of interlayer dielectric layers 22a and the plurality of vertical channels CHa disposed between a pair of adjacent first slits SLT1 may be configured into a first memory block BLK1. The plurality of electrode layers 20a and the plurality of interlayer dielectric layers 22a included in a first memory block BLK1 may be defined as a first electrode structure ES1.

[0072] Multiple first slits SLT1 can be arranged or positioned on the first direction FD, and therefore, multiple first memory blocks BLK1 can be arranged or positioned on the first direction FD. The number of vertical channels CHa included in a first memory block BLK1 can be determined by the spacing between a pair of adjacent first slits SLT1.

[0073] The spacing between adjacent first slits SLT1 can be A1. A1 can correspond to the width of the first memory block BLK1 in the first direction FD. The number of vertical channels CHa included in different first memory blocks BLK1 can be the same, and therefore the number of cell strings CSTRa included in different first memory blocks BLK1 can be the same. Each first memory block BLK1 can include the same number of memory cells.

[0074] The first bit line BLa can be positioned above multiple first memory blocks BLK1. The bit line contact BLCa can be positioned below the first bit line BLa to connect the first bit line BLa and the vertical channel CHa. Figure 4 It is a cross-sectional view taken along the first line BLa. Although Figure 4 The diagram shows only one first line BLa, but it should be understood that multiple first lines BLa are arranged in the second direction SD.

[0075] A dielectric layer 30a can be defined on the substrate 12a to fill the first slit SLT1 and cover a plurality of first memory blocks BLK1 and a first bit line BLa. The top surface of the dielectric layer 30a can form a surface for bonding the first wafer W1 to the second wafer W2. A bonding pad PAD1 can be exposed on the top surface of the dielectric layer 30a. The bonding pad PAD1 can be connected to the first bit line BLa via a contact CNT1.

[0076] The second chip W2 may include a substrate 12b and a plurality of electrode layers 20b and a plurality of interlayer dielectric layers 22b alternately stacked on the bottom surface of the substrate 12b. The electrode layers 20b may be formed of the same material as the electrode layers 20a. At least one electrode layer 20b, starting from the uppermost electrode layer 20b, may be configured with a source select line SSLb. At least one electrode layer 20b, starting from the lowermost electrode layer 20b, may be configured with a drain select line DSLb. The electrode layers 20b between the source select line SSLb and the drain select line DSLb may be configured with word lines WLb. The interlayer dielectric layers 22b may be formed of the same material as the interlayer dielectric layers 22a.

[0077] Multiple vertical channels CHb passing through electrode layer 20b and interlayer dielectric layer 22b in the vertical direction VD can be defined in the second wafer W2. The vertical channels CHb can be configured in the same manner as the vertical channels CHa. Source select transistors can be configured around the vertical channels CHb via source select line SSLb. Memory cells can be configured around the vertical channels CHb via word line WLb. Drain select transistors can be configured around the vertical channels CHb via drain select line DSLb. A cell string CSTRb can be configured along a vertical channel CHb containing source select transistors, multiple memory cells, and drain select transistors. The second wafer W2 may include multiple cell strings CSTRb.

[0078] Each of a plurality of second slits SLT2 is defined through a plurality of electrode layers 20b and a plurality of interlayer dielectric layers 22b. The plurality of second slits SLT2 divide the alternately stacked plurality of electrode layers 20b and interlayer dielectric layers 22b into second memory block cells. The second slits SLT2 may extend in a second direction SD and a vertical direction VD. A plurality of electrode layers 20b, a plurality of interlayer dielectric layers 22b, and a plurality of vertical channels CHb disposed between a pair of adjacent second slits SLT2 can be configured into a second memory block BLK2. The plurality of electrode layers 20b and the plurality of interlayer dielectric layers 22b included in a second memory block BLK2 can be defined as a second electrode structure ES2.

[0079] The number of stacked word lines WLb in the second memory block BLK2 can be the same as the number of stacked word lines WLa in the first memory block BLK1. Therefore, the number of memory cells included in a unit string CSTRb can be the same as the number of memory cells included in a unit string CSTRa. The number of vertical channels CHa per unit area in the first memory block BLK1 and the number of vertical channels CHb per unit area in the second memory block BLK2 can be the same.

[0080] Multiple second slits SLT2 can be arranged or positioned on the first direction FD, and therefore, multiple second memory blocks BLK2 can be arranged or positioned on the first direction FD. The number of vertical channels CHb included in a second memory block BLK2 can be determined by the spacing between a pair of adjacent second slits SLT2.

[0081] The spacing between adjacent second slits SLT2 can be A2. A2 can correspond to the width of the second memory block BLK2 in the first direction FD. The number of vertical channels CHb (and the number of cell strings CSTRb) included in different second memory blocks BLK2 can be the same. Each second memory block BLK2 can include the same number of memory cells.

[0082] A1 can be less than A2, such that the number of vertical channels CHa (the number of cell strings CSTRa) included in the first memory block BLK1 can be less than the number of vertical channels CHb (the number of cell strings CSTRb) included in the second memory block BLK2.

[0083] The second bit line BLb can be positioned below multiple second memory blocks BLK2. The bit line contact BLCb can be positioned above the second bit line BLb to connect the second bit line BLb and the vertical channel CHb. Although Figure 4 The diagram shows only one second bit line BLb, but it should be understood that multiple second bit lines BLb are arranged on the second direction SD.

[0084] A dielectric layer 30b can be defined on the bottom surface of the substrate 12b to fill the second slit SLT2 and cover a plurality of second memory blocks BLK2 and second bit lines BLb. The bottom surface of the dielectric layer 30b can form a surface on which the second wafer W2 is bonded to the first wafer W1. Bonding pads PAD2 can be exposed on the bottom surface of the dielectric layer 30b. Bonding pads PAD2 can be connected to the second bit lines BLb via contacts CNT2. One surface of the second wafer W2 can be bonded to one surface of the first wafer W1, and bonding pads PAD2 can be connected to bonding pads PAD1.

[0085] Figure 5 It is shown Figure 3 The circuit diagrams representing examples of the first and second memory blocks are shown.

[0086] Reference Figure 5The first memory block BLK1 may include multiple cell strings CSTRa connected between multiple first bit lines BLa and a common source line CSLa. The first bit lines BLa may extend along a first direction FD and may be arranged along a second direction SD. Multiple cell strings CSTRa may be connected in parallel to each first bit line BLa. Multiple cell strings CSTRa may be collectively connected to the common source line CSLa. Multiple cell strings CSTRa may be connected between multiple first bit lines BLa and a common source line CSLa.

[0087] Each of the multiple cell strings CSTRa may include a drain-select transistor DSTA connected to the first bit line BLa, a source-select transistor SSTa connected to the common source line CSLa, and multiple memory cells MCa connected between the drain-select transistor DSTA and the source-select transistor SSTa. The drain-select transistor DSTA, the multiple memory cells MCa, and the source-select transistor SSTa included in a cell string CSTRa may be connected in series in the vertical direction VD.

[0088] The source select line SSLa, multiple word lines WLa, and drain select line DSLa can be arranged vertically on VD between the common source line CSLa and the first bit line BLa. Each drain select line DS1a can be connected to the gate of the corresponding drain select transistor DSTa. Each word line WLa can be connected to the gate of the corresponding memory cell MCa. The source select line SSLa can be connected to the gate of the source select transistor SSTa. Memory cells MCa that are all connected to a single word line WLa can be configured as one physical page.

[0089] The second memory block BLK2 may include multiple cell strings CSTRb connected between multiple second bit lines BLb and a common source line CSLb. The second bit lines BLb may extend along a first direction FD and may be arranged along a second direction SD. Multiple cell strings CSTRb may be connected in parallel to each second bit line BLb. Multiple cell strings CSTRb may be collectively connected to the common source line CSLb. Multiple cell strings CSTRb may be connected between multiple second bit lines BLb and a common source line CSLb.

[0090] Each of the multiple cell strings CSTRb may include a drain-select transistor DSTb connected to the second bit line BLb, a source-select transistor SSTb connected to the common source line CSLb, and multiple memory cells MCb connected between the drain-select transistor DSTb and the source-select transistor SSTb. The drain-select transistor DSTb, the multiple memory cells MCb, and the source-select transistor SSTb included in a cell string CSTRb may be connected in series in the vertical direction VD.

[0091] The source select line SSLb, multiple word lines WLb, and drain select line DSLb can be arranged vertically on VD between the common source line CSLb and the second bit line BLb. Each drain select line DSLb can be connected to the gate of the corresponding drain select transistor DSTb. Each word line WLb can be connected to the gate of the corresponding memory cell MCb. The source select line SSLb can be connected to the gate of the source select transistor SSTb. Memory cells MCb that are all connected to a single word line WLb can be configured as one physical page.

[0092] The number of first bit lines BLa and the number of second bit lines BLb can be the same. The interval between adjacent first bit lines BLa and the interval between adjacent second bit lines BLb can be the same. The number of memory cells MCa included in a unit string CSTRa and the number of memory cells MCb included in a unit string CSTRb can be the same.

[0093] The number of memory cells MCa connected to a word line WLa in a first memory block BLK1 can be less than the number of memory cells MCb connected to a word line WLb in a second memory block BLK2. For example, the number of memory cells MCa connected to a word line WLa in a first memory block BLK1 can be half the number of memory cells MCb connected to a word line WLb in a second memory block BLK2.

[0094] The number of cell strings CSTRa included in the first memory block BLK1 can be less than the number of cell strings CSTRb included in the second memory block BLK2. For example, each first bit line BLa can be connected to two cell strings CSTRa in the first memory block BLK1, and each second bit line BLb can be connected to four cell strings CSTRb in the second memory block BLK2. In this case, the number of cell strings CSTRa included in the first memory block BLK1 can be half the number of cell strings CSTRb included in the second memory block BLK2.

[0095] The number of memory cells MCa included in the first memory block BLK1 can be less than the number of memory cells MCb included in the second memory block BLK2. The first memory block BLK1 can be a small block, and the second memory block BLK2 can be a large block.

[0096] Despite the above references Figures 3 to 5The described implementation illustrates an example where the number of cell strings CSTRa included in the first memory block BLK1 is half the number of cell strings CSTRb included in the second memory block BLK2, but this disclosure is not limited thereto. The ratio of the number of cell strings CSTRa included in the first memory block BLK1 to the number of cell strings CSTRb included in the second memory block BLK2 can be varied.

[0097] Figure 6 It is shown Figure 2 A diagram illustrating another example of a schematic arrangement of the first wafer W1 and the second wafer W2.

[0098] Reference Figure 6 The width of the first memory block BLK1 in the first direction FD can be A1. The width of the second memory block BLK2 in the first direction FD can be A2, where A2 is smaller than A1. Therefore, the number of first memory blocks BLK1 included in the first wafer W1 can be less than the number of second memory blocks BLK2 included in the second wafer W2.

[0099] The lengths of the first memory block BLK1 and the second memory block BLK2 in the second direction SD can be substantially the same. The heights of the first memory block BLK1 and the second memory block BLK2 in the vertical direction VD can also be substantially the same.

[0100] The physical size of the first memory block BLK1 can be larger than the physical size of the second memory block BLK2. The first memory block BLK1 can be a large block, and the second memory block BLK2 can be a small block.

[0101] Figure 7 It is shown Figure 6 A cross-sectional view illustrating an example of the detailed structure of the first and second wafers shown.

[0102] Reference Figure 7 The interval A1 between adjacent first slits SLT1 can be greater than the interval A2 between adjacent second slits SLT2. That is, the width of the first memory block BLK1 in the first direction FD can be greater than the width of the second memory block BLK2 in the first direction FD.

[0103] exist Figure 7 In this context, the number of cell strings CSTRa included in a first memory block BLK1 can be greater than the number of cell strings CSTRb included in a second memory block BLKb.

[0104] Figure 8 It is shown Figure 6The circuit diagrams representing examples of the first and second memory blocks are shown.

[0105] Reference Figure 8 The number of memory cells MCa connected to a word line WLa in a first memory block BLK1 can be greater than the number of memory cells MCb connected to a word line WLb in a second memory block BLK2. For example, the number of memory cells MCa connected to a word line WLa in a first memory block BLK1 can be twice the number of memory cells MCb connected to a word line WLb in a second memory block BLK2.

[0106] The number of cell strings CSTRa included in the first memory block BLK1 can be greater than the number of cell strings CSTRb included in the second memory block BLK2. For example, each first bit line BLa can be connected to four cell strings CSTRa in the first memory block BLK1, and each second bit line BLb can be connected to two cell strings CSTRb in the second memory block BLK2. In this case, the number of cell strings CSTRa included in the first memory block BLK1 can be twice the number of cell strings CSTRb included in the second memory block BLK2.

[0107] The number of memory cells MCa included in the first memory block BLK1 can be greater than the number of memory cells MCb included in the second memory block BLK2. The first memory block BLK1 can be a large block, and the second memory block BLK2 can be a small block.

[0108] Despite the above references Figures 6 to 8 The described implementation illustrates an example where the number of cell strings CSTRa included in the first memory block BLK1 is twice the number of cell strings CSTRb included in the second memory block BLK2, but this disclosure is not limited thereto. The ratio of the number of cell strings CSTRa included in the first memory block BLK1 to the number of cell strings CSTRb included in the second memory block BLK2 can be varied.

[0109] Figure 9 It is shown Figure 2 A diagram illustrating another example of a schematic arrangement of the first and second wafers.

[0110] Reference Figure 9The width of the first memory block BLK1 in the first direction FD and the width of the second memory block BLK2 in the first direction FD can be substantially the same. The length of the first memory block BLK1 in the second direction SD and the length of the second memory block BLK2 in the second direction SD can also be substantially the same. The height of the first memory block BLK1 in the vertical direction VD can be H1. The height of the second memory block BLK2 in the vertical direction VD can be H2, where H2 is greater than H1.

[0111] The physical size of the first memory block BLK1 can be smaller than the physical size of the second memory block BLK2. The first memory block BLK1 can be a small block, and the second memory block BLK2 can be a large block.

[0112] Figure 10 It is shown Figure 9 A cross-sectional view illustrating an example of the detailed structure of the first and second wafers shown.

[0113] Reference Figure 10 The spacing A1 between adjacent first slits SLT1 and the spacing A2 between adjacent second slits SLT2 can be the same. The width of the first memory block BLK1 in the first direction FD and the width of the second memory block BLK2 in the first direction FD can be the same. (Refer to the previous text) Figure 9 The lengths of the first memory block BLK1 and the second memory block BLK2 in the second direction SD can be substantially the same. In this case, the number of cell strings CSTRa included in the first memory block BLK1 and the number of cell strings CSTRb included in the second memory block BLK2 can be the same as each other.

[0114] The number of stacked word lines WLa in the first memory block BLK1 can be less than the number of stacked word lines WLb in the second memory block BLK2. As a result, the number of memory cells included in a single unit string CSTRa can be less than the number of memory cells included in a single unit string CSTRb. For example, the number of stacked word lines WLa in the first memory block BLK1 can be half the number of stacked word lines WLb in the second memory block BLK2, and the number of memory cells included in a single unit string CSTRa can be half the number of memory cells included in a single unit string CSTRb.

[0115] Figure 11 It is shown Figure 9 The circuit diagrams representing examples of the first and second memory blocks are shown.

[0116] Reference Figure 11The number of cell strings CSTRa included in the first memory block BLK1 and the number of cell strings CSTRb included in the second memory block BLK2 can be the same as each other.

[0117] The number of memory cells MCa included in a unit string CSTRa can be less than the number of memory cells MCb included in a unit string CSTRb. For example, the number of memory cells MCa included in a unit string CSTRa can be half the number of memory cells MCb included in a unit string CSTRb. The number of memory cells MCa included in the first memory block BLK1 can be less than the number of memory cells MCb included in the second memory block BLK2. The first memory block BLK1 can be a small block, and the second memory block BLK2 can be a large block.

[0118] Figure 12 It is shown Figure 2 A diagram illustrating another example of a schematic arrangement of the first and second wafers.

[0119] Reference Figure 12 The width of the first memory block BLK1 in the first direction FD and the width of the second memory block BLK2 in the first direction FD can be substantially the same. The length of the first memory block BLK1 in the second direction SD and the length of the second memory block BLK2 in the second direction SD can be substantially the same. The height of the first memory block BLK1 in the vertical direction VD can be H1. The height of the second memory block BLK2 in the vertical direction VD can be H2, where H2 is less than H1.

[0120] The physical size of the first memory block BLK1 can be larger than the physical size of the second memory block BLK2. The first memory block BLK1 can be a large block, and the second memory block BLK2 can be a small block.

[0121] Figure 13 It is shown Figure 12 A cross-sectional view illustrating an example of the detailed structure of the first and second wafers shown.

[0122] Reference Figure 13 The spacing A1 between adjacent first slits SLT1 and the spacing A2 between adjacent second slits SLT2 can be the same. The width of the first memory block BLK1 in the first direction FD and the width of the second memory block BLK2 in the first direction FD can be the same. (Refer to the previous text) Figure 12The lengths of the first memory block BLK1 and the second memory block BLK2 in the second direction SD can be substantially the same. In this case, the number of cell strings CSTRa included in the first memory block BLK1 and the number of cell strings CSTRb included in the second memory block BLK2 can be the same as each other.

[0123] The number of stacked word lines WLa in the first memory block BLK1 can be greater than the number of stacked word lines WLb in the second memory block BLK2. As a result, the number of memory cells included in a single unit string CSTRa can be greater than the number of memory cells included in a single unit string CSTRb. For example, the number of stacked word lines WLa in the first memory block BLK1 can be twice the number of stacked word lines WLb in the second memory block BLK2, and the number of memory cells included in a single unit string CSTRa can be twice the number of memory cells included in a single unit string CSTRb.

[0124] Figure 14 It is shown Figure 12 The circuit diagrams representing examples of the first and second memory blocks are shown.

[0125] Reference Figure 14 The number of cell strings CSTRa included in the first memory block BLK1 and the number of cell strings CSTRb included in the second memory block BLK2 can be the same as each other.

[0126] The number of memory cells MCa included in each cell string CSTRa can be greater than the number of memory cells MCb included in each cell string CSTRb. For example, the number of memory cells MCa included in cell string CSTRa can be twice the number of memory cells MCb included in cell string CSTRb. The number of memory cells MCa included in the first memory block BLK1 can be greater than the number of memory cells MCb included in the second memory block BLK2. The first memory block BLK1 can be a large block, and the second memory block BLK2 can be a small block.

[0127] Figure 15 It is shown Figure 2 A diagram illustrating another example of a schematic arrangement of the first and second wafers.

[0128] Reference Figure 15The width of the first memory block BLK1 in the first direction FD can be A1. The width of the second memory block BLK2 in the first direction FD can be A2, where A2 is greater than A1. As a result, the number of second memory blocks BLK2 included in the second wafer W2 can be less than the number of first memory blocks BLK1 included in the first wafer W1.

[0129] The lengths of the first memory block BLK1 and the second memory block BLK2 in the second direction SD can be substantially the same. The height of the first memory block BLK1 in the vertical direction VD can be H1. The height of the second memory block BLK2 in the vertical direction VD can be H2, where H2 is greater than H1.

[0130] The physical size of the first memory block BLK1 can be smaller than the physical size of the second memory block BLK2. The first memory block BLK1 can be a small block, and the second memory block BLK2 can be a large block.

[0131] Figure 16 It is shown Figure 15 A cross-sectional view illustrating an example of the detailed structure of the first and second wafers shown.

[0132] Reference Figure 16 The spacing A1 between adjacent first slits SLT1 can be smaller than the spacing A2 between adjacent second slits SLT2. That is, the width of the first memory block BLK1 in the first direction FD can be smaller than the width of the second memory block BLK2 in the first direction FD. (Refer to the previous text.) Figure 15 The lengths of the first memory block BLK1 and the second memory block BLK2 in the second direction SD can be substantially the same. The number of cell strings CSTRa included in the first memory block BLK1 can be less than the number of cell strings CSTRb included in the second memory block BLK2.

[0133] The number of stacked word lines WLa in the first memory block BLK1 can be less than the number of stacked word lines WLb in the second memory block BLK2. As a result, the number of memory cells included in a single unit string CSTRa can be less than the number of memory cells included in a single unit string CSTRb. For example, the number of stacked word lines WLa in the first memory block BLK1 can be half the number of stacked word lines WLb in the second memory block BLK2, and the number of memory cells included in a single unit string CSTRa can be half the number of memory cells included in a single unit string CSTRb.

[0134] Figure 17 It is shown Figure 15The circuit diagrams representing examples of the first and second memory blocks are shown.

[0135] Reference Figure 17 The number of memory cells MCa connected to a word line WLa in the first memory block BLK1 can be less than the number of memory cells MCb connected to a word line WLb in the second memory block BLK2. For example, the number of memory cells MCa connected to a word line WLa in the first memory block BLK1 can be half the number of memory cells MCb connected to a word line WLb in the second memory block BLK2.

[0136] The number of cell strings CSTRa included in the first memory block BLK1 can be less than the number of cell strings CSTRb included in the second memory block BLK2. For example, each first bit line BLa can be connected to two cell strings CSTRa in the first memory block BLK1, and each second bit line BLb can be connected to four cell strings CSTRb in the second memory block BLK2. In this case, the number of cell strings CSTRa included in the first memory block BLK1 can be half the number of cell strings CSTRb included in the second memory block BLK2.

[0137] The number of memory cells MCa included in each unit string CSTRa can be less than the number of memory cells MCb included in each unit string CSTRb. For example, the number of memory cells MCa included in a unit string CSTRa can be half the number of memory cells MCb included in a unit string CSTRb.

[0138] In one example, the number of memory cells MCa included in the first memory block BLK1 can be one-quarter (1 / 4) of the number of memory cells MCb included in the second memory block BLK2. The first memory block BLK1 can be a small block, and the second memory block BLK2 can be a large block.

[0139] Although in reference Figures 15 to 17In the described implementation, the number of cell strings CSTRa included in the first memory block BLK1 is less than the number of cell strings CSTRb included in the second memory block BLK2, and the number of memory cells MCa included in a cell string CSTRa in the first memory block BLK1 is less than the number of memory cells MCb included in a cell string CSTRb in the second memory block BLK2. However, opposite or reverse implementations are also possible. In other words, the number of cell strings CSTRa included in the first memory block BLK1 can be greater than the number of cell strings CSTRb included in the second memory block BLK2, and the number of memory cells MCa included in a cell string CSTRa in the first memory block BLK1 can be greater than the number of memory cells MCb included in a cell string CSTRb in the second memory block BLK2.

[0140] Figure 18 It is shown Figure 2 A diagram illustrating another example of a schematic arrangement of the first and second wafers.

[0141] Reference Figure 18 The width of the first memory block BLK1 in the first direction FD can be A1. The width of the second memory block BLK2 in the first direction FD can be A2, where A2 is smaller than A1. As a result, the number of first memory blocks BLK1 included in the first wafer W1 can be less than the number of second memory blocks BLK2 included in the second wafer W2.

[0142] The lengths of the first memory block BLK1 and the second memory block BLK2 in the second direction SD can be substantially the same. The height H1 of the first memory block BLK1 in the vertical direction VD can be less than the height H2 of the second memory block BLK2 in the vertical direction VD.

[0143] Figure 19 It is shown Figure 18 A cross-sectional view illustrating an example of the detailed structure of the first and second wafers shown.

[0144] Reference Figure 19 The spacing A1 between adjacent first slits SLT1 can be greater than the spacing A2 between adjacent second slits SLT2. That is, the width of the first memory block BLK1 in the first direction FD can be greater than the width of the second memory block BLK2 in the first direction FD. (Refer to the previous text.) Figure 18The lengths of the first memory block BLK1 and the second memory block BLK2 in the second direction SD can be substantially the same. The number of cell strings CSTRa included in the first memory block BLK1 can be greater than the number of cell strings CSTRb included in the second memory block BLK2.

[0145] The number of stacked word lines WLa in the first memory block BLK1 can be less than the number of stacked word lines WLb in the second memory block BLK2. As a result, the number of memory cells included in a single cell string CSTRa can be less than the number of memory cells included in a single cell string CSTRb.

[0146] Figure 20 It is shown Figure 18 The circuit diagrams representing examples of the first and second memory blocks are shown.

[0147] Reference Figure 20 The number of memory cells MCa connected to a word line WLa in the first memory block BLK1 can be greater than the number of memory cells MCb connected to a word line WLb in the second memory block BLK2. For example, the number of memory cells MCa connected to a word line WLa in the first memory block BLK1 can be twice the number of memory cells MCb connected to a word line WLb in the second memory block BLK2.

[0148] The number of cell strings CSTRa included in the first memory block BLK1 can be greater than the number of cell strings CSTRb included in the second memory block BLK2. For example, each first bit line BLa can be connected to four cell strings CSTRa in the first memory block BLK1, and each second bit line BLb can be connected to two cell strings CSTRb in the second memory block BLK2. In this case, the number of cell strings CSTRa included in the first memory block BLK1 can be twice the number of cell strings CSTRb included in the second memory block BLK2.

[0149] The number of memory cells MCa included in a unit string CSTRa can be less than the number of memory cells MCb included in a unit string CSTRb. For example, the number of memory cells MCa included in a unit string CSTRa can be three, and the number of memory cells MCb included in a unit string CSTRb can be eight.

[0150] In this case, the number of memory cells MCa included in the first memory block BLK1 can be defined as the product of the number of cell strings CSTRa connected to a first bit line BLa in the first memory block BLK1 (iv), the number of memory cells MCa included in a cell string CSTRa (iii), and the number of first bit lines BLa. That is, the number of memory cells MCa included in the first memory block BLK1 can be twelve (12) times the number of first bit lines BLa. Furthermore, the number of memory cells MCb included in the second memory block BLK2 can be defined as the product of the number of cell strings CSTRb connected to a second bit line BLb in the second memory block BLK2 (ii), the number of memory cells MCb included in a cell string CSTRb (viii), and the number of second bit lines BLb. That is, the number of memory cells MCb included in the second memory block BLK2 can be sixteen (16) times the number of second bit lines BLb.

[0151] Since the number of first bit lines BLa is the same as the number of second bit lines BLb, the ratio of the number of memory cells MCa included in the first memory block BLK1 to the number of memory cells MCb included in the second memory block BLK2 can be 12:16. The first memory block BLK1 can be a small block, and the second memory block BLK2 can be a large block.

[0152] Below, we will refer to Figures 21 to 25 The connection structure between the memory cell array and logic circuitry of a memory device according to embodiments of the present disclosure is described.

[0153] Figure 21 This is a cross-sectional view illustrating an example of the connection structure between the bit lines and page buffer circuitry of a memory device according to an embodiment of the present disclosure.

[0154] Reference Figure 21 The logic structure P may include a transistor TR_PB defined on the substrate 10. Figure 21 The transistor TR_PB shown can be configured with a page buffer circuit.

[0155] As referenced above Figure 4 The first bit line BLa of the first chip W1 and the corresponding second bit line BLb of the second chip W2 can be connected to each other via contacts CNT1 and CNT2 and bonding pads PAD1 and PAD2. The first bit line BLa of the first chip W1 can be connected to the transistor TR_PB via contacts CNT11 and CNT12 and wiring M11.

[0156] To insulate the electrode layer 20a and the contact CNT11 from each other, the dielectric layer 24a (instead of the electrode layer 20a) can be alternately stacked with the interlayer dielectric layer 22a in certain regions. That is, in these regions, multiple dielectric layers 24a can be alternately stacked with multiple interlayer dielectric layers 22a on the substrate 12a. The dielectric layer 24a can be formed of a dielectric material that has etch selectivity relative to the interlayer dielectric layer 22a. For example, the interlayer dielectric layer 22a can be silicon oxide, and the dielectric layer 24a can be silicon nitride.

[0157] The contact CNT11 can pass through multiple alternating interlayer dielectric layers 22a and multiple dielectric layers 24a in the vertical direction VD.

[0158] Figure 22 This is a cross-sectional view illustrating an example of the connection structure between the row lines and the row decoder of a memory device according to an embodiment of the present disclosure.

[0159] Reference Figure 22 The memory device may include multiple cell regions CAR1 and CAR2 and multiple link regions CNR1 and CNR2. The multiple cell regions CAR1 and CAR2 and the multiple link regions CNR1 and CNR2 may be alternately arranged on the second direction SD. In the following text, for ease of explanation, the link region CNR1 located between adjacent cell regions CAR1 and CAR2 is defined as the first link region, and the link region CNR2 located at the edge of the memory device is defined as the second link region. Cell region CAR2 may be located between the first link region CNR1 and the second link region CNR2.

[0160] The second transistor TR2_XDEC and a plurality of first transistors TR1_XDEC can be defined on the substrate 10 of the logic structure P. Figure 22 This is a cross-sectional view taken along the arrangement direction of the drain regions of the second transistor TR2_XDEC and the plurality of first transistors TR1_XDEC, and it should be understood that... Figure 22 Components other than the drain region, such as the gate and source regions, are not shown for configuring the first transistor TR1_XDEC and the second transistor TR2_XDEC. Although for the sake of simplicity, Figure 22 Only one second transistor TR2_XDEC is shown, but it should be understood that multiple second transistors TR2_XDEC corresponding to multiple electrode layers 20a are defined on the substrate 10.

[0161] The plurality of first transistors TR1_XDEC can be transfer transistors for transferring operating voltage to electrode layer 20b of the second wafer W2, and the plurality of second transistors TR2_XDEC can be transfer transistors for transferring operating voltage to electrode layer 20a of the first wafer W1. Figure 22 The first transistor TR1_XDEC and the second transistor TR2_XDEC shown can be configured as line decoders.

[0162] In this embodiment, a plurality of first transistors TR1_XDEC can be disposed in the first connection area CNR1. A plurality of bonding pads PAD3, each corresponding to a first transistor TR1_XDEC, can be defined in the first connection area CNR1 on a surface where the first wafer W1 is bonded to the second wafer W2. Each bonding pad PAD3 can be connected to the corresponding first transistor TR1_XDEC via contacts CNT21, CNT22, and CNT23 and wirings M21 and M22.

[0163] To insulate the electrode layer 20a and the contact CNT 22 from each other, the dielectric layer 24a (instead of the electrode layer 20a) can be alternately stacked with the interlayer dielectric layer 22a in the first connection region CNR1. That is, in the first connection region CNR1, a dielectric stack can be defined because multiple dielectric layers 24a and multiple interlayer dielectric layers 22a are alternately stacked on the substrate 12a. The dielectric layer 24a can be formed of a dielectric material that has etch selectivity relative to the interlayer dielectric layer 22a. For example, the interlayer dielectric layer 22a can be silicon oxide, and the dielectric layer 24a can be silicon nitride. In the first connection region CNR1, the contact CNT 22 can pass through the alternately stacked multiple interlayer dielectric layers 22a and multiple dielectric layers 24a in the vertical direction VD.

[0164] In the first connection region CNR1, each electrode layer 20b of the second wafer W2 may have a pad portion LPb. Since the pad portions LPb of the electrode layers 20b are staggered, a stepped structure can be configured. The contact CNT24 can be connected to the pad portion LPb of the electrode layers 20b. In the first connection region CNR1, the pad portion LPb of the electrode layers 20b may overlap with the insulating stack of the first wafer W1 (i.e., the alternating stacked interlayer dielectric layers 22a and dielectric layers 24a) in the vertical direction VD.

[0165] In the first connection area CNR1, bonding pads PAD4 corresponding to the pad portions LPb of electrode layer 20b can be defined on a surface of the second wafer W2 that is bonded to the first wafer W1. Contacts CNT24 connected to the pad portions LPb of electrode layer 20b can be connected to the bonding pads PAD4 via wiring M23 and contacts CNT25. The bonding pads PAD4 of the second wafer W2 can be bonded to the bonding pads PAD3 of the first wafer W1 to configure the electrical path connecting electrode layer 20b and the first transistor TR1_XDEC.

[0166] In the second connection region CNR2, each electrode layer 20a of the first wafer W1 may have a pad portion LPa. Since the pad portions LPa of the electrode layers 20a are staggered, a stepped structure can be configured.

[0167] Contact CNT26 can be connected to the pad portion LPa of electrode layer 20a. Contact CNT26 can be connected to the second transistor TR2_XDEC via wirings M24 and M25 and contacts CNT27 and CNT28. In this way, the electrical path connecting electrode layer 20a and the second transistor TR2_XDEC can be configured. Although for the sake of simplicity, Figure 22 Only one of each of the contacts CNT26, CNT27, and CNT28 and the wirings M24 and M25 is shown, but it should be understood that each of the contacts CNT26, CNT27, and CNT28 and the wirings M24 and M25 can be provided in multiples.

[0168] Figure 23 It is shown Figure 22 A top view showing an example of the main components of the first connection area.

[0169] Reference Figure 23 From the top view, the pad portions LPb of the electrode layer 20b can be arranged on the second direction SD. Each pad portion LPb can have a first length d1 on the second direction SD.

[0170] An active region ACT defined by an isolation layer can be contained within a substrate 10. The active region ACT can be arranged along a second direction SD. A gate G extending along the second direction SD and traversing the active region ACT can be contained within the substrate 10. Since the active region ACT is doped with impurities on both sides of the gate G, a drain region and a source region can be defined. The gate G, as well as the drain and source regions on both sides of the gate G, can be included in a first transistor TR1_XDEC.

[0171] The first transistor TR1_XDEC can be set at a constant pitch on the second direction SD. The pitch of the first transistor TR1_XDEC can be defined as the sum of the width of an active region ACT on the second direction SD and the spacing between adjacent edges of adjacent active regions ACT on the second direction SD. The pitch of the first transistor TR1_XDEC can be substantially the same as a first length d1, which is the length of the pad portion LPb on the second direction SD.

[0172] Contact CNT22 can overlap with the drain region of the corresponding first transistor TR1_XDEC in the vertical direction VD. (Refer to the above.) Figure 22The first transistor TR1_XDEC can be connected to the corresponding pad LPb via contact CNT22. The first transistor TR1_XDEC can overlap with the corresponding pad LPb in the vertical direction VD. By arranging the interconnected first transistor TR1_XDEC and the pad LPb to overlap in the vertical direction VD, the electrical path connecting the first transistor TR1_XDEC and the pad LPb can be configured as a straight line. Therefore, the length of the electrical path can be minimized, thereby minimizing the load on the electrical path and contributing to improved operational reliability of the memory device. Furthermore, due to the configuration of the electrical path, area consumption can be reduced, thus contributing to a smaller memory device size.

[0173] As referenced above Figures 3 to 20 The memory device may include small blocks and large blocks. In some embodiments, the width of the large block in the first direction FD may be configured to be greater than the width of the small block in the first direction FD. In such embodiments, the number of large blocks included in the memory device may be less than the number of small blocks included. Therefore, compared to embodiments where all memory blocks are configured as small blocks, only a small number of electrical paths are required to connect word lines and logic circuits. In memory devices according to some embodiments of this disclosure, the number of electrical paths connecting word lines and logic circuits can be reduced, thereby helping to reduce the complexity of wiring for configuring electrical paths and simplifying wiring design.

[0174] Figures 24A to 24E This is a cross-sectional view illustrating an example of the steps involved in manufacturing a memory structure for a first wafer according to an embodiment of the present disclosure.

[0175] Reference Figure 24A By alternately stacking multiple interlayer dielectric layers 22a and multiple dielectric layers 24a on substrate 12a, a pre-stacked layer PS can be formed. Although not shown, substrate 12a can be disposed on logic structure P (see [link to documentation]). Figure 22 Interlayer dielectric layer 22a and dielectric layer 24a can be formed of different materials. Dielectric layer 24a, which serves as a sacrificial layer, can be formed of a material that has etch selectivity relative to interlayer dielectric layer 22a. For example, interlayer dielectric layer 22a can be formed of oxide, and dielectric layer 24a can be formed of nitride.

[0176] A mask pattern PR exposing a portion of the second interconnect region CNR2 can be formed on the pre-stacked layer PS. The pre-stacked layer PS can be etched using a pad etching process that uses the mask pattern PR as an etching mask. The etching thickness of the pad etching process can correspond to the vertical spacing of the interlayer dielectric layer 22a. The vertical spacing of the interlayer dielectric layer 22a can be defined as the sum of the thickness of one interlayer dielectric layer 22a and the thickness of one dielectric layer 24a.

[0177] A trimming process can be performed on the mask pattern PR. Specifically, isotropic etching can be performed on the mask pattern PR. An etchant capable of removing the mask pattern PR can be used to perform the trimming process. Therefore, the height and width of the mask pattern PR can be reduced. Because the width of the mask pattern PR is reduced, the area of ​​the second connection region CNR2 exposed by the mask pattern PR can be increased. The pad etching process and the trimming process can form a cycle for creating a step in the second connection region CNR2.

[0178] Reference Figure 24B As the cycle is repeated multiple times, a stepped structure can be formed in the pre-stacked PS within the second connection region CNR2. The stepped structure can have multiple steps corresponding to multiple dielectric layers 24a, respectively. The mask pattern PR can be formed by photoresist and can be removed after the stepped structure is formed.

[0179] Reference Figure 24C A dielectric layer 31 covering the pre-stacked PS can be formed on the substrate 12a. A slit passing through the dielectric layer 31 and the pre-stacked PS in the vertical direction VD can be formed around the first connection region CNR1, and a sidewall dielectric layer 40 can be formed by filling the slit.

[0180] The sidewall dielectric layer 40, which serves as an etching barrier in the subsequent process of removing dielectric layer 24a, can be formed of a material that has etch selectivity relative to dielectric layer 24a. For example, if dielectric layer 24a is formed of nitride, sidewall dielectric layer 40 can be formed of oxide.

[0181] Multiple vertical channels CHa passing through dielectric layer 31 and pre-stacked PS in the vertical direction VD can be confined in the first cell region CAR1 and the second cell region CAR2. The order of the process for forming the sidewall dielectric layer 40 and the process for forming the vertical channels CHa can be reversed.

[0182] Reference Figure 24D An etching process for removing dielectric layer 24a can be performed. For this etching process, an etchant capable of removing dielectric layer 24a can be introduced. Since the sidewall dielectric layer 40 acts as an etching barrier in the etching process, dielectric layer 24a of the first connection region CNR1 can be retained without removal, and dielectric layers 24a of the first unit region CAR1, the second unit region CAR2, and the second connection region CNR2 can be removed to create empty spaces.

[0183] The removal of dielectric layer 24a creates empty spaces, which may reduce the structural stability of the pre-stacked PS. The dielectric layer 24a retained in the first interconnect region CNR1 can support the interlayer dielectric layer 22a to increase structural stability and prevent bending or collapse of the pre-stacked PS.

[0184] Reference Figure 24E The electrode layer 20a can be defined by filling the space where the dielectric layer 24a has been removed with a conductive material. The conductive material may include at least one selected from doped semiconductors (e.g., doped silicon), metals (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and transition metals (e.g., titanium or tantalum).

[0185] Figure 25 This is a cross-sectional view illustrating an example of another connection structure between a row line and a row decoder of a memory device according to an embodiment of the present disclosure.

[0186] Reference Figure 25 Multiple cell regions (CARs) and multiple connection regions (CNRs) can be alternately set on the second direction (SD). Each connection region (CNR) can be divided into a first connection region (CNR1) and a second connection region (CNR2). The first connection region (CNR1) and the second connection region (CNR2) included in a single connection region (CNR) can be set adjacent to each other on the second direction (SD).

[0187] Multiple electrode layers 20a and multiple interlayer dielectric layers 22a can be alternately stacked on the substrate 12a of the first wafer W1 in the cell region CAR and the second interconnect region CNR2. Multiple vertical channels CHa passing through the alternately stacked electrode layers 20a and interlayer dielectric layers 22a in the vertical direction VD can be defined in the cell region CAR.

[0188] Each electrode layer 20a may have a pad portion LPa. A contact CNT31 may be connected to the pad portion LPa. Although for the sake of simplicity, Figure 25 A limited number of contacts CNT31 are shown that are connected to the pad portion LPa, but it should be understood that the contacts CNT31 are connected to the pad portion LPa of each electrode layer 20a.

[0189] The pad portion LPa of the electrode layer 20a can be disposed in the second connection area CNR2. The pad portion LPa of the electrode layer 20a can be grouped into multiple groups based on the distance between the pad portion LPa and the substrate 12a, with each group disposed in a different second connection area CNR2. For example, the pad portion LPa of the electrode layer 20a can be grouped into pad portions LPa of the electrode layer 20a that are relatively close to the substrate 12a in the vertical direction VD and pad portions LPa of the electrode layer 20a that are relatively far away from the substrate 12a in the vertical direction VD. Figure 25In this context, the pad portion LPa of the electrode layer 20a, which is relatively close to the substrate 12a, can be disposed in a second connection area CN2 (e.g., in...). Figure 25 The pad portion LPa of the electrode layer 20a, which is located relatively far from the substrate 12a, can be disposed in another second connection area CN2 (e.g., in the middle, on the left side), while the pad portion LPa of the electrode layer 20a, which is located relatively far from the substrate 12a, can be disposed in another second connection area CN2 (e.g., in the middle, on the left side). Figure 25 (The middle is located on the right).

[0190] In each second connection region CNR2, since the pad portions LPa of the electrode layer 20a are staggered relative to each other, a stepped structure can be configured. The number of pad portions LPa provided in a second connection region CNR2 can be less than the number of electrode layers 20a stacked.

[0191] In each first connection region CNR1, a dielectric stack can be configured because multiple dielectric layers 24a and multiple interlayer dielectric layers 22a are alternately stacked on the substrate 12a of the first wafer W1. The dielectric layers 24a can be disposed on the same layer as the electrode layers 20a. The dielectric layers 24a can have the same thickness as the electrode layers 20a disposed on the same layer. The dielectric layers 24a can be formed of a dielectric material that has etch selectivity relative to the interlayer dielectric layers 22a. For example, if the interlayer dielectric layers 22a are formed of silicon oxide, the dielectric layers 24a can be formed of silicon nitride.

[0192] Multiple electrode layers 20b and multiple interlayer dielectric layers 22b can be alternately stacked on the substrate 12b of the second wafer W2. Multiple vertical channels CHb passing through the alternately stacked electrode layers 20b and interlayer dielectric layers 22b in the vertical direction VD can be defined in the cell region CAR.

[0193] Each electrode layer 20b may have a pad portion LPb. A contact CNT32 may be connected to the pad portion LPb. In each first connection area CNR1, since the pad portions LPb of the electrode layers 20b are staggered, a stepped structure can be configured. Although for the sake of simplicity, Figure 25 A limited number of contacts CNT32 are shown that are connected to some of the pad portions LPb of the electrode layer 20b, but it should be understood that the contacts CNT32 are connected to each pad portion LPb of the electrode layer 20b.

[0194] The pad portions LPb of the electrode layer 20b can be disposed in multiple first connection areas CNR1. The pad portions LPb of the electrode layer 20b can be grouped into multiple groups based on the distance between the pad portions LPb and the substrate 12b, with each group disposed in a different first connection area CNR1. For example, the pad portions LPb of the electrode layer 20b can be grouped into lower pad portions LPb of the electrode layer 20b that are relatively close to the substrate 12b in the vertical direction VD, and upper pad portions LPb of the electrode layer 20b that are relatively far away from the substrate 12b in the vertical direction VD. Figure 25 In this context, the pad portion LPb of the electrode layer 20b, which is relatively close to the substrate 12b, can be disposed in a first connection area CNR1 (e.g., in...). Figure 25 The pad portion LPb of the electrode layer 20b, which is located on the left side and is relatively far from the substrate 12b, can be disposed in another first connection area CNR1 (e.g., in...). Figure 25 (The middle is located on the right).

[0195] In each first connection region CNR1, since the pad portions LPb of the electrode layer 20b are staggered relative to each other, a stepped structure can be configured. The number of pad portions LPb provided in a first connection region CNR1 can be less than the number of electrode layers 20b stacked. In each of the plurality of first connection regions CNR1, the pad portions LPb of the electrode layer 20b can overlap with the insulating stack (configured by alternating layers of dielectric layers 24a and interlayer dielectric layers 22a) in the vertical direction VD.

[0196] Multiple first transistors TR1_XDEC and multiple second transistors TR2_XDEC can be defined on the substrate 10 of the logic structure P. The multiple first transistors TR1_XDEC can be transfer transistors for transferring operating voltage to the electrode layer 20b of the second wafer W2, and the multiple second transistors TR2_XDEC can be transfer transistors for transferring operating voltage to the electrode layer 20a of the first wafer W1. Figure 25 The first transistor TR1_XDEC and the second transistor TR2_XDEC shown can be configured as line decoders.

[0197] In the first connection area CNR1, multiple bonding pads PAD3, each corresponding to a respective first transistor TR1_XDEC, can be defined on a surface of the first wafer W1 bonded to the second wafer W2. The bonding pads PAD3 can be connected to the corresponding first transistor TR1_XDEC via contacts CNT33, CNT34, and CNT35 and wirings M31 and M32. Contacts CNT34 can pass through the insulating stack in each of the multiple first connection areas CNR1 in the vertical direction VD.

[0198] In the first connection area CNR1, multiple bonding pads PAD4, each corresponding to a pad portion LPb of a respective electrode layer 20b, can be defined on a surface of the second wafer W2 that is bonded to the first wafer W1. The bonding pads PAD4 can be connected to the corresponding pad portion LPb of the electrode layer 20b via contacts CNT36 and CNT32 and wiring M33. The bonding pads PAD4 of the second wafer W2 can be bonded to the bonding pads PAD3 of the first wafer W1. Based on this, electrical paths connecting the electrode layer 20b and the first transistor TR1_XDEC can be configured.

[0199] Contact CNT31 can be connected to the pad portion LPa of electrode layer 20a in the second connection area CNR2. Wiring M34 can be connected to the top of contact CNT31. Wiring M34 can extend from the second connection area CNR2 to the adjacent first connection area CNR1. In the first connection area CNR1, wiring M34 can be connected to contact CNT37. Contact CNT37 can pass through multiple alternately stacked dielectric layers 24a and multiple interlayer dielectric layers 22a in the vertical direction VD in the first connection area CNR1. Contact CNT37 can be connected to the second transistor TR2_XDEC through wiring M35 and contact CNT38.

[0200] To simplify the illustration, Figure 25 Only the first transistor TR1_XDEC and its electrical path connected to some electrode layers 20b are shown; however, it should be understood that a first transistor TR1_XDEC and its electrical path are provided for each electrode layer 20b. For the sake of simplicity, Figure 25 Only the second transistor TR2_XDEC and electrical path connected to some electrode layers 20a are shown, but it should be understood that a second transistor TR2_XDEC and electrical path are provided for each electrode layer 20a.

[0201] When the memory device is operational, a high-level operating voltage can be provided to electrode layers 20a and 20b. To transmit this high voltage, the first transistor TR1_XDEC and the second transistor TR2_XDEC should have a large size capable of withstanding the high voltage. Therefore, the first transistor TR1_XDEC and the second transistor TR2_XDEC can be positioned along the length direction (i.e., the second direction SD).

[0202] As a measure to improve integration, the size of pads LPa and LPb is being reduced. If pads LPa and LPb are densely arranged in one area, the length differences between the electrical paths used to connect the pads LPa and LPb to the first transistor TR1_XDEC and the second transistor TR2_XDEC may be significant due to the mismatch between their dimensions and the dimensions of the first transistor TR1_XDEC and the second transistor TR2_XDEC. Large length deviations between electrical paths increase the load differences between them, potentially reducing the operational reliability of the memory device.

[0203] According to this embodiment, the pad portions LPa of electrode layer 20a are distributed in multiple regions, and the pad portions LPb of electrode layer 20b are also distributed in multiple regions. Therefore, the length difference between the electrical paths used to connect the pad portions and the transistors can be reduced. This reduces the load difference between the electrical paths, thereby contributing to improved operational reliability of the memory device.

[0204] Figure 26A and Figure 26B This is a diagram illustrating an example of the bias conditions during an erase operation of a memory device according to an embodiment of the present disclosure. Specifically, Figure 26A The bias conditions are shown in an example where only the first memory block BLK1 is erased, and Figure 26B The bias conditions are shown in an example where only the second memory block BLK2 is erased.

[0205] Reference Figure 26A A ground voltage is applied to the drain select line DSLa and the source select line SSLa of the first memory block BLK1, and then floated. A voltage of 0V is applied to the word line WLa of the first memory block BLK1.

[0206] Apply a ground voltage to the drain select line DSLb and source select line SSLb of the second memory block BLK2, and then float them. Float the word line WLb of the second memory block BLK2.

[0207] An erase voltage Verase is applied to the common source line CSLa and bit line BLa of the first memory block BLK1, and a voltage of 0V is applied to the common source line CSLb of the second memory block BLK2. Because the second bit line BLb of the second memory block BLK2 is connected to the first bit line BLa of the first memory block BLK1, the erase voltage Verase is also applied to the second bit line BLb of the second memory block BLK2.

[0208] Due to this bias, the channel potential of the cell string CSTRa of the first memory block BLK1 and the channel potential of the cell string CSTRb of the second memory block BLK2 rise to the level of the erase voltage Verase.

[0209] If the channel potential of the cell string CSTRa in the first memory block BLK1 rises to the level of the erase voltage Verase, then the memory cell MCa of the first memory block BLK1 is erased because the difference between the channel potential and the potential (0V) of the word line WLa becomes equal to or greater than the amplitude required to erase the memory cell. On the other hand, if the channel potential of the cell string CSTRb in the second memory block BLK2 rises to the level of the erase voltage Verase, then the potential of the floating word line WLb of the second memory block BLK2 rises along with the channel potential through coupling. Therefore, since the difference between the channel potential and the potential of the word line WLb becomes less than the amplitude required to erase the memory cell, the memory cell MCb of the second memory block BLK2 is not erased.

[0210] The erase operation on the second memory block BLK2 is similar to the erase operation on the first memory block BLK1.

[0211] Reference Figure 26B A ground voltage is applied to the drain select line DSLa and the source select line SSLa of the first memory block BLK1, and then floated. The word line WLa of the first memory block BLK1 is floated. A ground voltage is applied to the drain select line DSLb and the source select line SSLb of the second memory block BLK2, and then floated. A voltage of 0V is applied to the word line WLb of the second memory block BLK2.

[0212] A 0V voltage is applied to the common source line CSLa of the first memory block BLK1, and an erase voltage Verase is applied to the common source line CSLb and the bit line BLb of the second memory block BLK2. Because the first bit line BLa of the first memory block BLK1 is connected to the second bit line BLb of the second memory block BLK2, the erase voltage Verase is also applied to the first bit line BLa of the first memory block BLK1.

[0213] Due to this bias, the channel potential of the cell string CSTRa of the first memory block BLK1 and the channel potential of the cell string CSTRb of the second memory block BLK2 increase.

[0214] If the channel potential of the cell string CSTRa in the first memory block BLK1 rises to the level of the erase voltage Verase, the potential of the floating word line WLa in the first memory block BLK1 rises along with the channel potential through coupling. Therefore, since the difference between the channel potential and the potential of the word line WLa becomes less than the amplitude required to erase the memory cell, the memory cell MCa in the first memory block BLK1 is not erased. On the other hand, if the channel potential of the cell string CSTRb in the second memory block BLK2 rises to the level of the erase voltage Verase, the memory cell MCb in the second memory block BLK2 is erased because the difference between the channel potential and the potential (0V) of the word line WLb becomes equal to or greater than the amplitude required to erase the memory cell.

[0215] Based on the erase bias voltage described above, the first memory block BLK1 and the second memory block BLK2, which have different sizes, can be erased independently.

[0216] Figure 27 This is a schematic block diagram illustrating an example of a memory system according to an embodiment of the present disclosure.

[0217] Reference Figure 27 The memory system 1000 according to embodiments of the present disclosure may include a memory device 100 and a memory controller 200.

[0218] The memory device 100 may include multiple memory blocks and can operate in response to the control of the memory controller 200. The operation of the memory device 100 may include, for example, read operations, write operations (also known as programming operations), and erase operations.

[0219] The memory blocks of memory device 100 may include multiple large blocks (LB) and multiple small blocks (SB). See above for reference. Figures 3 to 20 The large block (LB) and the small block (SB) can be defined in different wafers. For example, the small block (SB) can be defined in a first wafer, and the large block (LB) can be defined in a second wafer.

[0220] The memory device 100 can be configured to receive commands and addresses from the memory controller 200 and access address-selected regions in the memory cell array. In other words, the memory device 100 can perform operations corresponding to commands on the address-selected regions. For example, the memory device 100 can perform write operations, read operations, and erase operations. Specifically, in a write operation, the memory device 100 can program data into the address-selected region. In a read operation, the memory device 100 can read data from the address-selected region. In an erase operation, the memory device 100 can erase data stored in the address-selected region.

[0221] The memory controller 200 can control write (programming) operations, read operations, erase operations, and background operations on the memory device 100. For example, background operations may include at least one of garbage collection (GC), wear leveling (WL), and bad block management (BBM).

[0222] The memory controller 200 can control the operation of the memory device 100 according to a request from the host. Alternatively, the memory controller 200 can control the operation of the memory device 100 regardless of a request from the host. The memory controller 200 and the host can be separate devices. The memory controller 200 and the host can also be integrated into a single device. Hereinafter, for ease of explanation, an example will be provided showing that the memory controller 200 and the host are separate devices.

[0223] Flash memory has a lifespan that can be determined based on the number of write / erase cycles. Due to its physical characteristics, flash memory cannot be overwritten. That is, in flash memory, when a write operation is to be performed on a memory block containing data, an erase operation must be performed on the memory block before the write operation is performed. Because of this characteristic of flash memory, system software called a flash translation layer (hereinafter referred to as "FTL") is used between the host's file system and the memory device 100.

[0224] A flash translation layer (FTL) provides an interface connection for hiding the erase operations of the flash memory between the host file system and the memory device 100. Disadvantages of flash memory devices (e.g., pre-write erase and mismatch between erase and write cells) can be addressed by the flash translation layer (FTL). The flash translation layer (FTL) maps logical addresses generated by the file system to physical addresses of the memory device 100 during write operations of the memory device 100. The flash translation layer (FTL) driven by the memory controller 200 can map addresses according to a log mapping method. However, the advantages of this disclosure can be applied to various address mapping methods other than log mapping.

[0225] The memory controller 200 can allocate log blocks by referring to the size of the input data. Specifically, the memory controller 200 can allocate log blocks in units of small blocks (SB) or large blocks (LB) by referring to the size of the data. In the following text, allocating memory blocks existing in the free block pool as log blocks and allocating memory blocks existing in the free block pool as data blocks will have similar meanings. Therefore, allocating a memory block selected from the free block pool as a log block means that it can also be allocated as a data block.

[0226] As described above, the memory device 100 is configured with multiple memory blocks, and each memory block consists of multiple pages. For example, a memory block may consist of 64 or 128 pages. The memory device 100 performs write and read operations based on pages and erase operations based on memory blocks. The speeds of the various operations differ from each other. For example, the speed of a read operation is approximately 25 microseconds (25 μs), the speed of a write operation is approximately 250 microseconds (250 μs), and the speed of an erase operation is approximately 2000 microseconds (2000 μs), thus the speeds of the various operations are asymmetrical. In particular, the speed of the erase operation is much slower than the speeds of the read and write operations. The speed of the erase operation decreases as the size of the memory block increases. The slow erase operation is the main cause of the performance degradation of the memory device 100.

[0227] according to Figure 26A and Figure 26B The erase bias shown allows the memory device 100 according to embodiments of the present disclosure to erase in blocks or blocks. Therefore, the memory controller 200 can allocate log blocks in blocks or blocks.

[0228] If small blocks existing in the free block pool are allocated as log blocks, the allocated log blocks can be erased by a pre-write erase operation. According to embodiments of this disclosure, memory blocks can be erased in units of small blocks, thereby helping to improve memory block performance by reducing erase time.

[0229] Figure 28 This is an example representation of a flowchart that helps explain the writing method according to embodiments of this disclosure.

[0230] Reference Figure 28 In step S10, the memory controller can detect the size of the data to be written.

[0231] In step S20, when it is determined that the detected data size is smaller than the reference size (e.g., 30MB) (i.e., the data is small-sized data), the process proceeds to step S30. On the other hand, when it is determined that the size of the data to be written is equal to or greater than the reference size (i.e., the data is large-sized data), the process proceeds to step S40.

[0232] In step S30, small blocks are allocated as log blocks. That is, when the data to be written is small in size, small blocks from memory blocks existing in the free block pool are provided as log blocks. If log block allocation is completed, the process proceeds to step S50 to program the data into the allocated log blocks.

[0233] In step S40, large blocks are allocated as log blocks. That is, when the requested data to be written is large, large blocks from the memory blocks existing in the free block pool are provided as log blocks. If the log block allocation is completed, the process proceeds to step S50 to program the data into the allocated log blocks.

[0234] In step S50, the memory controller programs the requested data to be written into the allocated small or large block. An erase operation can be performed on the allocated memory block before programming the data. If programming of the requested data is complete, the programming cycle corresponding to a write request ends.

[0235] According to this embodiment, if the data to be written is small in size, a small block is allocated instead of a large block. Therefore, write amplification can be reduced, thereby helping to improve memory utilization efficiency. Furthermore, by allocating small blocks instead of large blocks when the data to be written is small in size, the time required for the pre-write erase operation can be reduced, thereby helping to improve the performance of the memory device.

[0236] Figures 29A to 29DThis is an example representation of a diagram that helps explain the memory block management method according to embodiments of the present disclosure.

[0237] Reference Figures 29A to 29D The memory device may include multiple memory blocks B1, B2, and B3. Memory blocks can be classified as large blocks LB or small blocks SB. Figure 29A and Figure 29B An example is shown where memory blocks are classified into small blocks (SB) and large blocks (LB) based on the number of cell strings included in each memory block. Figure 29C and Figure 29D An example is shown where memory blocks are classified into small blocks (SB) and large blocks (LB) based on the number of word lines included in each memory block.

[0238] Based on the type of data to be stored, memory can be classified into user area, system area, and over-provisioning (OP) area. User block B1 represents a memory block in the user area, system block B2 represents a memory block in the system area, and OP block B3 represents a memory block in the over-provisioning area.

[0239] Data requested by the host for writing can be stored in user block B1. User block B1 can be classified as a free block or a data block based on whether it contains data. A free block is an empty block that does not store data, while a data block is a block that contains data. Although not shown, a bad block is a memory block that cannot store data. Based on the time when a bad block occurs, bad blocks can be classified as manufacturing bad blocks (MBB) that occur during the manufacture of the memory device and growing bad blocks (GBB) that occur during the use of the memory block.

[0240] System information can be stored in system block B2. System information may include mapping data used to map information between logical and physical addresses, booting information necessary for booting the storage device, and setting information for the operation of the firmware of the memory controller.

[0241] Reserved space block B3 can be reserved space allocated to allow the smooth operation of various functions required to drive the memory device, such as wear leveling, garbage collection, and bad block management.

[0242] Generally, the size of user data randomly generated by users on mobile devices is not constant. For example, a memory block might be 100MB in size, and a user might generate and store 1MB of data. In this case, memory efficiency decreases because the remaining 99MB of space becomes unusable (write amplification). However, not all user data is small in size. In recent years, the number of pixels in cameras has been increasing, making it possible to store large image data. Meanwhile, large data is primarily stored in enterprise solid-state drives (eSSDs).

[0243] Figure 29A and Figure 29C This is a diagram illustrating a memory block management method for a memory device used in a mobile device, and Figure 29B and Figure 29D This is a diagram illustrating the memory block management method of a memory device used in an eSSD.

[0244] Reference Figure 29A and Figure 29C If the memory device is used in a mobile device, the memory controller can configure the proportions of small blocks (SB) and large blocks (LB) within user block B1, which is managed as a user region, to be the same or similar because the sizes of the data requested to be written vary. For example, half of user block B1, managed as a user region, can be small blocks (SB), and the other half can be large blocks (LB). Furthermore, the remaining blocks besides user block B1 can be used to configure system block B2 and reserved space block B3.

[0245] Reference Figure 29B and Figure 29D If the storage device is used in an eSSD, then because most of the data requested for writing is large, all large block loads (LBs) can be managed as user areas. The system area and reserved space area can be managed and configured within smaller block loads (SBs). Furthermore, after configuring the system area and reserved space area, there may be remaining smaller block loads, which can be managed as user areas.

[0246] Figure 30 This is a block diagram schematically illustrating an example of a computing system including a memory device according to an embodiment of the present disclosure.

[0247] Reference Figure 30A computing system 700 according to one embodiment may include a memory system 710, a microprocessor (CPU) 720, RAM 730, a user interface 740, and a modem 750 such as a baseband chipset, all electrically connected to a system bus 760. If the computing system 700 according to this embodiment is a mobile device, a battery (not shown) may be additionally provided to supply the operating voltage of the computing system 700. Although not shown in the figures, it will be apparent to those skilled in the art that the computing system 700 according to this embodiment may additionally include an application chipset, a camera image processor (CIS), and mobile DRAM, etc. The memory system 710 may be configured, for example, to use a solid-state drive / solid-state disk (SSD) to store data using non-volatile memory. Alternatively, the memory system 710 may be configured as a converged flash memory (e.g., OneNAND flash memory).

[0248] Although exemplary embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered descriptive only and not intended to limit the scope of the technology. The scope of this disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of this disclosure can be interpreted in conjunction with the appended claims and include all equivalents falling within the scope of the appended claims.

[0249] Cross-reference to related applications

[0250] This application claims priority to Korean Patent Application No. 10-2020-0068781, filed on June 8, 2020 with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A memory device comprising: A first memory block, the first memory block being defined in a first wafer; as well as A second memory block, defined within a second wafer, is disposed in a vertical direction relative to the first wafer. Wherein, the size of the first memory block is smaller than the size of the second memory block, and The number of memory cells in the first memory block is less than the number of memory cells in the second memory block.

2. The memory device according to claim 1, in, Each of the first memory block and the second memory block includes multiple word lines stacked on a substrate and multiple memory cells connected to the multiple word lines. The number of memory cells in each of the multiple word lines connected to the first memory block is less than the number of memory cells in each of the multiple word lines connected to the second memory block.

3. The memory device according to claim 1, in, Each of the first memory block and the second memory block includes multiple cell strings, and The number of cell strings in the first memory block is less than the number of cell strings in the second memory block.

4. The memory device according to claim 1, in, Each of the first memory block and the second memory block includes: Multiple electrode layers and multiple interlayer dielectric layers are alternately stacked on a substrate in the vertical direction; and Multiple vertical channels, the multiple vertical channels passing through the multiple electrode layers and the multiple interlayer dielectric layers, and The number of vertical channels included in the first memory block is less than the number of vertical channels included in the second memory block.

5. The memory device according to claim 1, in, Each of the first memory block and the second memory block includes multiple bit lines and multiple cell strings connected to the multiple bit lines, and The number of cell strings connected to each of the multiple bit lines in the first memory block is less than the number of cell strings connected to each of the multiple bit lines in the second memory block.

6. The memory device according to claim 1, in, Each of the first memory block and the second memory block includes: Multiple word lines and multiple interlayer dielectric layers, wherein the multiple word lines and the multiple interlayer dielectric layers are alternately stacked on a substrate in the vertical direction; and Multiple vertical channels, the multiple vertical channels passing through the multiple word lines and the multiple interlayer dielectric layers in the vertical direction, The vertical channel is connected to multiple bit lines extending in a first direction parallel to the top surface of the substrate, and Wherein, the width of the first memory block in the first direction is smaller than the width of the second memory block in the first direction.

7. The memory device according to claim 1, in, Each of the first memory block and the second memory block includes a string of cells, and The number of memory cells in the cell string of the first memory block is less than the number of memory cells in the cell string of the second memory block.

8. The memory device according to claim 1, in, Each of the first memory block and the second memory block includes: Multiple word lines and multiple interlayer dielectric layers, wherein the multiple word lines and the multiple interlayer dielectric layers are alternately stacked on a substrate; and Multiple vertical channels pass through the multiple word lines and the multiple interlayer dielectric layers in the vertical direction, and The number of word lines included in the first memory block is less than the number of word lines included in the second memory block.

9. The memory device according to claim 1, further comprising: The first bit line is defined in the first chip and connected to the first memory block; The second bit line is defined in the second chip and connected to the second memory block; The first bonding pad is disposed on a surface of the first wafer that is bonded to the second wafer, and is connected to the first bit line; as well as The second bonding pad is disposed on a surface of the second wafer that is bonded to the first wafer, connected to the second bit line, and bonded to the first bonding pad.

10. The memory device according to claim 1, in, The first chip also includes logic circuitry for controlling the operation of the first memory block and the second memory block, and The logic circuit is disposed on a substrate below the first memory block.

11. The memory device according to claim 1, in, The second chip also includes logic circuitry for controlling the operation of the first memory block and the second memory block, and The logic circuit is disposed on a substrate below the second memory block.

12. The memory device according to claim 1, wherein, The first memory block and the second memory block are erased independently of each other.

13. A memory system comprising: Memory devices; as well as Memory controller, The memory device includes: Small pieces, said small pieces being defined within a first wafer; and A large block, defined within a second wafer, the second wafer being disposed in a vertical direction relative to the first wafer. The memory controller stores data in the small block or the large block by referring to the size of the data to be written, and The number of memory cells in the small block is less than the number of memory cells in the large block.

14. The memory system according to claim 13, wherein, If the size of the requested data to be written is smaller than the reference size, the data is stored in the small block; if the size of the requested data to be written is equal to or greater than the reference size, the data is stored in the large block.

15. The memory system according to claim 13, in, Each of the small blocks and the large blocks comprises multiple unit strings, and The number of unit strings included in the small block is less than the number of unit strings included in the large block.

16. The memory system according to claim 13, wherein, The small and large blocks are erased independently of each other.

17. A method for writing data to a memory device, the memory device comprising small blocks and large blocks, the writing method comprising the following steps: Receive write requests; Detect the size of the data to be written in the request; as well as The data is stored in the small block or the large block according to the detection results, and The number of memory cells in the small block is less than the number of memory cells in the large block.

18. The writing method according to claim 17, wherein, If the size of the requested data to be written is smaller than the reference size, the data is stored in the small block; and if the size of the requested data to be written is equal to or greater than the reference size, the data is stored in the large block.

19. The writing method according to claim 17, further comprising the following steps: If the size of the data to be written is smaller than the reference size, the small block is erased before the data is stored in the small block.

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