Wafer packaging method, device, electronic equipment and storage medium

Abstract

The application provides a wafer packaging method and device, electronic equipment and storage medium, and relates to the technical field of semiconductors. The method comprises the following steps: performing wafer testing on a wafer, obtaining a test wafer map corresponding to the wafer, and recording the position of each chip in the wafer and the corresponding test result in the test wafer map; based on the test result, superimposing a plurality of test wafer maps to determine whether the chip at each position in a plurality of wafers is a risk chip, and generating a target wafer map; and packaging the plurality of wafers based on the target wafer map. The method provided in the embodiment of the application can improve the risk chip rejection efficiency.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to a wafer packaging method, apparatus, electronic device, and storage medium. Background Technology

[0002] With increasingly higher chip integration, chip testing is becoming more complex. In applications with high chip quality requirements, such as automotive electronics and industrial-grade chips, anomalies in one area during wafer manufacturing often indicate similar risks in neighboring areas. However, during testing, these areas often fail to detect the chips due to critical or non-fatal physical damage, resulting in the chips ultimately reaching the customer and causing significant losses.

[0003] Currently, to reduce chip failure rates or ensure that chip failure rates meet requirements, each chip must be tested, which is inefficient in detecting and eliminating risky chips. Summary of the Invention

[0004] The purpose of this application is to provide a wafer packaging method, apparatus, electronic device, and storage medium to improve the efficiency of rejecting risky chips.

[0005] In a first aspect, embodiments of this application provide a wafer packaging method, including:

[0006] The wafer is tested to obtain a test wafer image corresponding to the wafer. The test wafer image records the position of each chip in the wafer and the corresponding test results.

[0007] Based on the test results superimposed with multiple test wafer images, it is determined whether the chip at each location in the multiple wafers is a risk chip, and a target wafer image is generated; and

[0008] The plurality of wafers are packaged based on the target wafer diagram.

[0009] In the above implementation process, by overlaying test wafer images of multiple wafers, a target wafer image that can more clearly show the abnormal areas of the wafer is generated. This identifies the risk areas where risky chips are located in the same batch of wafers. By packaging the chips in the wafer using the target wafer image, the problem of increasing time costs caused by testing each chip can be avoided. This allows for the rapid removal of potentially missed risky chips and improves chip quality.

[0010] Optionally, the step of superimposing multiple test wafer images based on the test results includes:

[0011] Using the first test wafer image as the initial wafer image, the next test wafer image is read sequentially and compared with the reference wafer image to obtain the comparison result, determining whether the chip at each position in the test wafer image is the risk chip; and

[0012] The initial wafer image is updated based on the comparison results. After reading multiple test wafer images and updating the initial wafer image based on the comparison results, the target wafer image is obtained.

[0013] In the above implementation process, by superimposing failure information from multiple wafers, risk areas are identified in the target wafer map. During wafer packaging, multiple wafers in a batch can be packaged based on a single target wafer map, thereby improving chip quality and packaging efficiency. Simultaneously, failure tracking of risky chips can be performed based on the target wafer map, facilitating the identification of the causes of anomalies in that area.

[0014] Optionally, the step of sequentially reading the next test wafer image and comparing it with the reference wafer image to obtain a comparison result, and determining whether the chip at each position in the test wafer image is the risk chip, includes:

[0015] The test wafer image is compared bit by bit with the reference wafer image;

[0016] When the first position in the test wafer diagram is a failure position, the failure position is recorded and the chip corresponding to the failure position is determined to be the risk chip.

[0017] When the first position in the test wafer diagram is a qualified position, it is determined whether the position in the reference wafer diagram related to the first position is a failed position. If so, the chip corresponding to the qualified position is determined to be the risk chip.

[0018] In the above implementation process, a reference wafer image is generated by overlaying a batch of test wafer images. The reference wafer image is used to determine which locations on the wafer are prone to quality risks. By comparing the reference wafer image and the test wafer image, the corresponding chip locations are eliminated, thereby improving the chip yield and increasing the efficiency of eliminating risky chips.

[0019] Optionally, before performing wafer testing on the wafer, the method further includes:

[0020] The first test wafer image of the specified batch is used as the initial reference wafer image. The next test wafer image is read sequentially and compared with the initial reference wafer image to obtain the comparison result.

[0021] The initial reference wafer image is updated based on the comparison results. After reading multiple test wafer images and updating the initial reference wafer image based on the comparison results, the reference wafer image is obtained.

[0022] In the above implementation process, by determining the number of times the same location is detected in multiple test wafer images, the abnormal area in the target wafer image can be determined, which can accurately reflect the wafer manufacturing abnormalities, thereby improving the efficiency of rejecting risky chips.

[0023] Optionally, in a preferred embodiment, the packaging of the plurality of wafers based on the target wafer pattern includes:

[0024] The number of times the chip at each position in multiple test wafer images is the risk chip is counted to determine the abnormal area in the target wafer image;

[0025] Chips located in the abnormal region of the wafer are removed, and the remaining chips in the wafer are packaged.

[0026] Optionally, in another preferred embodiment, the packaging of the plurality of wafers based on the target wafer pattern includes:

[0027] Obtain the failure item corresponding to the chip at each position in the test wafer diagram;

[0028] Receive a rejection instruction, the rejection instruction including the invalid items to be rejected;

[0029] Mark the target location of the chip corresponding to the rejection instruction in the target wafer diagram;

[0030] Based on a preset rejection scheme, chips related to the target location in the wafer are rejected, and the other chips in the wafer are packaged.

[0031] In the above implementation process, risky chips with one or more specific failure items in the wafer can be removed based on a preset rejection scheme, which can improve the flexibility of chip screening.

[0032] Optionally, obtaining the test wafer pattern corresponding to the wafer includes:

[0033] Import the test data from the wafer testing into the JMP software;

[0034] The test data is converted into the test wafer image using the graphics generator in the JMP software.

[0035] Secondly, embodiments of this application provide a wafer packaging apparatus, comprising:

[0036] The testing module is used to perform wafer testing on the wafer and obtain a test wafer map corresponding to the wafer. The test wafer map records the position of each chip in the wafer and the corresponding test results.

[0037] The overlay module is used to overlay multiple test wafer images based on the test results, determine whether the chip at each location in the multiple wafers is a risk chip, and generate a target wafer image; and

[0038] The packaging module is used to package the plurality of wafers based on the target wafer diagram.

[0039] In the above implementation process, by overlaying test wafer images of multiple wafers, a target wafer image that can more clearly show the abnormal areas of the wafer is generated. This identifies the risk areas where risky chips are located in the same batch of wafers. By packaging the chips in the wafer using the target wafer image, the problem of increasing time costs caused by testing each chip can be avoided. This allows for the rapid removal of potentially missed risky chips and improves chip quality.

[0040] Optionally, the overlay module can be specifically used for:

[0041] The first test wafer image is used as the initial wafer image. The next test wafer image is read sequentially and compared with the reference wafer image to obtain the comparison result. It is determined whether the chip at each position in the test wafer image is the risk chip. The initial wafer image is updated based on the comparison result. After reading multiple test wafer images and updating the initial wafer image based on the comparison result, the target wafer image is obtained.

[0042] In the above implementation process, by superimposing failure information from multiple wafers, risk areas are identified in the target wafer map. During wafer packaging, multiple wafers in a batch can be packaged based on a single target wafer map, thereby improving chip quality and packaging efficiency. Simultaneously, failure tracking of risky chips can be performed based on the target wafer map, facilitating the identification of the causes of anomalies in that area.

[0043] Optionally, the overlay module can also be used to: compare the test wafer image with the reference wafer image bit by bit; when the first position in the test wafer image is a failure position, record the failure position and determine that the chip corresponding to the failure position is the risk chip; when the first position in the test wafer image is a qualified position, determine whether the position in the reference wafer image related to the first position is a failure position, and if so, determine that the chip corresponding to the qualified position is the risk chip.

[0044] In the above implementation process, a reference wafer image is generated by overlaying a batch of test wafer images. The reference wafer image is used to determine which locations on the wafer are prone to quality risks. By comparing the reference wafer image and the test wafer image, the corresponding chip locations are eliminated, thereby improving the chip yield and increasing the efficiency of eliminating risky chips.

[0045] Optionally, the wafer packaging apparatus may further include a reference wafer pattern generation module, used to take the first test wafer pattern of a specified batch as an initial reference wafer pattern before performing wafer testing on the wafer, sequentially read the next test wafer pattern and compare it with the initial reference wafer pattern to obtain a comparison result; update the initial reference wafer pattern based on the comparison result, and obtain the reference wafer pattern after reading multiple test wafer patterns and updating the initial reference wafer pattern based on the comparison result.

[0046] In the above implementation process, by determining the number of times the same location is detected in multiple test wafer images, the abnormal area in the target wafer image can be determined, which can accurately reflect the wafer manufacturing abnormalities, thereby improving the efficiency of rejecting risky chips.

[0047] Optionally, the packaging module may be specifically used to: count the number of times the chip corresponding to each position in the multiple test wafer diagrams is the risk chip, determine the abnormal region in the target wafer diagram; remove the chip in the abnormal region from the wafer, and package the other chips in the wafer.

[0048] Optionally, the packaging module can also be used to: obtain the failure item corresponding to the chip at each position in the test wafer diagram; receive a rejection instruction, the rejection instruction including the failure item to be rejected; mark the target position of the chip corresponding to the rejection instruction in the target wafer diagram; reject the chip related to the target position in the wafer based on a preset rejection scheme, and package the other chips in the wafer.

[0049] In the above implementation process, risky chips with one or more specific failure items in the wafer can be removed based on a preset rejection scheme, which can improve the flexibility of chip screening.

[0050] Optionally, the testing module may be specifically used to: import test data from wafer testing into JMP software; and convert the test data into the test wafer image based on the graphics generator in the JMP software.

[0051] Thirdly, embodiments of this application provide an electronic device, which includes a memory and a processor. The memory stores program instructions, and when the processor reads and runs the program instructions, it executes the steps in any of the implementation methods of the wafer packaging method provided in the first aspect of this application.

[0052] Fourthly, embodiments of this application also provide a computer-readable storage medium storing computer program instructions, which, when read and executed by a processor, perform steps in any of the implementation methods of the wafer packaging method provided in the first aspect of this application. Attached Figure Description

[0053] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of the steps of the wafer packaging method provided in the embodiments of this application;

[0055] Figure 2 This is a schematic diagram illustrating a step of superimposing multiple test wafer images according to an embodiment of this application;

[0056] Figure 3 This is a schematic diagram illustrating the steps for determining whether a chip is a risky chip, provided in an embodiment of this application.

[0057] Figure 4 This is a schematic diagram illustrating the steps for generating a reference wafer pattern provided in an embodiment of this application;

[0058] Figure 5 A schematic diagram illustrating the steps of chip packaging provided in this application embodiment; and

[0059] Figure 6 This is a schematic diagram of a wafer packaging apparatus provided in an embodiment of this application. Detailed Implementation

[0060] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. For example, the flowcharts and block diagrams in the drawings illustrate the architecture, functions, and operations of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, program segment, or part of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions. In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0061] During their research, the applicant discovered that current chip testing only focuses on individual chips. However, during wafer manufacturing, if a chip malfunctions, the surrounding area often faces the same risk. Chips in these areas, often due to critical or non-fatal physical damage, are not detected and screened out, ultimately leading to damaged chips entering the market and causing losses for users. Currently, to reduce chip failure rates or ensure that chip failure rates meet requirements, every single chip must be tested, resulting in inefficient detection and rejection of risky chips.

[0062] This application provides a wafer packaging method that improves chip quality and increases the efficiency of risk chip rejection by marking potentially hazardous areas within the same batch of wafers, removing the hazardous chips from these areas, and packaging the chips from the remaining areas. Please refer to... Figure 1 , Figure 1 This is a schematic diagram illustrating the steps of a wafer packaging method provided in an embodiment of this application. The method may include the following steps:

[0063] In step S11, wafer testing is performed on the wafer to obtain a test wafer diagram corresponding to the wafer. The test wafer diagram records the position of each chip in the wafer and the corresponding test results.

[0064] In step S12, based on the test results, multiple test wafer images are superimposed to determine whether the chip at each position in the multiple wafers is a risk chip, and a target wafer image is generated.

[0065] In step S13, the plurality of wafers are packaged based on the target wafer diagram.

[0066] For example, chip probing (CP) can be performed on the wafer, where the chip pins are exposed. Probes are connected to a testing machine to determine the chip's logic function, pin function, communication function, etc., resulting in a corresponding wafer map. The wafer map represents the mapping relationship of the chip within the wafer. The wafer packaging method provided in this application can be implemented through multiple implementation objects. For example, the target wafer map in steps S11 to S12 can be implemented in a wafer fab, and the wafer fab sends the wafer and the corresponding target wafer map to a packaging plant for packaging the chips within the wafer.

[0067] Multiple test wafer images can be overlaid using a programming script. The programming script can be a Perl script, an awk script, a sed script, or another method. Alternatively, an image processing program can be used to visualize the test results, generate a test wafer image, and then overlay multiple test wafer images to obtain the target wafer image.

[0068] Specifically, the test wafer images of the entire batch, such as a single LOT wafer, can be superimposed to obtain the target wafer image. Typically, there are 25 wafers in a single LOT. By superimposing the test wafer images of a single LOT wafer, the target wafer image is produced to characterize whether the chip at each location in the entire batch of wafers is a risky chip. Based on the target wafer image, the area where the risky chip is located is eliminated, and the chips in other areas are packaged.

[0069] The overlay process can be as follows: take the first test wafer image as the initial wafer image, mark the comparison results of the subsequent test wafer image and the reference wafer image on the initial wafer image, and the reference wafer image can be a wafer image with multiple maximum failure probability positions recorded after testing a specified batch of wafers, or the comparison results of each test wafer image and the reference wafer image can be recorded on a new wafer image, and the new wafer image can be used as the target wafer image.

[0070] Therefore, this application embodiment generates a target wafer image that more clearly shows the abnormal areas of the wafer by superimposing test wafer images of multiple wafers, thereby determining the risk area where the risky chip is located in the same batch of wafers. By packaging the chip in the wafer using the target wafer image, the problem of increased time cost caused by testing each chip can be avoided, and risky chips that may be missed can be quickly eliminated, thus improving chip quality.

[0071] In an optional embodiment, for step S12, this application embodiment also provides an implementation process for overlaying multiple test wafer patterns, please refer to... Figure 2 , Figure 2 This application provides a schematic diagram of a process for superimposing multiple test wafer images. The process for superimposing multiple test wafer images may include:

[0072] In step S21, the first test wafer image is used as the initial wafer image, the next test wafer image is read sequentially and compared with the reference wafer image to obtain the comparison result, and it is determined whether the chip at each position in the test wafer image is the risk chip.

[0073] In step S22, the initial wafer image is updated based on the comparison result. After reading multiple test wafer images and updating the initial wafer image based on the comparison result, the target wafer image is obtained.

[0074] Specifically, the failure information of each chip in each wafer can be read from the wafer diagram using a programming script. The failure information can include the failure status, failure item, and chip location. The failure status is used to characterize whether the chip has failed, and the failure item is used to characterize the cause of the chip's failure.

[0075] For example, the programming script can be a Perl script, which can be used to obtain failure information from the test wafer image, record the number of failures of chips at the same location, and generate the target wafer image. Alternatively, failure information can also be obtained from the test wafer image using other programming language scripts or data reading programs.

[0076] For details, please refer to Figure 3 , Figure 3 This application provides a schematic diagram of a step for determining whether a chip is a risky chip. The implementation of determining whether a chip is a risky chip may include:

[0077] In step S31, the test wafer image is compared bit by bit with the reference wafer image.

[0078] In step S32, when the first position in the test wafer diagram is a failure position, the failure position is recorded and the chip corresponding to the failure position is determined to be the risk chip.

[0079] In step S33, when the first position in the test wafer diagram is a qualified position, it is determined whether the position in the reference wafer diagram related to the first position is a failed position. If it is, the chip corresponding to the qualified position is determined to be the risk chip.

[0080] For example, the comparison process can be as follows: A Perl script reads the test wafer image of a single wafer and compares it bit by bit with a reference wafer image. If a location on the test wafer is a failure location, that location is marked as failure, and the comparison proceeds to the next location. If that location is a passable location, the comparison is made with the relevant location on the reference wafer image to determine if the chip at that location meets the rejection requirements. The relevant location can be the same location on the reference wafer image, its surrounding locations, or locations within a specified interval from that location. If the relevant location is not a risk area, it is marked as a failure location. After comparing the entire wafer, the comparison results are recorded, and the initial wafer image is updated.

[0081] In one embodiment, the test results of each chip location can also be represented by color, letter, or number. For example, white, A, or 0 can be used to indicate that the chip location is a qualified location, while other colors or numbers can be used to indicate that the location is a failed location. Based on different colors, letters, or numbers, the failure items at each location can be represented. When chips are rejected, the corresponding locations can be rejected based on the failure items. When multiple failure items exist at the same location in the target wafer image, the area at that location can be evenly divided into multiple parts to indicate that multiple failure items exist at the same location in the same batch of wafers, or another color or number can be used to represent the set of multiple failure items.

[0082] Therefore, this embodiment of the application identifies risk areas in the target wafer map by superimposing failure information from multiple wafers. During wafer packaging, multiple wafers in a batch can be packaged based on a single target wafer map, thereby improving chip quality and packaging efficiency. Furthermore, failure tracking of risky chips can be performed based on the target wafer map, facilitating the identification of the causes of anomalies in that area.

[0083] Optionally, embodiments of this application also provide an implementation method for generating a reference wafer pattern, please refer to... Figure 4 , Figure 4 This is a schematic diagram illustrating the steps for generating a reference wafer pattern according to an embodiment of this application. The implementation of generating a reference wafer pattern may include the following steps:

[0084] In step S41, the first test wafer image of the specified batch is used as the initial reference wafer image, and the next test wafer image is read sequentially and compared with the initial reference wafer image to obtain the comparison result.

[0085] In step S42, the initial reference wafer image is updated based on the comparison result. After reading multiple test wafer images and updating the initial reference wafer image based on the comparison result, the reference wafer image is obtained.

[0086] The overlay and update method in generating the reference wafer map can refer to steps S21-S22 of the process for overlaying multiple test wafer maps, and will not be elaborated here. Alternatively, the reference wafer map can be generated based on prior knowledge or previous detection results, or the initial wafer map, i.e., the first test wafer map, can be directly used as the reference wafer map to compare with the test wafer map, identify risk areas in the wafer, and quickly remove chips with risks.

[0087] Therefore, the embodiments of this application adopt the method of generating a reference wafer image, superimposing a batch of test wafer images to generate a reference wafer image, using the reference wafer image to determine which positions of the chip in the wafer are prone to quality risks, and then comparing the reference wafer image and the test wafer image to remove the chip in the corresponding position, thereby improving the chip yield and improving the efficiency of removing risky chips.

[0088] In an optional embodiment, for step S13, this application embodiment also provides a chip packaging implementation method, please refer to... Figure 5 , Figure 5 This is a schematic diagram illustrating the chip packaging steps provided in an embodiment of this application. The chip packaging steps can be as follows:

[0089] In step S51, the number of times the chip corresponding to each position in the multiple test wafer diagrams is the risk chip is counted to determine the abnormal area in the target wafer diagram.

[0090] In step S52, the chips in the abnormal region of the wafer are removed, and the other chips in the wafer are packaged.

[0091] Specifically, when identifying abnormal regions in the target wafer image, the test data from the wafer test is imported into the JMP software; the test data is then converted into the test wafer image based on the graphics generator in the JMP software.

[0092] Specifically, a risk region map can be generated based on the graph builder in JMP, recording the number of times each chip is considered risky at each location. Contour lines can be added to the risk region map to show the rate of change of continuous measurements, which is helpful in judging chip risk trends. Additionally, a 3D scatter plot can be generated based on the number of times each chip is considered risky at each location to visually display the area with the highest risk probability.

[0093] When identifying abnormal areas, a risk threshold can be set. The risk threshold can be a natural number such as 0 or 1, and can also be specifically set according to the quantity of wafers in the same batch. When the number of risk occurrences exceeds the risk threshold, the location corresponding to that chip is determined to be a risk area.

[0094] Therefore, the embodiments of this application determine the abnormal area in the target wafer map by determining the number of times the same location is detected in multiple test wafer maps, which can accurately reflect the wafer manufacturing abnormalities and thus improve the efficiency of rejecting risky chips.

[0095] Alternatively, the implementation of packaging multiple wafers in step S13 can also be as follows:

[0096] Obtain the failure item corresponding to the chip at each position in the test wafer diagram; receive the rejection instruction, which includes the failure item to be rejected; mark the target position of the chip corresponding to the rejection instruction in the target wafer diagram; reject the chip related to the target position in the wafer based on the preset rejection scheme, and package the other chips in the wafer.

[0097] In one embodiment, after overlaying the information of the entire batch of wafers, a Perl script can be used to mark obviously abnormal areas. For example, if a batch consists of 25 wafers, and 23 of them have defects in a certain area, the remaining 2 wafers, although good, will still mark that area as defective. Areas similar to the above example can be marked as specific abnormal areas that need to be processed. The Perl script then uses the target wafer image containing the abnormal area information for chip rejection during output processing. The Perl script reads the target wafer image information that needs to be rejected, compares each chip's position on the wafer with the specified rejection area, and if it is within the area, it is marked as defective; otherwise, the original information is retained. After the comparison is complete, all chips in the abnormal areas of the wafer can be rejected.

[0098] In another embodiment, a Perl script can be used to obtain test wafer image data of a specified batch, remove relevant failure information according to the input requirements, process the location information of all failure items in the batch of test wafer image data based on Perl, and output a reference wafer image with location information and failure count.

[0099] The test wafer image to be processed is compared with the reference wafer image, and risky chips are rejected based on the specified rejection scheme, such as misalignment, nine-square grid, checkerboard, or a scheme that requires that all N chips around the good area must be good before the position can be recorded as good.

[0100] Therefore, the embodiments of this application can also eliminate risky chips with one or more specific failure items in the wafer based on a preset rejection scheme, which can improve the flexibility of chip screening.

[0101] Based on the same inventive concept, this application also provides a wafer packaging device 60, please refer to... Figure 6 , Figure 6This is a schematic diagram of a wafer packaging apparatus provided in an embodiment of this application. The wafer packaging apparatus 60 may include:

[0102] The test module 61 is used to perform wafer testing on the wafer and obtain a test wafer map corresponding to the wafer. The test wafer map records the position of each chip in the wafer and the corresponding test results.

[0103] The overlay module 62 is used to overlay multiple test wafer images based on the test results, determine whether the chip at each position in the multiple wafers is a risk chip, and generate a target wafer image.

[0104] The packaging module 63 is used to package the plurality of wafers based on the target wafer pattern.

[0105] Optionally, the overlay module 62 may be specifically used to: take the first test wafer image as the initial wafer image, sequentially read the next test wafer image and compare it with the reference wafer image to obtain a comparison result, and determine whether the chip at each position in the test wafer image is the risk chip; update the initial wafer image based on the comparison result, and after reading multiple test wafer images and updating the initial wafer image based on the comparison result, obtain the target wafer image.

[0106] Optionally, the overlay module 62 can also be used to: compare the test wafer map with the reference wafer map bit by bit; when the first position in the test wafer map is a failure position, record the failure position and determine that the chip corresponding to the failure position is the risk chip; when the first position in the test wafer map is a qualified position, determine whether the position in the reference wafer map related to the first position is a failure position, and if so, determine that the chip corresponding to the qualified position is the risk chip.

[0107] Optionally, the wafer packaging apparatus 60 may further include a reference wafer pattern generation module, used to take the first test wafer pattern of a specified batch as an initial reference wafer pattern before performing wafer testing on the wafer, sequentially read the next test wafer pattern and compare it with the initial reference wafer pattern to obtain a comparison result; update the initial reference wafer pattern based on the comparison result, and obtain the reference wafer pattern after reading multiple test wafer patterns and updating the initial reference wafer pattern based on the comparison result.

[0108] Optionally, the packaging module 63 may be specifically used to: count the number of times the chip corresponding to each position in the multiple test wafer diagrams is the risk chip, determine the abnormal area in the target wafer diagram; remove the chip in the abnormal area of ​​the wafer, and package the other chips in the wafer.

[0109] Optionally, the packaging module 63 can also be used to: obtain the failure item corresponding to the chip at each position in the test wafer diagram; receive a rejection instruction, the rejection instruction including the failure item to be rejected; mark the target position of the chip corresponding to the rejection instruction in the target wafer diagram; reject the chip related to the target position in the wafer based on a preset rejection scheme, and package the other chips in the wafer.

[0110] Optionally, the test module 61 may be specifically used to: import test data of wafer testing into JMP software; and convert the test data into the test wafer image based on the graphics generator in the JMP software.

[0111] Based on the same inventive concept, embodiments of this application also provide an electronic device, which includes a memory and a processor. The memory stores program instructions, and when the processor reads and runs the program instructions, it executes the steps in any of the implementation methods of the wafer packaging method provided in the first aspect of this application.

[0112] Based on the same inventive concept, embodiments of this application also provide a computer-readable storage medium storing computer program instructions. When the computer program instructions are read and executed by a processor, they perform the steps in any of the implementation methods of the wafer packaging method provided in the first aspect of this application.

[0113] The computer-readable storage medium can be any medium capable of storing program code, such as Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM). The storage medium stores the program, and the processor executes the program after receiving an execution instruction. The method executed by the electronic terminal as defined in any embodiment of this invention can be applied to the processor or implemented by the processor.

[0114] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0115] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0116] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0117] It can be replaced and can be implemented, wholly or partially, through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, wholly or partially, in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated.

[0118] The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0119] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0120] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A wafer packaging method, characterized in that, include: The wafer is tested to obtain a test wafer image corresponding to the wafer. The test wafer image records the position of each chip in the wafer and the corresponding test results. Based on the test results, multiple test wafer images are superimposed to determine whether the chip at each location in the multiple wafers is a risk chip, and a target wafer image is generated. as well as The plurality of wafers are packaged based on the target wafer diagram; The step of overlaying multiple test wafer images based on the test results includes: using the first test wafer image as the initial wafer image; sequentially reading the next test wafer image and comparing it with a reference wafer image to obtain a comparison result, and determining whether the chip at each position in the test wafer image is the risk chip; reading the failure information of each chip from the test wafer image, the failure information including the chip's failure state, failure item, and chip location; updating the initial wafer image based on the comparison result; and obtaining the target wafer image after reading multiple test wafer images and updating the initial wafer image based on the comparison result. The step of sequentially reading the next test wafer image and comparing it with the reference wafer image to obtain a comparison result, and determining whether the chip at each position in the test wafer image is the risk chip, includes: comparing the test wafer image with the reference wafer image position by position; when the first position in the test wafer image is a failure position, recording the failure position and determining the chip corresponding to the failure position as the risk chip; when the first position in the test wafer image is a qualified position, determining whether the position in the reference wafer image related to the first position is a failure position; if so, determining the chip corresponding to the qualified position as the risk chip.

2. The method according to claim 1, characterized in that, Prior to performing wafer testing on the wafer, the method further includes: Using the first test wafer image of a specified batch as the initial reference wafer image, the next test wafer image is sequentially read and compared with the initial reference wafer image to obtain the comparison result; and The initial reference wafer image is updated based on the comparison results. After reading multiple test wafer images and updating the initial reference wafer image based on the comparison results, the reference wafer image is obtained.

3. The method according to claim 1, characterized in that, The process of packaging the plurality of wafers based on the target wafer pattern includes: The number of times the chip at each position in multiple test wafer images is the risk chip is counted to determine the abnormal area in the target wafer image; Chips located in the abnormal region of the wafer are removed, and the remaining chips in the wafer are packaged.

4. The method according to claim 1, characterized in that, The process of packaging the plurality of wafers based on the target wafer pattern includes: Obtain the failure item corresponding to the chip at each position in the test wafer diagram; Receive a rejection instruction, the rejection instruction including the invalid items to be rejected; Mark the target location of the chip corresponding to the rejection instruction in the target wafer diagram; and Based on a preset rejection scheme, chips related to the target location in the wafer are rejected, and the other chips in the wafer are packaged.

5. The method according to claim 1, characterized in that, The step of obtaining the test wafer image corresponding to the wafer includes: Import the test data from the wafer testing into the JMP software; and The test data is converted into the test wafer image using the graphics generator in the JMP software.

6. A wafer packaging device, characterized in that, include: The testing module is used to perform wafer testing on the wafer and obtain a test wafer map corresponding to the wafer. The test wafer map records the position of each chip in the wafer and the corresponding test results. The overlay module is used to overlay multiple test wafer images based on the test results, determine whether the chip at each position in the multiple wafers is a risk chip, and generate a target wafer image; as well as A packaging module is used to package the plurality of wafers based on the target wafer pattern; The overlay module is specifically used to: take the first test wafer image as the initial wafer image, sequentially read the next test wafer image and compare it with the reference wafer image to obtain the comparison result, and determine whether the chip at each position in the test wafer image is the risk chip; Failure information for each chip is read from the test wafer diagram. The failure information includes the chip's failure state, failure item, and chip location. The initial wafer image is updated based on the comparison results. After reading multiple test wafer images and updating the initial wafer image based on the comparison results, the target wafer image is obtained. The overlay module is further configured to: compare the test wafer image with the reference wafer image bit by bit; when the first position in the test wafer image is a failure position, record the failure position and determine that the chip corresponding to the failure position is the risk chip; When the first position in the test wafer diagram is a qualified position, determine whether the position in the reference wafer diagram related to the first position is a failed position; If so, then the chip corresponding to the qualified position is determined to be the risk chip.

7. An electronic device, characterized in that, The electronic device includes a memory and a processor. The memory stores program instructions, and when the processor executes the program instructions, it performs the steps of the method according to any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, perform the steps of the method according to any one of claims 1-5.

Images