Semiconductor packaging structure and fabrication method, fabrication method of chip to be packaged

Abstract

This application provides a semiconductor packaging structure and its fabrication method, specifically a method for fabricating a chip to be packaged using the semiconductor packaging structure. The semiconductor packaging structure includes: a packaging substrate, a multilayer chip stacking structure, and a molding compound layer. The multilayer chip stacking structure is attached to the packaging substrate and includes multiple chips stacked sequentially. The molding compound layer is formed on the surface of the packaging substrate and encapsulates the multilayer chip stacking structure. The chip includes: a semiconductor substrate, a circuit layer, and a reinforcing and anti-warping film. The semiconductor substrate includes opposing first and second surfaces. The circuit layer is formed on the first surface, and the reinforcing and anti-warping film covers the second surface. The semiconductor packaging structure and its chip structure provided in this application effectively avoid the risk of chip breakage or warping and the problem of packaged device failure by changing the release direction of local mechanical stress in the chip and increasing the mechanical strength of the chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure and its fabrication method, as well as a method for fabricating a chip to be packaged for use in a semiconductor packaging structure. Background Technology

[0002] Semiconductor packaging devices typically involve two processing steps: chip manufacturing and chip packaging. Therefore, the characteristics of the chip itself and the quality of the packaging technology directly determine the final performance of the semiconductor packaging device product.

[0003] With the continuous development of semiconductor technology, the overall thickness of chips is getting thinner, while the metal circuit layers are getting thicker. As a result, in the packaging structure of ultra-thin chips such as 3D memory, the mechanical strength of the chips is getting worse and worse. At the same time, the thermal stress generated by thermal matching during the packaging process may cause the chips to warp. Therefore, conventional semiconductor packaging devices and their intermediates often suffer from chip cracks, damage or warping, and semiconductor packaging device failure due to the above reasons. Summary of the Invention

[0004] This application provides a semiconductor packaging structure, a method for preparing the semiconductor packaging structure, and a method for preparing a chip to be packaged for the semiconductor packaging structure, which can at least partially solve the above-mentioned problems existing in the related art.

[0005] This application provides a semiconductor packaging structure, including: a packaging substrate; a multilayer chip stacking structure attached to the packaging substrate and including a plurality of chips stacked sequentially; and a molding compound layer formed on the surface of the packaging substrate and encapsulating the multilayer chip stacking structure, wherein the chip includes: a semiconductor substrate including opposing first and second surfaces; a circuit layer formed on the first surface; and a reinforcing anti-warping film covering the second surface.

[0006] In one embodiment of this application, the semiconductor substrate further includes a substrate sidewall connecting the first surface and the second surface; and the reinforcing anti-warping film also covers the substrate sidewall and the sidewall of the circuit layer.

[0007] In one embodiment of this application, the thickness of the reinforcing anti-warping film is 1% to 17% of the common thickness of the semiconductor substrate and the circuit layer.

[0008] In one embodiment of this application, the common thickness of the semiconductor substrate and the circuit layer is 30 micrometers to 50 micrometers, and the thickness of the reinforcing anti-warping film is 0.5 micrometers to 5 micrometers.

[0009] In one embodiment of this application, while the common thickness remains constant, the thickness of the reinforcing anti-warping film increases as the thickness of the circuit layer increases.

[0010] In one embodiment of this application, the reinforced anti-warping membrane is a single-layer structure or a composite structure.

[0011] In one embodiment of this application, the reinforced anti-warping film is at least one of a nitride layer, a silicide layer, and an oxide layer.

[0012] In one embodiment of this application, the reinforced anti-warping film is prepared by chemical vapor deposition.

[0013] In one embodiment of this application, the chip includes a three-dimensional non-volatile memory, wherein the three-dimensional non-volatile memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0014] Another aspect of this application provides a method for fabricating a semiconductor packaging structure, comprising: attaching a multilayer chip stacking structure to a packaging substrate, wherein the multilayer chip stacking structure includes a plurality of chips stacked sequentially; and forming a molding compound layer for encapsulating the multilayer chip stacking structure on the surface of the packaging substrate, wherein the chip includes: a semiconductor substrate including opposing first and second surfaces; a circuit layer formed on the first surface; and a reinforcing anti-warping film covering the second surface.

[0015] In one embodiment of this application, the semiconductor substrate further includes a substrate sidewall connecting the first surface and the second surface; and the reinforcing anti-warping film also covers the substrate sidewall and the sidewall of the circuit layer.

[0016] In one embodiment of this application, the thickness of the reinforcing anti-warping film is 1% to 17% of the common thickness of the semiconductor substrate and the circuit layer.

[0017] In one embodiment of this application, the common thickness of the semiconductor substrate and the circuit layer is 30 micrometers to 50 micrometers, and the thickness of the reinforcing anti-warping film is 0.5 micrometers to 5 micrometers.

[0018] In one embodiment of this application, while keeping the common thickness constant, the thickness of the reinforcing anti-warping film is set to increase as the thickness of the circuit layer increases.

[0019] In one embodiment of this application, the reinforced anti-warping membrane is configured as a single-layer structure or a composite structure.

[0020] In one embodiment of this application, the reinforced anti-warping film is at least one of a nitride layer, a silicide layer, and an oxide layer.

[0021] In one embodiment of this application, the reinforced anti-warping film is prepared using a chemical vapor deposition process.

[0022] In one embodiment of this application, the chip includes a three-dimensional non-volatile memory, wherein the three-dimensional non-volatile memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0023] This application also provides a method for fabricating a chip to be packaged in a semiconductor packaging structure, comprising: half-cutting the wafer from the front side where a circuit layer is disposed; disposing a temperature-resistant shaping layer on the front side; thinning the wafer from the back side opposite to the front side to separate the wafer into multiple independent sub-wafers fixed on the temperature-resistant shaping layer; forming a reinforcing anti-warping film on the surface of the sub-wafers that is not in contact with the temperature-resistant shaping layer; attaching a dicing film to a portion of the surface of the reinforcing anti-warping film and removing the temperature-resistant shaping layer; and performing a dicing process to obtain multiple independent chips to be packaged, wherein the chips to be packaged include the sub-wafers and the reinforcing anti-warping film formed on a portion of the surface of the sub-wafers.

[0024] In one embodiment of this application, the sub-wafer includes an opposing upper surface and a lower surface, and a side surface of the sub-wafer connecting the upper surface and the lower surface. The upper surface of the sub-wafer is fixed on the heat-resistant shaping layer. Forming a reinforcing and anti-warping film on the surface of the sub-wafer that is not in contact with the heat-resistant shaping layer includes forming the reinforcing and anti-warping film on the lower surface of the sub-wafer and the side surface of the sub-wafer.

[0025] In one embodiment of this application, forming a reinforced anti-warping film on the surface of the sub-wafer that is not in contact with the temperature-resistant shaping layer includes: forming the reinforced anti-warping film on the surface of the sub-wafer that is not in contact with the temperature-resistant shaping layer using a chemical vapor deposition process.

[0026] In one embodiment of this application, the heat-resistant shaping layer is a quartz glass layer.

[0027] In one embodiment of this application, providing a heat-resistant shaping layer on the front side includes: applying an adhesive or lamination process to provide the heat-resistant shaping layer on the front side.

[0028] In one embodiment of this application, the chip to be packaged includes a three-dimensional non-volatile memory, wherein the three-dimensional non-volatile memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0029] According to at least one embodiment of the present application, the semiconductor packaging structure, the method for preparing the semiconductor packaging structure, and the method for preparing the chip to be packaged for the semiconductor packaging structure, by forming a reinforcing and anti-warping film covering the bottom surface of the semiconductor substrate (or covering the bottom surface, side surface, and side surface of the semiconductor substrate and the side surface of the circuit layer) in the structure of the chip to be packaged, the release direction of local mechanical stress in the chip can be changed, the mechanical strength of the chip can be increased, and the risks of chip cracks, damage or warping and the failure of semiconductor packaging devices can be effectively avoided.

[0030] Furthermore, according to at least one embodiment of this application, before forming the hardening and anti-warping film, a film layer with temperature-resistant shaping characteristics can be first formed on the front side of the half-cut wafer (the wafer is used to cut the chip to be packaged, which includes a semiconductor substrate and a circuit layer). While fixing and protecting the wafer, the film layer can make the subsequently formed hardening and anti-warping film thinner, which is more suitable for the packaging structure of ultra-thin chips such as three-dimensional memory. Attached Figure Description

[0031] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0032] Figure 1A This is a cross-sectional schematic diagram of a semiconductor packaging structure according to one embodiment of this application;

[0033] Figure 1B This is an enlarged cross-sectional view of a portion of a semiconductor package structure at point A according to one embodiment of this application.

[0034] Figure 2 These are photographs showing cracks and damage in chips manufactured using conventional semiconductor packaging methods.

[0035] Figure 3 This is a cross-sectional schematic diagram showing warping and damage in a multilayer chip stacking structure formed by conventional semiconductor packaging structure fabrication methods;

[0036] Figure 4 This is a cross-sectional schematic diagram showing warping and damage in a multilayer chip stacking structure formed by conventional semiconductor packaging structure fabrication methods;

[0037] Figure 5 This is a schematic diagram showing the distribution of mechanical stress in a chip within a conventional semiconductor packaging structure;

[0038] Figure 6 This is a schematic diagram of the distribution of mechanical stress in a chip within a semiconductor packaging structure, according to one embodiment of this application.

[0039] Figure 7This is a flowchart of a method for fabricating a semiconductor packaging structure according to one embodiment of this application;

[0040] Figure 8 This is a flowchart illustrating a method for fabricating a chip to be packaged for a semiconductor packaging structure according to one embodiment of this application; and

[0041] Figures 9 to 15 These are schematic diagrams illustrating a method for fabricating a chip to be packaged for a semiconductor packaging structure according to one embodiment of this application. Detailed Implementation

[0042] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first surface discussed herein may also be referred to as the second surface, and vice versa.

[0044] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0045] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0046] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0047] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0048] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0049] Figure 1A This is a cross-sectional view of a semiconductor package structure 1000 according to one embodiment of this application. Figure 1B This is an enlarged cross-sectional view of a portion of point A in a semiconductor package structure 1000 according to one embodiment of this application.

[0050] like Figure 1A and Figure 1B As shown, the semiconductor packaging structure 1000 provided in this application may include: a packaging substrate 100, a multilayer chip stack structure 200, and a molding compound layer 300. The multilayer chip stack structure 200 is attached to the packaging substrate 100 and may include a plurality of chips 201 stacked sequentially. The molding compound layer 300 is formed on the surface 110 of the packaging substrate 100 and encapsulates the multilayer chip stack structure 200. The chip 201 may include a semiconductor substrate 210, a circuit layer 220, and a hardening anti-warping film 230. The semiconductor substrate 210 includes a first surface 11 and a second surface 12 opposite to each other. The circuit layer 220 is formed on the first surface 11 of the semiconductor substrate 210 and has a circuit layer side surface 14. The hardening anti-warping film 230 covers the second surface 12 of the semiconductor substrate 210.

[0051] Furthermore, as an alternative, the semiconductor substrate 210 also includes a substrate sidewall 13 connecting the first surface 11 and the second surface 12. The circuit layer 220 also has a circuit layer sidewall 14. The reinforcing anti-warping film 230 covers the second surface 12 of the semiconductor substrate 210 and further covers the substrate sidewall 13 and the circuit layer sidewall 14.

[0052] Specifically, in one embodiment of this application, the chip 201 in the multilayer chip stack structure 200 may include device structures and interconnect structures of the device structures. The device structures may include at least one of active devices and passive devices. Active devices may include, for example, MOS devices, memory devices, or other semiconductor devices, wherein memory devices may include, for example, non-volatile memory or random access memory. Non-volatile memory may include, for example, floating-gate field-effect transistors such as NOR-type memory and NAND-type memory, or ferroelectric memory, phase-change memory, etc. Passive devices may include, for example, resistors, capacitors, or inductors. Furthermore, the device structure may be a planar device or a three-dimensional device, wherein three-dimensional devices may be, for example, FIN-FETs (fin field-effect transistors) and three-dimensional memory.

[0053] The specific parameters and characteristics of the packaging substrate 100, such as material, thickness, or size, can be selected according to actual needs, such as the specific type of the multilayer chip stack structure 200 to be supported. The multilayer chip stack structure 200 can be adhered to the surface 110 of the packaging substrate 100 by an adhesive layer, and the adhesive layer is only located within the projection area of ​​the multilayer chip stack structure 200 on the packaging substrate 100.

[0054] Alternatively, the chips 201 in the multilayer chip stacking structure 200 can be stacked on the packaging substrate 100 in a zigzag pattern, thereby providing space for the bonding lines of the chips 201 to be formed subsequently; or the chips 201 can be stacked vertically on each other and / or separated laterally, thereby providing space for the bonding lines to be formed subsequently. This application does not limit the stacking method of the chips 201 in the multilayer chip stacking structure 200.

[0055] Furthermore, despite Figure 1A Multiple chips 201 are shown to have the same chip size, but in some embodiments, multiple chips 201 may have different chip sizes.

[0056] The molding compound layer 300 can be formed from any suitable material, such as silicon oxide filler or resin. Alternatively, the molding compound layer 300 may include an epoxy molding compound (EMC). Typically, the molding compound layer 300 and the chip 201 have different coefficients of thermal expansion and thermal conductivity.

[0057] Figure 2 These are photographs showing cracks and damage in chips manufactured using conventional semiconductor packaging methods. Figure 3 This is a cross-sectional schematic diagram showing warping and damage in a multilayer chip stack structure formed by conventional semiconductor packaging methods. Figure 4 This is a cross-sectional schematic diagram showing warping and damage in a multilayer chip stack structure formed by conventional semiconductor packaging methods.

[0058] Semiconductor packaging typically involves two processes: chip manufacturing and chip packaging. Therefore, the characteristics of the chip itself and the quality of the packaging technology directly determine the final performance of the semiconductor device. Conventional semiconductor packaging technologies typically include: halving the wafer; applying a thinning protective film to the front side of the wafer; thinning the wafer from the back side to separate it into multiple independent sub-wafers (chips to be packaged) fixed on the thinning protective film; applying a dicing film to the back side of the wafer and removing the thinning protective film; picking up the sub-wafers and forming a multilayer chip stack structure; wire bonding the chips in the multilayer chip stack structure; and forming a molding compound layer to encapsulate the multilayer chip stack structure.

[0059] However, as Figures 2 to 4 As shown, with the continuous development of semiconductor technology, the overall thickness of chips is getting thinner, while the metal circuit layer inside is getting thicker. As a result, in the packaging structure of ultra-thin chips such as three-dimensional memory, the mechanical strength of the chip is getting worse and worse. At the same time, the thermal stress generated by thermal matching during the packaging process may cause the chip to warp. Therefore, conventional semiconductor packaging devices and their intermediates often suffer from failure problems such as cracks, breaks or damage due to the above reasons.

[0060] Figure 2 The left and right images are photographs of cracks and damage appearing in chips formed after wafer backside thinning during the conventional semiconductor packaging process. In the left image, the area circled by the ellipse shows a crack, which may have extended into the chip's interior. In subsequent steps, such as wire bonding, this could lead to chip breakage and failure. In the right image, the area circled by the ellipse shows surface damage, which could directly cause the semiconductor package device to fail.

[0061] like Figure 3 As shown, in conventional semiconductor packaging, it is necessary to achieve electrical connection (wire bonding) between the chip in the multilayer chip stack structure and the external packaging frame to ensure smooth transmission of electrical signals. Specifically, a wire bonder 10 and wire bonding can be used to solder the chip 30 in the multilayer chip stack structure 20 to the packaging frame to achieve electrical connection between the chip 30 and the packaging frame. However, the heat generated during the wire bonding process often further exacerbates the warpage of the chip in the ultra-thin chip packaging structure, which can lead to failure problems such as cracks, breaks, or damage in the semiconductor packaged device and its intermediates.

[0062] like Figure 4As shown, in a conventional semiconductor packaging process, a molding compound layer 40 for encapsulating a multilayer chip stack structure 20 can be formed on the surface of the packaging substrate 50. As the number of metal layers included in the chip 30 within the multilayer chip stack structure 20 increases, the circuit density becomes higher, and the mechanical strength of the chip 30 deteriorates. Simultaneously, thermal stress generated during the packaging process can cause the chip 30 to warp (as shown by the polygonal circle in the figure). Furthermore, as the molding compound layer 40, such as the plastic film resin, becomes thinner, and the number of multilayer chip stack structures 20 encapsulated within it increases, semiconductor packaged devices are prone to failure problems such as breakage or damage.

[0063] The semiconductor packaging structure provided in this application, by forming a reinforcing and anti-warping film covering the bottom surface of the semiconductor substrate in the structure of the chip to be packaged, can change the release direction of local mechanical stress in the chip, increase the mechanical strength of the chip, and thus effectively avoid the risk of chip cracking, damage or warping and the failure of semiconductor packaging devices during the packaging process.

[0064] In addition, to enhance the above-mentioned beneficial effects, a reinforcing anti-warping film can be further applied to the sides of the semiconductor substrate and the sides of the circuit layer.

[0065] Specifically, the following will take the example of the reinforcing anti-warping film 230 covering the bottom surface 12, side surface 13, and side surface 14 of the semiconductor substrate 210 and the circuit layer 220 to explain in detail the technical features, preparation steps, and effects of the above-mentioned reinforcing anti-warping film 230. However, those skilled in the art should understand that without departing from the teachings of this application, this application does not limit the constituent materials, structure, formation process, and implementation method of the reinforcing anti-warping film. As long as it can solve the same technical problem and achieve the same technical effect as the reinforcing anti-warping film in this embodiment, it shall fall within the protection scope of this application.

[0066] Refer again Figure 1B In one embodiment of this application, the thickness D1 of the hardening anti-warping film 230 is 1% to 17% of the common thickness D2 of the semiconductor substrate 210 and the circuit layer 220. Alternatively, when the common thickness D2 of the semiconductor substrate 210 and the circuit layer 220 is 30 micrometers to 50 micrometers, the thickness D1 of the hardening anti-warping film 230 can be 0.5 micrometers to 5 micrometers. In other words, compared with the overall thickness of the chip 201, the thickness of the hardening anti-warping film 230 is relatively thin, making it more suitable for packaging structures of ultra-thin chips such as 3D memory.

[0067] Furthermore, in one embodiment of this application, when the common thickness D2 of the semiconductor substrate 210 and the circuit layer 220 remains constant, the thickness D1 of the reinforcing anti-warping film 230 increases as the thickness of the circuit layer 220 increases. For example, when the common thickness D2 of the semiconductor substrate 210 and the circuit layer 220 is 40 micrometers, when the thickness of the circuit layer 220 is only 5 micrometers, the thickness D1 of the reinforcing anti-warping film 230 can be selected from 0.2 micrometers to 1 micrometer; when the thickness of the circuit layer 220 is 20 micrometers, the thickness D1 of the reinforcing anti-warping film 230 can be selected from 3 micrometers to 5 micrometers.

[0068] Since the circuit layer 220 typically includes multiple metal layers, and these metal layers have a higher coefficient of thermal expansion and thermal conductivity than the semiconductor substrate 210, increasing the thickness of the circuit layer 220 often leads to uneven thermal stress in the chip 201 during the packaging process due to thermal mismatch. Therefore, the reinforcing and anti-warping film 230 encapsulating the semiconductor substrate 210 and the circuit layer 220 can be appropriately thickened when the thickness of the circuit layer 220 is increased, in order to improve its effect of changing the direction of local mechanical stress release in the chip 201 and increasing the mechanical strength of the chip.

[0069] In one embodiment of this application, the hardened anti-warping film 230 can be a single-layer structure or a composite structure. Specifically, the hardened anti-warping film 230 can be at least one of a nitride layer, a silicide layer, and an oxide layer. Furthermore, the materials and structure for preparing the hardened anti-warping film 230 can be determined based on factors such as the thickness of the circuit layer 220 in the chip 201, the device type of the chip 201, the number of layers in the multilayer chip stacking structure 20, and the specific parameters involved in the packaging process; this application does not limit these factors. For example, as an alternative, the material for preparing the hardened anti-warping film 230 can be silicon nitride, silicon oxide, silicon oxynitride, silicon carbide (SiOC), silicon nitride containing a certain number of hydrogen atoms (SixNyHz), etc.

[0070] Alternatively, in one embodiment of this application, the hardened anti-warping film 230 can be prepared by chemical vapor deposition (CVD). The hardened anti-warping film 230 formed by CVD can have a thinner film thickness and a denser film structure, which is beneficial for changing the release direction of local mechanical stress in the chip, increasing the mechanical strength of the chip, and is suitable for packaging structures of ultra-thin chips such as 3D memory.

[0071] Figure 5 This is a schematic diagram of the distribution of mechanical stress in a chip within a conventional semiconductor packaging structure 60. Figure 6 This is a schematic diagram of the distribution of mechanical stress in a chip within a semiconductor packaging structure 70 according to one embodiment of this application.

[0072] like Figure 5As shown, a conventional semiconductor package structure 60 may include a package substrate and a stack of multiple chips formed thereon, wherein each chip may include a semiconductor substrate 61 and a circuit layer 62 located on the semiconductor substrate 61. When warping or cracking occurs in the conventional semiconductor package structure 60, the chip inside will experience upward bending mechanical stress as indicated by the arrow in the figure. In addition, if the semiconductor substrate 61 and the circuit layer 62 have different material types or structures, the chip may also experience downward bending mechanical stress. Both the downward bending and upward bending mechanical stresses mentioned above prevent the chip from maintaining a flat state, thus making the semiconductor package device prone to failure problems such as breakage or damage.

[0073] like Figure 6 As shown, the semiconductor packaging structure 70 provided in this application may include a packaging substrate and a multilayer chip stack structure formed thereon. The multilayer chip stack structure includes a plurality of chips stacked sequentially. Each chip may include a semiconductor substrate 71, a circuit layer 72 formed on the semiconductor substrate 71, and a reinforcing anti-warping film 73 in a semi-enclosed state. The reinforcing anti-warping film 73 may include two parts, wherein a first part 73-1 covers the bottom surface of the semiconductor substrate 71, and a second part 73-2 covers the side surface of the semiconductor substrate 71 and the side surface of the circuit layer 72. Therefore, when warping or cracks occur in the semiconductor package structure 70, the second part 73-2 of the reinforcing anti-warping film 73 can prevent deformation of the semiconductor substrate 71 and the circuit layer 72. Under the combined force of the first part 73-1 and the second part 73-2, the release direction of the mechanical stress inside the chip can be changed, and the mechanical stress of downward or upward bending can be decomposed into mechanical stress perpendicular to the semiconductor substrate 71 and mechanical stress parallel to the semiconductor substrate 71. Thus, the risk of chip damage or warping and the problem of package device failure can be effectively avoided.

[0074] Figure 7 This is a flowchart of a method for fabricating a semiconductor packaging structure according to one embodiment of this application, 2000.

[0075] like Figure 7 As shown, the method for fabricating a semiconductor packaging structure 2000 may include:

[0076] S11, attaching a multilayer chip stacking structure to a packaging substrate, wherein the multilayer chip stacking structure includes a plurality of chips stacked sequentially, wherein each chip includes a semiconductor substrate, a circuit layer and a hardening and anti-warping film, the semiconductor substrate includes a first surface and a second surface opposite to each other, the circuit layer is formed on the first surface, and the hardening and anti-warping film covers the second surface.

[0077] S12, a molding compound layer for encapsulating a multilayer chip stack structure is formed on the surface of the packaging substrate.

[0078] The following examples illustrate the specific processes of each step in the above-mentioned semiconductor packaging structure fabrication method 2000.

[0079] Step S11

[0080] Specifically, in one embodiment of this application, the specific parameter characteristics of the packaging substrate, such as material, thickness, or size, can be selected according to actual needs; or, according to the specific type of the multilayer chip stacking structure to be carried.

[0081] The packaging substrate may contain conductive lines, and one side of the packaging substrate may have an electrical connector (e.g., a solder ball) that is electrically connected to the conductive lines. The multilayer chip stack structure can be adhered to the other side of the packaging substrate by an adhesive layer, and the adhesive layer is only located within the projection area of ​​the multilayer chip stack structure on the packaging substrate.

[0082] In some implementations, the multilayer chip stacking structure may include multiple chips stacked sequentially on a packaging substrate in a shingled manner. Alternatively, the multiple chips may be stacked one-to-one.

[0083] Furthermore, in some implementations, the multilayer chip stack structure can utilize, for example, wire bonding technology, to electrically connect the pads within each chip to the conductive lines within the package substrate via wire bonding, thereby ensuring the smooth transmission of electrical signals.

[0084] The chip may include a semiconductor substrate, a circuit layer, and a hardening anti-warping film. The semiconductor substrate includes opposing first surfaces, a second surface, and substrate sidewalls connecting the first and second surfaces. The circuit layer is formed on the first surface of the semiconductor substrate and has circuit layer sidewalls.

[0085] In one embodiment of this application, the chip may include a three-dimensional non-volatile memory, wherein the three-dimensional non-volatile memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0086] As an alternative, a reinforcing anti-warping film can be applied to the second surface of the semiconductor substrate. Therefore, when warping or cracks occur in the semiconductor package structure, the reinforcing anti-warping film can prevent deformation of the semiconductor substrate and, based on this, change the direction of stress release within the chip, effectively avoiding the risk of chip breakage or warping and the failure of semiconductor packaged devices.

[0087] Alternatively, the hardening anti-warping film can cover the second surface and side surfaces of the semiconductor substrate, and also cover the side surfaces of the circuit layer. In other words, in this option, the hardening anti-warping film can include two parts, wherein the first part covers the bottom surface of the semiconductor substrate, and the second part covers the side surfaces of the semiconductor substrate and the side surfaces of the circuit layer.

[0088] Therefore, when warping or cracks occur in the semiconductor packaging structure, the second part of the anti-warping film can prevent deformation of the semiconductor substrate and circuit layer due to its fixing effect. Under the combined force of the first and second parts, the release direction of mechanical stress inside the chip can be changed, decomposing the mechanical stress of downward or upward bending into mechanical stress perpendicular to the semiconductor substrate and mechanical stress parallel to the semiconductor substrate. Thus, the risk of chip damage or warping and the failure of semiconductor packaging devices can be effectively avoided.

[0089] In one embodiment of this application, the thickness of the hardening anti-warping film is 1% to 17% of the common thickness of the semiconductor substrate and the circuit layer. Alternatively, when the common thickness of the semiconductor substrate and the circuit layer is 30 micrometers to 50 micrometers, the thickness of the hardening anti-warping film can be 0.5 micrometers to 5 micrometers. In other words, compared with the overall thickness of the chip, the thickness of the hardening anti-warping film is relatively thin, making it more suitable for packaging structures of ultra-thin chips such as 3D memory.

[0090] Furthermore, in one embodiment of this application, while keeping the common thickness of the semiconductor substrate and the circuit layer constant, the thickness of the reinforcing anti-warping film can increase as the thickness of the circuit layer increases. For example, when the common thickness of the semiconductor substrate and the circuit layer is micrometers, when the thickness of the circuit layer is only 5 micrometers, the thickness of the reinforcing anti-warping film can be selected from 0.2 micrometers to 1 micrometer; when the thickness of the circuit layer is 20 micrometers, the thickness of the reinforcing anti-warping film can be selected from 3 micrometers to 5 micrometers.

[0091] Since circuit layers typically consist of multiple metal layers, and metal layers have higher coefficients of thermal expansion and thermal conductivity than the semiconductor substrate, increasing the thickness of the circuit layers often leads to uneven thermal stress caused by thermal mismatch during the chip packaging process, resulting in warping. Therefore, a reinforcing and anti-warping film encapsulating the semiconductor substrate and circuit layers can be appropriately increased in thickness even when the circuit layer thickness is increased, in order to improve its effect of changing the direction of local mechanical stress release in the chip and increasing the mechanical strength of the chip.

[0092] In one embodiment of this application, the hardening anti-warping film can be a single-layer structure or a composite structure. Specifically, the hardening anti-warping film can be at least one of a nitride layer, a silicide layer, and an oxide layer, or any combination thereof. Furthermore, the materials and structure for preparing the hardening anti-warping film can be determined based on factors such as the thickness of the circuit layers in the chip, the device type of the chip, the number of layers in the multilayer chip stacking structure, and the specific parameters involved in the packaging process; this application does not limit these factors. For example, as an alternative, the materials for preparing the hardening anti-warping film can be silicon nitride, silicon oxide, silicon oxynitride, silicon carbide (SiOC), silicon nitride containing a certain number of hydrogen atoms (SixNyHz), etc.

[0093] Alternatively, in one embodiment of this application, a reinforced anti-warping film can be prepared using a chemical vapor deposition (CVD) process. The reinforced anti-warping film formed by CVD can have a thinner film thickness and a denser film structure, which is more conducive to changing the release direction of local mechanical stress in the chip and increasing the mechanical strength of the chip.

[0094] Step S12

[0095] Specifically, in one embodiment of this application, the molding compound layer can be formed from any suitable material, such as a non-conductive polymer. Alternatively, the molding compound layer can be prepared using silicon oxide fillers or resins. Another option is that the molding compound layer may include an epoxy molding compound (EMC). Typically, the molding compound layer and the chip have different coefficients of thermal expansion and thermal conductivity.

[0096] In one embodiment of this application, a molding compound can be injected onto the surface of a packaging substrate using, for example, an injection molding process, to encapsulate a multilayer chip stack structure. Then, a curing process is used to cure the molding compound to form a molding compound layer.

[0097] Since the content described above regarding semiconductor packaging structures can be fully or partially applied to the semiconductor packaging structure fabrication methods described here, related or similar content will not be repeated.

[0098] According to at least one embodiment of the semiconductor packaging structure preparation method provided in this application, by forming a reinforcing and anti-warping film covering the bottom surface of the semiconductor substrate (or covering the bottom surface, side surface and side surface of the semiconductor substrate and the side surface of the circuit layer) in the structure of the chip to be packaged, the release direction of local mechanical stress in the chip can be changed, the mechanical strength of the chip can be increased, and thus the risk of chip cracking, breakage or warping and the problem of semiconductor packaging device failure can be effectively avoided.

[0099] Figure 8This is a flowchart of a method 3000 for preparing a semiconductor packaging structure according to one embodiment of this application.

[0100] like Figure 8 As shown, the method 3000 for fabricating a chip to be packaged for a semiconductor packaging structure may include:

[0101] S21, the wafer is half-cut from the front side of the wafer where the circuit layer is located.

[0102] S22, a temperature-resistant shaping layer is set on the front side of the wafer.

[0103] S23, from the back side of the wafer opposite to the front side, the wafer is thinned to separate the wafer into multiple, independent sub-wafers fixed on a heat-resistant shaping layer.

[0104] S24 forms a reinforced anti-warping film on the surface of the sub-wafer that is not in contact with the heat-resistant shaping layer.

[0105] S25, attach the stencil film to the surface of the reinforced anti-warping film and remove the heat-resistant shaping layer.

[0106] S26, perform dicing to obtain multiple, independent chips to be packaged, wherein the chips to be packaged include sub-wafers and a reinforcing anti-warping film formed on a portion of the surface of the sub-wafers.

[0107] The following will combine Figures 9 to 15 The specific processes of each step in the above-mentioned method 3000 for preparing a chip to be packaged for a semiconductor packaging structure are illustrated with examples.

[0108] Step S21

[0109] Figure 9 This is a top view schematic diagram of a half-cut process performed on the front side 821 of a wafer 82 where a circuit layer is provided, according to one embodiment of this application.

[0110] Specifically, such as Figure 9 As shown, in one embodiment of this application, a dicing device 81 can be used to slit and separate a wafer 82 on which a circuit layer has been formed. Optionally, the wafer 82 can be partially diced from the front side 821 where the circuit layer is formed; in other words, the wafer 82 is not cut through, and a portion of the thickness of the wafer 82 is retained. Alternatively, the dicing device 81 can use a diamond blade for dicing, or it can use a laser for dicing.

[0111] Step S22

[0112] Figure 10This is a top view schematic diagram of a heat-resistant shaping layer 83 provided on the front side 821 of a diced wafer 82 according to one embodiment of this application.

[0113] Specifically, such as Figure 10 As shown, in one embodiment of this application, a temperature-resistant shaping layer 83 can be formed on the front side 821 of wafer 82 using processes such as adhesive or lamination. The temperature-resistant shaping layer 83 formed on the front side 821 of wafer 82 has the characteristics of temperature resistance, shaping, and easy removal. Therefore, it is beneficial to protect and fix the sub-wafer during the subsequent formation of a reinforcement and anti-warping film on the surface of a sub-wafer (formed by dividing wafer 82) that is not in contact with the temperature-resistant shaping layer 83, so as to form a relatively thin reinforcement and anti-warping film that can partially enclose the sub-wafer. Alternatively, the temperature-resistant shaping layer 83 can be a quartz glass layer; however, those skilled in the art should understand that this application does not limit the specific structure and material of the temperature-resistant shaping layer 83, and its specific structural and material characteristic parameters can be set according to relevant parameters during the subsequent formation of the reinforcement and anti-warping film.

[0114] The method for fabricating a chip to be packaged for a semiconductor packaging structure provided in this application first forms a film layer with temperature resistance and shaping characteristics on the front side of the halved wafer (including the semiconductor substrate and circuit layer) before forming the hardening and anti-warping film. This film layer can fix and protect the wafer while making the formed hardening and anti-warping film thinner, which is more suitable for packaging structures of ultra-thin chips such as three-dimensional memory.

[0115] Step S23

[0116] Figure 11 This is a top view of a wafer 82 that has been thinned from the back side 822 of the wafer 82 according to one embodiment of this application. Figure 12 This is a cross-sectional schematic diagram of a thinned wafer 82 forming multiple sub-wafers 85 according to one embodiment of this application.

[0117] Specifically, such as Figure 11 and Figure 12 As shown, in one embodiment of this application, wafer 82 is thinned from the back side 822 opposite to the front side 821 of wafer 82 to separate wafer 82 into multiple, independent sub-wafers 85 fixed on a heat-resistant shaping layer 83.

[0118] In one embodiment of this application, the thinning process may, for example, include: using a thinning processing device 84 to thin the back side 822 of the wafer 82 using processes such as chemical mechanical polishing, acid etching, or polishing to form a thinned back side. Alternatively, the thinning process may also include, for example, thinning the back side 822 of the wafer 82 using at least two thinning processes to form a thinned back side. For example, a first thinning process, such as chemical mechanical polishing, can be performed first, which has a faster thinning rate, followed by a second thinning process, such as acid etching, which has a slower rate but allows for better flatness of the thinned surface.

[0119] The thinning process described above allows the partially cut wafer 82, which retains a portion of its thickness (after half-cutting), to be completely separated into multiple sub-wafers 85, and enables the sub-wafers 85 to achieve a predetermined package thickness. Each sub-wafer 85, fixed on the heat-resistant shaping layer 83, may include a semiconductor substrate 851 and a circuit layer 852 formed thereon.

[0120] Refer again Figure 12 Alternatively, the upper surface 01 of multiple sub-wafers 85 can be fixed on the temperature-resistant shaping layer 83, while the lower surface 03 (the surface away from the circuit layer) opposite to the upper surface 01 and the side surface 02 connecting the upper surface 01 and the lower surface 03 are not in contact with the temperature-resistant shaping layer 83.

[0121] Step S24

[0122] Figure 13 This is a schematic cross-sectional view of a structure formed after a reinforcing anti-warping film 86 is formed on the surface of a plurality of sub-wafers 85 according to one embodiment of this application.

[0123] Specifically, such as Figure 12 and Figure 13 As shown, a reinforcing anti-warping film 86 can be formed on the surface of the sub-wafer 85 that is not in contact with the heat-resistant shaping layer 83. Alternatively, the reinforcing anti-warping film 86 can be formed on the lower surface 03 and the side surface 02 of the sub-wafer 85. In other words, the reinforcing anti-warping film 86 can wrap the bottom surface (the surface away from the circuit layer 852) and the side surface of the semiconductor substrate 851 in the sub-wafer 85, and wrap the side surface of the circuit layer 852 in the sub-wafer 85. After the reinforcing anti-warping film 86 is formed on part of the surface of the sub-wafer 85, the chip to be packaged is formed.

[0124] In one embodiment of this application, the chip to be packaged includes a three-dimensional non-volatile memory, wherein the three-dimensional non-volatile memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0125] The method for fabricating a chip to be packaged for a semiconductor packaging structure provided in this application can change the release direction of local mechanical stress in the chip to be packaged and increase the mechanical strength of the chip by forming a reinforcing and anti-warping film covering part of the surface of the sub-wafer in the structure of the chip to be packaged. This can effectively avoid the risk of cracks, damage or warping of the chip to be packaged and the problem of failure of semiconductor packaging devices.

[0126] Furthermore, in one embodiment of this application, a chemical vapor deposition (CVD) process can be used to form a reinforced anti-warping film 86 on the surface of the sub-wafer 85 that is not in contact with the temperature-resistant shaping layer 83. The reinforced anti-warping film 86 formed by the chemical vapor deposition process can have a thinner film thickness and a denser film structure, which is beneficial for changing the release direction of local mechanical stress in the chip, increasing the mechanical strength of the chip, and is suitable for packaging structures of ultra-thin chips such as 3D memory.

[0127] Specifically, the reinforced anti-warping film 86 can be prepared using chemical vapor deposition processes such as plasma-enhanced chemical vapor deposition (PECVD). Alternatively, the process temperature of the chemical vapor deposition process can be between 300°C and 500°C.

[0128] As an alternative, the materials used to prepare the reinforced anti-warping film 86 can be silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide (SiOC), silicon nitride containing a certain number of hydrogen atoms (SixNyHz), etc.

[0129] Taking the preparation of a reinforced anti-warping film 86 using silicon nitride (SixNyHz) containing a certain amount of hydrogen atoms as an example, the Si / N ratio in normal silicon nitride (SixNy) is 0.75. However, the stoichiometry of silicon nitride deposited by PECVD varies with different processes. Therefore, in addition to Si and N, the silicon nitride formed by PECVD deposition also contains a certain proportion of hydrogen atoms. In other words, the silicon nitride formed by PECVD deposition is silicon nitride (SixNyHz), which has characteristics such as dense structure, high hardness, and high dielectric strength. Furthermore, by controlling the above process parameters, the thickness of the reinforced anti-warping film 86 can also be controlled, so that the formed reinforced anti-warping film 86 not only has a denser film structure but also a thinner film thickness.

[0130] Step S25

[0131] Figure 14 This is a schematic diagram of a scribe film 87 being pasted onto a portion of the surface of a reinforcing anti-warping film 86 according to one embodiment of this application. Figure 15 This is a schematic diagram of removing the heat-resistant shaping layer 83 in a wafer 82 according to one embodiment of this application.

[0132] Specifically, such as Figures 12 to 15As shown, roller 88 can be pressed against a portion of the surface of the reinforcing anti-warping film 86 to adhere the dicing film 87 to that portion of the surface of the reinforcing anti-warping film 86. Roller 88 can move and roll in a predetermined direction. The dicing film 87 can be a cut film or a DAF film, etc., and this application does not limit it.

[0133] Alternatively, the surface of the reinforcing anti-warping film 86 on which the dicing film 87 is attached can be the surface directly opposite the lower surface 03 of the sub-wafer 85.

[0134] Furthermore, after forming the dicing film 87, the temperature-resistant shaping layer 83 located on the upper surface 01 of the sub-wafer 85 can be removed. The temperature-resistant shaping layer 83 is characterized by its temperature resistance, shaping properties, and ease of removal, and can be removed after forming the reinforcing and anti-warping film 86. In one embodiment of this application, a decuring process such as ultraviolet light (UV), heating, or laser can be used to remove the temperature-resistant shaping layer 83. This application does not limit the process for removing the temperature-resistant shaping layer 83.

[0135] Step S26

[0136] The method 3000 for preparing a chip to be packaged for a semiconductor packaging structure provided in this application further includes step S26: performing a dicing process to obtain multiple, independent chips to be packaged, wherein the chips to be packaged include a sub-wafer and a reinforcing anti-warping film formed on a portion of the surface of the sub-wafer.

[0137] In one embodiment of this application, the dicing film adhered to a portion of the surface of the reinforcing anti-warping film is a thin film with an adhesive layer, which can fix multiple independent chips to be packaged. However, since the spacing between these individual chips to be packaged is very small, this spacing can be further increased to facilitate subsequent chip pickup.

[0138] As an alternative, cold ablation can be used to increase the spacing between individual chips to be packaged. In cold ablation, the diced wafer is placed in a low-temperature environment, typically below room temperature, which causes the dicing film to be stressed outward along the wafer radius, resulting in stretching deformation of the dicing film and increasing the spacing between the chips to be packaged.

[0139] Furthermore, since the content described above regarding semiconductor packaging structures and fabrication methods can be fully or partially applied to the fabrication methods of the chips to be packaged for semiconductor packaging structures described herein, related or similar content will not be repeated.

[0140] The method for fabricating a chip to be packaged for a semiconductor packaging structure provided in this application can change the release direction of local mechanical stress in the chip to be packaged and increase the mechanical strength of the chip by forming a reinforcing and anti-warping film covering part of the surface of the sub-wafer in the structure of the chip to be packaged. This can effectively avoid the risk of cracks, damage or warping of the chip to be packaged and the problem of failure of semiconductor packaging devices.

[0141] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor package structure, comprising: Packaging substrate; A multilayer chip stacking structure is attached to the packaging substrate and includes a plurality of chips stacked sequentially. as well as A molding compound layer is formed on the surface of the packaging substrate and encapsulates the multilayer chip stack structure. The chip is characterized in that it comprises: A semiconductor substrate includes opposing first surfaces, second surfaces, and substrate sidewalls connecting the first surface and the second surface; A circuit layer is formed on the first surface; and A reinforced anti-warping film is used to cover the second surface, the side surface of the substrate, and the side surface of the circuit layer.

2. The semiconductor packaging structure according to claim 1, characterized in that, The thickness of the reinforcing anti-warping film is 1% to 17% of the combined thickness of the semiconductor substrate and the circuit layer.

3. The semiconductor packaging structure according to claim 1, characterized in that, The combined thickness of the semiconductor substrate and the circuit layer is 30 to 50 micrometers, and the thickness of the reinforcing anti-warping film is 0.5 to 5 micrometers.

4. The semiconductor packaging structure according to claim 3, characterized in that, With the common thickness remaining constant, the thickness of the reinforcing anti-warping film increases as the thickness of the circuit layer increases.

5. The semiconductor packaging structure according to claim 1, characterized in that, The reinforced anti-warping membrane is a single-layer structure or a composite structure.

6. The semiconductor packaging structure according to claim 1, characterized in that, The reinforced anti-warping film is at least one of a nitride layer, a silicide layer, and an oxide layer.

7. The semiconductor packaging structure according to claim 1, characterized in that, The reinforced anti-warping film is prepared by chemical vapor deposition.

8. The semiconductor packaging structure according to claim 1, characterized in that, The chip includes a three-dimensional non-volatile memory, wherein the three-dimensional non-volatile memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

9. A method for fabricating a semiconductor packaging structure, characterized in that, include: A multilayer chip stack structure is attached to a packaging substrate, wherein the multilayer chip stack structure comprises a plurality of chips stacked sequentially. as well as A molding compound layer for encapsulating the multilayer chip stack structure is formed on the surface of the packaging substrate. The chip includes: A semiconductor substrate includes opposing first surfaces, second surfaces, and substrate sidewalls connecting the first surface and the second surface; A circuit layer is formed on the first surface; and A reinforced anti-warping film is used to cover the second surface, the side surface of the substrate, and the side surface of the circuit layer.

10. The method according to claim 9, characterized in that, The thickness of the reinforcing anti-warping film is 1% to 17% of the combined thickness of the semiconductor substrate and the circuit layer.

11. The method according to claim 9, characterized in that, The combined thickness of the semiconductor substrate and the circuit layer is 30 to 50 micrometers, and the thickness of the reinforcing anti-warping film is 0.5 to 5 micrometers.

12. The method according to claim 11, characterized in that, With the common thickness remaining constant, the thickness of the reinforcing anti-warping film is set to increase as the thickness of the circuit layer increases.

13. The method according to claim 9, characterized in that, The reinforced anti-warping membrane can be configured as a single-layer structure or a composite structure.

14. The method according to claim 9, characterized in that, The reinforced anti-warping film is at least one of a nitride layer, a silicide layer, and an oxide layer.

15. The method according to claim 9, characterized in that, The reinforced anti-warping film was prepared using a chemical vapor deposition process.

16. The method according to claim 9, characterized in that, The chip includes a three-dimensional non-volatile memory, wherein the three-dimensional non-volatile memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

17. A method for fabricating a chip to be packaged for a semiconductor packaging structure, characterized in that, include: The wafer is half-cut from the front side of the wafer where the circuit layer is provided; A heat-resistant shaping layer is provided on the front side; The wafer is thinned from the back side opposite to the front side to separate the wafer into multiple, independent sub-wafers fixed on the heat-resistant shaping layer; A reinforcing anti-warping film is formed on the surface of the sub-wafer that is not in contact with the heat-resistant shaping layer; A scribe film is pasted onto a portion of the surface of the reinforced anti-warping film, and the heat-resistant shaping layer is removed; as well as The process involves dicing to obtain multiple, independent chips to be packaged, wherein each chip includes a sub-wafer and a reinforcing anti-warping film formed on a portion of the surface of the sub-wafer. The sub-wafer includes an upper surface and a lower surface opposite to each other, and a side surface of the sub-wafer connecting the upper surface and the lower surface. The upper surface of the sub-wafer is fixed on the heat-resistant shaping layer. Forming a reinforcing and anti-warping film on the surface of the sub-wafer that is not in contact with the heat-resistant shaping layer includes forming the reinforcing and anti-warping film on the lower surface of the sub-wafer and the side surface of the sub-wafer.

18. The method according to claim 17, characterized in that, Forming a reinforcing anti-warping film on the surface of the sub-wafer that is not in contact with the heat-resistant shaping layer includes: The reinforced anti-warping film is formed on the surface of the sub-wafer that is not in contact with the temperature-resistant shaping layer using a chemical vapor deposition process.

19. The method according to claim 17, characterized in that, The heat-resistant shaping layer is a quartz glass layer.

20. The method according to claim 17, characterized in that, The heat-resistant shaping layer on the front side includes: The heat-resistant shaping layer is applied to the front surface using an adhesive or lamination process.

21. The method according to claim 17, characterized in that, The chip to be packaged includes a three-dimensional non-volatile memory, wherein the three-dimensional non-volatile memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

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