Three-dimensional memory and methods of manufacturing the same

Abstract

The present application provides a three-dimensional memory device and a manufacturing method thereof. The three-dimensional memory device comprises: a stacked layer located on a substrate; and a gate slit structure extending through the stacked layer in a first direction to divide the stacked layer into a plurality of finger-shaped regions. The gate slit structure comprises a first gate slit structure and a second gate slit structure, wherein the first gate slit structure extends continuously, and a plurality of second gate slit structures are segmented along the first direction between adjacent first gate slit structures, and the spacing between adjacent second gate slit structures is greater than the spacing between a first gate slit structure and its adjacent second gate slit structure. The present application can increase the process window at the ends of the second gate slit structure, thereby improving device yield.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology. Specifically, the present application relates to a three-dimensional memory and a manufacturing method thereof. BACKGROUND

[0002] Three-dimensional memory architecture can solve the density limitation of planar memory. For three-dimensional non-volatile memory (3D NAND), a stack layer is formed by alternately stacking multiple layers of gate conductor layers and dielectric layers. Generally, the stack layer is divided into multiple memory areas by forming gate slit structures in the stack layer. Some gate slit structures can be disconnected at a predetermined area to form a notch (H-Cut) so that the gate conductor layers located in different memory areas are electrically connected at the notch.

[0003] It should be appreciated that the background section is intended to provide useful background information for understanding the technology and does not necessarily constitute an acknowledgement or any form of suggestion that any of the preceding material constitutes prior art. SUMMARY

[0004] In one aspect of the present application, a three-dimensional memory is provided, comprising: a stack layer located on a substrate; a gate slit structure passing through the stack layer, the gate slit structure extending in a first direction parallel to the substrate to divide the stack layer into multiple finger areas; wherein the gate slit structure comprises first gate slit structures and second gate slit structures, the first gate slit structures continuously extending in the first direction, and the second gate slit structures being segmentally arranged between adjacent first gate slit structures; and a memory channel structure passing through the stack layer, the finger areas comprising multiple rows of the memory channel structures arranged along the first direction, any second gate slit structure and a row of the memory channel structures adjacent thereto having a first preset interval, and any first gate slit structure and a row of the memory channel structures adjacent thereto having a second preset interval, wherein the first preset interval is greater than the second preset interval.

[0005] In one embodiment of the present application, in a second direction parallel to the substrate and intersecting the first direction, any adjacent second gate slit structure has a third preset interval, and any first gate slit structure and the second gate slit structure adjacent thereto has a fourth preset interval, wherein the third preset interval is greater than the fourth preset interval.

[0006] In one embodiment of the present application, the gate slit structure comprises an isolation layer and a conductive channel located on the isolation layer.

[0007] In an embodiment of the application, the stack of layers includes a gate conductor layer, the gate conductor layer of the plurality of the finger regions is electrically connected by a portion between the segmented second gate slit structures.

[0008] In an embodiment of the application, each of the second gate slit structures includes an end portion and an extension portion, the extension portion extends along the first direction.

[0009] In an embodiment of the application, the end portion has a profile shape of a portion of a circle or a portion of an ellipse.

[0010] In an embodiment of the application, any of the end portions has a first preset minimum distance to an adjacent row of the memory channel structures, wherein the first preset minimum distance is greater than or equal to the second preset distance.

[0011] In an embodiment of the application, the first preset minimum distance is in a range of 100 nm to 200 nm.

[0012] In an embodiment of the application, the three-dimensional memory further includes dummy channel structures passing through the stack of layers, the finger regions include a plurality of rows of the dummy channel structures arranged along the first direction, any of the second gate slit structures has a fifth preset distance to an adjacent row of the dummy channel structures, any of the first gate slit structures has a sixth preset distance to an adjacent row of the dummy channel structures, wherein the fifth preset distance is greater than the sixth preset distance.

[0013] In an embodiment of the application, any of the end portions has a second preset minimum distance to an adjacent row of the dummy channel structures, wherein the second preset minimum distance is greater than or equal to the sixth preset distance.

[0014] In another aspect of the present application, a three-dimensional memory manufacturing method is provided, the method comprising: forming a stacking structure on a substrate; forming a plurality of storage channel structures through the stacking structure; and forming a plurality of gate slit structures extending in a first direction parallel to the substrate through the stacking structure, which divides the stacking structure into a plurality of finger-shaped areas, each of the finger-shaped areas comprising a plurality of rows of the storage channel structures arranged along the first direction; the gate slit structures comprising a first gate slit structure and a second gate slit structure, the first gate slit structure extending continuously in the first direction, the second gate slit structure being segmentedly arranged between adjacent first gate slit structures; wherein any second gate slit structure has a first preset spacing with an adjacent row of the storage channel structures, and any first gate slit structure has a second preset spacing with an adjacent row of the storage channel structures, and the first preset spacing is greater than the second preset spacing.

[0015] In one embodiment of the present application, in a second direction parallel to the substrate and intersecting the first direction, any adjacent second gate slit structures have a third preset spacing, and any first gate slit structure and its adjacent second gate slit structure have a fourth preset spacing, wherein the third preset spacing is greater than the fourth preset spacing.

[0016] In one embodiment of the present application, forming the gate slit structure includes:

[0017] An isolation layer is formed in a gate slot passing through the stack structure; and a conductive channel is formed on the isolation layer.

[0018] In one embodiment of the present application, each section of the second gate slit structure includes an end portion and an extension portion, and the extension portion extends along the first direction.

[0019] In one embodiment of the present application, the contour shape of the end portion is a part of a circle or a part of an ellipse.

[0020] In one embodiment of the present application, a row of the storage channel structures adjacent to any of the end portions has a first preset shortest distance, wherein the first preset shortest distance is greater than or equal to the second preset distance.

[0021] In one embodiment of the present application, the manufacturing method further comprises: forming a plurality of dummy channel structures through the stack structure, each of the finger-shaped regions comprises a plurality of rows of the dummy channel structures arranged along the first direction, any of the second gate slit structures and a row of the dummy channel structures adjacent thereto have a fifth preset interval, any of the first gate slit structures and a row of the dummy channel structures adjacent thereto have a sixth preset interval, wherein the fifth preset interval is greater than the sixth preset interval.

[0022] In one embodiment of the present application, any of the end portions and a row of the dummy channel structures adjacent thereto have a second preset minimum interval, wherein the second preset minimum interval is greater than or equal to the sixth preset interval.

[0023] The present application increases the process window at the end portion of the second gate slit structure by setting the interval between the second gate slit structure and a row of the storage channel structures adjacent thereto to be greater than the interval between the first gate slit structure and a row of the storage channel structures adjacent thereto, thereby avoiding the process operation at the end portion of the second gate slit structure from damaging the adjacent channel structures, and improving the device yield. BRIEF DESCRIPTION OF DRAWINGS

[0024] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings. In the drawings,

[0025] Figure 1 A partial enlarged schematic view of a semiconductor structure after forming a gate slit according to some embodiments of the present application is shown.

[0026] Figure 2 A partial schematic view of a three-dimensional memory 100 according to some embodiments of the present application is shown.

[0027] Figure 3 A top schematic view of a core region of a three-dimensional memory 100 according to some embodiments of the present application is shown.

[0028] Figure 4 A flowchart of a three-dimensional memory manufacturing method 10 according to some embodiments of the present application is shown.

[0029] Figures 5a to 5j Schematic views of various stages of a three-dimensional memory manufacturing method according to some embodiments of the present application are shown. DETAILED DESCRIPTION

[0030] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the drawings. It is to be noted that these detailed descriptions are merely descriptive of exemplary embodiments of the present application and are not intended in any way to limit the scope of the present application. Throughout the specification, like drawing reference numerals refer to like elements.

[0031] Note that references to "one embodiment," "an embodiment," "example embodiments," "some embodiments," etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily indicative of a singularly and homogenously grouped embodiment. Further, where a particular feature, structure, or characteristic is described in connection with an embodiment, it will be within the knowledge of those skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0032] Generally, the terminology can be understood at least in part from usage of the singular throughout the present description and the claims. For example, at least depending on the context, the terms "one," "a," or "an" as used herein can be taken to mean one or more than one, and the singular can also include the plural unless it is explicitly stated otherwise. Similarly, "another" can mean at least two or more. As used herein, the term "including" and its various forms can mean "including, but not limited to," unless expressly specified otherwise. As used herein, the term "based on" can mean "based, at least in part, on," unless expressly specified otherwise.

[0033] It will be readily understood that the terms "on," "above," and "upper" as used herein encompass the meanings set forth in the broadest sense, such that "on" means not only "directly on" but also "on" with intervening features or layers therebetween, and "above" or "upper" means not only "above" or "upper" but also can include "above" or "upper" with no intervening features or layers therebetween (i.e., directly on).

[0034] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein can likewise be interpreted accordingly.

[0035] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire upper or lower structure, or can have a smaller extent than the lower or upper structure. Further, a layer can be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any pair of horizontal planes between or at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, thereabove, and / or therebelow. A layer can include multiple layers.

[0036] In the drawings, the thicknesses of components, sizes, and shapes can have been slightly adjusted for ease of illustration. The drawings are merely schematic and are not drawn to scale. For example, the terms "approximately," "about," and similar terms as used herein are used as terms of approximation and not as terms of degree, unless otherwise indicated, and are meant to allow for a reasonable range of variability in measurement or calculation values due to inherent deviations that would be recognized by one of ordinary skill in the art.

[0037] It should also be understood that the terms "comprise", "comprising", "having", "include", "including", "contain", "containing", "involving", and / or "including" when used in this specification, specify the presence of stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or groups thereof. Furthermore, as used herein, expressions such as "at least one of" when preceding the list of two or more members, denote the least one of the members but also the possibility of more than one of the members. Moreover, when describing the embodiments of the present application, the use of "can" means "one or more embodiments of the present application." Also, the use of the term "exemplary" is intended to present an example or an illustration.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and not

[0039] Figure 1 FIG. 1 is a schematic diagram of a semiconductor structure according to some embodiments of the present application. FIG. 2 is a schematic diagram of a semiconductor structure according to some embodiments of the present application. Figure 1As shown, in some embodiments, the gate slit 102 includes a first gate slit 1021 continuously extending and a second gate slit 1022 discontinuously extending, where the second gate slit 1022 can be discontinuous at multiple locations and form notches. In some examples, the notches can be formed by an etching process. The inventors have found that due to the direction and selectivity difference of the etching, the second gate slit 1022 at the notches can form a protruding end portion 1023 and an extension portion 1024 connected to the end portion 1023, and in the Y direction, the cross-sectional size of the end portion 1023 is larger than that of the extension portion 1024. For example, the end portion 1023 can be a part of a circle or a part of an ellipse, and the circular arc of the end portion 1023 protrudes towards the portion between each segment of the second gate slit structure 1032.

[0040] The gate slit is usually equidistant at the beginning of the design, for example, when the second gate slit 1022 is formed by photolithography, the design size of each segment of the second gate slit 1022 on the mask in the Y direction is equal. Since the first gate slit 1021 continuously extends, the distance d2 between the first gate slit 1021 and the adjacent row of channel structures 110 remains uniform. However, the second gate slit 1022 has a protruding end portion 1023, which causes the distance between the end portion 1023 and the extension portion 1024 and the adjacent channel structure 110 to be non-uniform, and the distance d1 between the end portion 1023 and the adjacent channel structure 110 is smaller than d2, and d1 can be 20-30 nm smaller than d2. Therefore, when the second gate slit 1022 performs a deposition-etching process, the channel structure 110 at the smaller distance is easily damaged, leading to erasure and programming failure, thereby reducing product yield.

[0041] The present application provides a three-dimensional memory and a manufacturing method thereof to solve the above problems. Figure 2 For the three-dimensional memory 100 according to the embodiments of the present application, for example, the three-dimensional memory 100 can be a 3D NAND memory, and the three-dimensional memory 100 can include a substrate 101, a stack layer 120 on the substrate, a plurality of storage channel structures 110 passing through the stack layer 120, and a plurality of gate slit structures 103 passing through the stack layer 120. In some examples, the storage channel structures 110 and the gate slit structures 103 can extend into the substrate 101.

[0042] In some embodiments, the substrate 101 can have opposite first and second surfaces, and the top surface of the substrate can be either the first surface or the second surface, with the "top surface" denoting the surface in contact with the stack of layers 120. A first direction in or parallel to the top surface of the substrate denotes the X direction, and a second direction in or parallel to the top surface of the substrate denotes the Y direction, with the first and second directions intersecting, and in some examples, the first and second directions can be perpendicular or approximately perpendicular. A symbol near the letter "X" and showing a combination of a circle and a cross denotes that the X direction in the figure points inward with respect to the drawing page of the figure. A third direction perpendicular to the top surface of the substrate denotes the Z direction.

[0043] The substrate 101 can be, for example, a composite substrate. The material of fabrication of the substrate 101 can be selected from any suitable semiconductor material, such as monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or a group III-V compound such as gallium arsenide, etc.

[0044] In some embodiments, the stack of layers 120 includes a plurality of insulating layers 122 and a plurality of gate conductor layers 121 stacked alternately, and the number of layers of the stack of layers 120 can increase in the Z direction along the top surface of the substrate 101. The insulating layer 122 and the adjacent gate conductor layer 121 can form an insulating layer / gate conductor layer pair, and in some examples, each pair can have the same thickness, and in other examples, some pairs can have different thicknesses. The number of pairs can be selected according to various application scenarios. For example, the number of pairs can be 32, 64, 96, 128, 160, 192, 224, 256, or more.

[0045] In some examples, the gate conductor layer 121 includes a conductive material including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. The gate electrode of the gate conductor layer 121 can extend laterally as a word line.

[0046] In some examples, the insulating material of the insulating layer 122 includes silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric material, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitride and silicates thereof, and organic insulating material, commonly referred to as high dielectric constant (high-k) dielectric oxide.

[0047] In some implementations, the stack of layers 120 can include a core region and a step region located on both sides of the core region or between adjacent core regions. Figure 2(not shown) can be disposed through the stack 120 in the core region. In some examples, the three-dimensional memory 100 can also include dummy channel structures (not shown) that do not have storage functionality, e.g., a plurality of dummy channel structures can be disposed through the stack 120 in the step region and / or portions of the core region proximate to the step region.

[0048] In some embodiments, the storage channel structure 110 can include a storage film (not shown) and a channel layer (not shown), the storage film can include a tunneling layer (not shown), a storage layer (not shown), and a blocking layer (not shown). In some examples, the storage channel structure 110 can have a columnar (e.g., cylindrical) profile shape, the channel layer, the tunneling layer, the storage layer, and the blocking layer can be disposed radially from the center of the column toward the outer surface in that order.

[0049] In some examples, the tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the storage film can be a composite layer including silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0050] In some examples, the material of the channel layer can include silicon, e.g., amorphous silicon, polysilicon, or single-crystal silicon. As an option, the remaining space of the storage channel structure 110 can be partially or completely filled with a dielectric material including, e.g., silicon oxide, or an air gap.

[0051] In some embodiments, the gate slit structure 103 can vertically pass through the stack 120 and extend along the X-direction to divide the stack 120 into a plurality of finger regions, the gate slit structure 103 includes an isolation layer 140 covering the inner wall of the gate slit structure 103 and a conductive via 130 on the isolation layer 140, the conductive via 130 can serve as an outgoing channel for a common source line electrical connection, the isolation layer 140 can be used to electrically isolate the conductive via 130 from the gate conductor layer 121. In some examples, the material of the conductive via 130 includes, but is not limited to, titanium nitride and / or Ti and / or W, the material of the isolation layer 140 includes, but is not limited to, silicon oxide.

[0052] Figure 3 is a top-down schematic view of a core region of the three-dimensional memory 100. As Figure 3 shown, in some embodiments, the gate slit structure (e.g., Figure 2The illustrated gate slit structure 103 includes a plurality of first gate slit structures 1031 (e.g., first gate slit structures 1031a, 1031b, and 1031c) and a second gate slit structure 1032. The plurality of first gate slit structures 1031 extend continuously along the X-direction and divide the three-dimensional memory 100 into a plurality of memory blocks (e.g., memory block a and memory block b). In some examples, the first gate slit structure 1031 may extend continuously along the X-direction in a step region. In some embodiments, the plurality of second gate slit structures 1032 (e.g., second gate slit structure 1032a and second gate slit structure 1032b) may be segmented along the X-direction between adjacent first gate slit structures 1031 to further divide the memory blocks into a plurality of finger-shaped regions.

[0053] In some embodiments, multiple rows of storage channel structures 110 may be provided in each finger region of the core area. The portion between each segment of the second gate slit structure 1032 electrically connects the gate conductor layer 121 of the multiple finger regions. The term "row" as used herein may be parallel to the X-direction, and the arrangement direction of "multiple rows" may be parallel to the Y-direction.

[0054] In some examples, multiple rows of dummy channel structures may be provided in each finger region of the step region.

[0055] like Figure 3 As shown, the first gate slit structure 1031a and the first gate slit structure 1031b define a memory block a, and the first gate slit structure 1031b and the first gate slit structure 1031c define a memory block b. For example, the second gate slit structure 1032a and the second gate slit structure 1032b may be segmented along the X direction between the first gate slit structure 1031a and the first gate slit structure 1031b, further dividing the memory block a into three finger-shaped regions (f1, f2, and f3). In some examples, the second gate slit structure 1032a may be disconnected at predetermined regions along the X direction to form multiple segments, such as segment 1032a-1. The second gate slit structure 1032b may be disconnected at the same predetermined region to form segments corresponding to the second gate slit structure 1032a.

[0056] In some examples, the second gate slit structure 1032 may include an end portion (not shown) proximal to the notch and an extension portion (not shown) connected to the end portion and extending in the X direction. As an example, in the Y direction, the cross-sectional dimensions of the end portion of the second gate slit structure 1032 are greater than the cross-sectional dimensions of the extension portion. For example, the end portion of the second gate slit structure 1032 may be a portion of a circle or a portion of an ellipse, wherein the arc of the circle or ellipse protrudes toward the portion between each segment of the second gate slit structure 1032.

[0057] Reference againFigure 3 In some embodiments, the spacing between any second gate slit structure 1032 and a row of storage channel structures 110 adjacent to it is W1, and the spacing between any first gate slit structure 1031 and a row of storage channel structures 110 adjacent to it is W2, where W1 is greater than W2, thereby increasing the spacing between the end of the second gate slit structure 1032 and a row of storage channel structures 110 adjacent to it, and thereby increasing the process window at the end of the second gate slit structure 1032, reducing damage to the storage channel structure, and improving the device yield.

[0058] In some examples, the first preset shortest spacing between the end of the second gate slit structure 1032 and a row of storage channel structures 110 adjacent thereto may be equal to W2; illustratively, the first preset shortest spacing may range from 100nm to 200nm. Alternatively, the first preset shortest spacing may also range from 150nm to 180nm.

[0059] like Figure 3 As shown, as an example, in the Y direction, the spacing between the second gate slit structure 1032a and its adjacent second gate slit structure 1032b is W3, and the spacing between the first gate slit structure 1031a and its adjacent second gate slit structure 1032a is W4. W3 may be greater than W4. To adjust the spacing W1 to be greater than W2, auxiliary adjustment can be made by adjusting the spacing between W3 and W4, leaving more adjustment space for W1 and W2, thereby optimizing the overall structure of the three-dimensional memory.

[0060] In some examples, a distance between any second gate slit structure 1032 and an adjacent row of dummy channel structures may be greater than a distance between any first gate slit structure 1031 and an adjacent row of dummy channel structures.

[0061] In some embodiments, the second preset shortest distance between an end of any second gate slit structure 1032 and an adjacent row of dummy channels may be greater than or equal to the distance between any first gate slit structure 1031 and an adjacent row of dummy channels.

[0062] It should be noted that "the pitch of any adjacent second gate slit structure 1032 is W3" described herein can mean "the vertical distance between the extensions of any adjacent second gate slit structure 1032 is W3"; "the pitch of any first gate slit structure 1031 and its adjacent second gate slit structure 1032 is W4" can mean "the vertical distance between the extensions of any first gate slit structure 1031 and its adjacent second gate slit structure 1032 is W4; "the pitch of any second gate slit structure 1032 and its adjacent row of storage channel structures 110 is W2" can mean "the vertical distance between the extensions of any second gate slit structure 1032 and its adjacent row of storage channel structures 110 is W2".

[0063] It should be understood by those skilled in the art that the cross-sectional dimension (Y direction) of the end portion of the second gate slit structure 1032 at any point in the Z direction can not be the same, therefore, the "first preset minimum distance" in the "the minimum distance between the end portion of any second gate slit structure 1032 and its adjacent row of storage channel structures 110" described in the present application can mean the minimum distance between the end portion of the second gate slit structure 1032 at the point where the cross-sectional dimension (Y direction) in the Z direction is the largest and its adjacent row of storage channel structures 110. The explanation of "the second preset minimum distance between the end portion of any second gate slit structure 1032 and its adjacent row of dummy channel structures" can refer to the description above. In an embodiment of the present application, the size of the head portion of the extension close to the end portion of the second gate slit structure 1032 can be smaller than the size of the tail portion of the extension away from the end portion, and the tail portion can extend in the X direction to optimize the shape of the gate slit structure and further improve the uniformity of the thickness of the isolation layer 140.

[0064] The embodiments of the present application also provide a three-dimensional memory manufacturing method, Figure 4 A flowchart of a three-dimensional memory manufacturing method 10 according to an embodiment of the present application is shown. As shown in the figure, Figure 4 The manufacturing method includes:

[0065] S10: forming a stack structure on a substrate;

[0066] S20: forming a plurality of storage channel structures through the stack structure;

[0067] S30: forming a plurality of gate slit structures extending in a first direction parallel to the substrate through the stacked structure, dividing the stacked structure into a plurality of finger-shaped regions, each of the finger-shaped regions including a plurality of rows of the storage channel structures arranged along the first direction; the gate slit structures including a first gate slit structure and a second gate slit structure, the first gate slit structure extending continuously in the first direction, and the second gate slit structure being segmented and arranged between adjacent first gate slit structures;

[0068] The second gate slit structure and an adjacent row of storage channel structures have a first preset distance, the first gate slit structure and an adjacent row of storage channel structures have a second preset distance, and the first preset distance is greater than the second preset distance.

[0069] The following will refer to Figures 5a-5j The schematic diagram of each stage of the three-dimensional memory manufacturing method shown in FIG. 1 describes the above steps S1-S3 respectively, wherein: Figures 5a-5j The diagrams shown in the figure are cross-sectional views of a schematic structure of a three-dimensional memory device formed after each process step. When describing the embodiments of the present application in detail, for ease of explanation, the cross-sectional views of the device structure may be partially enlarged and not in accordance with general scale. Furthermore, the diagrams are merely illustrative and should not limit the scope of protection of the present application. Furthermore, in actual production, a three-dimensional spatial scale of length, width, and depth should be included. It should be understood that the operations shown in the method are not exhaustive, and other operations may be performed before, after, or between any of the operations described.

[0070] Reference Figure 4 The manufacturing method 10 begins with operation S10, where a stacked structure may be formed on a substrate. Figure 5a As shown, multiple insulating layers 122 and multiple sacrificial layers 123 can be alternately deposited on the substrate 101 to form a stacked structure 170. The stacked structure 170 can be formed by using one or more film deposition processes including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0071] The etching selectivity of the sacrificial layer 123 to the insulating layer 122 is high in the same etching process, so as to ensure that the insulating layer 122 is hardly removed when the sacrificial layer 123 is removed subsequently. The insulating layer 122 and the adjacent sacrificial layer 123 form an insulating layer / sacrificial layer pair. Each pair can be at a different height relative to a reference surface (e.g., a top surface of the substrate). In embodiments of the present application, each pair can have the same thickness, and in other embodiments of the present application, some pairs can have different thicknesses. The number of pairs can be selected according to various application scenarios. For example, the number of pairs can be 32, 64, 96, 128, 160, 192, 224, 256, or more.

[0072] Referring back to Figure 4 , the operation proceeds to S20, a plurality of memory channel structures can be formed through the stack structure. The stack structure 170 can include a core region and a step region (not shown in the figure) located on both sides of the core region. In some embodiments, a plurality of memory channel structures with memory functions can be formed through the stack structure in the core region. In some examples, dummy channel structures through the stack structure can also be formed in the step region. In some examples, dummy channel structures through the stack structure can also be formed in the core region.

[0073] As shown in Figure 5a , in some embodiments, a plurality of memory channel structures 110 can be formed vertically or substantially vertically through the stack structure 170. For example, a channel hole can be formed through the stack structure 170, and the vertical cross-sectional shape of the channel hole can include, for example, a cylindrical shape, and then a memory film and a channel layer can be formed in the center of the cylindrical shape in sequence along the sidewall of the channel hole. In some examples, the memory film along the sidewall of the channel hole can include a tunneling layer, a storage layer, and a barrier layer (not shown). Figure 5a In some examples, the memory film and the channel layer can be formed by using one or more film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0074] It should also be noted that, for the sake of clarity and conciseness of the present application, only a single sub-stack structure is taken as an example in the stack structure 170 in this paper, and those skilled in the art should understand that the stack structure 170 can also include a plurality of sub-stack structures, that is, the stack structure 170 can also be formed by a plurality of sub-stack structures stacked in sequence.

[0075] Referring back to Figure 4 , the operation proceeds to S30, a plurality of gate slit structures extending in a first direction parallel to the substrate can be formed through the stack structure.

[0076] In operation S30, as shown in Figure 5bAs shown, after the formation of the memory channel structures 110, the gate slits 102 parallel to the memory channel structures 110 can be formed through the stack structure 170, and the gate slits 102 can extend along the X direction to divide the stack structure 170 into a plurality of finger-shaped regions, each of which can include a plurality of rows of memory channel structures 110 and can also include a plurality of rows of dummy channel structures.

[0077] As an example, a photoresist can be coated on the stack structure 170, and a mask can be formed by patterning the photoresist using a photolithography process, and a portion of the stack structure 170 can be removed by anisotropic etching through the mask to form the gate slits 102, and the anisotropic etching can be dry etching, such as ion milling etching, plasma etching, reactive ion etching, or laser ablation. After etching, the photoresist mask can be removed by dissolving in a solvent or ashing.

[0078] As shown, in some embodiments, a first gate slit 1021 can be formed to continuously extend along the X direction, and a plurality of second gate slits 1022 can be formed to be arranged in segments along the X direction between adjacent first gate slits 1021. Figure 5c As shown, in some embodiments, a first gate slit 1021 can be formed to continuously extend along the X direction, and a plurality of second gate slits 1022 can be formed to be arranged in segments along the X direction between adjacent first gate slits 1021.

[0079] Figure 5c As shown, in some embodiments, a first gate slit 1021 can be formed to continuously extend along the X direction, and a plurality of second gate slits 1022 can be formed to be arranged in segments along the X direction between adjacent first gate slits 1021.

[0080] As shown, in some embodiments, a first gate slit 1021 can be formed to continuously extend along the X direction, and a plurality of second gate slits 1022 can be formed to be arranged in segments along the X direction between adjacent first gate slits 1021. Figure 5c As shown, in some embodiments, a first gate slit 1021 can be formed to continuously extend along the X direction, and a plurality of second gate slits 1022 can be formed to be arranged in segments along the X direction between adjacent first gate slits 1021.

[0081] As shown, in some embodiments, a first gate slit 1021 can be formed to continuously extend along the X direction, and a plurality of second gate slits 1022 can be formed to be arranged in segments along the X direction between adjacent first gate slits 1021.​Figure 1 ) and an extension portion 1024 ( Figure 1 ), and in the Y direction, the cross-sectional dimension of the end portion 1023 is greater than the cross-sectional dimension of the extension portion 1024. For example, the end portion may be a portion of a circle or a portion of an ellipse, the arc of which bulges toward the portion between each segment, and the extension portion may be parallel to the X direction.

[0082] In some embodiments of the present application, the spacing W1 between the second gate slit 1022 and an adjacent row of storage channel structures 110 may be greater than the spacing W2 between any first gate slit 1021 and an adjacent row of storage channel structures 110 , thereby increasing the process window at the end of the second gate slit 1022 .

[0083] In some embodiments, the distance between any second gate slit 1022 and an adjacent row of dummy channel structures may be greater than the distance between any first gate slit 1021 and an adjacent row of dummy channel structures.

[0084] like Figure 5d As shown, in some examples, two second gate slits extending along the X direction are included between adjacent first gate slits. Taking storage block a as an example, while keeping the size of the existing storage block a unchanged, the second gate slit 1022a can be moved toward the adjacent first gate slit 1021a by a first preset distance in the direction indicated by the arrow, and the second gate slit 1022b can be moved toward the adjacent first gate slit 1021b by the same first preset distance; in the direction indicated by the arrow, the multiple rows of storage channel structures 110-1 (also referred to as "storage array 110-1") between the second gate slit 1022a and the first gate slit 1021a can be moved toward the first gate slit 1021a by a second preset distance, and the multiple rows of storage channel structures 110-2 (also referred to as "storage array 110-3") between the second gate slit 1022b and the first gate slit 1021b can be moved toward the first gate slit 1021b by the same second preset distance. This processing method can ensure that the total number of memory blocks remains unchanged while increasing the distance between the end of the second gate slit 1022a (not shown) and the closest row of memory channel structures in the memory arrays 110-1 and 110-2, and at the same time increasing the distance between the end of the second gate slit 1022b (not shown) and the closest row of memory channel structures in the memory arrays 110-2 and 110-3. It should be understood that Figure 5d In the example, similar operations as those of the above-mentioned storage block a can be performed on the storage block b.

[0085] like Figure 5eAs shown, in some examples, three second gate slits extending along the X direction are included between adjacent first gate slits. Taking the storage block a' as an example, in the case of keeping the size of the existing storage block a' unchanged, the second gate slit 1022a can be moved to the adjacent first gate slit 1021a by a first preset distance in the direction indicated by the arrow, and the second gate slit 1022c can be moved to the adjacent first gate slit 1021b by the same first preset distance. In the direction indicated by the arrow, the multiple rows of storage channel structures 110-1 (which can also be referred to as "storage array 110-1") between the second gate slit 1022a and the first gate slit 1021a can be moved to the first gate slit 1021a by a second preset distance, and the multiple rows of storage channel structures 110-4 (which can also be referred to as "storage array 110-4") between the second gate slit 1022c and the first gate slit 1021b can be moved to the first gate slit 1021b by the same second preset distance. In the direction indicated by the arrow, the storage array 110-2 and the storage array 110-3 can be moved to the second gate slit 1022a and 1022c by a third preset distance, respectively. This processing manner can ensure that, in the case of keeping the total amount of storage blocks unchanged, the distance between the end (not shown) of the second gate slit 1022a and the closest row of storage channel structures in the storage arrays 110-1 and 110-2 is increased, the distance between the end (not shown) of the second gate slit 1022b and the closest row of storage channel structures in the storage arrays 110-2 and 110-3 is increased, and the distance between the end (not shown) of the second gate slit 1022c and the closest row of storage channel structures in the storage arrays 110-3 and 110-4 is increased. It should be understood that, in the case of keeping the total amount of storage blocks unchanged, the distance between the end (not shown) of the second gate slit 1022a and the closest row of storage channel structures in the storage arrays 110-1 and 110-2 can be increased, the distance between the end (not shown) of the second gate slit 1022b and the closest row of storage channel structures in the storage arrays 110-2 and 110-3 can be increased, and the distance between the end (not shown) of the second gate slit 1022c and the closest row of storage channel structures in the storage arrays 110-3 and 110-4 can be increased. Figure 5e In the case of keeping the total amount of storage blocks unchanged, the distance between the end (not shown) of the second gate slit 1022a and the closest row of storage channel structures in the storage arrays 110-1 and 110-2 can be increased, the distance between the end (not shown) of the second gate slit 1022b and the closest row of storage channel structures in the storage arrays 110-2 and 110-3 can be increased, and the distance between the end (not shown) of the second gate slit 1022c and the closest row of storage channel structures in the storage arrays 110-3 and 110-4 can be increased.

[0086] It should be noted that the number of second gate slits extending along the X direction included in one storage block can exceed three, and the second gate slits exceeding three in one storage block can be processed in a similar manner as shown in Figure 5e .

[0087] In other examples, the distance between adjacent first gate slits 1021 can be compressed under the condition that the end of the second gate slit 1022 has a process window, i.e., under the condition that the end of the second gate slit 1022 has a critical distance m from the adjacent storage channel structure 110. This processing manner can ensure that, in the case of keeping the distance between the end of the second gate slit 1022 and the adjacent storage channel structure 110 meeting the process condition, the size of the storage block is reduced, thereby improving the storage density.

[0088] As shown in Figure 5fAs shown, in some embodiments, the gate slit 102 can be used as an etchant passage to remove the sacrificial layer 123 in the stack structure 170, e.g., using an isotropic wet etching process, to form the cavity 124.

[0089] As shown, in some embodiments, the gate slit 102 can be used as a deposition passage to fill the gate slit 102 and the cavity 124 with a conductive material 125, e.g., using an atomic layer deposition process, where the conductive material 125 can include W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped Si, silicides (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof. Figure 5g As shown, in some embodiments, a portion of the conductive material 125 can be removed to re-form the gate slit 102, to form a gate conductor layer 121 in the cavity 124 as shown, where the gate conductor layer 121 can be electrically connected to an external circuitry via the word line, and where the gate conductor layers 121 in different finger regions can be electrically connected at the notches.

[0090] Figure 5h As shown, in some embodiments, a portion of the conductive material 125 can be removed to re-form the gate slit 102, to form a gate conductor layer 121 in the cavity 124 as shown, where the gate conductor layer 121 can be electrically connected to an external circuitry via the word line, and where the gate conductor layers 121 in different finger regions can be electrically connected at the notches. Figure 5f As shown, in some embodiments, the gate slit 102 can be filled with an insulating material 105, e.g., including silicon dioxide, by one or more film deposition processes including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0091] Figure 5i As shown, in some embodiments, a portion of the insulating material 105 can be removed to form an isolation layer 140 on the sidewalls of the gate slit 102. For example, etching gas can be introduced in the X direction at the end of the second gate slit 1022 and in the Y direction at the extension of the second gate slit 1022 to remove a portion of the insulating material 105 in the gate slit 102 to form the isolation layer 140 covering the sidewalls of the second gate slit 1022. In some examples, the cavity volume at the end of the second gate slit 1022 limits the etching of the insulating material located therein from the X and Y directions, respectively, to make the thickness of the isolation layer 140 at the end and the extension of the second gate slit 1022 more uniform.

[0092] As shown, in some embodiments, a portion of the insulating material 105 can be removed to form an isolation layer 140 on the sidewalls of the gate slit 102. For example, etching gas can be introduced in the X direction at the end of the second gate slit 1022 and in the Y direction at the extension of the second gate slit 1022 to remove a portion of the insulating material 105 in the gate slit 102 to form the isolation layer 140 covering the sidewalls of the second gate slit 1022. In some examples, the cavity volume at the end of the second gate slit 1022 limits the etching of the insulating material located therein from the X and Y directions, respectively, to make the thickness of the isolation layer 140 at the end and the extension of the second gate slit 1022 more uniform. Figure 5j In some embodiments, a conductive via can be formed on the isolation layer 140 after the isolation layer 140 is formed (as shown in

[0093] ) to form the gate slit structure. Figure 5j

[0094] ​​​It should be noted that the embodiments and features of the present application can be combined with each other, as long as there is no conflict. In addition, unless specifically defined or limited in the context, the specific steps in the methods described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0095] The above description is merely illustrative of the embodiments of the present application and the principles of the technology used. Those skilled in the art should understand that the scope of protection in the present application is not limited to the technical solutions formed by the specific combinations of the technical features described above, but also covers other technical solutions formed by any combinations of the technical features described above or their equivalent features, without departing from the technical concept. For example, the technical solutions formed by replacing the above-described features with the technical features disclosed in the present application (but not limited to) having similar functions.

Claims

1. Three-dimensional memory, including: a stacked layer, located on a substrate; a gate slit structure passing through the stacked layer, the gate slit structure extending in a first direction parallel to the substrate to divide the stacked layer into a plurality of finger-shaped regions; wherein the gate slit structure includes a first gate slit structure and a second gate slit structure, the first gate slit structure extending continuously in the first direction, the second gate slit structure being segmented between adjacent first gate slit structures, and each segment of the second gate slit structure including an end portion and an extension portion; and A storage channel structure passes through the stacked layer, the finger-shaped area includes multiple rows of the storage channel structures arranged along the first direction, the extension portion of the second gate slit structure and the adjacent row of storage channel structures have a first preset spacing, and the first gate slit structure and the adjacent row of storage channel structures have a second preset spacing, wherein the first preset spacing is greater than the second preset spacing.

2. The three-dimensional memory according to claim 1, wherein the extending portion extends along the first direction, The end portion and a row of storage channel structures adjacent thereto have a first preset shortest distance, wherein the first preset shortest distance is greater than or equal to the second preset distance.

3. The three-dimensional memory according to claim 2, wherein: The first preset shortest distance ranges from 100 nm to 200 nm.

4. The three-dimensional memory according to claim 1, wherein: In a second direction parallel to the substrate and intersecting the first direction, there is a third preset spacing between two adjacent second gate slit structures, and there is a fourth preset spacing between the first gate slit structure and its adjacent second gate slit structure, wherein the third preset spacing is greater than the fourth preset spacing.

5. The three-dimensional memory according to claim 2, further comprising: A dummy channel structure passes through the stacked layer, the finger-shaped area includes multiple rows of the dummy channel structures arranged along the first direction, the second gate slit structure and the adjacent row of the dummy channel structures have a fifth preset spacing, the first gate slit structure and the adjacent row of the dummy channel structures have a sixth preset spacing, wherein the fifth preset spacing is greater than or equal to the sixth preset spacing.

6. The three-dimensional memory according to claim 5, characterized in that The end portion and a row of dummy channel structures adjacent thereto have a second preset shortest spacing, wherein the second preset shortest spacing is greater than or equal to the sixth preset spacing.

7. The three-dimensional memory according to claim 1, wherein: The gate slit structure includes an isolation layer and a conductive channel located on the isolation layer.

8. The three-dimensional memory according to claim 1, wherein: The stacked layer includes a gate conductor layer, and the gate conductor layer of the plurality of finger-shaped regions is electrically connected through portions between the segmented second gate slit structures.

9. The three-dimensional memory according to claim 2, wherein: The contour shape of the end portion is a part of a circle or a part of an ellipse.

10. A method for manufacturing a three-dimensional memory, characterized in that: The method comprises: forming a stacked structure on a substrate; forming a plurality of storage channel structures through the stack structure; and A plurality of gate slit structures extending in a first direction parallel to the substrate are formed through the stacked structure, dividing the stacked structure into a plurality of finger-shaped regions, each of the finger-shaped regions including a plurality of rows of the storage channel structures arranged along the first direction; the gate slit structures include a first gate slit structure and a second gate slit structure, the first gate slit structure extending continuously in the first direction, the second gate slit structure being segmented between adjacent first gate slit structures, and each segment of the second gate slit structure including an end portion and an extension portion; Among them, the extension portion of any second gate slit structure and the adjacent row of storage channel structures have a first preset distance, and any first gate slit structure and the adjacent row of storage channel structures have a second preset distance, and the first preset distance is greater than the second preset distance.

11. The manufacturing method according to claim 10, wherein the extending portion extends along the first direction, The end portion and a row of storage channel structures adjacent thereto have a first preset shortest distance, wherein the first preset shortest distance is greater than or equal to the second preset distance.

12. The manufacturing method according to claim 11, further comprising: A plurality of dummy channel structures are formed through the stacked structure, each of the finger-shaped regions includes a plurality of rows of the dummy channel structures arranged along the first direction, any of the second gate slit structures and an adjacent row of the dummy channel structures have a fifth preset spacing, and any of the first gate slit structures and an adjacent row of the dummy channel structures have a sixth preset spacing, wherein the fifth preset spacing is greater than or equal to the sixth preset spacing.

13. The manufacturing method according to claim 12, characterized in that: A row of the dummy channel structures adjacent to any one of the ends has a second preset shortest spacing, wherein the second preset shortest spacing is greater than or equal to the sixth preset spacing.

14. The manufacturing method according to claim 10, characterized in that In a second direction parallel to the substrate and intersecting the first direction, any adjacent second gate slit structures have a third preset spacing, and any first gate slit structure has a fourth preset spacing with its adjacent second gate slit structure, wherein the third preset spacing is greater than the fourth preset spacing.

15. The manufacturing method according to claim 10, wherein forming the gate slit structure comprises: forming an isolation layer in a gate slit passing through the stack structure; as well as A conductive path is formed on the isolation layer.

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