Semiconductor structure, method of fabrication, three-dimensional memory and storage system

Abstract

Embodiments of the present application provide a semiconductor structure, a preparation method, a three-dimensional memory and a storage system. In an embodiment of the present application, the semiconductor structure comprises: a stack structure comprising gate layers and insulating layers alternately stacked, the stack structure having a plurality of steps on one side; an etching stop structure comprising a barrier layer and an etching stop layer surrounded by the barrier layer, the barrier layer being located on top surfaces of the steps; and a conductive contact portion penetrating the etching stop structure and extending to the gate layers. The semiconductor structure provided by the present application can reduce the short circuit of the gate layers and the failure of the memory.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and more particularly, to a semiconductor structure, a preparation method, a three-dimensional memory and a storage system. BACKGROUND

[0002] With the development of artificial intelligence, mobile communication, mobile devices and cloud storage, the demand for memory capacity is growing exponentially. Three-dimensional memory has gradually become a mainstream semiconductor memory due to its high integration, low power consumption, fast programming and erasing speed, good reliability, low cost and other characteristics, and has attracted widespread attention.

[0003] However, as the number of three-dimensional memory stack layers increases, the depth of the contact hole is increasingly deep, which easily causes the gate layer to be broken down during the process of forming the contact hole. In this case, after filling the conductive material for forming the conductive contact in the contact hole, short circuits between different gate layers (i.e., word line bridging between different layers) are caused, thereby causing the memory to fail. SUMMARY

[0004] Embodiments of the present application provide a semiconductor structure, a preparation method, a three-dimensional memory and a storage system, which can at least partially solve the above-mentioned problems in the prior art.

[0005] In one aspect, the embodiments of the present application provide a semiconductor structure, comprising: a stack structure comprising alternately stacked gate layers and insulating layers, the stack structure having a plurality of steps on one side; an etching stop structure comprising a barrier layer and an etching stop layer surrounded by the barrier layer, the barrier layer being located on the top surface of the steps; and a conductive contact portion penetrating the etching stop structure and extending to the gate layers.

[0006] In some example embodiments of the present application, the top surface of the etching stop structure does not exceed the top surface of the last step adjacent thereto.

[0007] In some example embodiments of the present application, at least two etching stop structures located on different steps have different sizes in the vertical direction of the stack structure.

[0008] In some example embodiments of the present application, the etching stop structures located on different steps have the same size in the vertical direction of the stack structure.

[0009] In some example embodiments of the present application, the etching stop structure has an arc-shaped cross-sectional shape in the vertical direction of the stack structure.

[0010] In some example embodiments of the present application, at least one step of the plurality of steps is provided with the etching stop structure.

[0011] In some example embodiments of the present application, the etch stop structure is in contact with the gate layer.

[0012] In some example embodiments of the present application, the etch stop structure is in contact with the insulating layer.

[0013] In some example embodiments of the present application, the semiconductor structure further comprises: a gate gap structure penetrating through the stack structure, comprising a spacer layer and a fill layer surrounded by the spacer layer, wherein the etch stop layer is in contact with the spacer layer.

[0014] In some example embodiments of the present application, the spacer layer comprises a first spacer layer and a second spacer layer surrounded by the first spacer layer, the first spacer layer comprises the same material as the barrier layer in the etch stop structure.

[0015] In some example embodiments of the present application, the etch stop layer comprises a first material, and the second spacer layer comprises an oxide of the first material.

[0016] Another aspect of the embodiments of the present application provides a method for manufacturing a semiconductor structure, comprising: forming a stack structure comprising a plurality of steps on a substrate, each step comprising a gate sacrificial layer and an insulating layer; forming a buffer layer covering top surfaces of the steps, and forming a dielectric layer covering sidewalls of the steps and the buffer layer; removing the buffer layer to form a space; and sequentially forming a barrier layer and an etch stop layer surrounded by the barrier layer in the space.

[0017] In some example embodiments of the present application, before forming the barrier layer and the etch stop layer, the method further comprises: removing the gate sacrificial layer to form a sacrificial gap; and filling a first conductive material in the sacrificial gap to form a gate layer.

[0018] In some example embodiments of the present application, after forming the barrier layer and the etch stop layer, the method further comprises: forming a contact hole penetrating through the dielectric layer and extending to the gate layer in a direction perpendicular to the substrate; extending the contact hole to the gate layer in the direction perpendicular to the substrate; and filling a second conductive material in the contact hole to form a conductive contact.

[0019] In some example embodiments of the present application, sequentially forming the barrier layer and the etch stop layer in the space comprises: forming the barrier layer covering sidewalls of the space, and filling a first dielectric material in the space after forming the barrier layer to form the etch stop layer.

[0020] In some example embodiments of the present application, before removing the buffer layer, the method further comprises: forming a gate gap penetrating through the stack structure, wherein, while forming the barrier layer, the method further comprises: forming a first spacer layer covering sidewalls of the gate gap.

[0021] In some example embodiments of the present application, filling the space after the barrier layer with the first dielectric material to form the etch stop layer comprises filling the space after the barrier layer with the first dielectric material to form the etch stop layer through the gate slit.

[0022] In some example embodiments of the present application, the method further comprises forming a second spacer intermediate layer covering the first spacer layer in the gate slit simultaneously with forming the etch stop layer; oxidizing the second spacer intermediate layer to obtain a second spacer layer, and filling the gate slit with the second dielectric material to form the fill layer after forming the second spacer layer.

[0023] In some example embodiments of the present application, a top surface of the buffer layer does not exceed a top surface of an immediately adjacent upper step.

[0024] In some example embodiments of the present application, removing the buffer layer and removing the gate sacrificial layer are performed simultaneously.

[0025] In some example embodiments of the present application, an etching rate of the buffer layer is greater than or equal to an etching rate of the gate sacrificial layer.

[0026] In some example embodiments of the present application, before removing the buffer layer, the method further comprises forming a gate slit through the stack structure; wherein filling the sacrificial slit with the first conductive material to form the gate layer comprises depositing the first conductive material through the gate slit, wherein the first conductive material fills the sacrificial slit to form the gate layer, and removing the first conductive material deposited in the sidewall of the gate slit and in the space.

[0027] In some example embodiments of the present application, forming the buffer layer covering the top surfaces of the steps comprises forming the buffer layer covering the top surfaces and the sidewalls of the steps, and removing portions of the buffer layer to space the buffer layers covering the steps apart from each other.

[0028] In some example embodiments of the present application, removing portions of the buffer layer to space the buffer layers covering the steps apart from each other comprises removing the buffer layer covering the sidewalls of the steps to space the buffer layers covering the steps apart from each other.

[0029] In some example embodiments of the present application, removing portions of the buffer layer to space the buffer layers covering the steps apart from each other comprises removing portions of the buffer layer covering the top surfaces of the steps to space the buffer layers covering the steps apart from each other.

[0030] Another aspect of the embodiments of the present application also provides a three-dimensional memory, comprising: a first semiconductor structure comprising the semiconductor structure as mentioned above; and a second semiconductor structure comprising a peripheral circuit electrically connected to the first semiconductor structure.

[0031] The application further provides a storage system, comprising the three-dimensional memory mentioned above and a controller electrically connected with the three-dimensional memory and used for controlling the three-dimensional memory.

[0032] According to the semiconductor structure, the preparation method, the three-dimensional memory and the storage system provided by the application, the etching stop structure is formed on the top surface of the step, the etching stop layer in the etching stop structure can be used as a stop layer in the process of etching to form the contact hole, and the contact hole is extended to the gate layer on the basis of stopping at the etching stop layer, so that the process window of the conductive contact part is increased, the process controllability of the step area is improved, and the situation of memory failure caused by the bridge connection between different gate layers in the process of forming the contact hole is effectively reduced. In addition, in the process of forming the etching stop structure, the etching stop layer can be used to fill the barrier layer, so as to reduce the situation of blank in the etching stop structure, and further reduce the probability of problems such as DVC (Dark Voltage Contrast, DVC, dark voltage contrast). BRIEF DESCRIPTION OF DRAWINGS

[0033] Other features, objects and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments with reference to the attached drawings. In which:

[0034] Figure 1a and Figure 1b are structural schematic diagrams of semiconductor structures in some processes;

[0035] Figure 2a is a three-dimensional structural schematic diagram of a semiconductor structure according to an embodiment of the application;

[0036] Figure 2b and Figure 2c are partial cross-sectional schematic diagrams of a semiconductor structure according to an embodiment of the application;

[0037] Figure 3 is a flowchart of a preparation method of a semiconductor structure according to an embodiment of the application;

[0038] Figure 4a and Figure 4b are partial cross-sectional schematic diagrams of a semiconductor structure after forming a step according to an embodiment of the application;

[0039] Figure 5a and Figure 5b are partial cross-sectional schematic diagrams of a semiconductor structure after forming a buffer layer covering the top surface and the sidewall of the step according to an embodiment of the application;

[0040] Figure 6a and Figure 6bFIG. 1 is a partial cross-sectional view of a semiconductor structure after removal of a buffer layer and formation of a dielectric layer according to an embodiment of the present application;

[0041] Figure 7a and Figure 7b FIG. 2 is a partial cross-sectional view of a semiconductor structure after removal of a buffer layer and a gate sacrificial layer according to an embodiment of the present application;

[0042] Figure 8a and Figure 8b FIG. 3 is a partial cross-sectional view of a semiconductor structure after formation of a gate layer according to an embodiment of the present application;

[0043] Figure 9a and Figure 9b FIG. 4 is a partial cross-sectional view of a semiconductor structure after removal of a first conductive material deposited in a space and a gate gap according to an embodiment of the present application;

[0044] Figure 10a and Figure 10b FIG. 5 is a partial cross-sectional view of a semiconductor structure after formation of a barrier layer and a first spacer layer according to an embodiment of the present application;

[0045] Figure 11a and Figure 11b FIG. 6 is a partial cross-sectional view of a semiconductor structure after formation of an etch stop layer and a second spacer intermediate layer according to an embodiment of the present application;

[0046] Figure 12a and Figure 12b FIG. 7 is a partial cross-sectional view of a semiconductor structure after oxidation of a second spacer intermediate layer according to an embodiment of the present application;

[0047] Figure 13a and Figure 13b FIG. 8 is a partial cross-sectional view of a semiconductor structure after formation of a fill layer according to an embodiment of the present application;

[0048] Figure 14a and Figure 14b FIG. 9 is a partial cross-sectional view of a semiconductor structure after formation of a contact hole extending to an etch stop layer according to an embodiment of the present application;

[0049] Figure 15a and Figure 15b FIG. 10 is a partial cross-sectional view of a semiconductor structure after a contact hole extends to a gate layer according to an embodiment of the present application;

[0050] Figure 16 FIG. 11 is a schematic diagram of a structure of a three-dimensional memory according to an exemplary embodiment of the present application;

[0051] Figure 17is a connection schematic diagram of a first semiconductor structure and a second semiconductor structure according to an exemplary embodiment of the present application;

[0052] Figure 18A and Figure 18B is a structure schematic diagram of a memory system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0053] For a better understanding of the present embodiments, reference will be made to the various aspects of the present embodiments which will be described in greater detail. It should be appreciated that the detailed description is merely descriptive of illustrative embodiments of the present application and not intended in any way to limit the scope of the present embodiments. Throughout the specification, like drawing reference numerals will be understood to refer to like parts throughout the specification and claims. The singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

[0054] It should be noted that in this specification and appended claims, the terms first, second, third, etc. are used merely as labels, and are not intended to signify importance or one before the other, unless the context clearly indicates otherwise. Thus, the first spacer layer discussed in the present embodiments can also be referred to as the second spacer layer, the first conductive material can also be referred to as the second conductive material, and vice versa, without departing from the teachings of the present embodiments.

[0055] In the drawings, the thicknesses of components, sizes, and shapes can have been slightly adjusted for the sake of explanation. The drawings are merely schematic and are not strictly to scale, as the illustrations serve to describe and explain principles of the present embodiments. As used in this document, the terms "approximately," "about," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the tolerance in the measurement of a value or the calculation of a value that would be appreciated by one of ordinary skill in the art.

[0056] It should also be understood that expressions such as "include", "including", "have", "has", "contain", and / or "containing", and the like, are open-ended expressions that are used to specify the presence of stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations of them. Furthermore, when such expressions as "at least one of", "one or more of", and / or the like, appear in a list of elements, such expressions are used to modify each element of the list, not the list as a whole. Furthermore, when describing the embodiments of the present application, the use of "can" means "one or more embodiments of the present application". Also, the use of the term "exemplary" is intended to present an example or an illustration.

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0058] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other without conflict. In addition, unless specifically limited or contradicted by context, the specific steps contained in the methods described in the embodiments of the present application do not have to be limited to the order described, but can be executed in any order or in parallel. The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0059] In addition, in the embodiments of the present application, when "connected" or "coupled" is used, it can mean direct contact or indirect contact between the corresponding components, unless otherwise specifically limited or derived from the context.

[0060] As the number of stacked layers of three-dimensional memory increases, the depth of the contact hole is increasingly deep, and in the process of forming the contact hole, the gate layer is easily broken. Currently, in some processes, such as Figure 1a As shown, the stack structure 110 includes alternately stacked gate sacrificial layers 111 and insulating layers 112 forming a plurality of steps, the top surfaces of the steps are covered with a first buffer layer 121 and a second buffer layer 122, the first buffer layer 121 and the second buffer layer 122 may, for example, be silicon nitride materials with different nitrogen-to-silicon ratios and different proportions of other elements, so that the etching rates of the first buffer layer 121 and the second buffer layer 122 are different, to reduce the case that when only the same material buffer layer is deposited on the steps, the buffer layer on the deep step is not etched clean, and the buffer layer on the shallow step is etched clean and starts to etch other material layers. As shown in Figure 1b After the first buffer layer 121 and the second buffer layer 122 are formed, tungsten is used to replace the gate sacrificial layer 111 to form a gate layer 113, and tungsten is used to replace the first buffer layer 121 and the second buffer layer 122 to form a conductive contact structure 123, thereby realizing the electrical connection of the gate layer 113 and the conductive contact (not shown). However, as the number of stacked layers of three-dimensional memory increases, the thickness of the conductive contact structure 123 also needs to increase, and it is possible that tungsten cannot completely fill the inside of the conductive contact structure 123, thereby causing problems such as DVC (Dark Voltage Contrast, DVC).

[0061] Based on this, Figure 2a is a schematic diagram of a three-dimensional structure of a semiconductor structure according to an embodiment of the present application,Figure 2b and Figure 2c is a partial cross-sectional view of a semiconductor structure according to an embodiment of the present application. In which, Figure 2b is a cross-sectional view along the word line direction (x direction in Figure 2a ), Figure 2c is a cross-sectional view along the bit line direction (y direction in Figure 2a ) perpendicular to the word line direction.

[0062] As shown in Figure 2a , Figure 2b and Figure 2c , the semiconductor structure may, for example, include: a stack structure 210 including alternately stacked gate layers 211 and insulating layers 212, the stack structure 210 having a plurality of steps on one side thereof; an etching stop structure 220 including a barrier layer 221 and an etching stop layer 222 surrounded by the barrier layer 221, the barrier layer 221 being located on a top surface of the steps; and a conductive contact 230 extending through the etching stop structure 220 and to the gate layers 211. In which, the top surface of the steps mentioned in the present application may, for example, be the side of the steps away from the substrate 200.

[0063] The semiconductor structure provided according to at least one embodiment of the present application forms the etching stop structure on the top surface of the steps, the etching stop layer in the etching stop structure can be used as a stop layer in the process of etching to form a contact hole, and on the basis of stopping at the etching stop layer, the contact hole is further extended to the gate layers, which increases the process window of the conductive contact, improves the process controllability of the step area, effectively reduces the case of memory failure caused by word line bridging between different gate layers in the process of forming the contact hole. In addition, in the process of forming the etching stop structure, the etching stop layer can be used to fill the inside of the barrier layer, reducing the case of blank in the etching stop structure, and further reducing the probability of problems such as DVC.

[0064] In some embodiments of the present application, the semiconductor structure may, for example, further include a substrate 200, and the stack structure 210 is formed on one side of the substrate 200. The substrate 200 can be made of any suitable semiconductor material. For example, it can be monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), or group III-V compound such as gallium arsenide. Alternatively, the substrate 200 can be made of monocrystalline silicon material.

[0065] As an option, the substrate 200 can be, for example, a composite substrate for supporting a device structure thereon. A plurality of layers made of different materials can be sequentially disposed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the substrate 200. Portions of the substrate 200 can also form well regions doped by N-type or P-type dopants via an ion implantation or diffusion process. The dopants can include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of the present application, the well regions can be made of the same dopant or different dopants. The doping concentrations of the well regions can be the same or different, which is not limited in the present application.

[0066] In some embodiments of the present application, as shown in Figure 2b and Figure 2c , the stack structure 210 can include, for example, a plurality of stacked layers formed by alternately stacking gate layers 211 and insulating layers 212, wherein the insulating layers 212 include, but are not limited to, silicon oxide (SiO X ). The gate layers 211 include a first conductive material, such as any one or combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide, etc. The number of layers of the stack structure 210 is not limited to the number of layers shown in the figure, and can be additionally provided as needed, for example, the number of layers of the stack structure 210 can be, for example, 32 layers, 64 layers, 128 layers, etc.

[0067] In one embodiment of the present application, as shown in Figure 2b and Figure 2c , the barrier layer 221 in the etching stop structure 220 can include, but is not limited to, an insulating material such as silicon oxide. The etching stop layer 222 can include, for example, a backfillable material for etching stop such as polysilicon.

[0068] In one embodiment of the present application, as shown in Figure 2b , the top surface of the etching stop structure 220 is flush with the top surface of the immediately preceding step. However, the etching stop structure 220 in the figure is only exemplary, and in other embodiments, the top surface of the etching stop structure 220 can also be slightly lower than the top surface of the immediately preceding step. Since the surface of the etching stop structure 220 is flush with or slightly lower than the top surface of the immediately preceding step, that is, the thickness of the deposited buffer layer 260 (see Figure 5a ) is thicker, the space 261 formed is larger, which can reduce the removal of the first conductive material deposited in the space formed by removing the buffer layer 260 later. Figure 5a Figure 7a ​The smaller size of the first conductive material deposited at space 261 results in a lower etching rate and an increased etching time, leading to an increase in the side-hole area at gate layer 211.

[0069] As an option, such as Figure 2b As shown, the etch stop structures 220 located on different steps have approximately the same dimensions in the direction perpendicular to the stacked structure 210. In other words, the heights of the etch stop structures 220 are approximately the same. Since the heights of the etch stop structures 220 are approximately the same, the subsequent oxidation of the second intermediate spacer layer 2412 ( Figure 11b During the process, the oxidation depth is roughly the same, and the etching stop structure 220 formed at each step provides a more consistent process window size for the conductive contact.

[0070] It should be understood that the etch stop structure 220 in the figure is merely exemplary. In other embodiments, at least two etch stop structures 220 located on different steps have different dimensions in the direction perpendicular to the stacked structure 210. In other words, the heights of the etch stop structures 220 located on the top surfaces of each step may also be different from each other or partially different. For example, due to the process of forming contact holes, the distance from the substrate 200 (see...) Figure 2a The steps are more prone to over-etching. Therefore, in order to better ensure the process window of the contact area on each step, the height of the etch stop structure 220, which is further away from the substrate 200, can be set higher.

[0071] As an option, such as Figure 2b and Figure 2c As shown, the shapes of each side of the etch stop structure 220 are arc-shaped. The arc-shaped surfaces are smoother, resulting in better interfacial bonding between the barrier layer 221 and the dielectric layer 250 during the removal of the buffer layer 260 and backfilling with dielectric material to form the barrier layer 221. However, the etch stop structure 220 shown in the figure is merely exemplary. In other embodiments, at least one side of the etch stop structure 220 may also be square, for example.

[0072] As an option, such as Figure 2b and Figure 2c As shown, the contact surface between the etching stop structure 220 and the insulating layer 212 can be, for example, a plane. It should be understood that, without departing from the teachings of this application, the contact surface can also be, for example, a convex surface or other shapes.

[0073] It should be understood that, in the embodiments of the present application, the insulating layer 212 is located on the side of the gate layer 211 away from the substrate 200 (i.e. the insulating layer 212 is located above the gate layer 211), and the etching stop structure 220 is in contact with the insulating layer 212, which is an example of the three-dimensional structure of the semiconductor structure. Without departing from the teachings of the present application, the insulating layer 212 can also be located on the side of the gate layer 211 close to the substrate 200 (i.e. the insulating layer 212 is located below the gate layer 211), and the etching stop structure 220 is in contact with the gate layer 211, which is not limited by the present application.

[0074] It should be understood that, in the embodiments of the present application, the etching stop structure 220 is formed on each step, which is an example of the present application. Without departing from the teachings of the present application, the etching stop structure 220 is provided on at least one of the plurality of steps. In other words, the etching stop structure 220 can be formed on some steps, and not formed on some steps. For example, the etching stop structure 220 is formed on the step away from the substrate 200 (see Figure 2a ), and not formed on the step close to the substrate 200, which is not limited by the present application.

[0075] In one embodiment of the present application, as shown in Figure 2c , the semiconductor structure can further include, for example, a gate slit structure 240. The gate slit structure 240 penetrates the stack structure 210 and includes a spacer layer 241 and a filling layer 242 surrounded by the spacer layer 241, wherein the etching stop layer 222 is in contact with the spacer layer 241. The gate slit structure 240 can be used to divide the stack structure 210 into a plurality of memory blocks.

[0076] Alternatively, the spacer layer 241 includes a first spacer layer 2411 (see Figure 10b ) and a second spacer layer 2413 (see Figure 12b ) surrounded by the first spacer layer 2411. The first spacer layer 2411 and the barrier layer 221 in the etching stop structure 220 are made of the same material. For example, the first spacer layer 2411 and the barrier layer 221 in the etching stop structure 220 can be formed by the same material in the same process step, thereby reducing the process difficulty and saving the preparation cost without increasing the process steps.

[0077] Alternatively, the etching stop layer 222 includes a first material, and the second spacer layer 2413 (see Figure 12b ) includes an oxide of the first material. For example, the second spacer layer 2413 (see Figure 12bformed by oxidizing the second spacer intermediate layer 2412. In this embodiment, the second spacer intermediate layer 2412 is formed in the same process step as the etching stop layer 222 in the etching stop structure 220 by the same material. Since the second spacer intermediate layer 2412 is formed in the process of forming the etching stop layer 222 in the gate slit 243 (see Figure 7b ), oxidizing the second spacer intermediate layer 2412 can avoid the case that the gate electrode layers 211 are electrically connected through the conductive contact 230 (see Figure 2b ), the etching stop layer 222 and the second spacer intermediate layer 2412. In comparison with the way of removing the second spacer intermediate layer 2412 by etching and then depositing a new spacer layer, oxidizing the second spacer intermediate layer 2412 to the second spacer layer 2413 in this embodiment can avoid the influence of the etching process of the second spacer intermediate layer 2412 on the etching stop layer 222 and the gate electrode layers 211, and further avoid the case that the process window is reduced due to the etching of the etching stop layer 222 and the gate electrode layers 211.

[0078] As an option, the gate slit structure 240 can extend through the stack structure 210 and into the substrate 200 (see Figure 2a ). It should be understood that the gate slit structure 240 can also be arranged to extend into different layer structures included in the substrate 200 according to different three-dimensional architectures of the semiconductor structure without departing from the teachings of the present application, or the gate slit structure 240 can also extend only through the stack structure 210.

[0079] Referring again to Figure 2b and Figure 2c , in one embodiment of the present application, the semiconductor structure can further include, for example, a dielectric layer 250. The dielectric layer 250 covers the steps and the etching stop structure 220. The etching stop structure 220 located on the top surface of the adjacent steps is separated by the dielectric layer 250.

[0080] As an option, the dielectric layer 250 can be planarized by a process such as chemical mechanical polishing, so that the dielectric layer 250 can provide a flat upper surface for the stepped region of the stack structure 210.

[0081] Figure 3 is a flowchart of a method for preparing a semiconductor structure according to an exemplary embodiment of the present application. As shown in Figure 3 , the preparation method 1000 includes the following steps:

[0082] S11, forming a stack structure including a plurality of steps on a substrate, each step including a gate electrode sacrificial layer and an insulating layer.

[0083] S12, forming a buffer layer covering the top surfaces of the steps, and forming a dielectric layer covering the sidewalls of the steps and the buffer layer.

[0084] S13, removing the buffer layer to form a space.

[0085] S14, sequentially forming a barrier layer and an etching stop layer surrounded by the barrier layer in the space.

[0086] According to the method for manufacturing the semiconductor structure provided in at least one embodiment of the present application, the etching stop structure is formed on the top surface of the step, the etching stop layer in the etching stop structure can be used as a stop layer in the process of etching to form the contact hole, and the contact hole is further extended to the gate layer on the basis of stopping at the etching stop layer, so that the process window of the conductive contact part is increased, the process controllability of the step area is improved, and the situation of word line bridging between different gate layers caused by the process of forming the contact hole is effectively reduced, and the memory failure is avoided. In addition, in the process of forming the etching stop structure, the etching stop layer can be used to fill the inside of the barrier layer, so that the situation of blank in the etching stop structure is reduced, and the probability of DVC and other problems is reduced.

[0087] The above manufacturing method 1000 will be described in detail below. Figure 4a to Figure 15b The specific process of each step of the above manufacturing method 1000 will be described in detail.

[0088] Step S11

[0089] Figure 4a And Figure 4b is a partial cross-sectional view of the semiconductor structure after forming the step according to one embodiment of the present application. Wherein, Figure 4a is a cross-sectional view along the word line direction (indicated as the x direction), Figure 2a is a cross-sectional view along the bit line direction perpendicular to the word line direction (indicated as the y direction). Figure 4b Figure 2a As shown in and

[0090] in one embodiment of the present application, a laminated structure 210 can be formed on one side of the substrate 200 by one or more thin film deposition processes on the substrate 200 (see Figure 4a ). Figure 4b The thin film deposition process can include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, which is not limited in the present application. Figure 2a In some embodiments of the present application, the manufacturing material of the substrate 200 can be selected from any suitable semiconductor material, such as monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or group III-V compound such as gallium arsenide. Alternatively, the substrate 200 can be prepared by selecting a monocrystalline silicon material.

[0091] ​

[0092] As an option, the substrate 200 can be, for example, a composite substrate for supporting a device structure thereon. A plurality of layers made of different materials can be sequentially disposed by thin film deposition processes such as CVD, PVD, ALD, or any combination thereof to form the substrate 200.

[0093] In some embodiments of the present application, as shown in Figure 4a and Figure 4b , the stack structure 210 can include, for example, a plurality of pairs of insulating layers 212 and gate sacrificial layers 213 stacked alternately with each other. For example, the stack structure 210 can include 64 pairs, 128 pairs, or more than 128 pairs of insulating layers 212 and gate sacrificial layers 213. In some embodiments, the insulating layers 212 include a third dielectric material, and the gate sacrificial layers 213 include a fourth dielectric material different from the third dielectric material. Exemplary materials for forming the insulating layers 212 and the gate sacrificial layers 213 can include silicon oxide and silicon nitride, respectively. The silicon oxide layers can be used as the insulating layers 212 to isolate the gate sacrificial layers 213, and the silicon nitride layers can be used as the gate sacrificial layers 213.

[0094] The stack structure 210 can have a core region (not shown) and a step region (as shown in Figure 4a ), wherein the core region is used to form a memory cell array including a plurality of memory cells provided in the form of memory strings, which are a plurality of interconnected memory cells formed in a direction perpendicular to the substrate 200 (see Figure 2a ), and the step region is used to form conductive contacts 230 (see Figure 2b ) on the gate sacrificial layers 213 to draw current therefrom.

[0095] It should be noted that, for the sake of clarity and conciseness of the present application, the process is only described herein by way of example with the stack structure 210 including a single sub-stack, and it should be understood by those skilled in the art that the stack structure 210 can also include a plurality of sub-stacks, i.e., the stack structure 210 can be formed by a single sub-stack or can be formed by a plurality of sub-stacks stacked sequentially. It should also be noted that, for the sake of clarity, only the portion of the stack structure 210 in the step region is shown in the drawings of the present application.

[0096] Referring again to Figure 4a , in one embodiment of the present application, a plurality of steps are formed in the step region of the stack structure 210. As an example, the plurality of steps can be formed in the step region by a repeated etch-trim process on the stack structure 210 using a patterned mask (not shown), which can include a photoresist or a carbon-based polymer material and can be removed after the steps are formed. Referring to Figure 4aThe top surface of each step can be, for example, the insulating layer 212 of the stacked structure 210. That is, each step includes at least one level, and each level includes, from top to bottom, the insulating layer 212 and the gate sacrificial layer 213.

[0097] In various embodiments of this application, steps may be formed on one or more edges of the laminated structure 210 (e.g., Figure 4a As shown), a step area can also be formed at the center of the stacked structure 210 (not shown). As an example, the step area at the center may also include a first connecting area, a second connecting area, and a third connecting area arranged sequentially, with a step formed only in the second connecting area, and no steps formed in the first connecting area and the third connecting area located on both sides of the second connecting area.

[0098] In various embodiments of this application, the height of the step may gradually increase along the direction away from the core area of ​​the stacked structure 210, or may gradually decrease along the direction away from the core area of ​​the stacked structure 210, or may be arranged symmetrically with respect to the center.

[0099] In various embodiments of this application, the step area may be, for example, a single-step structure, or, for example, a partitioned step, which may have different partitions (e.g., 3 partitions, 4 partitions or more partitions, etc.).

[0100] It should be noted that, for the sake of brevity and clarity, the accompanying figures only show the case where each step comprises one level. It should also be noted that the number of levels per step can be adjusted as needed.

[0101] Step S12

[0102] Figure 5a and Figure 5b This is a partial cross-sectional schematic diagram of a semiconductor structure after forming a buffer layer 260 covering the top surface and sidewalls of a step, according to one embodiment of this application. Figure 5a It is along the direction of the character line ( Figure 2a A cross-sectional view (shown in the x-direction). Figure 5b It is along the direction of the bit line ( Figure 2a The cross-sectional view (shown in the y-direction). Figure 6a and Figure 6b This is a partial cross-sectional schematic diagram of a semiconductor structure after removing the buffer layer 260 of the sidewall of the step and forming the dielectric layer 250 according to one embodiment of this application. Figure 6a It is along the direction of the character line ( Figure 2a A cross-sectional view (shown in the x-direction). Figure 6b It is along the direction of the bit line ( Figure 2a The cross-sectional view (shown in the y-direction).

[0103] likeFigure 5a 、 Figure 5b 、 Figure 6a and Figure 6b In one embodiment of the present application, the buffer layer 260 covering the top surface of the step can comprise, for example, a buffer layer 260 covering the top surface and sidewall of the step (see Figure 5a and Figure 5b ), and a portion of the buffer layer 260 is removed to space the buffer layers 260 covering the steps apart (see Figure 6a and Figure 6b ). Thus, when the gate sacrificial layer 213 is subsequently replaced by the gate layer 211, such spacing can effectively prevent the gate layer 211 in adjacent steps from bridging with each other and the first conductive material deposited in the space 261 (see Figure 7a and Figure 7b ) formed after the removal of the buffer layer 260.

[0104] Alternatively, as shown in Figure 6a and Figure 6b , the removal of a portion of the buffer layer 260 to space the buffer layers 260 covering the steps apart can comprise, for example, removing the buffer layer 260 covering the sidewall of the step to space the buffer layers 260 covering the steps apart.

[0105] Alternatively, the removal of a portion of the buffer layer 260 to space the buffer layers 260 covering the steps apart can comprise, for example, removing a portion of the buffer layer 260 covering the top surface of the step to space the buffer layers 260 covering the steps apart.

[0106] In one embodiment of the present application, as shown in Figure 6a and Figure 6b , the top surface of the buffer layer 260 on the top surface of the step is flush with the top surface of the immediately preceding step. However, the buffer layer 260 in the figures is merely exemplary, and in other embodiments, the top surface of the buffer layer 260 can be slightly lower than the top surface of the immediately preceding step. Since the thickness of the buffer layer 260 is thicker, when the buffer layer 260 is removed later to replace the gate sacrificial layer 213 with the first conductive material to form the gate layer 211, the space 261 (see Figure 7a ) is smaller, the etching rate of the first conductive material deposited in the space 261 is lower, the etching time is increased, and the side etching area of the gate layer 211 is increased.

[0107] For example, the thickness of the buffer layer 260 can be greater than or equal to 40 nm to reduce the side etching area of the gate layer 211 when the buffer layer 260 is removed later to replace the gate sacrificial layer 213 with the first conductive material to form the gate layer 211. Figure 7a) smaller, the first conductive material deposited at the space 261 is etched at a lower rate, the etching time is increased, and the side etching area at the gate layer 211 is increased.

[0108] As an example, the buffer layer 260 can be formed on the top surface and sidewall of each step by one or more deposition processes, including but not limited to ALD, PVD, CVD, or any combination thereof. For example, the buffer layer 260 can be formed by an ALD process.

[0109] As an option, the buffer layer 260 can be made of the same dielectric material as the material of the gate sacrificial layer 213. Since the material of the gate sacrificial layer 213 and the material of the buffer layer 260 are the same, the material of the gate sacrificial layer 213 and the buffer layer 260 can be removed by the same etching process, the process flow is simpler, and the cost is lower. As an example, the material forming the buffer layer 260 and the gate sacrificial layer 213 can be nitride. For example, silicon nitride (SiN) can be used as the buffer layer 260.

[0110] As another option, the buffer layer 260 can be made of a dielectric material having an etching rate greater than that of the gate sacrificial layer 213, so that the etching rate of the buffer layer 260 is greater than or equal to that of the gate sacrificial layer 213. As an example, the material forming the gate sacrificial layer 213 can be SiN, and the material forming the buffer layer 260 can be TS SiN. For example, when wet etching is performed using phosphoric acid or the like as an etchant, the TS SiN material has an etching rate about two to three times that of normal SiN material. The etching rate of the buffer layer 260 is greater than or equal to that of the gate sacrificial layer 213, so that in the case where the thicknesses of the buffer layer 260 and the gate sacrificial layer 213 are substantially the same, the buffer layer 260 is etched faster than the gate sacrificial layer 213, which is conducive to the formation of the etching stop structure 220 later.

[0111] It should be understood that other materials having an etching rate greater than or equal to that of the gate sacrificial layer 213 can also be used for the buffer layer 260 without departing from the teachings of the present application, which are not limited in this regard.

[0112] In an embodiment of the present application, the manner of removing the buffer layer formed on the sidewall of the stepped staircase can include but is not limited to etching. For example, dry etching such as deep ion reactive etching (RIDE) can be used, and wet etching can also be used.

[0113] Referring again to Figure 6a and Figure 6bIn one embodiment of this application, after removing the buffer layer 260 from the sidewalls of the step, the semiconductor structure fabrication method 1000 may further include, for example, forming a dielectric layer 250 covering the sidewalls of the step and the buffer layer 260 covering the top surface of the step. As an example, the dielectric layer 250 may be formed by depositing an oxide. The oxide may be, for example, a silicon oxide-based material.

[0114] In one embodiment of this application, the dielectric layer 250 may be a multilayer structure. For example, a first sublayer with good step coverage, such as silicon oxide (SiO) deposited by high-density plasma (HDP) or silicon oxide deposited by atomic layer deposition (ALD), is first formed; then a second sublayer with high filling efficiency is formed, such as TEOS-based silicon oxide (TESO-based SiO). The density of the first sublayer is higher than that of the second sublayer, thus the first sublayer has good step coverage while the second sublayer has high filling efficiency.

[0115] In one embodiment of this application, after the dielectric layer 250 is formed, the semiconductor structure fabrication method 1000 may further include, for example, performing planarization treatment on the dielectric layer 250 using a process such as chemical mechanical polishing, so that the dielectric layer 250 provides a substantially flat upper surface for the step region of the stacked structure 210.

[0116] Step S13

[0117] Figure 7a and Figure 7b This is a partial cross-sectional schematic diagram of a semiconductor structure after removing the buffer layer 260 and the gate sacrificial layer 213 covering the top surface of the step, according to one embodiment of this application. Figure 7a It is along the direction of the character line ( Figure 2a A cross-sectional view (shown in the x-direction). Figure 7b It is along the direction of the bit line ( Figure 2a The cross-sectional view (shown in the y-direction).

[0118] like Figure 7a and Figure 7b As shown, in one embodiment of this application, when removing the buffer layer 260 (see...) Figure 6a Prior to this, the semiconductor structure fabrication method 1000 may also include, for example, forming a gate gap 243 through the stacked structure 210. As an example, the gate gap 243 through the stacked structure 210 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes.

[0119] In one embodiment of this application, see Figure 7a and Figure 7bThe semiconductor structure preparation method 1000 can further include, for example, removing the gate sacrificial layer 213 to form the sacrificial gap 214.

[0120] Alternatively, the removing of the buffer layer 260 (see Figure 6a ) and the removing of the gate sacrificial layer 213 can be performed simultaneously.

[0121] As an example, the removing of the buffer layer 260 to form the space 261 and the removing of the gate sacrificial layer 213 to form the sacrificial gap 214 can include, for example, removing the buffer layer 260 (see Figure 6a ) via the gate gap 243 to form the space 261, and removing the gate sacrificial layer 213 via the gate gap 243 to form the sacrificial gap 214. In other words, the gate gap 243 can be used as a passage to provide etchant and chemical precursors, and a process such as wet etching can be used to remove all of the gate sacrificial layer 213 in the stack structure 210 to form the sacrificial gap 214, and to remove the buffer layer 260 to form the space 261, respectively. The removing of the buffer layer 260 simultaneously with the removing of the gate sacrificial layer 213 can reduce the process difficulty and save the manufacturing cost without increasing the process steps.

[0122] Figure 8a and Figure 8b are partial cross-sectional schematic views of the semiconductor structure after forming the gate layer 211 according to an embodiment of the present application. In the drawings, Figure 8a is a cross-sectional view along the word line direction (x direction shown in Figure 2a ), Figure 8b is a cross-sectional view along the bit line direction (y direction shown in Figure 2a ). Figure 9a and Figure 9b are partial cross-sectional schematic views of the semiconductor structure after removing the first conductive material deposited in the space 261 and the gate gap 243 according to an embodiment of the present application. In the drawings, Figure 9a is a cross-sectional view along the word line direction (x direction shown in Figure 2a ), Figure 9b is a cross-sectional view along the bit line direction (x direction shown in Figure 2a ).

[0123] As shown in Figure 8a , Figure 8b , Figure 9a and Figure 9b , in an embodiment of the present application, the semiconductor structure preparation method 1000 can further include, for example, filling the first conductive material in the sacrificial gap 214 to form the gate layer 211. The first conductive material can be, for example, any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide.

[0124] As an example, filling the first conductive material in the sacrificial slots 214 to form the gate layers 211 can comprise, for example, depositing the first conductive material through the gate slots 243, wherein the first conductive material fills the sacrificial slots 214 to form the gate layers 211 (see FIG. 2C-1), and removing the first conductive material deposited within the spaces 261 formed after removing the side walls of the gate slots 243 and the buffer layer 260 (see FIG. 2C-2). Figure 8a and Figure 8b ). Figure 9a and Figure 9b .

[0125] As an option, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, can be employed to form the gate layers 211 in the sacrificial slots 214.

[0126] As an option, a gate recessing process can be selected in the process of removing the first conductive material deposited within the spaces 261 formed after removing the side walls of the gate slots 243 and the buffer layer 260. For example, after forming the plurality of gate layers 211, the first conductive material within the gate slots 243 and the first conductive material within the spaces 261 can be removed by a recessing etching process (e.g., a wet etching process) to ensure insulation between the gate layers 211.

[0127] Step S14

[0128] Figure 10a and Figure 10b are partial cross-sectional schematic views of a semiconductor structure after forming the barrier layer 221 and the first spacer layer 2411 according to an embodiment of the present application. In Figure 10a is a cross-sectional view along the word line direction (x direction as shown in Figure 2a ), Figure 10b is a cross-sectional view along the bit line direction (y direction as shown in Figure 2a ). Figure 11a and Figure 11b are partial cross-sectional schematic views of a semiconductor structure after forming the etching stop layer 222 and the second spacer intermediate layer 2412 according to an embodiment of the present application. In Figure 11a is a cross-sectional view along the word line direction (x direction as shown in Figure 2a ), Figure 11b is a cross-sectional view along the bit line direction (y direction as shown in Figure 2a ).

[0129] In an embodiment of the present application, as shown in Figure 10a , Figure 10b , Figure 11a and Figure 11b , forming the barrier layer 221 and the etching stop layer 222 in the spaces 261 in sequence can comprise, for example, forming the barrier layer 221 covering the side walls of the spaces 261 (see FIG. 2C-1), and forming the etching stop layer 222 covering the barrier layer 221 (see FIG. 2C-2).Figure 10a and Figure 10b ), and filling the space 261 with a first dielectric material after forming the barrier layer 221 to form an etch stop layer 222 (see Figure 11a and Figure 11b ).

[0130] Referring to Figure 10a and Figure 10b , in one embodiment of the present application, the method of fabricating a semiconductor structure further comprises forming a first spacer layer 2411 covering the sidewall of the gate slit 243 while forming the barrier layer 221. In other words, the barrier layer 221 of the etch stop structure 220 and the first spacer layer 2411 of the gate slit structure 240 (see Figure 2b ) are formed simultaneously in one process step. The material forming the barrier layer 221 and the first spacer layer 2411 includes, but is not limited to, oxide, such as silicon oxide (SiO X ).

[0131] It should be appreciated that the barrier layer 221 and the first spacer layer 2411 can be formed by using any suitable deposition process, such as an atomic layer deposition process, without limitation.

[0132] Referring to Figure 11a and Figure 11b , in one embodiment of the present application, filling the space 261 with a first dielectric material after forming the barrier layer 221 to form an etch stop layer 222 can for example comprise filling the space 261 with a first dielectric material after forming the barrier layer 221 through the gate slit 243 to form an etch stop layer 222. The method of fabricating a semiconductor structure 1000 can further for example comprise forming a second spacer intermediate layer 2412 covering the first spacer layer 2411 within the gate slit 243 while forming the etch stop layer 222. In other words, the first dielectric material is deposited in the gate slit 243 to form the second spacer intermediate layer 2412 during the deposition of the etch stop layer 222. The first dielectric material can for example be a backfillable, etch stop material such as polysilicon.

[0133] It should be appreciated that the etch stop layer 222 and the second spacer intermediate layer 2412 can be formed by using any suitable deposition process, such as an atomic layer deposition process, without limitation.

[0134] Figure 12a and Figure 12b are partial cross-sectional schematic views of the semiconductor structure after oxidizing the second spacer intermediate layer 2412 according to one embodiment of the present application. In Figure 12a is a cross-sectional view along the word line direction, Figure 12b is a cross-sectional view along the bit line direction.

[0135] In one embodiment of the present application, as shown in Figure 12a and Figure 12b , the method 1000 of preparing the semiconductor structure can further comprise, for example, oxidizing the second spacer intermediate layer 2412 to obtain a second spacer layer 2413. Figure 12b In the above embodiment, the dashed line can be used to exemplarily distinguish the first spacer layer 2411 formed by deposition and the second spacer layer 2412 formed by oxidation. Since the second spacer intermediate layer 2412 (see Figure 7b ) is formed in the gate slit 243 (see Figure 11b ) in the process of forming the etching stop layer 222, oxidizing the second spacer intermediate layer 2412 can avoid the case that the gate electrode layers 211 are electrically connected through the conductive contact 230 (see Figure 2b ), the etching stop layer 222 and the second spacer intermediate layer 2412. In comparison with the way of removing the second spacer intermediate layer 2412 by etching and then re-depositing a new spacer layer, in the present embodiment, oxidizing the second spacer intermediate layer 2412 to the second spacer layer 2413 can avoid the influence of the etching process of the second spacer intermediate layer 2412 on the etching stop layer 222 and the gate electrode layers 211, and further avoid the case that the process window is reduced due to the etching of the etching stop layer 222 and the gate electrode layers 211.

[0136] Figure 13a and Figure 13b are partial cross-sectional schematic views of the semiconductor structure after forming the filling layer 242 according to one embodiment of the present application. In the above embodiment, Figure 13a is a cross-sectional view along the word line direction (x direction shown in Figure 2a ), Figure 13b is a cross-sectional view along the bit line direction (y direction shown in Figure 2a ).

[0137] In one embodiment of the present application, as shown in Figure 13a and Figure 13b , the method 1000 of preparing the semiconductor structure can further comprise, for example, filling a second dielectric material in the gate slit 243 in which the second spacer layer 2413 (see Figure 12b ) is formed, to form a filling layer 242.

[0138] It should be understood that the second dielectric material can be selected according to the function of the gate slit structure 240 in the semiconductor structure without departing from the teachings of the present application. For example, if the gate slit structure 240 serves as a common source electrode, the second dielectric material can be, for example, a conductive material such as polysilicon, and the conductive material such as polysilicon is in contact with the substrate 200 (see Figure 2a ) or other material layer serving as a source electrode layer; if the gate slit structure 240 does not serve as a common source electrode, the second dielectric material can be, for example, an insulating material, which is not limited in the present application.

[0139] Figure 14a and Figure 14b is a partial cross-sectional view of a semiconductor structure after the contact hole 231 extends to the gate layer 211 according to an embodiment of the present application. In this embodiment, Figure 14a is a cross-sectional view along the word line direction (x direction as shown in Figure 2a ), Figure 14b is a cross-sectional view along the bit line direction (y direction as shown in Figure 2a ). Figure 15a and Figure 15b is a partial cross-sectional view of a semiconductor structure after the contact hole 231 extends to the gate layer 211 according to an embodiment of the present application. In this embodiment, Figure 15a is a cross-sectional view along the word line direction (x direction as shown in Figure 2a ), Figure 15b is a cross-sectional view along the bit line direction (y direction as shown in Figure 2a ).

[0140] In one embodiment of the present application, as shown in Figure 14a , Figure 14b , Figure 15a and Figure 15b , the method 1000 of fabricating a semiconductor structure can further comprise, for example: forming a contact hole 231 extending through the dielectric layer 250 and to the etch stop layer 222; extending the contact hole 231 to the gate layer 211 along a direction perpendicular to the substrate 200 (see Figure 2a ); and filling the contact hole 231 with a second conductive material to form a conductive contact 230 (as shown in Figure 2b and Figure 2c ).

[0141] As an example, a plurality of contact holes 231 can be formed in the step region by a deep hole etching process first, as shown in Figure 14a and Figure 14b . Since the etch stop structure 220 is formed on the step, the deep hole etching will stop at the etch stop layer 222 of the etch stop structure to reduce the risk of the deep hole etching process breaking through the next gate layer, resulting in a short circuit of the gate layers. Then, a plasma or the like is used as an etching material to perform an etching operation again on the basis of the contact holes 231, as shown in Figure 14a and Figure 14b , to extend the contact holes 231 to the gate layer 211 (as shown in Figure 15a and Figure 15b ). See Figure 2b and Figure 2cA second conductive material such as iron nitride, tungsten alloy, etc. is filled in the contact hole 231 to form a conductive contact 230. Since the etching material has a greater etching selectivity to the etching stop layer 222 and the barrier layer 221 than to the gate layer 211, the contact hole 231 can be extended to the gate layer 211 in the re-etching operation. It can be seen that the conductive contact 230 is electrically connected to the gate layer 211 of the corresponding layer, thereby leading out the gate current.

[0142] In one embodiment of the present application, an etching material having etching selectivity to both the etching stop layer 222 and the barrier layer 221 can be selected to extend the contact hole 231 to the gate layer 211, so as to reduce the process flow.

[0143] In another embodiment of the present application, a first etching material having a higher etching selectivity to the etching stop layer 222 and a lower etching selectivity to the barrier layer 221 can be selected to extend the contact hole 231 to the barrier layer 221, and a second etching material having a higher etching selectivity to the barrier layer 221 and a lower etching selectivity to the gate layer 211 can be selected to extend the contact hole 231 to the gate layer 211. The barrier layer 221 also serves as an etching stop layer, so that the depth of the contact hole 231 etched to the gate layer 211 is more uniform.

[0144] It should be understood that the etching process of the contact hole 231 shown in FIGS. 1A to 1C can be selected as needed without departing from the teachings of the present application. Figure 14a and Figure 14b The present application does not limit the etching process of the contact hole 231.

[0145] It should be understood that the etching times and etching processes of the process of extending the contact hole 231 to the gate layer 211 can be selected as needed without departing from the teachings of the present application, and the present application does not limit the etching times and etching processes.

[0146] In one embodiment of the present application, the method 1000 of preparing a semiconductor structure can further include, for example, forming a virtual channel hole (not shown) extending through the step region and to the substrate 200 in the step region, and filling the virtual channel hole with an insulating material to form a virtual channel (not shown) to support the structures in each of the stack structures 210.

[0147] Since the content described above in the description of the structure of the semiconductor structure can be fully or partially applicable to the method of preparing the semiconductor structure described herein, the related or similar content is not described again. Accordingly, the content and method described herein in the description of the method of preparing the semiconductor structure can be fully or partially applicable to the structure of the semiconductor structure described above.

[0148] According to the method for manufacturing the semiconductor structure provided in at least one of the embodiments of the present application, the etching stop structure is formed on the top surface of the step, and the etching stop layer in the etching stop structure can be used as a stop layer in the process of etching to form the contact hole. On the basis of stopping at the etching stop layer, the contact hole is further extended to the gate layer, thereby increasing the process window of the conductive contact part and improving the process controllability of the step region, and effectively reducing the case of word line bridging between different gate layers caused in the process of forming the contact hole and the case of memory failure. In addition, in the process of forming the etching stop structure, the etching stop layer can be used to fill the internal space of the blocking layer, thereby reducing the case of blank space in the etching stop structure and further reducing the probability of problems such as DVC.

[0149] Although the exemplary method for manufacturing the semiconductor structure and the structure are described herein, it can be understood that one or more features can be omitted, replaced or added from the structure of the semiconductor structure. For example, various well regions can be formed in the substrate as needed. In addition, the materials of the layers exemplified are only exemplary.

[0150] In the subsequent process of the method for manufacturing the semiconductor structure, steps such as forming a peripheral circuit in the semiconductor structure are further included. The embodiments and process flow in the present application only show the intermediate body of the semiconductor structure for forming the gate gap structure.

[0151] Figure 16 is a structural schematic diagram of a three-dimensional memory 300 according to an exemplary embodiment of the present application. As shown in Figure 16 , the three-dimensional memory 300 includes a first semiconductor structure 310 including a semiconductor structure as mentioned in the above embodiments, and a second semiconductor structure 320 including a peripheral circuit electrically connected to the first semiconductor structure 310.

[0152] Figure 17 is a connection schematic diagram of the first semiconductor structure and the second semiconductor structure according to an exemplary embodiment of the present application. As shown in Figure 17 , the peripheral circuit of the second semiconductor structure 320 can include, for example, a page buffer / sense amplifier 321, a column decoder / bit line (BL) driver 322, a row decoder / word line (WL) driver 323, a voltage generator 324, a control logic unit 325, a register 326, an interface 327 and a data bus 328. It should be understood that the three-dimensional memory 300 can further include additional peripheral circuits not shown in Figure 16 .

[0153] The page buffer / sense amplifier 321 can be configured to read and program (write) data from and to the memory cell array of the first semiconductor structure 310 according to a control signal from the control logic unit 325.

[0154] In one example, the page buffer / sense amplifier 321 can store a page of program data (write data) to be programmed into one page of the array of memory cells of the first semiconductor structure 310.

[0155] In another example, the page buffer / sense amplifier 321 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells coupled to the selected word line.

[0156] In yet another example, the page buffer / sense amplifier 321 can also sense a low power signal representing a data bit stored in a memory cell from a bit line during a read operation, and amplify the small voltage swing to an identifiable logic level. The column decoder / bit line driver 322 can be configured to be controlled by the control logic unit 325, and select one or more memory strings by applying a bit line voltage generated by the voltage generator 324.

[0157] The row decoder / word line driver 323 can be configured to be controlled by the control logic unit 325, and select / deselect a memory block of the array of memory cells, and select / deselect a word line of the memory block. The row decoder / word line driver 323 can also be configured to drive the word line using a word line voltage generated by the voltage generator 324.

[0158] In some embodiments, the row decoder / word line driver 323 can also select / deselect and drive a source select gate line (not shown) and a drain select gate (not shown).

[0159] The voltage generator 324 can be configured to be controlled by the control logic unit 325, and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be provided to the array of memory cells.

[0160] The control logic unit 325 can be coupled to each of the peripheral circuits described above, and configured to control the operation of each of the peripheral circuits. The control logic unit 325 can perform the operation methods of the flash memory described below. The register 326 can be coupled to the control logic unit 325, and include a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each of the peripheral circuits.

[0161] The interface 327 can be coupled to the control logic unit 325 and act as a control buffer to buffer control commands received from a host (not shown) and forward them to the control logic unit 325, and to buffer status information received from the control logic unit 325 and forward them to the host. The interface 327 can also be coupled to the column decoder / bit line driver 322 via a data bus 328 and act as a data input / output (I / O) interface and data buffer, thereby buffering and forwarding data to and from the memory cell array.

[0162] Figure 18A and Figure 18B is a structural schematic diagram of a storage system according to an exemplary embodiment of the present application. As shown in Figure 18A and Figure 18B , the storage system 400 comprises a three-dimensional memory 410 as mentioned in the above embodiments; and a controller 420 electrically connected with the three-dimensional memory 410, for controlling the three-dimensional memory 410.

[0163] In an example as shown in Figure 18A , the controller 420 and the single three-dimensional memory 410 can be integrated into a memory card. The memory card can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash storage card (UFS), etc. The memory card can also include a memory card connector 430 coupling the memory card with a host (not shown).

[0164] In another example as shown in Figure 18B , the controller 420 and the plurality of three-dimensional memories 410 can be integrated into a solid state drive (SSD). The solid state drive can also include an SSD connector 430 coupling the solid state drive with a host (not shown). In some embodiments, the storage capacity and / or operating speed of the solid state drive is higher than that of the memory card as shown in Figure 18A .

[0165] According to the semiconductor structure, the manufacturing method, the three-dimensional memory and the storage system provided by the embodiment of the present application, the etching stop structure is formed on the top surface of the step, and the etching stop layer in the etching stop structure can be used as a stop layer in the process of etching to form the contact hole. On the basis of stopping at the etching stop layer, the contact hole is further extended to the gate layer, so as to increase the process window of the conductive contact part, improve the process controllability of the step area, effectively reduce the word line bridging between different gate layers caused in the process of forming the contact hole, and reduce the storage failure. In addition, in the process of forming the etching stop structure, the etching stop layer can be used to fill the internal part of the blocking layer, so as to reduce the existence of the blank in the etching stop structure, and further reduce the probability of the DVC problem.

[0166] The above description is only the embodiment of the present application and the explanation of the technical principles. Those skilled in the art should understand that the protection scope of the present application is not limited to the technical solutions formed by the specific combination of the technical features, and should also cover other technical solutions formed by the combination of the above technical features or equivalent features without departing from the technical concept. For example, the technical solutions formed by the mutual replacement of the above features and the technical features disclosed in the present application (but not limited to) having similar functions.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a stack structure comprising gate layers and insulating layers stacked alternately, the stack structure having a plurality of steps on one side; an etching stop structure comprising a barrier layer and an etching stop layer surrounded by the barrier layer, wherein, in a cross section in a word line direction, the barrier layer surrounds the etching stop layer on both sides in a direction perpendicular to the stack structure and on both sides in a direction parallel to the stack structure, the barrier layer is on and in contact with a top surface of the step, and the etching stop structure has a spacing distance from a sidewall of an adjacent step; and a conductive contact portion penetrating the etching stop structure and extending to the gate layer.

2. The semiconductor structure of claim 1, wherein, A top surface of the etching stop structure does not exceed a top surface of an immediately preceding step adjacent to the etching stop structure.

3. The semiconductor structure of claim 1, wherein, At least two etching stop structures located on different steps have different sizes in a direction perpendicular to the stack structure.

4. The semiconductor structure of claim 1, wherein, The etching stop structures located on different steps have the same size in a direction perpendicular to the stack structure.

5. The semiconductor structure of claim 1, wherein, A cross-sectional shape of the etching stop structure in a direction perpendicular to the stack structure is arc-shaped.

6. The semiconductor structure of claim 1, wherein, At least one step of the plurality of steps is provided with the etching stop structure.

7. The semiconductor structure of claim 1, wherein, The etching stop structure is in contact with the gate layer.

8. The semiconductor structure of claim 1, wherein, The etching stop structure is in contact with the insulating layer.

9. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a dielectric layer covering the steps and the etching stop structure.

10. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a gate slit structure penetrating the stack structure, comprising a spacer layer and a filling layer surrounded by the spacer layer, wherein the etching stop layer is in contact with the spacer layer.

11. The semiconductor structure of claim 10, wherein, The spacer layer comprises a first spacer layer and a second spacer layer surrounded by the first spacer layer, and the first spacer layer comprises the same material as the barrier layer in the etching stop structure.

12. The semiconductor structure of claim 11, wherein, The etching stop layer comprises a first material, and the second spacer layer comprises an oxide of the first material.

13. A method of fabricating a semiconductor structure, characterized by, The method comprises: forming a stack structure comprising a plurality of steps on a substrate, each of the steps comprising a gate sacrificial layer and an insulating layer; forming a buffer layer covering top surfaces of the steps, and forming a dielectric layer covering sidewalls of the steps and the buffer layer, wherein the buffer layer has a spacing distance from sidewalls of adjacent steps; removing the buffer layer to form spaces; and forming a barrier layer and an etching stop layer surrounded by the barrier layer in the spaces in sequence, wherein, in a cross section in a word line direction, the barrier layer surrounds the etching stop layer on both sides in a direction perpendicular to the stack structure and on both sides in a direction parallel to the stack structure.

14. The method of claim 13, wherein, Before forming the barrier layer and the etching stop layer, the method further comprises: removing the gate sacrificial layer to form a sacrificial slit; filling a first conductive material in the sacrificial slit to form a gate layer.

15. The method of claim 14, wherein, After forming the barrier layer and the etching stop layer, the method further comprises: forming a contact hole penetrating the dielectric layer and extending to the etching stop layer; extending the contact hole to the gate layer in a direction perpendicular to the substrate; and filling a second conductive material in the contact hole to form a conductive contact portion.

16. The method of claim 13, wherein, The method of forming a barrier layer and an etching stop layer in the spaces in sequence comprises: forming the barrier layer covering sidewalls of the space, and filling a first dielectric material in the space after forming the barrier layer to form the etch stop layer.

17. The method of claim 16, wherein, Before removing the buffer layer, the method further comprises: forming a gate slit through the stack structure, simultaneously with forming the barrier layer, the method further comprises: forming a first spacer layer covering sidewalls of the gate slit.

18. The method of claim 17, wherein, filling a first dielectric material in the space after forming the barrier layer to form the etch stop layer, comprises: filling a first dielectric material in the space after forming the barrier layer to form the etch stop layer through the gate slit.

19. The method of claim 18, wherein, the method further comprises: simultaneously with forming the etch stop layer, forming a second spacer intermediate layer covering the first spacer layer in the gate slit; oxidizing the second spacer intermediate layer to obtain a second spacer layer, and filling a second dielectric material in the gate slit after forming the second spacer layer to form a fill layer.

20. The method of claim 13, wherein, a top surface of the buffer layer of the top surface of the step does not exceed a top surface of an immediately adjacent upper step.

21. The method of claim 14, wherein, removing the buffer layer and removing the gate sacrificial layer are performed simultaneously.

22. The method of claim 21, wherein, an etching rate of the buffer layer is greater than or equal to an etching rate of the gate sacrificial layer.

23. The method of claim 14, wherein, Before removing the buffer layer, the method further comprises: forming a gate slit through the stack structure; wherein filling a first conductive material in the sacrificial slit to form a gate layer comprises: depositing a first conductive material through the gate slit, wherein the first conductive material fills the sacrificial slit to form the gate layer, and removing the first conductive material deposited in the sidewalls of the gate slit and in the space.

24. The method of claim 13, wherein, forming the buffer layer covering the top surface of the step, comprises: forming a buffer layer covering the top surface and sidewalls of the step; and removing portions of the buffer layer to space the buffer layers covering the steps from each other.

25. The method of claim 24, wherein, removing portions of the buffer layer to space the buffer layers covering the steps from each other, comprises: removing the buffer layer covering the sidewalls of the step to space the buffer layers covering the steps from each other.

26. The method of claim 24, wherein, removing portions of the buffer layer to space the buffer layers covering the steps from each other, comprises: removing portions of the buffer layer covering the top surface of the step to space the buffer layers covering the steps from each other.

27. A three-dimensional memory, comprising: comprises: a first semiconductor structure comprising the semiconductor structure of any one of claims 1 to 12; and a second semiconductor structure comprising a peripheral circuit electrically connected to the first semiconductor structure.

28. A storage system, comprising: comprises: the three-dimensional memory of claim 27; and a controller electrically connected to the three-dimensional memory for controlling the three-dimensional memory.

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