Array substrate, manufacturing method thereof and display panel
By introducing a top gate structure that electrically connects the conductive layer to the gate layer and an electrical connection to the second thin-film transistor in the array substrate, the problem of low charging rate of thin-film transistors is solved, achieving high refresh rate and simplified manufacturing process for e-readers.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2021-11-18
- Publication Date
- 2026-06-05
AI Technical Summary
The low charging rate of thin-film transistors in existing e-readers results in a low refresh rate, which affects display quality.
A conductive layer is introduced into the array substrate and electrically connected to the gate layer of the first thin-film transistor. The conductive layer is designed as a top gate structure to increase the channel width and improve the charging rate. At the same time, a second thin-film transistor is set in the non-display area and electrically connected to the gate line. The voltage of the conductive layer is controlled to avoid affecting the thin-film transistor in the off state.
By increasing the channel width of thin-film transistors, the charging rate and refresh rate are improved, the manufacturing process is simplified, and the cost is reduced.
Smart Images
Figure CN114093893B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more specifically, to an array substrate and its manufacturing method, and a display panel. Background Technology
[0002] In recent years, e-paper has seen continuous growth in scale due to its advantages such as eye protection and low power consumption, and has gradually expanded into fields such as education and healthcare. E-readers using e-paper have also gradually grown into a key product form. The higher the resolution and refresh rate of an e-reader product, the better the user experience. A higher refresh rate is achieved through the high charging rate of thin-film transistors in e-reader products.
[0003] However, the low charging rate of thin-film transistors in existing e-readers results in a low refresh rate, which affects the display quality and makes it difficult to meet the requirements. Summary of the Invention
[0004] This application addresses the shortcomings of existing methods by proposing an array substrate, its fabrication method, and a display panel to solve the problems of low charging rate and refresh rate in existing e-readers.
[0005] In a first aspect, embodiments of this application provide an array substrate, comprising:
[0006] Substrate;
[0007] A switching device layer is disposed on one side of the substrate and includes a first thin-film transistor, wherein the first thin-film transistor includes a first gate layer, a first active layer and a first source-drain layer;
[0008] A conductive layer is disposed on the side of the switching device layer away from the substrate, and the orthographic projection of the conductive layer on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate;
[0009] A pixel electrode layer is disposed on the side of the conductive layer away from the substrate, and the pixel electrode layer is electrically connected to the first source and drain layer;
[0010] The conductive layer is insulated from the pixel electrode layer and electrically connected to the first gate layer.
[0011] Optionally, the switching device layer further includes a second thin-film transistor, which is offset from the first thin-film transistor;
[0012] The second thin-film transistor includes a second gate layer and a second source-drain layer, the first gate layer and the second gate layer are electrically connected, and the second source-drain layer is electrically connected to the conductive layer.
[0013] Optionally, the switching device layer includes a gate line, which is electrically connected to the first gate layer and the second gate layer respectively, and is electrically connected to the second source-drain layer. The gate line, the first gate layer and the second gate layer are disposed in the same layer.
[0014] Optionally, the array substrate includes a plurality of pixel regions and a non-display region located between the plurality of pixel regions, wherein the second thin-film transistor is located in the non-display region.
[0015] Optionally, the orthographic projection of the second thin-film transistor on the substrate overlaps with the orthographic projection of the gate line on the substrate, and the portion of the gate line corresponding to the second thin-film transistor is multiplexed as the second gate layer.
[0016] Optionally, the first thin-film transistor includes a first gate insulating layer disposed between the first gate layer and the first source-drain layer, and the second thin-film transistor includes a second gate insulating layer disposed between the second gate layer and the second source-drain layer, wherein the first gate insulating layer and the second gate insulating layer are disposed in the same layer;
[0017] The second gate insulating layer has a first via, and the second source-drain layer passes through the first via and is electrically connected to the gate line.
[0018] Optionally, the array substrate further includes a passivation layer disposed between the switching device layer and the conductive layer. The passivation layer has a second via, the position of which corresponds to the position of the second thin film transistor. The conductive layer passes through the second via and is electrically connected to the second source-drain layer.
[0019] Optionally, the array substrate includes an insulating layer disposed between the conductive layer and the pixel electrode layer.
[0020] Optionally, the second thin-film transistor includes a second active layer disposed between the second gate layer and the second source / drain layer;
[0021] The first active layer and the second active layer are disposed on the same layer; and / or, the first source-drain layer and the second source-drain layer are disposed on the same layer.
[0022] Optionally, both the first active layer and the second active layer include an intrinsic semiconductor layer and a doped layer sequentially stacked along the direction from the substrate to the pixel electrode layer.
[0023] Optionally, the orthographic projection of the conductive layer on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate.
[0024] Secondly, embodiments of this application provide a display panel, including the array substrate described in embodiments of this application.
[0025] Thirdly, embodiments of this application provide a method for fabricating an array substrate, comprising:
[0026] Provide a substrate;
[0027] A switching device layer is fabricated on one side of the substrate. The switching device layer includes a first thin-film transistor, which includes a first gate layer, a first active layer, and a first source-drain layer.
[0028] A conductive layer is formed on the side of the switching device layer away from the substrate, and the conductive layer is electrically connected to the first gate layer. The orthographic projection of the conductive layer on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate.
[0029] A pixel electrode layer is formed on the side of the conductive layer away from the substrate, and the pixel electrode layer is electrically connected to the first source-drain layer.
[0030] Optionally, the fabrication of the switching device layer on one side of the substrate includes:
[0031] A first gate layer, a second gate layer, and gate lines are fabricated on one side of the substrate using a patterning process.
[0032] A first gate insulating layer is fabricated on the side of the first gate layer away from the substrate using a patterning process, and a second gate insulating layer is fabricated on the side of the second gate layer away from the substrate.
[0033] A first active layer is fabricated on the side of the first gate insulating layer away from the substrate using a patterning process, and a second active layer is fabricated on the side of the second gate layer away from the substrate.
[0034] A first source / drain layer is fabricated on the side of the first active layer away from the substrate using a patterning process, and a second source / drain layer is fabricated on the side of the second active layer away from the substrate to form a first thin-film transistor and a second thin-film transistor.
[0035] The step of fabricating a conductive layer on the side of the switching device layer away from the substrate includes:
[0036] A passivation layer is formed on the side of the switching device layer away from the substrate, and a second via is formed in the passivation layer at a position corresponding to the position of the second source and drain layer;
[0037] A conductive layer is formed on the side of the passivation layer away from the substrate, and the conductive layer is electrically connected to the second source and drain layer through the second via.
[0038] The beneficial technical effects of the technical solutions provided in this application include:
[0039] The array substrate in this embodiment includes a substrate and a switching device layer, a conductive layer, and a pixel electrode layer sequentially disposed on one side of the substrate. The switching device layer includes a first thin-film transistor (TFT), which includes a first gate layer, a first active layer, and a first source-drain layer. The pixel electrode layer is electrically connected to the first source-drain layer. The orthographic projection of the conductive layer onto the substrate at least partially overlaps with the orthographic projection of the first active layer onto the substrate. The conductive layer is insulated from the pixel electrode layer and electrically connected to the first gate layer. By electrically connecting the conductive layer to the first gate layer, when a gate-on voltage is applied to the first TFT, the conductive layer also has a voltage. The conductive layer can act as the top gate of the first TFT, attracting electrons to accumulate in the back channel region, thereby increasing the channel width of the first TFT and increasing the on-state current of the first TFT. Therefore, the charging rate of the first TFT and the refresh rate of the display device can be improved.
[0040] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description
[0041] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:
[0042] Figure 1 This is a top view of the array substrate structure in the prior art;
[0043] Figure 2 for Figure 1 Schematic diagram of the structure at section AA;
[0044] Figure 3 This is a top view of an array substrate provided in an embodiment of this application;
[0045] Figure 4 for Figure 3 Schematic diagram of the structure at section AA;
[0046] Figure 5 for Figure 3 Schematic diagram of the structure at the mid-section BB;
[0047] Figure 6 A schematic diagram illustrating the fabrication process of an array substrate provided in an embodiment of this application;
[0048] Figures 7a to 7i The diagram shows the structure of different processes for fabricating the array substrate provided in the embodiments of this application.
[0049] In the picture:
[0050] 10-Array substrate; 11-Substrate; 12-Switch device layer; 121-First thin-film transistor;
[0051] 1210 - First gate layer; 1211 - First gate insulating layer; 1212 - First active layer; 1213 - First source / drain layer; 122 - Second thin-film transistor; 1220 - Second gate layer; 1221 - Second gate insulating layer; 1222 - Second active layer; 1223 - Second source / drain layer; 100 - Intrinsic semiconductor layer; 101 - Doped layer; 1200 - Gate line;
[0052] 13a-Top metal structure; 13b-Conductive layer; 14-Pixel electrode layer; 15-Passivation layer; 16-Insulating layer; 20-Pixel area; 21-Non-display area; 31-First via; 32-Second via; 40-Channel area; Channel width W; 41-Back channel area; 42-Front channel area. Detailed Implementation
[0053] This application is described in detail below. Examples of embodiments of this application are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. Furthermore, detailed descriptions of known technologies that are unnecessary for the features of this application are omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0054] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.
[0055] The inventors of this application considered that electronic paper has advantages such as being eye-friendly and having low power consumption, and is widely used in e-reader products such as e-books and e-newspapers. Electronic paper technology involves coating electronic ink onto a pixel electrode film, and then using thin-film transistors to control the arrangement of electronic ink particles on the pixel electrode film to form the desired pattern. To achieve a good display effect, the e-reader needs to have good resolution and refresh rate; ideally, the refresh rate needs to reach 85Hz, completing the image refresh within 200 milliseconds.
[0056] Combination Figure 1 and Figure 2 As shown, the array substrate of an existing e-reader includes a first thin-film transistor (TFT) and a pixel electrode layer. Since e-reader products are intended for outdoor use, to prevent the TFT from being affected by light and thus causing abnormal screen refresh, a top metal structure 13a is placed on top of the TFT to shield its first active layer. The top metal structure 13a is electrically connected to the pixel electrode layer 14, so the voltage on the top metal structure 13a is consistent with the voltage on the pixel electrode layer 14. When the driving circuit (not shown) sends a gate-on voltage (VGH) to the first gate of the TFT, the TFT is turned on, and the channel region is conducting. To improve the charging rate, the resistance of the channel region needs to be sufficiently low to meet a certain on-state current and a certain charging rate. However, due to limitations in pixel space and substrate load, the channel width W cannot be too large, thus limiting the charging rate and refresh rate.
[0057] The array substrate, its manufacturing method, and the display panel provided in this application are intended to solve the above-mentioned technical problems of the prior art.
[0058] The array substrate, its manufacturing method, and the display panel provided in the embodiments of this application are described in detail below with reference to the accompanying drawings.
[0059] Combination Figure 3 , Figure 4 and Figure 5 As shown, the array substrate 10 in this embodiment includes:
[0060] Substrate 11;
[0061] The switching device layer 12 is disposed on one side of the substrate 11 and includes a first thin film transistor 121. The first thin film transistor 121 includes a first gate layer 1210, a first active layer 1212 and a first source-drain layer 1213.
[0062] The conductive layer 13b is disposed on the side of the switching device layer 12 away from the substrate 11, and the orthographic projection of the conductive layer 13b on the substrate 11 at least partially overlaps with the orthographic projection of the first active layer 1212 on the substrate 11.
[0063] The pixel electrode layer 14 is disposed on the side of the conductive layer 13b away from the substrate 11, and the pixel electrode layer 14 is electrically connected to the first source-drain layer 1213.
[0064] The conductive layer 13b is insulated from the pixel electrode layer 14 and is electrically connected to the first gate layer 1210.
[0065] Specifically, such as Figure 4 As shown, the first gate layer 1210 and the first active layer 1212 are disposed opposite to each other and insulated from each other. The first source-drain layer 1213 is located at both ends of the first active layer 1212. The region of the first active layer 1212 that is offset from the first source-drain layer 1213 is the channel region 40. The conductive layer 13b is made of metal, and its orthographic projection on the substrate 11 at least partially overlaps with the orthographic projection of the first active layer 1212 on the substrate 11. The position and size of the conductive layer 13b can be adjusted. Optionally, the orthographic projection of the first active layer 1212 on the substrate 11 is located within the orthographic projection of the conductive layer 13b on the substrate 11. In actual design, the area of the conductive layer 13b is larger than the area of the first active layer 1212 so that the conductive layer 13b can completely block the first active layer 1212 and prevent the characteristics of the first thin-film transistor 121 from being affected by light.
[0066] The pixel electrode layer 14 is made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode layer 14 is electrically connected to the first source / drain layer 1213. An insulating layer 16 is provided between the pixel electrode layer 14 and the conductive layer 13b to insulate the pixel electrode layer 14 from the conductive layer 13b. The insulating layer 16 is made of resin.
[0067] like Figure 3 and Figure 4 As shown, by electrically connecting the conductive layer 13b to the first gate layer 1210, when a gate turn-on voltage is applied to the first thin-film transistor 121, the conductive layer 13b also has a voltage, allowing the conductive layer 13b to serve as the top gate of the thin-film transistor. At this time, the front channel region 42 in the channel region 40 is subjected to the positive voltage of the first gate layer 1210, causing electrons to accumulate and becoming the main conductive channel; the conductive layer 13b also exerts a positive voltage on the channel, attracting some electrons to accumulate in the back channel region 41 in the channel region 40, thus also becoming a conductive channel. This is equivalent to increasing the channel width of the first thin-film transistor 121, thereby increasing the on-state current of the first thin-film transistor 121, improving the charging rate of the first thin-film transistor 121 and the refresh rate of the display device.
[0068] In practice, the electrical connection between the conductive layer 13b and the first gate layer 1210 can be achieved in various ways. For example, a via (not shown in the figure) can be provided in a region offset from the first thin-film transistor 121, and then the conductive layer 13b can be connected to the first gate layer 1210 through the via. The specific method can be adjusted according to the actual situation. However, if the conductive layer 13b and the first gate layer 1210 are directly connected, when a gate turn-off voltage (VGL) is applied to the first gate layer 1210 and the first thin-film transistor 121 is in the off state, the conductive layer 13b still has a voltage, and its magnitude is the same as the gate turn-off voltage. The voltage on the conductive layer 13b will affect the turn-off of the first thin-film transistor 121, resulting in abnormal display refresh.
[0069] Optional, combined Figure 3 and Figure 5 As shown in the embodiments of this application, the switching device layer 12 further includes a second thin-film transistor 122, which is offset from the first thin-film transistor 121. The second thin-film transistor 122 includes a second gate layer 1220 and a second source-drain layer 1223. The first gate layer 1210 and the second gate layer 1220 are electrically connected, and the second source-drain layer 1223 is electrically connected to the conductive layer 13b. Since the first gate layer 1210 and the second gate layer 1220 are electrically connected, when a gate turn-on voltage is applied to the first gate layer 1210, the second gate layer 1220 also has the same voltage as the first gate layer 1210. When the first thin-film transistor 121 is in the turn-on state, the second thin-film transistor 122 is also in the turn-on state, and the channel region 40 of the second thin-film transistor 122 is turned on, i.e. Figure 5 The second source / drain layer 1223 on the left and the second source / drain layer 1223 on the right are electrically connected, thereby giving the conductive layer 13b, which is electrically connected to the second source / drain layer 1223, a voltage. The magnitude of the voltage on the conductive layer 13b is... Figure 5 The voltage on the second source-drain layer 1223 on the left side is the same, and the voltage on the conductive layer 13b can be controlled by controlling the voltage applied to the second source-drain layer 1223.
[0070] When a gate turn-off voltage is applied to the first gate layer 1210, the first thin-film transistor 121 and the second thin-film transistor 122 are in the off state. Figure 5 The second source-drain layer 1223 on the left and the second source-drain layer 1223 on the right are disconnected, and the voltage on the second source-drain layer 1223 on the right is zero. Since there is no storage capacitor, the voltage on the conductive layer 13b cannot be maintained, and the voltage on the conductive layer 13b is also zero, thereby avoiding any impact on the first thin-film transistor 121 which is in the off state.
[0071] Since the conductive layer 13b is electrically connected to the second source / drain layer 1223, the magnitude of the voltage on the conductive layer 13b is... Figure 5 The voltage on the second source-drain layer 1223 is the same, and the voltage on the conductive layer 13b can be controlled by controlling the voltage applied to the second source-drain layer 1223. Optionally, in embodiments of this application, combined with Figure 3 , Figure 4 and Figure 5 As shown, the switching device layer 12 includes a gate line 1200, which is electrically connected to the first gate layer 1210 and the second gate layer 1220, respectively. The gate line 1200 is also electrically connected to the second source-drain layer 1223. The gate line 1200, the first gate layer 1210, and the second gate layer 1220 are disposed on the same layer. By electrically connecting the gate line 1200 to the first gate layer 1210 and the second gate layer 1220, the first thin-film transistor 121 and the second thin-film transistor 122 can be controlled by the same gate line 1200 to achieve switching, making control more convenient. Furthermore, since the gate line 1200 is electrically connected to the second source-drain layer 1223, and the second source-drain layer 1223 is electrically connected to the conductive layer 13b, when the first thin-film transistor 121 receives the gate turn-on voltage, the voltage on the conductive layer 13b is the same as the gate turn-on voltage. Therefore, the effect of the conductive layer 13b on the back channel region 41 can be consistent with the effect of the first gate layer 1210 on the front channel region 42, which is beneficial to increase the channel width of the first thin-film transistor 121 and increase the on-state current of the first thin-film transistor 121. The co-layer arrangement of the gate line 1200, the first gate layer 1210, and the second gate layer 1220 means that during the fabrication of the array substrate 10, the gate line 1200, the first gate layer 1210, and the second gate layer 1220 are formed in a single patterning process, which simplifies the fabrication process and saves manufacturing costs.
[0072] It should be noted that the position of the second thin-film transistor 122 can be adjusted according to the actual situation. For example... Figure 3 As shown, in an embodiment of this application, the array substrate 10 includes a plurality of pixel regions 20. Figure 3 Only one pixel region 20 is shown in the diagram, along with a non-display region 21 located between multiple pixel regions 20. The second thin-film transistor 122 is located in the non-display region 21. The pixel region 20 is the area corresponding to the pixel electrode. By placing the second thin-film transistor 122 in the non-display region 21, the space of the pixel region 20 can be avoided when the second thin-film transistor 122 is placed in the pixel region 20.
[0073] Optional, combined Figure 3 and Figure 5As shown, in the embodiments of this application, the orthographic projection of the second thin-film transistor 122 on the substrate 11 overlaps with the orthographic projection of the gate line 1200 on the substrate 11, and the portion of the gate line 1200 corresponding to the second thin-film transistor 122 is multiplexed as the second gate layer 1220. Specifically, the second thin-film transistor 122 is disposed at a position corresponding to the gate line 1200, and a portion of the gate line 1200 is multiplexed as the second gate layer 1220, thereby simplifying the film layer structure of the array substrate 10. When fabricating the array substrate 10, it is not necessary to fabricate the second gate layer 1220 separately, which helps to simplify the fabrication process.
[0074] In the embodiments of this application, combined with Figure 3 , Figure 4 and Figure 5 As shown, the first thin-film transistor 121 includes a first gate insulating layer 1211 disposed between the first gate layer 1210 and the first source-drain layer 1213, and the second thin-film transistor 122 includes a second gate insulating layer 1221 disposed between the second gate layer 1220 and the second source-drain layer 1223. The first gate insulating layer 1211 and the second gate insulating layer 1221 are disposed in the same layer. The first gate insulating layer 1211 is used to insulate the first gate layer 1210 and the first active layer in the region corresponding to the first active layer 1212, and the second gate insulating layer 1221 is used to insulate the second gate layer 1220 and the second active layer in the region corresponding to the second active layer 1222. The materials of the first gate insulating layer 1211 and the second gate insulating layer 1221 include materials with good insulating properties such as silicon oxide or silicon nitride, which can be determined according to the actual situation. The co-layer arrangement of the first gate insulating layer 1211 and the second gate insulating layer 1221 means that during the fabrication of the array substrate 10, the first gate insulating layer 1211 and the second gate insulating layer 1221 can be fabricated in a single patterning process, thereby simplifying the fabrication process. A first via 31 is provided on the second gate insulating layer 1221, through which the second source-drain layer 1223 passes and is electrically connected to the gate line 1200. Connecting the second source-drain layer 1223 and the gate line 1200 via the first via 31 results in a relatively simple structure that is easy to implement. The position of the first via 31 corresponds to the position of the second source-drain layer 1223, and can be determined according to the specific circumstances.
[0075] In embodiments of this application, the array substrate 10 further includes a passivation layer 15, the material of which includes an insulating material such as silicon oxide or silicon nitride. The specific location of the passivation layer 15 can be determined according to actual conditions; optionally, it can be combined with... Figure 3 and Figure 5As shown, a passivation layer 15 is disposed between the switching device layer 12 and the conductive layer 13b. A second via 32 is provided on the passivation layer 15, and the position of the second via 32 corresponds to the position of the second thin-film transistor 122. The conductive layer 13b passes through the second via 32 and is electrically connected to the second source-drain layer 1223. By making the conductive layer 13b electrically connected to the second source-drain layer 1223 through the second via 32, it is easy to implement in terms of process.
[0076] It should be noted that the specific location of the insulating layer 16 between the pixel electrode layer 14 and the conductive layer 13b can be determined according to the actual situation. Optionally, it can be combined with... Figure 3 , Figure 4 and Figure 5 As shown, the insulating layer 16 is disposed between the conductive layer 13b and the pixel electrode layer 14. The insulating layer 16 is disposed below the conductive layer 13b (e.g., Figure 2 Compared to the method shown, only a second via 32 needs to be provided on the passivation layer 15 to achieve electrical connection between the conductive layer 13b and the second source / drain layer 1223, avoiding the need to drill deep holes (i.e., to open vias that penetrate the passivation layer 15 and the insulating layer 16), which helps to simplify the manufacturing process.
[0077] In the embodiments of this application, such as Figure 5 As shown, the second thin-film transistor 122 includes a second active layer 1222 disposed between the second gate layer 1220 and the second source-drain layer 1223, wherein the first active layer 1212 and the second active layer 1222 are disposed on the same layer; and / or, the first source-drain layer 1213 and the second source-drain layer 1223 are disposed on the same layer. The co-location of the first active layer 1212 and the second active layer 1222 means that the first active layer 1212 and the second active layer 1222 are formed through a single patterning process during the fabrication of the array substrate 10. The co-location of the first source-drain layer 1213 and the second source-drain layer 1223 means that the first source-drain layer 1213 and the second source-drain layer 1223 are formed through a single patterning process during the fabrication of the array substrate 10. Optionally, combined with... Figure 3 , Figure 4 and Figure 5 As shown, the first active layer 1212 and the second active layer 1222 are disposed on the same layer, and the first source-drain layer 1213 and the second source-drain layer 1223 are also disposed on the same layer, thereby simplifying the structure and fabrication process of the array substrate 10.
[0078] It should be noted that the materials of the first active layer 1212 and the second active layer 1222 can be indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), or polycrystalline silicon. When amorphous silicon is used as the active layer, the thin-film transistor exhibits less self-heating and better stability. Alternatively, such as... Figure 4 and Figure 5 As shown, both the first active layer 1212 and the second active layer 1222 include a direction along the substrate 11 pointing towards the pixel electrode layer 14. Figure 4 and Figure 5 An intrinsic semiconductor layer 100 and a doped layer 101 are sequentially stacked in a vertically upward direction. The intrinsic semiconductor layer 100 is made of undoped amorphous silicon. The doped layer 101 can be formed by first depositing an amorphous silicon layer and then performing a doping process on the amorphous silicon layer. In the embodiments of this application, in order to make the conductive layer 13b have a positive voltage effect on the channel, that is, to attract some electrons to accumulate in the back channel region 41 in the channel region 40, thereby increasing the channel width of the first thin film transistor 121 and increasing the on-state current of the first thin film transistor 121, an N-type doping process is performed on the amorphous silicon layer during the fabrication of the doped layer 101, so that the doped layer 101 is an N-type semiconductor layer.
[0079] In embodiments of this application, the orthographic projection of the conductive layer 13b onto the substrate 11 at least partially overlaps with the orthographic projection of the second active layer 1222 onto the substrate 11. The specific location and size of the conductive layer 13b can be determined according to actual conditions; optionally, in combination with... Figure 3 and Figure 5 As shown, the orthographic projection of the conductive layer 13b on the substrate 11 overlaps with the orthographic projection of the second active layer 1222 on the substrate 11. The area of the conductive layer 13b is larger than the area of the second active layer 1222. Therefore, the conductive layer 13b can block the second active layer 1222, preventing the characteristics of the second thin film transistor 122 from being affected by light.
[0080] Based on the same inventive concept, this application also provides a display panel, which includes the array substrate 10 provided in the embodiments of this application. Since the display panel includes the array substrate 10 provided in the embodiments of this application, the display panel has the same beneficial effects as the array substrate 10, which will not be described again here.
[0081] Based on the same inventive concept, embodiments of this application also provide a method for fabricating an array substrate 10, such as... Figure 6 As shown, the manufacturing method includes:
[0082] S101, Provide a substrate;
[0083] S102. A switching device layer is fabricated on one side of the substrate. The switching device layer includes a first thin film transistor. The first thin film transistor includes a first gate layer, a first active layer, and a first source-drain layer.
[0084] S103. A conductive layer is formed on the side of the switching device layer away from the substrate, so that the conductive layer is electrically connected to the first gate layer, and the orthogonal projection of the conductive layer on the substrate and the orthogonal projection of the first active layer on the substrate at least partially overlap.
[0085] S104. A pixel electrode layer is formed on the side of the conductive layer away from the substrate. The pixel electrode layer is electrically connected to the first source and drain layer, and the pixel electrode layer is insulated from the conductive layer.
[0086] In the manufacturing method provided in this application embodiment, by electrically connecting the conductive layer 13b to the first gate layer 1210, when a gate turn-on voltage is applied to the first thin-film transistor 121, the conductive layer 13b also has a voltage, allowing the conductive layer 13b to serve as the top gate of the thin-film transistor. At this time, the front channel region 42 in the channel region 40 is subjected to the positive voltage of the first gate layer 1210, causing electrons to accumulate and becoming the main conductive channel; the conductive layer 13b also exerts a positive voltage on the channel, attracting some electrons to accumulate in the back channel region 41 in the channel region 40, thus also becoming a conductive channel, which is equivalent to increasing the channel width of the first thin-film transistor 121. This increases the on-state current of the first thin-film transistor 121, improves the charging rate of the first thin-film transistor 121 and the refresh rate of the display device, without increasing the manufacturing cost.
[0087] Specifically, in this embodiment of the application, a switching device layer 12 is fabricated on one side of the substrate 11, including:
[0088] A first gate layer, a second gate layer, and gate lines are fabricated on one side of a substrate using a patterning process.
[0089] A first gate insulating layer is fabricated on the side of the first gate layer away from the substrate using a patterning process, and a second gate insulating layer is fabricated on the side of the second gate layer away from the substrate.
[0090] The first active layer is fabricated on the side of the first gate insulating layer away from the substrate using a patterning process, and the second active layer is fabricated on the side of the second gate layer away from the substrate.
[0091] A first source-drain layer is fabricated on the side of the first active layer away from the substrate using a patterning process, and a second source-drain layer is fabricated on the side of the second active layer away from the substrate to form a first thin-film transistor and a second thin-film transistor.
[0092] A conductive layer 13b is formed on the side of the switching device layer away from the substrate 11, including:
[0093] A passivation layer is formed on the side of the switching device layer away from the substrate, and a second via is formed in the passivation layer at a position corresponding to the position of the second source and drain layer.
[0094] A conductive layer is fabricated on the side of the passivation layer away from the substrate, and the conductive layer is electrically connected to the second source and drain layer through a second via.
[0095] The specific process of fabricating the array substrate 10 in the embodiments of this application is described in detail below with reference to the accompanying drawings. The patterning process in the embodiments of this application includes the processes of coating, exposing, developing, etching, and removing part or all of the photoresist.
[0096] like Figure 7a As shown, a substrate 11 is first provided.
[0097] like Figure 7b As shown, a first gate layer 1210, a second gate layer 1220, and a gate line 1200 are then fabricated on the substrate 11 using a patterning process. The first gate layer 1210 is located in the region where the first thin-film transistor 121 is to be fabricated, and the second gate layer 1220 is located in the region where the second thin-film transistor 122 is to be fabricated. Specifically, the gate line 1200 is reused as the second gate layer 1220, that is, the position on the gate layer 1200 corresponding to the position of the second thin-film transistor 122 is used as the second gate layer 1220.
[0098] like Figure 7c As shown, a first gate insulating layer 1211 is formed on the side of the first gate layer 1210 away from the substrate 11 using a patterning process, and a second gate insulating layer 1221 is formed on the side of the second gate layer 1220 away from the substrate 11. A first via 31 is formed in the second gate insulating layer 1221, extending to the gate line 1200. The materials of the first gate insulating layer 1211 and the second gate insulating layer 1221 include materials with good insulating properties such as silicon oxide or silicon nitride.
[0099] like Figure 7d As shown, next, a first active layer 1212 is fabricated on the side of the first gate insulating layer 1211 away from the substrate 11 using a patterning process, and a second active layer 1222 is fabricated on the side of the second gate insulating layer 1221 away from the substrate 11. Specifically, two layers of amorphous silicon are first deposited on the side of the first gate insulating layer 1211 and the second gate insulating layer 1221 away from the substrate 11, then the amorphous silicon layers are patterned, and finally the upper amorphous silicon layer is N-type doped to form a stacked intrinsic semiconductor layer 100 and a doped layer 101.
[0100] like Figure 7e As shown, a first source-drain layer 1213 is then fabricated on the side of the first active layer 1212 away from the substrate 11 using a patterning process to form a first thin-film transistor 121; a second source-drain layer 1223 is fabricated on the side of the second active layer 1222 away from the substrate 11, and the second source-drain layer 1223 is connected to the gate line 1200 through the first via 31 to form a second thin-film transistor 122.
[0101] like Figure 7fAs shown, a passivation layer 15 is then formed on the side of the first source-drain layer 1213 and the second source-drain layer away from the substrate 11, and a second via 32 is formed on the passivation layer 15 by a patterning process. The position of the second via 32 corresponds to the position of the second thin film transistor 122.
[0102] like Figure 7g As shown, a conductive layer 13b is then fabricated on the side of the passivation layer 15 away from the substrate 11 using a patterning process. The conductive layer 13b is then electrically connected to the second source / drain layer 1223 through the second via 32. The orthographic projection of the conductive layer 13b on the substrate 11 overlaps with the orthographic projections of the first thin-film transistor 121 and the second thin-film transistor 122 on the substrate 11. The material of the conductive layer 13b includes metal.
[0103] like Figure 7h As shown, next, an insulating layer 16 is formed on the side of the conductive layer 13b away from the substrate 11 by a patterning process. The material of the insulating layer 16 includes resin.
[0104] like Figure 7i As shown, next, a pixel electrode layer 14 is fabricated on the side of the insulating layer 16 away from the substrate 11 by a patterning process to complete the fabrication of the array substrate 10.
[0105] By applying the embodiments of this application, at least the following beneficial effects can be achieved:
[0106] 1. In the embodiments of this application, the array substrate 10 electrically connects the conductive layer 13b to the first gate layer 1210. When a gate turn-on voltage is applied to the first thin-film transistor 121, the conductive layer 13b also has a voltage, allowing the conductive layer 13b to serve as the top gate of the thin-film transistor. At this time, the front channel region 42 in the channel region 40 is subjected to the positive pressure of the first gate layer 1210, causing electrons to accumulate and becoming the main conductive channel. The conductive layer 13b also exerts a positive pressure on the channel, attracting some electrons to accumulate in the back channel region 41 in the channel region 40, thus also becoming a conductive channel. This is equivalent to increasing the channel width of the first thin-film transistor 121, thereby increasing the on-state current of the first thin-film transistor 121, improving the charging rate of the first thin-film transistor 121 and the refresh rate of the display device.
[0107] 2. By providing a second thin-film transistor 122 in the switching device layer 12 and electrically connecting the second source-drain layer 1223 of the second thin-film transistor 122 to the conductive layer 13b, and electrically connecting the second gate layer 1220 of the second thin-film transistor 122 to the first gate layer 1210 of the first thin-film transistor 121, when a gate turn-off voltage is applied to the first gate layer 1210, the first thin-film transistor 121 and the second thin-film transistor 122 are in the off state. Since there is no storage capacitor, the voltage on the conductive layer 13b cannot be maintained, and the voltage on the conductive layer 13b is also zero, thereby avoiding any impact on the first thin-film transistor 121 which is in the off state.
[0108] 3. In the embodiments of this application, by placing the second thin-film transistor 122 at a position corresponding to the gate line 1200, a portion of the gate line 1200 is reused as the second gate layer 1220, thereby simplifying the film layer structure of the array substrate 10. When fabricating the array substrate 10, it is not necessary to fabricate the second gate layer 1220 separately, which helps to simplify the fabrication process.
[0109] 4. In the embodiments of this application, an insulating layer 16 is disposed between the conductive layer 13b and the pixel electrode layer 14. Compared with the method of disposing the insulating layer 16 below the conductive layer 13b, only a second via 32 needs to be provided on the passivation layer 15 to achieve electrical connection between the conductive layer 13b and the second source / drain layer 1223, avoiding the need for deep vias (i.e., opening vias that penetrate the passivation layer 15 and the insulating layer 16), which helps to simplify the manufacturing process.
[0110] 5. In the embodiments of this application, the materials of the first active layer 1212 and the second active layer 1222 are amorphous silicon, which results in a smaller self-heating effect and better stability of the thin film transistor. By making the first active layer 1212 and the second active layer 1222 include an intrinsic semiconductor layer 100 and a doped layer 101 sequentially stacked along the direction from the substrate 11 to the pixel electrode layer 14, even if the first active layer 1212 and the second active layer 1222 are a double-layer structure, it is beneficial to increase the channel width of the first thin film transistor 121, so as to increase the on-state current of the first thin film transistor 121.
Claims
1. An array substrate, characterized in that, include: Substrate; A switching device layer is disposed on one side of the substrate and includes a first thin-film transistor, wherein the first thin-film transistor includes a first gate layer, a first active layer and a first source-drain layer; A conductive layer is disposed on the side of the switching device layer away from the substrate, wherein the orthographic projection of the conductive layer on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate, so as to shield the first active layer. A pixel electrode layer is disposed on the side of the conductive layer away from the substrate, and the pixel electrode layer is electrically connected to the first source and drain layer; The conductive layer is insulated from the pixel electrode layer. The switching device layer further includes a second thin-film transistor, which is offset from the first thin-film transistor. The second thin-film transistor includes a second gate layer and a second source / drain layer; The switching device layer further includes a gate line, which is electrically connected to the first gate layer and the second gate layer respectively. The gate line is electrically connected to one side of the second source-drain layer, and the other side of the second source-drain layer is electrically connected to the conductive layer.
2. The array substrate according to claim 1, characterized in that, The gate line, the first gate layer, and the second gate layer are disposed on the same layer.
3. The array substrate according to claim 2, characterized in that, The array substrate includes multiple pixel areas and a non-display area located between the multiple pixel areas, and the second thin-film transistor is located in the non-display area.
4. The array substrate according to claim 3, characterized in that, The orthographic projection of the second thin-film transistor on the substrate overlaps with the orthographic projection of the gate line on the substrate, and the portion of the gate line corresponding to the second thin-film transistor is multiplexed as the second gate layer.
5. The array substrate according to claim 2, characterized in that, The first thin-film transistor includes a first gate insulating layer disposed between the first gate layer and the first source-drain layer, and the second thin-film transistor includes a second gate insulating layer disposed between the second gate layer and the second source-drain layer, wherein the first gate insulating layer and the second gate insulating layer are disposed in the same layer; The second gate insulating layer has a first via, and the second source-drain layer passes through the first via and is electrically connected to the gate line.
6. The array substrate according to claim 2, characterized in that, The array substrate further includes a passivation layer disposed between the switching device layer and the conductive layer. The passivation layer has a second via, the position of which corresponds to the position of the second thin film transistor. The conductive layer passes through the second via and is electrically connected to the second source-drain layer.
7. The array substrate according to claim 2, characterized in that, The array substrate includes an insulating layer disposed between the conductive layer and the pixel electrode layer.
8. The array substrate according to claim 2, characterized in that, The second thin-film transistor includes a second active layer disposed between the second gate layer and the second source / drain layer; The first active layer and the second active layer are disposed on the same layer; and / or, the first source-drain layer and the second source-drain layer are disposed on the same layer.
9. The array substrate according to claim 8, characterized in that, Both the first active layer and the second active layer include an intrinsic semiconductor layer and a doped layer that are sequentially stacked along the direction from the substrate to the pixel electrode layer.
10. The array substrate according to claim 8, characterized in that, The orthographic projection of the conductive layer on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate.
11. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 10.
12. A method for fabricating an array substrate, characterized in that, The method for manufacturing an array substrate as described in any one of claims 1 to 10 includes: Provide a substrate; A switching device layer is fabricated on one side of the substrate. The switching device layer includes a first thin-film transistor, which includes a first gate layer, a first active layer, and a first source-drain layer. A conductive layer is formed on the side of the switching device layer away from the substrate, and the conductive layer is electrically connected to the first gate layer. The orthographic projection of the conductive layer on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate. A pixel electrode layer is formed on the side of the conductive layer away from the substrate, and the pixel electrode layer is electrically connected to the first source / drain layer; the formation of a switching device layer on one side of the substrate includes: A first gate layer, a second gate layer, and gate lines are fabricated on one side of the substrate using a patterning process. A first gate insulating layer is fabricated on the side of the first gate layer away from the substrate using a patterning process, and a second gate insulating layer is fabricated on the side of the second gate layer away from the substrate. A first active layer is fabricated on the side of the first gate insulating layer away from the substrate using a patterning process, and a second active layer is fabricated on the side of the second gate layer away from the substrate. A first source / drain layer is fabricated on the side of the first active layer away from the substrate using a patterning process, and a second source / drain layer is fabricated on the side of the second active layer away from the substrate to form a first thin-film transistor and a second thin-film transistor. The step of fabricating a conductive layer on the side of the switching device layer away from the substrate includes: A passivation layer is formed on the side of the switching device layer away from the substrate, and a second via is formed in the passivation layer at a position corresponding to the position of the second source and drain layer; A conductive layer is formed on the side of the passivation layer away from the substrate, and the conductive layer is electrically connected to the second source and drain layer through the second via.