Radio frequency amplification circuit

Abstract

The present application provides a radio frequency amplification circuit which suppresses variation in the output phase of an output signal regardless of the signal level of the output signal. The RF amplification circuit includes: a first amplification transistor which amplifies a radio frequency signal supplied to a base and outputs the radio frequency signal; a first bias transistor which is connected in current mirror to the first amplification transistor and supplies bias to the base of the first amplification transistor; a second bias transistor which is connected in emitter follower to the base of the first amplification transistor and supplies bias to the base of the first amplification transistor; and a first capacitor which has a first terminal connected to the base of the first amplification transistor and a second terminal connected to the emitter of the second bias transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to a radio frequency amplification circuit. BACKGROUND

[0002] In a mobile communication apparatus such as a portable telephone, a radio frequency (RF) amplification circuit is used in order to amplify the power of an RF signal to be transmitted to a base station. In such an RF amplification circuit, an amplification circuit that amplifies an RF signal and a bias circuit that applies a bias to an amplification transistor that constitutes the amplification circuit are included (for example, Patent Literature 1).

[0003] PRIOR ART LITERATURE

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent No. 5939404

[0006] In the RF amplification circuit described in Patent Literature 1, a bias is supplied to the amplification transistor by a first bias transistor that is connected in current mirror with the amplification transistor and a second bias transistor that is connected in emitter follower with the amplification transistor.

[0007] In the RF amplification circuit described in Patent Literature 1, even if a control voltage applied to the base of the second bias transistor is a low voltage of 2.35 V, a bias can be supplied by the first bias transistor in a low level region in which the signal level of the RF signal is small, and a bias can be supplied by the second bias transistor in a region in which the signal level of the RF signal is large. Thus, the variation in the gain in the RF amplification circuit can be suppressed from the low level region to the high level region.

[0008] On the other hand, the output phase of an RF signal (hereinafter, sometimes referred to as an output signal) that is amplified and output by the RF amplification circuit sometimes varies depending on the signal level of the output signal. The output phase of the output signal is preferably fixed regardless of the signal level of the output signal. SUMMARY

[0009] PROBLEMS TO BE SOLVED BY THE INVENTION

[0010] The present application has been achieved in view of such circumstances, and aims to provide an RF amplification circuit that suppresses the variation in the output phase of an output signal regardless of the signal level of the output signal.

[0011] MEANS FOR SOLVING THE PROBLEMS

[0012] One aspect of the present application relates to an RF amplification circuit including: a first amplification transistor that amplifies a radio frequency signal supplied to a base and outputs the radio frequency signal; a first bias transistor that is connected in a current mirror with the first amplification transistor and supplies a bias to the base of the first amplification transistor; a second bias transistor that is connected in an emitter follower with the base of the first amplification transistor and supplies a bias to the base of the first amplification transistor; and a first capacitor that has a first terminal connected to the base of the first amplification transistor and a second terminal connected to an emitter of the second bias transistor.

[0013] Effects of the Invention

[0014] According to the present application, it is possible to provide an RF amplification circuit that suppresses variation in the output phase of an output signal regardless of the signal level of the output signal. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a circuit diagram of a power amplification circuit according to a first embodiment of the present application.

[0016] Figure 2 is a graph showing an example of the time variation of the voltage at the base of the amplification transistor according to Reference Example 1.

[0017] Figure 3 is a graph showing an example of the time variation of the current at the base of the amplification transistor according to Reference Example 1.

[0018] Figure 4 is a graph showing an example of the IV characteristic at the base of the amplification transistor according to Reference Example 1.

[0019] Figure 5 is a graph showing an example of the time variation of the voltage at the base of the amplification transistor according to Reference Example 2.

[0020] Figure 6 is a graph showing an example of the time variation of the current at the base of the amplification transistor according to Reference Example 2.

[0021] Figure 7 is a graph showing an example of the IV characteristic at the base of the amplification transistor according to Reference Example 2.

[0022] Figure 8 is a graph showing an example of the time variation of the voltage at the base of the amplification transistor according to Reference Example 3.

[0023] Figure 9 is a graph showing an example of the time variation of the current at the base of the amplification transistor according to Reference Example 3.

[0024] Figure 10FIG. 5 is a graph showing an example of a time change in voltage at the base of the amplification transistor involved in Reference Example 3.

[0025] Figure 11 FIG. 6 is a graph showing an example of a time change in voltage at the base of the amplification transistor involved in the first embodiment of the present application.

[0026] Figure 12 FIG. 7 is a graph showing an example of a time change in current at the base of the amplification transistor involved in the first embodiment of the present application.

[0027] Figure 13 FIG. 8 is a graph showing an example of IV characteristics at the base of the amplification transistor involved in the first embodiment of the present application.

[0028] Figure 14 FIG. 9 is a graph showing an example of AM / AM characteristics of the RF amplification circuit involved in the first embodiment of the present application.

[0029] Figure 15 FIG. 10 is a graph showing an example of AM / PM characteristics of the RF amplification circuit involved in the first embodiment of the present application.

[0030] Figure 16 FIG. 11 is a graph showing an example of a change in the bias voltage with respect to the input power in the RF amplification circuit involved in the first embodiment of the present application.

[0031] Figure 17 FIG. 12 is a graph showing an example of a change in the bias voltage with respect to the input power at each resistance value of the resistance element 313 involved in the first embodiment of the present application.

[0032] Figure 18 FIG. 13 is a graph showing an example of AM / PM characteristics of the RF amplification circuit at each resistance value of the resistance element 313 involved in the first embodiment of the present application.

[0033] Figure 19 FIG. 14 is a graph showing an example of AM / AM characteristics of the RF amplification circuit at each resistance value of the resistance element 313 involved in the first embodiment of the present application.

[0034] Figure 20 FIG. 15 is a graph showing an example of a frequency change in the impedance ZL1 in the RF amplification circuit involved in the first embodiment of the present application.

[0035] Figure 21 FIG. 16 is a circuit diagram of a power amplification circuit involved in the second embodiment of the present application.

[0036] Figure 22 FIG. 17 is a circuit diagram of a power amplification circuit involved in the third embodiment of the present application.

[0037] Reference Signs

[0038] 1, 2, 3... power amplification circuit

[0039] 11, 12, 13... RF amplification circuit

[0040] 31... RF signal input terminal

[0041] 32... RF signal output terminal

[0042] 35, 36... wiring

[0043] 101, 201... amplifier

[0044] 202... amplification transistor

[0045] 203... capacitor

[0046] 204... resistance element

[0047] 205... final stage HBT bias node

[0048] 301... bias circuit

[0049] 311... current mirror side circuit

[0050] 312... bias transistor

[0051] 313... resistance element

[0052] 314... bias supply node

[0053] 321... emitter follower side circuit

[0054] 322... bias transistor

[0055] 323... resistance element

[0056] 324, 325... transistor

[0057] 326, 331... capacitor

[0058] 401, 402... current source

[0059] 501... amplifier

[0060] 502... amplification transistor

[0061] 503... capacitor

[0062] 504... resistance element

[0063] 505... primary stage HBT bias node

[0064] 601... bias circuit

[0065] 611...current mirror side circuit

[0066] 612...bias transistor

[0067] 613...resistance element

[0068] 614...bias supply node

[0069] 621...emitter follower side circuit

[0070] 622...bias transistor

[0071] 623...resistance element

[0072] 624, 625...transistor

[0073] 626, 631...capacitor

[0074] 701, 702...current source DETAILED DESCRIPTION

[0075] Hereinafter, an embodiment of the present application will be described in detail with reference to the drawings. In addition, the same reference numerals are assigned to the same elements throughout the drawings, and overlapping description will be omitted as much as possible.

[0076] [1st Embodiment]

[0077] A power amplification circuit related to the 1st embodiment will be described. Figure 1 is a circuit diagram of the power amplification circuit related to the 1st embodiment of the present application. The power amplification circuit 1 is provided with an RF amplification circuit 11 and current sources 401 and 402. The RF amplification circuit 11 includes a bias circuit 301 and amplifiers 101 and 201. The RF amplification circuit 11 is a circuit that amplifies an input signal (RF signal) RFin input from an RF signal input terminal 31 and outputs an output signal (amplified signal) RFout from an RF signal output terminal 32.

[0078] In the present embodiment, description will be made assuming that the amplifiers are constituted by bipolar transistors such as heterojunction bipolar transistors (HBTs). The HBTs are formed, for example, using gallium arsenide (GaAs) as a material. In addition, the HBTs can also be structures formed using other semiconductor raw materials.

[0079] The amplifiers 101 and 201 are amplifiers of a primary (driver stage) and an output stage (power stage), respectively. In addition, the amplifier 101 has the same structure as the amplifier 201, and thus detailed description about the amplifier 101 will be omitted.

[0080] The amplifier 101 includes an input terminal 101a connected to the RF signal input terminal 31 to which the input signal RFin is supplied through the wiring 35, and an output terminal 101b connected to the wiring 36 in which the inter-stage node 33 is provided. The amplifier 101 amplifies the input signal RFin input from the input terminal 101a, and outputs the amplified amplified signal RF1 from the output terminal 101b.

[0081] The amplifier 201 includes an input terminal 201a connected to the output terminal 101b of the amplifier 101 through the wiring 36, and an output terminal 201b connected to the RF signal output terminal 32. The amplifier 201 amplifies the amplified signal RF1 input from the input terminal 201a, and outputs the output signal RFout in which the amplified signal RF1 is amplified from the output terminal 201b.

[0082] In detail, the amplifier 201 further includes an amplification transistor 202 (1st amplification transistor), a capacitor 203, and a resistance element 204. The capacitor 203 functions as a matching circuit that matches the impedance between the amplifier 101 and the amplification transistor 202, for example, has a 1st terminal connected to the input terminal 201a, and a 2nd terminal connected to the final stage HBT bias node 205.

[0083] The resistance element 204 has a 1st terminal connected to the bias supply node 314 to which the bias is supplied from the bias circuit 301, and a 2nd terminal connected to the final stage HBT bias node 205. The amplification transistor 202 has a collector connected to the output terminal 201b, a base connected to the final stage HBT bias node 205, and an emitter grounded. The amplification transistor 202 amplifies the amplified signal RF1 supplied to the base, and outputs the amplified output signal RFout from the output terminal 201b to the RF signal output terminal 32. In addition, although not illustrated, the collector of the amplification transistor 202 is supplied with a power supply voltage. Furthermore, a resistance element, a capacitor, and an inductor can be provided in the wiring connecting the collector of the amplification transistor 202 and the power supply, for example.

[0084] The current sources 401 and 402 are each composed of a PMOS (P-channel Metal Oxide Semiconductor), for example, have a 1st terminal connected to a power supply node to which a battery voltage Vbat is supplied, and a 2nd terminal from which a current is output.

[0085] The bias circuit 301 includes a current mirror side circuit 311, an emitter follower side circuit 321, and a capacitor 331 (1st capacitor). The bias circuit 301 supplies the amplification transistor 202 of the amplifier 201 with a bias based on the currents received from the current sources 401 and 402.

[0086] The emitter follower side circuit 321 includes a transistor 322 (a second bias transistor), a resistive element 323, transistors 324 and 325, and a capacitor 326. The emitter follower side circuit 321 supplies a bias to the base of the amplifying transistor 202 on the basis of a current supplied from the current source 402.

[0087] In detail, the resistive element 323, the transistors 324 and 325, and the capacitor 326 supply a bias having a voltage of a given level to the base of the bias transistor 322. Specifically, the resistive element 323 has a first terminal to which a current from the current source 402 is supplied and a second terminal. The transistor 324 has a collector connected to the second terminal of the resistive element 323, a base connected to the collector, and an emitter. Hereinafter, the connection of the collector of a transistor and the base of the transistor will be sometimes referred to as a diode connection. The transistor 325 is diode-connected and has a collector connected to the emitter of the transistor 324 and an emitter grounded. The transistors 324 and 325 each function as a diode, and thus a voltage drop of two diode drops occurs in the path between the collector and the emitter of the transistor 324 and in the path between the collector and the emitter of the transistor 325. That is, the voltage of the collector and the base of the transistor 324 with reference to the ground becomes a voltage of a level corresponding to the voltage drop of two diode drops.

[0088] The capacitor 326 has a first terminal connected to the second terminal of the resistive element 323 and the collector of the transistor 324 and a second terminal grounded. The capacitor 326 stabilizes the voltage of the collector and the base of the transistor 324.

[0089] The bias transistor 322 is emitter-follower-connected to the base of the amplifying transistor 202 and supplies a bias to the base of the amplifying transistor 202. In detail, the bias transistor 322 has a collector connected to a power source node to which a battery voltage Vbat is supplied, a base connected to the second terminal of the resistive element 323, the collector of the transistor 324, and the first terminal of the capacitor 326, and an emitter connected to the bias supply node 314. The emitter of the bias transistor 322 is connected to the base of the amplifying transistor 202 through the resistive element 204, and thus the bias transistor 322 and the resistive element 204 constitute an emitter follower circuit.

[0090] The current mirror side circuit 311 includes a bias transistor 312 (a first bias transistor) and a resistive element 313 (a first resistive element).

[0091] The transistor 312 for bias is connected in a current mirror with the transistor 202 for amplification, and supplies bias to the base of the transistor 202 for amplification. Specifically, the transistor 312 for bias is connected in a diode connection, has a collector to which a current from the current source 401 is supplied, and has an emitter grounded.

[0092] The resistance element 313 has a first end connected to the collector and the base of the transistor 312 for bias, and has a second end connected to the bias supply node 314. The resistance value of the resistance element 313 is, for example, preferably 30 Ω or more and 800 Ω or less. The reason for this will be described later.

[0093] The base of the transistor 312 for bias connected in a diode connection is connected to the base of the transistor 202 for amplification through the resistance element 313 and 204, and thus the transistor 312 for bias and the transistor 202 for amplification constitute a current mirror circuit. As a result, a current corresponding to the size ratio of the transistor 312 for bias and the transistor 202 for amplification flows in the collector of the transistor 202 for amplification due to the current flowing in the collector of the transistor 312 for bias.

[0094] The capacitor 331 has a first end connected to the inter-stage node 33 and has a second end connected to the bias supply node 314. The function of the capacitor 331 will be described later.

[0095] [PROBLEMS]

[0096] The power amplification circuit 1 is mounted, for example, on a mobile communication device such as a portable terminal. A technology of high-speed communication such as CA (Carrier Aggregation) in which multiple frequency bands of waves are simultaneously used for wireless communication in order to increase the transmission capacity in wireless communication is adopted by mobile communication devices, and the circuit structure of the front end in the mobile communication device becomes complex. Furthermore, if the Sub-6 GHz band of waves in 5G (5th generation mobile communication system) is used by the mobile communication device, the circuit structure of the front end becomes more complex. As such, if the circuit structure of the front end becomes complex, there is a tendency for the load loss in the RF amplification circuit to increase. Therefore, for the RF amplification circuit, in addition to the technology of amplifying multiple frequency bands of waves, a technology of generating a large power of waves by amplification is also required. In addition, along with an increase in the number of applications (Applications) that are simultaneously used in the mobile communication device, the demand of the user to extend the duration of the battery is increasing, and a reduction in the power consumption in the mobile communication device is also required.

[0097] For the battery of the mobile communication device, for example, a lithium ion battery can be used. In the case of extending the duration of the lithium ion battery, it is sometimes effective to reduce the specified minimum voltage value (for example, from 3 volts to 2.7 volts).

[0098] However, in a structure in which the amplifying transistor is supplied with bias through the emitter follower circuit, if the battery voltage decreases to 2.7 volts, the DC bias current of the amplifying transistor sometimes becomes almost zero.

[0099] Specifically, the base-emitter rise voltage Vbe of a GaAs-based HBT (hereinafter, sometimes referred to as GaAs-HBT) is, for example, 1.35 volts or so. In a case where the base of the amplifying transistor is supplied with bias through the emitter follower circuit, the sum of the Vbe of the bias transistor constituting the emitter follower circuit and the amplifying transistor becomes approximately the same as the battery voltage, and thus the DC bias current of the amplifying transistor becomes almost zero. In particular, at low temperatures, since the base-emitter rise voltage Vbe becomes large, the bias of the amplifying transistor becomes insufficient, and thus the decrease in the gain of the amplifying transistor becomes apparent.

[0100] Although there is also a method using a BiHEMT (GaAs HBT-HEMT) process which simultaneously integrates a GaAs-HBT and a field effect transistor (FET) having a low rise voltage, the problem is that the process management becomes complicated due to an increase in the conditions for producing homogeneously, and the process cost increases. Thus, in a structure in which the amplifying transistor is supplied with bias through the emitter follower circuit, a technique is required which supplies the amplifying transistor with bias well even in a case where the supply voltage to the emitter follower circuit is low.

[0101] (Reference Example 1)

[0102] Figure 2 is a graph showing an example of the time variation of the voltage at the base of the amplifying transistor involved in Reference Example 1. In addition, in Figure 2 , the horizontal axis represents time with the unit of "ns", and the vertical axis represents voltage with the unit of "V".

[0103] In the bias circuit included in the RF amplification circuit involved in Reference Example 1 (hereinafter, sometimes referred to as the 1st reference circuit), the current mirror side circuit 311 and the capacitor 331 are not provided as compared with the bias circuit 301 shown in Figure 1 . That is, the bias circuit included in the 1st reference circuit includes only the emitter follower side circuit 321.

[0104] The inventors simulated the operation of the 1st reference circuit in a case where the Vbe of the bias transistor 322 and the amplifying transistor 202 is 1.35 volts and the battery voltage Vbat is supplied with 2.7 volts. Furthermore, the frequency of the input signal RFin was 1.9 GHz.

[0105] In Figure 2The diagram shows voltage waveform sets HPV1 and LPV1 representing the time-varying voltage at the final stage HBT bias node 205. Voltage waveform set HPV1 is the voltage waveform set when an input signal RFI is input to the RF signal input terminal 31 while varying the power in 1dBm steps within a high power range of 3dBm (hereinafter, sometimes referred to as large-signal operation). Voltage waveform set LPV1 is the voltage waveform set when an input signal RFI is input to the RF signal input terminal 31 while varying the power in 1dBm steps within a low power range of -10dBm (hereinafter, sometimes referred to as small-signal operation). At the final stage HBT bias node 205, during large-signal operation, a maximum voltage of approximately 1.7 volts is supplied.

[0106] Figure 3 This is a diagram illustrating an example of the time-varying current at the base of the amplifying transistor involved in Reference Example 1. Additionally, in Figure 3 In the diagram, the horizontal axis represents time in "ns" and the vertical axis represents current in "mA".

[0107] exist Figure 3 The diagram shows current waveform groups HPA1 and LPA1 representing the time-varying current at the bias node 205 of the final stage HBT. Current waveform group HPA1 represents the current waveform group during large-signal operation, corresponding to voltage waveform group HPV1. Current waveform group LPA1 represents the current waveform group during small-signal operation, corresponding to voltage waveform group LPV1.

[0108] like Figure 2 as well as Figure 3 As shown, during small signal operation, current flows through the bias node 205 of the final stage HBT around 0.3ns and 0.8ns, but there are periods between these times when almost no bias current flows.

[0109] Figure 4 This is a diagram illustrating an example of the IV characteristics at the base of the amplifying transistor involved in Reference Example 1. Additionally, in Figure 4 In the diagram, the horizontal axis represents the current in "mA" units, and the vertical axis represents the voltage in "V" units.

[0110] exist Figure 4 The diagram shows the dynamic load line HPD1 based on voltage waveform group HPV1 and current waveform group HPA1, and the dynamic load line LPD1 based on voltage waveform group LPV1 and current waveform group LPA1. The dynamic load line plots the voltage and current values ​​at the same time.

[0111] like Figure 4As shown, the region in which the dynamic load line LPD1 at the time of small signal operation is located is distributed over a wide range. In such a case, the characteristic representing the relationship between the output power and the gain (hereinafter, sometimes referred to as the AM / AM characteristic) sometimes deteriorates. Specifically, the gain at the time of small signal operation can be lower than the gain at the time of large signal operation. Details regarding the AM / AM characteristic will be described later.

[0112] Further, the region in which the dynamic load line LPD1 at the time of small signal operation is located includes a portion along the scale line at which the current is zero mA. This is because the battery voltage Vbat is low, and the base-emitter rising voltage Vbe cannot be supplied to the final stage HBT bias node 205 by the emitter follower side circuit 321 alone, and thus a condition in which the amplification transistor 202 hardly flows a bias current occurs. That is, it is difficult to supply the amplification transistor 202 with a bias to the extent that the first reference circuit operates as a Class A amplification circuit by the emitter follower side circuit 321 alone.

[0113] (Reference Example 2)

[0114] Figure 5 is a graph showing an example of the time variation of the voltage at the base of the amplification transistor involved in Reference Example 2. Further, Figure 5 the method of representation is the same as Figure 2 .

[0115] In the bias circuit included in the RF amplification circuit (hereinafter, sometimes referred to as the second reference circuit) involved in Reference Example 2, a capacitor 331 is not provided as compared with the bias circuit 301 shown in Figure 1 . That is, the bias circuit included in the second reference circuit includes the emitter follower side circuit 321 and the current mirror side circuit 311.

[0116] The inventors simulated the operation of the second reference circuit in a case where the Vbe of the bias transistor 322 and the amplification transistor 202 was 1.35 volts and the battery voltage Vbat supplied was 2.7 volts.

[0117] In Figure 5 , a voltage waveform group HPV2 and LPV2 representing the time variation of the voltage at the final stage HBT bias node 205 is shown. The voltage waveform group HPV2 and LPV2 are voltage waveform groups at the time of large signal operation and at the time of small signal operation, respectively. At the final stage HBT bias node 205, a voltage of approximately 1.7 volts is supplied at the maximum at the time of large signal operation.

[0118] Figure 6 is a graph showing an example of the time variation of the current at the base of the amplification transistor involved in Reference Example 2. Further, Figure 6 the method of representation is the same as Figure 3 .

[0119] In Figure 6 , a current waveform group HPA2 and LPA2 showing a time change of current at the final stage HBT bias node 205 are shown. The current waveform group HPA2 is a current waveform group at the time of large signal operation, and corresponds to the voltage waveform group HPV2. The current waveform group LPA2 is a current waveform group at the time of small signal operation, and corresponds to the voltage waveform group LPV2.

[0120] As Figure 5 and Figure 6 shown, at the time of small signal operation, current flows at the final stage HBT bias node 205, and thus becomes a state where a certain idling current is supplied to the amplifying transistor 202 by the current mirror side circuit 311.

[0121] Figure 7 is a graph showing an example of IV characteristics at the base of the amplifying transistor involved in Reference Example 2. In addition, Figure 7 the method of representation is the same as Figure 4 .

[0122] In Figure 7 , a dynamic load line HPD2 based on the voltage waveform group HPV2 and the current waveform group HPA2 and a dynamic load line LPD2 based on the voltage waveform group LPV2 and the current waveform group LPA2 are shown.

[0123] The region where the dynamic load line LPD2 at the time of small signal operation is located is narrower than the region where the dynamic load line LPD1 shown in Figure 4 is located. This is because a certain idling current is supplied to the amplifying transistor 202 by the current mirror side circuit 311, and thus the decrease in gain at the time of small signal operation is improved, and the AM / AM characteristics are improved.

[0124] Further, the dynamic load line LPD2 at the time of small signal operation is located at a position where, if the current becomes small, the voltage becomes large, and if the current becomes large, the voltage becomes small. This is because the phase of the current and the phase of the voltage differ by 180° or more, and thus in such a case, the characteristics showing the relationship between the output power and the output phase (hereinafter, sometimes referred to as AM / PM characteristics) sometimes deteriorate. Specifically, the change in output phase with respect to the output power does not become fixed, but varies. In addition, details regarding the AM / PM characteristics will be described later.

[0125] A circuit structure is required in which the region where the dynamic load line at the time of small signal operation is located is narrow and the phase of the current and the phase of the voltage coincide.

[0126] (Reference Example 3)

[0127] Figure 8 is a graph showing an example of a time change of a voltage at the base of the amplifying transistor involved in Reference Example 3. Also, Figure 8 the method of representation is the same as Figure 2 .

[0128] In the bias circuit included in the RF amplifying circuit (hereinafter, sometimes referred to as the 3rd reference circuit) involved in Reference Example 3, a current mirror side circuit 311 is not provided as compared with the bias circuit 301 shown in Figure 1 . That is, the bias circuit included in the 3rd reference circuit includes an emitter follower side circuit 321 and a capacitor 331.

[0129] The inventors simulated the operation of the 3rd reference circuit in a case where the Vbe of the bias transistor 322 and the amplifying transistor 202 is 1.35 volts and a battery voltage Vbat of 2.7 volts is supplied.

[0130] In Figure 8 , a voltage waveform group HPV3 and a voltage waveform group LPV3 showing a time change of a voltage at the final stage HBT bias node 205 are shown. The voltage waveform group HPV3 and the voltage waveform group LPV3 are voltage waveform groups at the time of large signal operation and at the time of small signal operation, respectively. At the final stage HBT bias node 205, a voltage of approximately 2.15 volts is supplied at the maximum at the time of large signal operation.

[0131] Figure 9 is a graph showing an example of a time change of a current at the base of the amplifying transistor involved in Reference Example 3. Also, Figure 9 the method of representation is the same as Figure 3 .

[0132] In Figure 9 , a current waveform group HPA3 and a current waveform group LPA3 showing a time change of a current at the final stage HBT bias node 205 are shown. The current waveform group HPA3 is a current waveform group at the time of large signal operation, corresponding to the voltage waveform group HPV3. The current waveform group LPA3 is a current waveform group at the time of small signal operation, corresponding to the voltage waveform group LPV3.

[0133] Figure 10 is a graph showing an example of an IV characteristic at the base of the amplifying transistor involved in Reference Example 3. Also, Figure 10 the method of representation is the same as Figure 4 .

[0134] In Figure 10 , a dynamic load line HPD3 based on the voltage waveform group HPV3 and the current waveform group HPA3 and a dynamic load line LPD3 based on the voltage waveform group LPV3 and the current waveform group LPA3 are shown.

[0135] The dynamic load line LPD3 at the time of small signal operation is located at a position where the voltage becomes smaller if the current becomes smaller and the voltage becomes larger if the current becomes larger. That is, the third reference circuit is improved compared to the second reference circuit so that the phase of the current and the phase of the voltage coincide.

[0136] However, the region in which the dynamic load line LPD3 at the time of small signal operation is located is wider than the region in which the dynamic load line LPD2 shown in FIG. 8 is located. Figure 7 Therefore, the AM / AM characteristic of the third reference circuit is worse than the AM / AM characteristic of the second reference circuit.

[0137] [Effects]

[0138] Figure 11 is a graph showing an example of the time change of the voltage at the base of the amplification transistor involved in the first embodiment of the present application. In addition, the method of representation of Figure 11 is the same as that of Figure 2 .

[0139] The inventors simulated the operation of the RF amplification circuit 11 in the case where the Vbe of the bias transistor 322 and the amplification transistor 202 was 1.35 volts and a battery voltage Vbat of 2.7 volts was supplied.

[0140] In Figure 11 , a voltage waveform group HPV4 and a voltage waveform group LPV4 showing the time change of the voltage at the final stage HBT bias node 205 are shown. The voltage waveform group HPV4 and the voltage waveform group LPV4 are voltage waveform groups at the time of large signal operation and at the time of small signal operation, respectively. At the final stage HBT bias node 205, a voltage of approximately 2.05 volts is supplied at the maximum at the time of large signal operation.

[0141] Figure 12 is a graph showing an example of the time change of the current at the base of the amplification transistor involved in the first embodiment of the present application. In addition, the method of representation of Figure 12 is the same as that of Figure 3 .

[0142] In Figure 12 , a current waveform group HPA4 and a current waveform group LPA4 showing the time change of the current at the final stage HBT bias node 205 are shown. The current waveform group HPA4 is a current waveform group at the time of large signal operation, corresponding to the voltage waveform group HPV4. The current waveform group LPA4 is a current waveform group at the time of small signal operation, corresponding to the voltage waveform group LPV4.

[0143] Figure 13 is a graph showing an example of the IV characteristic at the base of the amplification transistor involved in the first embodiment of the present application. In addition, the method of representation of Figure 13 is the same as that ofFigure 4 The same applies to the dynamic load line LPD4.

[0144] In Figure 13 , a dynamic load line HPV4 based on the voltage waveform group HPV4 and the current waveform group HPA4 and a dynamic load line LPD4 based on the voltage waveform group LPV4 and the current waveform group HPA4 are shown.

[0145] The dynamic load line LPD4 at the time of small signal operation is located at a position where, if the current becomes small, the voltage becomes small, and if the current becomes large, the voltage becomes large. In this case, the phase of the current and the phase of the voltage coincide, and thus the AM / PM characteristics of the RF amplification circuit 11 are improved compared to the AM / PM characteristics of the 2nd reference circuit.

[0146] Further, the region in which the dynamic load line LPD4 at the time of small signal operation is located is narrower than the region in which the dynamic load line LPD3 shown in Figure 10 is located. Thus, the AM / AM characteristics of the RF amplification circuit 11 are improved compared to the AM / AM characteristics of the 3rd reference circuit.

[0147] (AM / AM characteristics)

[0148] Figure 14 is a graph showing an example of the AM / AM characteristics of the RF amplification circuit to which the 1st embodiment of the present application is applied. In addition, in Figure 14 , the horizontal axis indicates the output power with the unit of "dBm", and the vertical axis indicates the gain with the unit of "dBm".

[0149] In the present embodiment, the gain curve G1 indicates the change in the gain with respect to the output power in the RF amplification circuit 11. Here, the output power is the power of the output signal RFout. The gain is indicated by the value obtained by dividing the output power by the power (input power) of the input signal RFin with the unit of "dBm".

[0150] The gain curves GR1, GR2, and GR3 indicate the change in the gain with respect to the output power in the 1st reference circuit, the 2nd reference circuit, and the 3rd reference circuit, respectively.

[0151] As shown in Figure 14 , the gain curves GR1 and GR3 decrease at the time of small output power. This is because, in the 1st reference circuit and the 3rd reference circuit which do not have the current mirror side circuit 311, it is difficult to supply sufficient bias to the final stage HBT bias node 205 at the time of small output power, and thus the amplification transistor 202 does not operate well.

[0152] On the other hand, the gain curve Gl and the gain curve GR2 can ensure the gain even when the output power is small. This is because the RF amplification circuit 11 and the second reference circuit have the current mirror side circuit 311, and thus a sufficient bias can be supplied to the final stage HBT bias node 205 even when the output power is small.

[0153] In addition, regarding the gain curve Gl, since the variation in the gain when the output power is large is small compared to the gain curve GR2, it is preferable.

[0154] That is, in the RF amplification circuit 11, when a small signal operates, a certain idle current is supplied to the amplification transistor 202 by the current mirror side circuit 311, and thus a good AM / AM characteristic can be achieved.

[0155] (AM / PM characteristic)

[0156] Figure 15 is a graph showing an example of the AM / PM characteristic of the RF amplification circuit according to the first embodiment of the present application. In addition, in Figure 15 , the horizontal axis indicates the output power with the unit of "dBm", and the vertical axis indicates the output phase with the unit of .

[0157] In the present embodiment, the phase curve Pl indicates the change in the output phase with respect to the output power in the RF amplification circuit 11. The phase curves PRl, PR2, and PR3 indicate the change in the output phase with respect to the output power in the first reference circuit, the second reference circuit, and the third reference circuit, respectively.

[0158] As shown in Figure 15 , regarding the phase curves PRl and PR3, since the change in the output phase with respect to the change in the output power is large, it is not preferable. The phase curve PR2, although the change in the output phase with respect to the change in the output power is suppressed compared to the phase curves PRl and PR3, the output phase changes in the region where the output power is large. The phase curve Pl, compared to the phase curve PR2, the change in the output phase with respect to the change in the output power is suppressed even in the region where the output power is large by the capacitor 331.

[0159] That is, in the RF amplification circuit 11, by providing the capacitor 331, the phase of the current and the phase of the voltage at the final stage HBT bias node 205 can be made to coincide, and thus a good AM / PM characteristic can be achieved.

[0160] (Self-bias voltage)

[0161] Figure 16is a graph showing an example of the change in the bias voltage in the RF amplification circuit according to the first embodiment of the present application with respect to the input power. Also, in Figure 16 the horizontal axis indicates the input power with the unit of "dBm", and the vertical axis indicates the bias voltage with the unit of "V" mainly in self-bias. Here, the bias voltage is the voltage of the final stage HBT bias node 205.

[0162] In the present embodiment, the bias voltage curve B1 shows the change in the bias voltage in the RF amplification circuit 11 with respect to the input power. The bias voltage curves BR1, BR2, and BR3 show the change in the bias voltage in the first reference circuit, the second reference circuit, and the third reference circuit, respectively, with respect to the input power.

[0163] As shown in Figure 16 , the bias voltage curves B1 and BR3 change such that the bias voltage becomes larger as the input power becomes larger in the case where the input power is greater than -10 dBm. This is because the capacitor 331 is provided in the RF amplification circuit 11 and the third reference circuit, and thus a part of the input power is supplied to the final stage HBT bias node 205 via the capacitor 331, and along with the detection action in the HBT accompanying the power input to the power stage circuit, the function of raising the bias point, that is, the contribution rate of the bias voltage to the self-bias, is exerted. By raising the bias voltage, the AM / AM characteristic and the AM / PM characteristic can be improved.

[0164] On the other hand, in the first reference circuit and the second reference circuit, since the capacitor 331 is not provided, the bias voltage curves BR1 and BR2 change such that the bias voltage becomes smaller as the input power becomes larger in the case where the input power is greater than -10 dBm.

[0165] (Resistance value of the resistance element 313)

[0166] Figure 17 is a graph showing an example of the change in the bias voltage with respect to the input power at each resistance value of the resistance element 313 according to the first embodiment of the present application. Also, Figure 17 the method of representation is the same as that of Figure 16 .

[0167] In Figure 17In FIG. 12, a bias voltage curve in a case where the resistance value of the resistance element 313 in the RF amplification circuit 11 is changed by every 10 Ω from 1 Ω to 801 Ω is shown. The bias voltage curves BL and BU indicate changes in the bias voltage with respect to the input power when the resistance value of the resistance element 313 is 1 Ω and 801 Ω, respectively. The bias voltage curve when the resistance value of the resistance element 313 is 11 Ω or more and 791 Ω or less is located between the bias voltage curve BL and the bias voltage curve BU. The bias voltage curve moves in a direction in which the bias voltage becomes larger every time the resistance value of the resistance element 313 is reduced by 10 Ω.

[0168] Figure 18 FIG. 13 is a graph showing an example of the AM / PM characteristics of the RF amplification circuit at each resistance value of the resistance element 313 according to the first embodiment of the present application. In addition, the resistance value of the resistance element 313 is changed by every 10 Ω from 1 Ω to 801 Ω. Figure 18 The method of representation is the same as Figure 15 .

[0169] In Figure 18 , a phase curve in a case where the resistance value of the resistance element 313 in the RF amplification circuit 11 is changed by every 10 Ω from 1 Ω to 801 Ω is shown. The phase curves PL and PU indicate changes in the output phase with respect to the output power when the resistance value of the resistance element 313 is 1 Ω and 801 Ω, respectively. The phase curve when the resistance value of the resistance element 313 is 11 Ω or more and 791 Ω or less is located between the phase curve PL and the phase curve PU. The phase curve moves in a direction in which the output phase becomes smaller every time the resistance value of the resistance element 313 is reduced by 10 Ω.

[0170] As shown in Figure 17 and Figure 18 , if the resistance value of the resistance element 313 becomes larger, the voltage drop of the resistance element 313 in the current mirror side circuit 311 based on the current flowing from the bias transistor 312 to the bias supply node 314 becomes larger. Therefore, if the resistance value of the resistance element 313 becomes larger, the bias voltage becomes smaller (refer to Figure 17 ).

[0171] In a case where the resistance value of the resistance element 313 is large, the bias voltage is small, and thus sufficient bias is not supplied to the amplification transistor 202. Therefore, the change in the output phase with respect to the output voltage becomes large (refer to Figure 18 ). That is, if the resistance value of the resistance element 313 becomes 801 Ω or more, the AM / PM characteristics become poor, and thus the resistance value of the resistance element 313 is preferably 800 Ω or less.

[0172] Figure 19 FIG. 14 is a graph showing an example of the AM / AM characteristics of the RF amplification circuit at each resistance value of the resistance element 313 according to the first embodiment of the present application. In addition, the resistance value of the resistance element 313 is changed by every 10 Ω from 1 Ω to 801 Ω. Figure 19The display method is the same as Figure 14 .

[0173] In Figure 19 , a case where the resistance value of the resistance element 313 in the RF amplification circuit 11 is changed by 10 Ω from 1 Ω to 801 Ω is shown. The gain curves GL and GU indicate changes in gain with respect to output power when the resistance value of the resistance element 313 is 1 Ω and 801 Ω, respectively. The gain curve when the resistance value of the resistance element 313 is 11 Ω or more and 791 Ω or less is located between the gain curve GL and the gain curve GU. The gain curve moves in a direction in which gain becomes smaller each time the resistance value of the resistance element 313 is reduced by 10 Ω.

[0174] Figure 20 is a graph showing an example of a frequency change in the impedance ZL1 in the RF amplification circuit according to the first embodiment of the present application. In Figure 20 , a change curve Z-PA based on a simulation result of the impedance ZL1 (refer to Figure 1 ) when the amplifier 201 is observed from the output terminal 101b of the amplifier 101 is shown on a Smith chart.

[0175] In detail, the change curve Z-PA is a value obtained by dividing the calculated value of the impedance ZL1 when the resistance value of the resistance element 313 is 1 Ω by the characteristic impedance when the frequency is changed from 1.89 GHz to 1.91 GHz. In Figure 20 , the symbol "m5" indicates the impedance ZL1 when the frequency is 1.91 GHz.

[0176] As shown in Figure 19 and Figure 20 , generally, the input impedance of the amplifier 201 of the output stage (power stage) is, for example, as small as approximately 3 Ω. If the resistance value of the resistance element 313 becomes smaller than 30 Ω and the impedance of the current mirror circuit decreases, the ratio of the input impedance of the amplifier 201 to the impedance of the current mirror circuit becomes significantly smaller, and the loss between stages becomes larger. Specifically, as shown in Figure 20 , the change curve Z-PA is located at a position far from the center of the Smith chart, and the impedance is low, and thus it is difficult to make the impedance on the bias circuit side appear large with respect to the power stage input impedance. That is, since the amount of crosstalk in which the RF input power leaks to the bias circuit side increases, as a result, the inter-stage matching loss increases and the gain of the entire power amplifier (PA) decreases. Therefore, in the case where the resistance value of the resistance element 313 is smaller than 30 Ω (for example, 1 Ω), the gain of the RF amplification circuit 11 decreases as in the gain curve GL shown in Figure 19 , and thus the resistance value of the resistance element 313 is preferably 30 Ω or more.

[0177] [Second Embodiment]

[0178] A power amplification circuit according to the second embodiment of the present application will be described. Hereinafter, description will be omitted on matters common to the first embodiment, and only the different points will be described. In particular, the same effects resulting from the same structures will not be mentioned in each of the embodiments.

[0179] Figure 21 is a circuit diagram of a power amplification circuit according to the second embodiment of the present application. A power amplification circuit 2 according to the second embodiment is different from the RF amplification circuit 11 according to the first embodiment in that the connection destination of the first terminal of the capacitor 331 in the RF amplification circuit 12 is different, as shown in Figure 21

[0180] In the power amplification circuit 2, the capacitor 331 in the bias circuit 301 has the first terminal connected to the RF signal input terminal 31 and the input terminal 101a of the amplifier 101 and the second terminal connected to the bias supply node 314.

[0181] [Third Embodiment]

[0182] A power amplification circuit according to the third embodiment of the present application will be described. Figure 22 is a circuit diagram of a power amplification circuit according to the third embodiment of the present application. As shown in Figure 22 , the power amplification circuit 3 according to the third embodiment is different from the power amplification circuit 1 according to the first embodiment in that the RF amplification circuit 13 and the current sources 701 and 702 are provided instead of the RF amplification circuit 11. The RF amplification circuit 13 includes an amplifier 501 and a bias circuit 601, as compared with the RF amplification circuit 11 shown in Figure 1 The amplifier 501 includes an input terminal 501a connected to the RF signal input terminal 31 to which the input signal RFin is supplied through the wiring 35, and an output terminal 501b connected to the wiring 36 in which the inter-stage node 33 is provided. The amplifier 501 amplifies the input signal RFin input from the input terminal 501a, and outputs the amplified amplified signal RF1 from the output terminal 501b.

[0183]

[0184] ​​In detail, the amplifier 501 further includes an amplification transistor 502 (2nd amplification transistor), a capacitor 503, and a resistive element 504. The capacitor 503 functions as a matching circuit that matches the impedance between the amplification transistor 502 and the input terminal 501a, for example, as a device for a pre-stage of the power amplification circuit 3, and has a 1st terminal connected to the input terminal 501a and a 2nd terminal connected to a primary HBT bias node 505.

[0185] The resistive element 504 has a 1st terminal connected to a bias supply node 614 to which a bias supplied from a bias circuit 601 is supplied, and a 2nd terminal connected to the primary HBT bias node 505. The amplification transistor 502 has a collector connected to the output terminal 501b, a base connected to the primary HBT bias node 505, and an emitter grounded. The amplification transistor 502 amplifies an input signal RFin supplied to the base, and outputs the amplified amplification signal RF1 through the output terminal 501b to the amplifier 201. In addition, although not illustrated, the collector of the amplification transistor 502 is supplied with a power supply voltage. Furthermore, a wiring connecting the collector of the amplification transistor 502 and a power supply can be provided with a resistive element, a capacitor, and an inductor, for example.

[0186] The current sources 701 and 702 are each composed of a PMOS, for example, and have a 1st terminal connected to a power supply node to which a battery voltage Vbat is supplied, and a 2nd terminal from which a current is output.

[0187] The bias circuit 601 includes a current mirror side circuit 611, an emitter follower side circuit 621, and a capacitor 631 (2nd capacitor). The bias circuit 601 supplies a bias to the amplification transistor 502 of the amplifier 501 based on the currents received from the current sources 701 and 702.

[0188] The emitter follower side circuit 621 is a circuit having the same structure as the emitter follower side circuit 321, and includes a bias transistor 622 (4th bias transistor), a resistive element 623, transistors 624 and 625, and a capacitor 626. The emitter follower side circuit 621 supplies a bias to the base of the amplification transistor 502 based on the current supplied from the current source 702.

[0189] In detail, the resistance element 623, the transistors 624 and 625, and the capacitor 626 supply a bias of a voltage of a given level to the base of the bias transistor 622. Specifically, the resistance element 623 has a first terminal to which a current from the current source 702 is supplied and a second terminal. The transistor 624 is diode-connected, having a collector connected to the second terminal of the resistance element 623 and an emitter. The transistor 625 is diode-connected, having a collector connected to the emitter of the transistor 624 and an emitter grounded. The transistors 624 and 625 each function as a diode, and thus a voltage drop of two diode drops occurs in a path between the collector and the emitter of the transistor 624 and a path between the collector and the emitter of the transistor 625. That is, the voltage of the collector and the base of the transistor 624 with reference to the ground becomes a voltage of a level equivalent to the voltage drop of two diode drops.

[0190] The capacitor 626 has a first terminal connected to the second terminal of the resistance element 623 and the collector of the transistor 624 and a second terminal grounded. The capacitor 626 stabilizes the voltage of the collector and the base of the transistor 624.

[0191] The bias transistor 622 is emitter-follower-connected to the base of the amplification transistor 502, and supplies a bias to the base of the amplification transistor 502. In detail, the bias transistor 622 has a collector connected to a power source node to which a battery voltage Vbat is supplied, a base connected to the second terminal of the resistance element 623, the collector of the transistor 624, and the first terminal of the capacitor 626, and an emitter connected to the bias supply node 614. The emitter of the bias transistor 622 is connected to the base of the amplification transistor 502 through the resistance element 504, and thus the bias transistor 622 and the resistance element 504 constitute an emitter-follower circuit.

[0192] The current mirror side circuit 611 includes a bias transistor 612 (a third bias transistor) and a resistance element 613 (a second resistance element). The bias transistor 612 is current-mirror-connected to the amplification transistor 502, and supplies a bias to the base of the amplification transistor 502. Specifically, the bias transistor 612 is diode-connected, having a collector to which a current from the current source 701 is supplied and an emitter grounded.

[0193] The resistance element 613 has a first terminal connected to the collector and the base of the bias transistor 612 and a second terminal connected to the bias supply node 614. The resistance value of the resistance element 613 is preferably 30 Ω or more and 800 Ω or less, based on the same reason as the resistance value of the resistance element 313.

[0194] The base of the diode-connected bias transistor 612 is connected to the base of the amplification transistor 502 through the resistive element 613 and the 504, and thus the bias transistor 612 and the amplification transistor 502 constitute a current mirror circuit. As a result, a current corresponding to the size ratio of the bias transistor 612 and the amplification transistor 502 flows in the collector of the amplification transistor 502 due to the current flowing in the collector of the bias transistor 612.

[0195] The capacitor 631 has the same function as the capacitor 331, has a first terminal connected to the node 34 on the input side of the wiring 35, and has a second terminal connected to the bias supply node 614.

[0196] In addition, in the power amplification circuit 1 of the present embodiment, the structure of the RF amplification circuit 11 including the amplifier 101 is described, but the RF amplification circuit 11 can also have a structure in which the amplifier 101 is not included and only the amplifier 201 and the bias circuit 301 are included.

[0197] The above describes an exemplary embodiment of the present application. The RF amplification circuits 11, 12, and 13 have: an amplification transistor 202 that amplifies and outputs an amplification signal RF1 supplied to the base; a bias transistor 312 that is connected in a current mirror with the amplification transistor 202 and supplies bias to the base of the amplification transistor 202; a bias transistor 322 that is connected in an emitter follower with the base of the amplification transistor 202 and supplies bias to the base of the amplification transistor 202; and a capacitor 331 that has a first terminal connected to the base of the amplification transistor 202 and a second terminal connected to the emitter of the bias transistor 322.

[0198] In a case where the supply voltage to the bias transistor 322 is low, only by the bias transistor 322 which is connected to the base of the amplification transistor 202 with an emitter follower, in a case where the power of the input signal is low, the bias to the amplification transistor 202 cannot be supplied sufficiently, and the AM / AM characteristic can sometimes be deteriorated. In contrast to this, by the structure in which the bias transistor 312 which is connected to the amplification transistor 202 with a current mirror is provided, even in a case where the supply voltage to the bias transistor 322 is low, a certain idle current can be supplied to the amplification transistor 202 by the bias transistor 312, and thus the decrease in the gain in a case where the power of the input signal is low can be suppressed. That is, a good AM / AM characteristic can be achieved. On the other hand, in the structure in which the capacitor 331 is not provided, the phases of the voltage of the bias supplied to the base of the amplification transistor 202 and the current by the bias transistors 312 and 322 are deviated, and thus the output phase of the amplified output signal RFout greatly changes depending on the signal level of the output signal RFout. That is, the AM / PM characteristic is deteriorated. In contrast to this, by the structure in which the capacitor 331 is provided between the base of the amplification transistor 202 to which the amplified signal RF1 is supplied and the emitter of the bias transistor 322, a part of the amplified signal RF1 can be supplied to the emitter of the bias transistor 322 through the capacitor 331. Thus, the phases of the voltage of the bias supplied to the base of the amplification transistor 202 and the current can be made coincident, and thus the change in the output phase of the output signal RFout with respect to the signal level of the output signal RFout can be suppressed. That is, a good AM / PM characteristic can be achieved. Therefore, an RF amplification circuit which suppresses the variation in the output phase of the output signal independently of the signal level of the output signal can be provided.

[0199] Further, the RF amplification circuits 11, 12, and 13 further have a resistance element 313 connected between the base of the bias transistor 312 and the emitter of the bias transistor 322.

[0200] By such a structure, the current flowing in the bias transistor 312 can be adjusted, and the AM / AM characteristic and the AM / PM characteristic can be improved.

[0201] Further, in the RF amplification circuits 11, 12, and 13, the resistance value of the resistance element 313 is 30 Ω or more and 800 Ω or less.

[0202] For example, in a case where the resistance value of the resistance element 313 is less than 30 Ω, the gain of the RF amplification circuit 11 sometimes decreases. Also, for example, in a case where the resistance value of the resistance element 313 is more than 800 Ω, the voltage drop in the resistance element 313 becomes large. In this case, it is difficult to supply sufficient bias to the amplification transistor 202, the bias voltage of the power stage HBT is small, and thus the AM / PM characteristic easily deteriorates. In contrast, by configuring the resistance value of the resistance element 313 to be 30 Ω or more and 800 Ω or less, it is possible to suppress the decrease in the gain of the RF amplification circuit 11, improve the AM / AM characteristic, and at the same time, supply sufficient bias to the amplification transistor 202 to improve the AM / PM characteristic.

[0203] Also, the RF amplification circuit 12 further includes the amplifier 101 connected between the 1st terminal of the capacitor 331 and the base of the amplification transistor 202.

[0204] As such, by configuring the 1st terminal of the capacitor 331 to be connected to the input terminal of the primary amplifier 101, it is possible to supply a part of the input signal RFin before amplified by the secondary amplifier to the emitter of the bias transistor 322 through the capacitor 331. This is utilized in a case where the range of low power is mainly utilized as the power dynamic range of the input power utilizing the self-bias effect, and it is desired to accurately perform bias tracking of the input power. Thus, it is possible to adjust the voltage and the current of the bias supplied to the amplification transistor 202 on the basis of the input signal RFin of small power, and thus it is possible to effectively improve the AM / PM characteristic.

[0205] Also, the RF amplification circuit 13 further includes: an amplification transistor 502 that amplifies the input signal RFin input to the base and outputs to the base of the amplification transistor 202; a bias transistor 612 that is current mirror-connected with the amplification transistor 502 and supplies bias to the base of the amplification transistor 502; a bias transistor 622 that is emitter-following-connected with the base of the amplification transistor 502 and supplies bias to the base of the amplification transistor 502; and a capacitor 631 that has a 1st terminal connected to the base of the amplification transistor 502 and a 2nd terminal connected to the emitter of the bias transistor 622.

[0206] With such a configuration, even in a configuration in which two-stage amplification transistors are provided, it is possible to supply good bias to the amplification transistor in each amplification stage, and thus it is possible to achieve good AM / AM characteristics and AM / PM characteristics. Note that a configuration in which three or more stages of amplification transistors are provided can also be employed.

[0207] Also, the RF amplification circuit 13 further includes a resistance element 613 connected between the base of the bias transistor 612 and the emitter of the bias transistor 622.

[0208] With such a configuration, the current flowing through the bias transistor 612 can be adjusted, and the AM / AM characteristics and the AM / PM characteristics can be improved.

[0209] Further, in the RF amplification circuit 13, the resistance value of the resistance element 613 is 30 Ω or more and 800 Ω or less.

[0210] With such a configuration, the decrease in the gain of the RF amplification circuit 13 can be suppressed, the AM / AM characteristics can be improved, and the AM / PM characteristics can be improved by supplying sufficient bias to the amplification transistor 502.

[0211] Note that the above-described embodiments are for facilitating understanding of the present application, and are not intended to limit the interpretation of the present application. The present application can be changed / modified without departing from the spirit thereof, and equivalents thereof are also included in the present application. That is, products to which design changes are appropriately applied by those skilled in the art to each of the embodiments are also included in the scope of the present application, as long as they have the characteristics of the present application. For example, each element and its arrangement, material, condition, shape, size, and the like possessed by each of the embodiments are not limited to the illustrated content, and can be appropriately changed. Further, each of the embodiments is illustrative, and it is self-evident that partial replacement or combination of the structures shown in different embodiments can be made, and these are also included in the scope of the present application, as long as they have the characteristics of the present application.

Claims

1. A radio frequency amplifier circuit, comprising: The first amplifying transistor amplifies and outputs the radio frequency signal supplied to the base. The first bias transistor is connected to the first amplifying transistor via a current mirror to supply bias to the base of the first amplifying transistor. A second bias transistor is connected to the base of the first amplifying transistor via an emitter follower connection, supplying bias to the base of the first amplifying transistor; and The first capacitor has a first terminal connected to the base of the first amplifying transistor and a second terminal connected to the emitter of the second biasing transistor. A current mirror circuit is used for small-signal operations, and an emitter follower circuit is used for large-signal operations.

2. The radio frequency amplifier circuit according to claim 1, wherein, It also has: The first resistive element is connected between the base of the first bias transistor and the emitter of the second bias transistor.

3. The radio frequency amplifier circuit according to claim 2, wherein, The resistance value of the first resistive element is 30Ω or more and 800Ω or less.

4. The radio frequency amplifier circuit according to any one of claims 1 to 3, wherein, It also has: An amplifier is connected between the first terminal of the first capacitor and the base of the first amplifying transistor.

5. The radio frequency amplifier circuit according to any one of claims 1 to 3, wherein, It also has: The second amplifying transistor amplifies the radio frequency signal input to the base and outputs it to the base of the first amplifying transistor; The third bias transistor is connected to the second amplifying transistor via a current mirror to supply bias to the base of the second amplifying transistor. The fourth bias transistor is connected to the base of the second amplifying transistor via an emitter follower connection, and provides bias to the base of the second amplifying transistor. as well as The second capacitor has a first terminal connected to the base of the second amplifying transistor and a second terminal connected to the emitter of the fourth biasing transistor.

6. The radio frequency amplifier circuit according to claim 5, wherein, It also has: The second resistive element is connected between the base of the third bias transistor and the emitter of the fourth bias transistor.

7. The radio frequency amplifier circuit according to claim 6, wherein, The resistance value of the second resistive element is 30Ω or more and 800Ω or less.

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