A system to avoid channel switching in I2S audio interface

Abstract

A system for preventing channel swapping of an I2S audio interface includes a host and a slave, wherein the slave receives a read serial clock signal, a read field selection signal, and serial data synchronized with the read serial clock signal sent by the host, and detects whether the read serial clock signal is abnormally lost; receives a write serial clock signal and a write field selection signal sent by the host, detects whether the write serial clock signal is abnormally lost, and converts parallel data into serial data and sends it to the host. The system for preventing channel swapping of an I2S audio interface of the present invention ensures that channel swapping does not occur in the I2S audio interface when in a sending or receiving mode, so that serial audio data can be correctly transmitted, bringing a better auditory experience to users.

Description

Technical Field

[0001] The present invention relates to the technical field of audio data transmission, and in particular to a system for preventing an I2S audio interface from switching channels. Background Art

[0002] I2S (Inter IC Sound) bus, also known as the integrated circuit built-in audio bus, is a bus standard developed by Philips for audio data transmission between digital audio devices.

[0003] The I2S bus has three main signals: serial data signal (Serial Data abbreviated as SD), word select signal (Word Select abbreviated as WS) and serial clock signal (Serial Clock abbreviated as SCK). It separates the data and clock signals and uses WS to distinguish the left and right channels.

[0004] The existing I2S protocol stipulates that both parties transmit the left channel first and then the right channel. However, if one of the host or the slave violates this agreement, the right channel and the left channel will be swapped, causing the sound heard to be misaligned between the left and right channels. That is, the data of the left and right channels in each frame do not match. The correct transmission and reception is that the left channel of the first frame and the right channel of the first frame are the first complete data frame. After the channel swap occurs, the first right channel and the left channel of the second frame will be merged into one frame, and the right channel of the second frame and the left channel of the third frame will be merged into the second frame, and so on, so that the wrong sound can be heard.

[0005] Therefore, how to avoid channel swapping becomes a key point in I2S interface circuit design. Summary of the invention

[0006] In order to solve the shortcomings of the prior art, the purpose of the present invention is to provide a system to prevent channel switching of an I2S audio interface. As a slave, it is protected at the beginning and end of WS and when WS and SCK end abnormally. As a slave, it can autonomously stop receiving / sending data when the host SCK and WS send abnormalities to avoid channel switching.

[0007] To achieve the above object, the present invention provides a system for preventing channel switching of an I2S audio interface, comprising a host and a slave, wherein:

[0008] The slave receives the read serial clock signal, the read field selection signal, and the serial data synchronized with the read serial clock signal sent by the host, and detects whether the read serial clock signal is abnormally lost; receives the write serial clock signal and the write field selection signal sent by the host, detects whether the write serial clock signal is abnormally lost, and converts the parallel data into serial data and sends it to the host.

[0009] Furthermore, the slave performs transmission anomaly detection on the read serial clock signal, the read field selection signal, the write serial clock signal and the write field selection signal sent by the host, and stops receiving or sending data when any of the above signals is detected to be abnormal.

[0010] Furthermore, the slave includes a slave receiving module and a slave sending module, wherein:

[0011] The slave receiving module receives a read serial clock signal, a read field selection signal, and serial data synchronized with the read serial clock signal sent by the host, and detects whether the read serial clock signal is abnormally lost;

[0012] The slave sending module receives the write serial clock signal and the write serial clock signal sent by the host, detects whether the write serial clock signal is abnormally lost, and converts parallel data into serial data and sends it to the host.

[0013] Furthermore, the slave receiving module further includes a slave reading clock monitor, a slave reading serial-to-parallel converter and a slave receiving buffer, wherein:

[0014] The slave read clock monitor is used to detect whether the read serial clock signal sent by the host is abnormally lost;

[0015] The slave reads the serial-to-parallel converter, which converts the serial data from the host into parallel data and then sends it to the slave receive buffer cache.

[0016] Furthermore, the slave reads the clock monitor, which counts the read serial clock signal, adds 1 to the binary counter for each clock; converts the binary counter into Gray code; synchronizes the Gray code to the system clock domain; generates a register and comparison signal in the system clock domain for a period of time, at which time the value of the Gray code is registered, and the value is compared with the previous registered value; if the two compared values ​​are different, it indicates that the read serial clock signal is normal; if the two values ​​are compared to be the same, it indicates that the read serial clock signal is lost during the comparison of the two values; if the read serial clock signal is lost, the enable signal is turned off, and the slave receive buffer is reset to ensure normal data transmission after the enable signal is turned on next time.

[0017] Furthermore, the slave sending module further includes a slave write clock monitor, a slave write serial-to-parallel converter and a slave sending buffer, wherein:

[0018] The slave write clock monitor is used to detect whether the write serial clock signal sent by the host is abnormally lost;

[0019] The slave write serial-to-parallel converter reads the parallel data of the slave send buffer, converts it into serial data through the write serial clock signal and the write field selection signal, and sends it to the host.

[0020] Furthermore, the slave write clock monitor counts the write serial clock signal, adds 1 to the binary counter for each clock; converts the binary counter into Gray code; synchronizes the Gray code to the system clock domain; generates a register and comparison signal in the system clock domain for a period of time, registers the value of the Gray code, and compares the value with the previous register value; if the two compared values ​​are different, it indicates that the write serial clock signal is normal; if the two values ​​are the same, it indicates that the write serial clock signal is lost during the comparison of the two values; if the write serial clock signal is lost, the enable signal is turned off, and the slave send buffer is reset to ensure normal data transmission after the enable signal is turned on next time.

[0021] In order to achieve the above object, the present invention further provides an audio processing chip, comprising the above system for preventing channel switching from occurring in an I2S audio interface.

[0022] In order to achieve the above object, the present invention also provides an electronic device, comprising the above audio processing chip.

[0023] The system for preventing channel switching of an I2S audio interface of the present invention has the following beneficial effects compared with the prior art:

[0024] The I2S audio interface is protected to avoid the abnormal situation of left and right channel sound misalignment caused by channel swapping; the slave can accurately receive / send data at the beginning of a frame, and automatically stop receiving / sending data when the host SCK and WS send abnormalities; it ensures that the I2S audio interface does not undergo channel swapping in the sending / receiving mode, so that the serial audio data can be transmitted correctly, bringing a better listening experience to users.

[0025] Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0027] Figure 1 A schematic diagram of a system for preventing channel swapping in an I2S audio interface according to the present invention;

[0028] Figure 2A timing diagram of starting protection of a slave according to the present invention;

[0029] Figure 3 A timing diagram of the slave normally ending protection according to the present invention;

[0030] Figure 4 A timing diagram of the slave abnormal termination protection according to the present invention;

[0031] Figure 5 FIG. 4 is a flowchart of the clock monitor according to the present invention. DETAILED DESCRIPTION

[0032] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0033] Example 1

[0034] Figure 1 A schematic diagram of a system for preventing channel switching of an I2S audio interface according to the present invention is shown as follows: Figure 1 As shown, the system for preventing channel switching of an I2S audio interface of the present invention comprises a slave 10 and a host 20, wherein:

[0035] The slave 10 further includes a slave receiving module 11 for receiving serial data from the host 20 and a slave sending module 12 for sending serial data to the host 20 .

[0036] The host 20 further includes a host sending module 21 for sending serial data to the slave 10 and a host receiving module 22 for receiving serial data from the slave 10 .

[0037] The slave receiving module 11 further includes a slave reading clock monitor 111, a slave reading serial-to-parallel converter 112 and a slave receiving buffer 113, wherein:

[0038] The slave read clock monitor 111 is used to detect whether the RXSCK (read serial clock signal) sent by the host sending module 21 of the host 20 is abnormally lost.

[0039] The slave receiving module 11 receives RXSCK (read serial clock signal), RXWS (read field selection signal), and serial data (RXDATA) synchronized with RXSCK sent by the host sending module 21 of the host 20, and after performing serial-to-parallel conversion of the data through the read serial-to-parallel converter 112, sends it to the slave receiving buffer (RX FIFO) 113 for caching.

[0040] The slave sending module 12 further includes a slave write clock monitor 121, a slave write serial-to-parallel converter 122 and a slave send buffer 123, wherein:

[0041] The slave write clock monitor 121 is used to detect whether the TXSCK (write serial clock signal) sent by the host receiving module 22 of the host 20 is abnormally lost.

[0042] The slave write serial-to-parallel converter 122 reads the parallel data from the slave transmit buffer 123 , converts it into serial data through TXSCK and TXWS (write field selection signal), and sends it to the host receiving module 22 of the host 20 .

[0043] Figure 2 The slave starts protection timing diagram according to the present invention, as shown in FIG. Figure 2 As shown, when WS is 1, the left channel data is transmitted, and when WS is 0, the right channel data is transmitted; enable1 and enable2 indicate that the time when the enable signal is synchronized to the SCK clock domain may fall on the left channel or the right channel (the enable signals enable1 and enable2 are generated by the system clock of the slave 10 and synchronized to the receive / send clock domain). If the receiving / sending of data is started immediately after the enable signal is received, the first data transmission error will be caused, and there is a 50% probability that the enable is turned on at the right channel, resulting in a channel swap, causing subsequent data transmission errors. Therefore, in order to avoid channel swaps caused by the randomness of the enable signal, after the slave 20 receives the enable signal, the enable signal is delayed to the beginning of the next frame of left channel data, that is, the data transmission starts at the moment when enable_real changes in the figure, to protect the transmission from channel swaps.

[0044] Figure 3 : is a timing diagram of the slave normally ending protection according to the present invention, such as Figure 3 As shown, enable1 and enable2 indicate that the enable signal is also random when it is turned off, and it may be located in the left channel or the right channel. If data transmission is stopped immediately upon receiving the enable signal turned off, the last data transmission error will be caused, and there is a 50% probability that the enable is turned off at the left channel, resulting in a channel swap, causing the data transmission to be wrong after the next enable is turned on. Therefore, in order to avoid channel swapping caused by the randomness of the enable signal being turned off, after receiving the enable signal turned off, the slave 20 delays the enable signal until the complete right channel data is received, that is, the data transmission is terminated at the change moment of enable_real in the figure, to protect the transmission from channel swapping.

[0045] Figure 4 is a timing diagram of the slave abnormal termination protection according to the present invention, Figure 5 For the working flow diagram of the clock monitor according to the present invention, the following will refer to Figure 4 and Figure 5, the working process of the clock monitor of the present invention is described in detail.

[0046] In the embodiment of the present invention, the slave write clock monitor 121 of the slave sending module 20 is taken as an example to describe its working process. The working process of the slave read clock monitor 111 is similar to that of the slave write clock monitor 121 .

[0047] (1) Count TXSCK, each clock is counter clk_cnt+1, the counter can overflow;

[0048] (2) Convert the binary counter clk_cnt into Gray code;

[0049] (3) synchronizing the Gray code to the system clock domain;

[0050] (4) In the system clock domain, a register and comparison signal cnt_cmp_vld is generated for a period of time, at which time the value of the Gray code is registered and compared with the previous registered value;

[0051] (5) If the two comparison values ​​are different, it means that TXSCK is normal; if the two values ​​are the same, it means that TXSCK is lost during the comparison of the two values;

[0052] (6) If TXSCK is lost, turn off the enable signal and reset the FIFO to ensure normal data transmission after the next enable signal is turned on.

[0053] The system for avoiding channel switching of an I2S audio interface of the present invention is as follows: after the enable signal is turned on, the slave 10 detects the edge of WS and counts, starts counting at the beginning of a frame of data, first receives the left channel, and then receives the right channel; after the enable signal is turned off, the reception / transmission of the complete right channel data is completed before the reception / transmission is actually stopped; in view of the situation that the SCK / WS of the host 10 may be abnormally interrupted, the SCK is monitored, and when the SCK interrupt is detected, the sending / receiving of data is immediately stopped.

[0054] Monitoring method: Set a counter in SCK, add 1 to it for each rising edge of SCK, and synchronize it to the system clock domain in Gray code, recorded as CNT1. The system clock domain will also have a counter to obtain the count value of the SCK clock domain within a certain period of time; when the comparison shows that the CNT1 taken twice is equal, it indicates that SCK is abnormally interrupted.

[0055] Example 2

[0056] An embodiment of the present invention further provides an audio processing chip, comprising the system for preventing channel switching from occurring in an I2S audio interface in the above-mentioned embodiment 1.

[0057] Example 3

[0058] An embodiment of the present invention further provides an electronic device, comprising the audio processing chip in the above-mentioned embodiment 2.

[0059] Those skilled in the art can understand that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention is described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions recorded in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A system for preventing channel switching of an I2S audio interface, comprising a host and a slave, characterized in that: The slave receives a read serial clock signal, a read field selection signal, and serial data synchronized with the read serial clock signal sent by the host, and detects whether the read serial clock signal is abnormally lost; Receive a write serial clock signal and a write field selection signal sent by the host, detect whether the write serial clock signal is abnormally lost, convert parallel data into serial data and send it to the host; The slave performs transmission anomaly detection on the read serial clock signal and the write serial clock signal sent by the host, and stops receiving or sending data when it is detected that any of the above signals is abnormally lost; After receiving the enable signal, the slave delays the enable signal until the beginning of the next frame of left channel data before starting to transmit data, thereby protecting the transmission from channel switching; after receiving the enable signal shutdown, the slave delays the enable signal until the complete right channel data is received before ending the data transmission, thereby protecting the transmission from channel switching; The enable signal is generated by the system clock of the slave and is synchronized to the receiving and / or transmitting clock domain.

2. The system for preventing channel switching of an I2S audio interface according to claim 1, characterized in that: The slave includes a slave receiving module and a slave sending module, wherein: The slave receiving module receives a read serial clock signal, a read field selection signal, and serial data synchronized with the read serial clock signal sent by the host, and detects whether the read serial clock signal is abnormally lost; The slave sending module receives the write serial clock signal and the write field selection signal sent by the host, detects whether the write serial clock signal is abnormally lost, and converts parallel data into serial data and sends it to the host.

3. The system for preventing channel switching of an I2S audio interface according to claim 2, characterized in that: The slave receiving module includes a slave reading clock monitor, a slave reading serial-to-parallel converter and a slave receiving buffer, wherein: The slave read clock monitor is used to detect whether the read serial clock signal sent by the host is abnormally lost; The slave read serial-to-parallel converter converts the serial data from the host into parallel data and then sends the parallel data to the slave receive buffer cache.

4. The system for preventing channel switching of an I2S audio interface according to claim 3, characterized in that: The slave read clock monitor counts the read serial clock signal, adds 1 to the binary counter for each clock; converts the binary counter into Gray code; synchronizes the Gray code to the system clock domain; generates a register and comparison signal in the system clock domain for a period of time, registers the value of the Gray code, and compares the value with the previous register value; if the two comparison values ​​are different, it means that the read serial clock signal is normal; If the two values ​​are the same, it means that the read serial clock signal is lost during the comparison of the two values; if the read serial clock signal is lost, the enable signal is turned off and the slave receiving buffer is reset to ensure normal data transmission after the enable signal is turned on next time.

5. The system for preventing channel switching of an I2S audio interface according to claim 2, characterized in that: The slave sending module, It includes a slave write clock monitor, a slave write serial-to-parallel converter and a slave send buffer, wherein: The slave write clock monitor is used to detect whether the write serial clock signal sent by the host is abnormally lost; The slave write serial-to-parallel converter reads the parallel data of the slave send buffer, converts it into serial data through the write serial clock signal and the write field selection signal, and sends it to the host.

6. The system for preventing channel switching of an I2S audio interface according to claim 5, characterized in that: The slave write clock monitor counts the write serial clock signal, adds 1 to the binary counter for each clock; converts the binary counter into Gray code; synchronizes the Gray code to the system clock domain; generates a register and compare signal in the system clock domain for a period of time, registers the value of the Gray code, and compares the value with the previous register value; if the two comparison values ​​are different, it means that the write serial clock signal is normal; If the two values ​​are the same, it means that the write serial clock signal is lost during the comparison of the two values; if the write serial clock signal is lost, the enable signal is turned off and the slave send buffer is reset to ensure normal data transmission after the enable signal is turned on next time.

7. An audio processing chip, characterized in that: The audio processing chip comprises the system for avoiding channel switching of an I2S audio interface according to any one of claims 1 to 6.

8. An electronic device, characterized in that: The electronic device comprises the audio processing chip according to claim 7.

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