Battery simulator synchronization method, device and storage medium

Abstract

The present application discloses a battery simulator synchronization method, device and storage medium. The control modules of multiple battery simulators can be connected together through a CAN bus or a CANFD bus, so that the output adjustment parameters required by each output channel module can be accurately transmitted to the corresponding battery simulator. At the same time, by designing a first clock line, a second clock line, a first enable line and a second enable line, and cleverly utilizing the changes in the enable signal and the clock signal, it is possible to transmit each output adjustment parameter to the corresponding output channel module and complete the synchronous output control of all output channel modules.

Description

Technical Field

[0001] The present application relates to the field of source-load systems, and in particular to a battery simulator synchronization method, device and storage medium. Background Art

[0002] At present, when a multi-channel battery simulator platform needs to connect multiple battery simulators in parallel or series and output multiple output channels synchronously, large output synchronization errors often occur due to the inconsistent time when each channel receives data. The existence of errors will make it impossible to form synchronous control, and thus cannot meet the needs of synchronous application scenarios. Summary of the invention

[0003] The present application aims to propose a battery simulator synchronization method, device and storage medium, which improve the synchronization of battery simulators in parallel or series.

[0004] According to the battery simulator synchronization method of the first aspect of the present application, it is used to synchronize multiple battery simulators in a multi-channel battery simulator platform, each of the battery simulators includes a control module, an FPGA module, and multiple output channel modules, the control module is communicatively connected to the FPGA module, and a serial communication line, a first enable line, and a first clock line are connected between the FPGA module and each of the output channel modules; the multiple battery simulators are arranged in sequence, and a second enable line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators; the multiple FPGA modules output synchronized clock signals to the corresponding output channel modules through the first clock line and the second clock line; the control modules of the multiple battery simulators are connected via a CAN bus or a CANFD bus; the battery simulator in the first position is the first simulator, and the remaining battery simulators are the second simulators;

[0005] The battery simulator synchronization method, applied to the control module of the first simulator, comprises:

[0006] Acquiring setting data, wherein the setting data includes output adjustment parameters of a plurality of output channel modules in each of the battery simulators;

[0007] Transmitting output adjustment parameters corresponding to the plurality of output channel modules in the first simulator to the FPGA module in the first simulator;

[0008] Transmitting the output adjustment parameters corresponding to the plurality of output channels in each of the second simulators to the FPGA module in the corresponding second simulator, so that the control module in each of the second simulators feeds back a slave response signal to the control module of the first simulator;

[0009] When receiving the slave response signal returned by each of the second simulators, adjusting the first enable line and each of the second enable lines to a high level, and transmitting the output adjustment parameters corresponding to the plurality of output channel modules in each of the battery simulators to each of the output channel modules, so that each of the output channel modules returns a channel response signal to the corresponding control module;

[0010] When the channel response signal transmitted and returned by each of the output channels in the first simulator is received, the first enable line and the second enable line are adjusted to a low level, so that each of the output channel modules, upon detecting a falling edge signal in the corresponding first enable line or the second enable line, responds to a trigger edge signal in the corresponding first clock line or the second clock line, and performs an output operation according to the received output adjustment parameters.

[0011] According to the battery simulator synchronization device of the second aspect of the present application, it is used to synchronize multiple battery simulators in a multi-channel battery simulator platform, each of the battery simulators includes a control module, an FPGA module, and multiple output channel modules, the control module is communicatively connected to the FPGA module, and a serial communication line, a first enable line, and a first clock line are connected between the FPGA module and each of the output channel modules; the multiple battery simulators are arranged in sequence, and a second enable line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators; the multiple FPGA modules output synchronized clock signals to the corresponding output channel modules through the first clock line and the second clock line; the control modules of the multiple battery simulators are connected via a CAN bus or a CANFD bus; the battery simulator in the first position is the first simulator, and the remaining battery simulators are the second simulators;

[0012] The battery simulator synchronization device, applied to the control module of the first simulator, comprises:

[0013] A setting data acquisition module, used to acquire setting data, wherein the setting data includes output adjustment parameters of a plurality of output channel modules in each of the battery simulators;

[0014] A first data sending module, used for transmitting output adjustment parameters corresponding to the plurality of output channel modules in the first simulator to the FPGA module in the first simulator;

[0015] A second data sending module, used for transmitting the output adjustment parameters corresponding to the plurality of output channels in each of the second simulators to the FPGA module in the corresponding second simulator, so that the control module in each of the second simulators feeds back a slave response signal to the control module of the first simulator;

[0016] a first synchronization control module, configured to adjust the first enable line and each of the second enable lines to a high level upon receiving the slave response signal returned by each of the second simulators, and transmit the output adjustment parameters corresponding to the plurality of output channel modules in each of the battery simulators to each of the output channel modules, so that each of the output channel modules returns a channel response signal to the corresponding control module;

[0017] A second synchronization control module is used to adjust the first enable line and the second enable line to a low level when receiving the channel response signal transmitted and returned by each of the output channels in the first simulator, so that each of the output channel modules, when detecting a falling edge signal in the corresponding first enable line or the second enable line, responds to a trigger edge signal in the corresponding first clock line or the second clock line and performs an output operation according to the received output adjustment parameters.

[0018] According to the computer-readable storage medium of the third aspect embodiment of the present application, computer-executable instructions are stored, and the computer-executable instructions are used to execute the battery simulator synchronization method as described in the first aspect embodiment above.

[0019] The battery simulator synchronization method, device and storage medium of the present application can connect the control modules of multiple battery simulators together through a CAN bus or a CANFD bus, so that the output adjustment parameters required by each output channel module can be accurately transmitted to the corresponding battery simulator. At the same time, by designing the first clock line, the second clock line, the first enable line and the second enable line, and cleverly utilizing the changes in the enable signal and the clock signal, it is possible to transmit each output adjustment parameter to the corresponding output channel module and complete the synchronous output control of all output channel modules.

[0020] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or may be understood by practicing the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0022] Figure 1 A schematic diagram of the structure of a multi-channel battery simulator platform provided in one embodiment of the present application;

[0023] Figure 2 A flowchart of a battery simulator synchronization method provided in one embodiment of the present application;

[0024] Figure 3 A schematic diagram of the structure of a battery simulator synchronization device provided in one embodiment of the present application.

[0025] Reference numerals:

[0026] Control module 110 , FPGA module 120 , and output channel module 130 . DETAILED DESCRIPTION

[0027] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0028] In the description of this application, if there is a description of first, second, etc., it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0029] In the description of the present application, it should be understood that the descriptions involving orientation, such as the orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0030] In the description of this application, it should be noted that, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meaning of the above terms in this application based on the specific content of the technical solution.

[0031] The technical solution of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described below are only part of the embodiments of the present application, not all of the embodiments.

[0032] In order to better describe the battery simulator synchronization method, device and storage medium of the embodiment of the present invention, a multi-channel battery simulator platform is proposed here, such as Figure 1As shown, the multi-channel battery simulator platform includes multiple battery simulators, each of which includes a control module 110, an FPGA (Field Programmable Gate Array) module 120, and multiple output channel modules 130. The control module 110 is connected to the FPGA module 120 for communication, and a serial communication line, a first enable line, and a first clock line are connected between the FPGA module 120 and each output channel module 130; multiple battery simulators are arranged in sequence, and a second enable line and a second clock line are arranged between the FPGA modules 120 of two adjacent battery simulators; multiple FPGA modules 120 output synchronized clock signals to the corresponding output channel modules 130 through the first clock line and the second clock line; the control modules 110 of multiple battery simulators are connected through a CAN (Controller Area Network) bus or a CANFD (CAN with Flexible Data rate) bus;

[0033] The control module 110 and the FPGA module 120 are connected via a fsmc (Flexible Static Memory Controller) bus.

[0034] The control modules 110 of the above-mentioned multiple battery simulators are connected via a CAN bus or a CANFD bus, which can avoid data transmission conflicts and ensure that each data frame can be transmitted to a designated battery simulator during transmission.

[0035] The above-mentioned multiple battery simulators are set in sequence, and the battery simulator in the first position is set as the first simulator, which can be understood as a host device, and the remaining battery simulators are set as the second simulator, which can be understood as slave devices.

[0036] After being started, the FPGA module 120 in the first simulator can continue to send clock signals through the first clock line and the second clock line. When the FPGA module 120 in each second simulator detects the clock signal sent by the second clock line, it will also output a clock signal synchronized with the clock signal output by the FPGA module 120 in the first simulator to the next second simulator through the second clock line, until the FPGA modules 120 in all battery simulators can output synchronized clock signals.

[0037] The above serial communication line can realize data transmission between the FPGA module 120 and the output channel.

[0038] The output channel module 130 has a built-in controller, which is used to implement data interaction with the FPGA module 120 and to implement control of the output of the output channel module 130 .

[0039] Based on the above power supply system, the power supply parallel synchronous output control method, device and storage medium according to the embodiment of the present invention are described below.

[0040] See also Figure 2 As shown, Figure 2 1 is a flowchart of a battery simulator synchronization method provided by an embodiment of the present application. The battery simulator synchronization method is applied to the control module 110 of the first simulator. The battery simulator synchronization method includes:

[0041] Acquire setting data, the setting data including output adjustment parameters of multiple output channel modules 130 in each battery simulator;

[0042] Transmitting output adjustment parameters corresponding to the plurality of output channel modules 130 in the first simulator to the FPGA module 120 in the first simulator;

[0043] Transmitting output adjustment parameters corresponding to the plurality of output channels in each second simulator to the FPGA module 120 in the corresponding second simulator, so that the control module 110 in each second simulator feeds back a slave response signal to the control module 110 of the first simulator;

[0044] When receiving the slave response signal returned by each second simulator, the first enable line and each second enable line are adjusted to a high level, and the output adjustment parameters corresponding to the multiple output channel modules 130 in each battery simulator are transmitted to each output channel module 130, so that each output channel module 130 returns a channel response signal to the corresponding control module 110;

[0045] When a channel response signal is received from each output channel in the first simulator, the first enable line and the second enable line are adjusted to a low level so that each output channel module 130, upon detecting a falling edge signal in the corresponding first enable line or the second enable line, responds to a trigger edge signal in the corresponding first clock line or the second clock line and performs an output operation according to the received output adjustment parameters.

[0046] In an embodiment of the present application, by connecting the control modules 110 of multiple battery simulators together on a CAN bus or a CANFD bus, the output adjustment parameters required by each output channel module 130 can be accurately transmitted to the corresponding battery simulator. At the same time, by designing the first clock line, the second clock line, the first enable line and the second enable line, and cleverly utilizing the changes in the enable signal and the clock signal, it is possible to transmit each output adjustment parameter to the corresponding output channel module 130 and complete the synchronous output control of all output channel modules 130.

[0047] The above setting data can be manually input through the interactive interface on the platform, or can be directly obtained by the host computer.

[0048] When synchronous control is required, the above setting data may include output adjustment parameters corresponding to each output channel module 130 in each battery simulator, and each output channel module 130 may complete output control according to the received output adjustment parameters.

[0049] After obtaining the setting data, the control module 110 in the first simulator can first parse out the output adjustment parameters required by its own output channel module 130, and transmit them to the FPGA module 120 in the first simulator through the Fsmc bus. The FPGA module 120 will temporarily store the output adjustment parameters.

[0050] After obtaining the setting data, the control module 110 in the above-mentioned first simulator can parse out the output adjustment parameters required by the output channel module 130 in each second simulator, and then transmit them to the control module 110 in each second simulator via the CAN bus or CANFD bus, and then be further transmitted to the FPGA module 120 by the control module 110 in each second simulator for temporary storage.

[0051] After transmitting the output adjustment parameters to the FPGA module 120 for temporary storage, the control module 110 in each of the second simulators will generate a slave response signal and transmit the slave response signal back to the first simulator via the CAN bus or the CANFD bus.

[0052] After receiving the slave response signal returned by each second simulator, the above-mentioned first simulator can determine that the FPGA module 120 in each second simulator has completed the temporary storage of the output adjustment parameters. At this time, the first enable line and each second enable line can be adjusted to a high level. When each battery simulator detects a high level signal, it can transmit the output adjustment parameters temporarily stored in the FPGA module 120 to the corresponding output channel module 130.

[0053] The first simulator may transmit the output adjustment parameters to the corresponding control module of the battery simulator in order from the second to the last position.

[0054] After receiving the output adjustment parameters, each of the above-mentioned output channel modules 130 will feedback the channel response signal to the corresponding control module 110. The control module 110 can determine whether there is data leakage or mistransmission based on the feedback channel response signal. For example, if there is an output channel module 130 that does not feedback the channel response signal to the corresponding control module 110, it can be determined that there is leakage. At this time, it is meaningless to perform synchronous control output, and an alarm can be generated to inform the operator.

[0055] After receiving the channel response signals fed back by the multiple output channel modules 130 corresponding to itself, the above-mentioned first simulator can determine that basically all the output channel modules 130 have received the output adjustment parameters. At this time, the first enable line and each second enable line can be adjusted to a low level. When each battery simulator detects a low-level signal, each output channel module 130 can wait for the jump of the clock signal in the first clock line or the second clock line, for example, wait for the rising edge. When the rising edge of the clock signal is identified, the output can be completed according to the received output adjustment parameters.

[0056] It should be noted that the clock signals in the first clock line or the second clock line are synchronous, so that the multiple output channel modules 130 can complete synchronous output control.

[0057] It should also be noted that multiple battery simulators usually use the same model. Although there may be slight differences in data transmission time between the internal control modules 110, FPGA modules 120, and output channel modules 130 of the two battery simulators due to manufacturing process problems, the first simulator still needs to adjust the level of the first enable line and each second enable line after the channel response signal. This short period of time is sufficient to make up for the aforementioned time error, and there will be no situation in which the output channel module 130 in the second simulator is about to output but the channel response signal has not yet been fed back.

[0058] In some implementations, the above-mentioned transmitting the output adjustment parameters corresponding to the plurality of output channels in each second simulator to the FPGA module 120 in the corresponding second simulator includes:

[0059] Transmitting the output adjustment parameters corresponding to the multiple output channels in each second simulator to the control module 110 in the corresponding second simulator, so that the control module 110 in each second simulator transmits the received output adjustment parameters to the corresponding FPGA module 120, and after the FPGA module 120 receives the output adjustment parameters, sends a slave response signal to the control module 110 of the first simulator;

[0060] Wherein, when the first simulator receives a slave response signal returned by a second simulator, it sends an output adjustment parameter corresponding to the next second simulator.

[0061] The output adjustment parameters corresponding to the multiple output channels in each of the second simulators are transmitted to the control module 110 in the corresponding second simulator, which can be accomplished through the CAN bus and the CANFD bus.

[0062] After receiving the output adjustment parameters corresponding to the multiple output channels, the control module 110 in each of the second simulators can transmit the output adjustment parameters corresponding to the multiple output channels to the FPGA module 120 through the Fsmc bus. In addition, after completing the transmission of the output adjustment parameters, the control module 110 in the second simulator will generate a slave response signal and feed the slave response signal back to the first simulator.

[0063] When the first simulator receives a slave response signal returned by a second simulator, it will send the output adjustment parameters corresponding to the next second simulator to avoid conflicts between the slave response signal fed back by the second simulator and the output adjustment parameters sent down, thereby ensuring the integrity and accuracy of the entire process.

[0064] In some embodiments, transmitting the output adjustment parameters corresponding to the plurality of output channels in each second simulator to the control module 110 in the corresponding second simulator includes:

[0065] Generate a slave control data frame according to the output adjustment parameters corresponding to the multiple output channel modules 130 in each second simulator, the slave control data frame includes the output adjustment parameters and register address data corresponding to the multiple output channels in the second simulator, wherein the control module 110 in each second simulator includes multiple registers, and the register address data of the multiple registers in the multiple control modules 110 are all different;

[0066] The slave control data frame is transmitted to the control module 110 in the second simulator of the register corresponding to the register address data through the CAN bus or the CANFD bus.

[0067] Each of the above-mentioned battery simulators may include multiple registers, each of which may be assigned a unique register address, and for ease of control, the register addresses of multiple registers in each battery simulator are set continuously, and multiple battery simulators then sequentially maintain continuous addresses.

[0068] The register address data is unique, and therefore, the register address data can be used as the target address in the slave control data frame, and then the slave control data frame can be transmitted to the control module 110 of the battery simulator corresponding to the register address data.

[0069] In some implementations, the control module 110 in each second simulator transmits the received output adjustment parameter to the corresponding FPGA module 120 through the following steps:

[0070] In response to the data reception interrupt, the slave control data frame is parsed to obtain the corresponding output adjustment parameter;

[0071] The received output adjustment parameters are transmitted to the corresponding FPGA module 120 .

[0072] In this embodiment, multiple battery simulators are connected by CAN bus or CANFD bus. Therefore, the CAN interrupt method can be directly used to complete the parsing of slave control data frames and the transmission of output adjustment parameters. There is no need to use the computing power of the control module 110 for additional judgment, which improves the integrity of data transmission and allows the control module 110 to better perform other tasks.

[0073] In some embodiments, the multiple registers of each control module 110 include a synchronous control register and an independent control register; when the register address data in the slave control data frame indicates a synchronous control register, each battery simulator performs an output operation according to the received output adjustment parameter after responding to a trigger edge signal in the corresponding first clock line or second clock line;

[0074] The battery simulator synchronization method further includes:

[0075] When the register address data in the slave control data frame indicates an independent control register, the slave control data frame is parsed to obtain a corresponding output adjustment parameter;

[0076] Transmitting the corresponding output adjustment parameter to the corresponding output channel module 130;

[0077] The multiple output channel enabling module 130 performs output operations according to the received output adjustment parameters.

[0078] In the present embodiment, the multiple registers of each control module 110 include synchronous control registers and independent control registers, and because each register corresponds to unique register address data, it is only necessary to judge the register address data to determine whether synchronous control is required. When it is determined that the register address data is an independent control register, it can be determined that synchronous control is not required. The output channel module 130 directly receives the output adjustment parameters and completes the output control according to the received output adjustment parameters. When it is determined to be a synchronous control register, it can be determined that synchronous control is required. At this time, it is necessary to wait for the synchronous control signal transmitted by the first simulator through the clock line and the enable line before completing the corresponding operation.

[0079] In some implementations, adjusting the first enable line and each second enable line to a high level includes:

[0080] Sending a write enable signal to the FPGA module 120 in the first simulator, so that the FPGA module 120 in the first simulator adjusts the first enable line to a high level and adjusts the second enable line connected to the adjacent FPGA module 120 to a high level;

[0081] The FPGA module 120 in each second simulator synchronously adjusts the second enable line connected to the next FPGA module 120 to a high level.

[0082] When receiving the slave response signal returned by each second simulator, the first simulator sends a write enable signal to the FPGA module 120 in the first simulator, and the FPGA module 120 can adjust the first enable line to a high level and synchronously adjust the second enable line connected to the adjacent FPGA module 120 to a high level. The FPGA module 120 in each second simulator can synchronously adjust the enable line connected to the next FPGA module 120 to a high level.

[0083] In this implementation, the characteristics of the FPGA module 120 are utilized to achieve synchronous transmission of corresponding enable signals.

[0084] In some embodiments, transmitting the output adjustment parameters corresponding to the multiple output channel modules 130 in each battery simulator to each output channel module 130 includes:

[0085] When the FPGA module 120 adjusts the first enable line to a high level in the first simulator, the corresponding output adjustment parameter is sent to the corresponding output channel module 130;

[0086] When the FPGA module 120 in each second simulator detects a rising edge signal in the second enable line, the FPGA module 120 in each second simulator sends the corresponding output adjustment parameter to the corresponding output channel module 130;

[0087] After receiving the corresponding output adjustment parameter, each output channel module 130 returns a channel response signal to the corresponding control module 110 through the corresponding FPGA module 120 .

[0088] In this real-time mode, the high level output by the FPGA module 120 in the first simulator through the second enable line can synchronously reach all second simulators. Based on this, each second simulator can synchronously send the corresponding output adjustment parameters to the corresponding output channel module 130 when detecting the rising edge signal in the second enable line. Moreover, the FPGA module 120 in the first simulator can also send the corresponding output adjustment parameters to the corresponding output channel module 130 when adjusting the first enable line to a high level, thereby realizing synchronous control of all output channel modules 130 receiving the output adjustment parameters.

[0089] In some implementations, adjusting the first enable line and the second enable line to a low level includes:

[0090] Sending an output enable signal to the FPGA module 120 in the first simulator, so that the FPGA module 120 in the first simulator adjusts the first enable line corresponding to the output channel module 130 to a low level, and adjusts the second enable line connected to the adjacent FPGA module 120 to a low level;

[0091] The FPGA module 120 in each second simulator adjusts the second enable line connected to the next FPGA module 120 to a low level.

[0092] In this embodiment, the low level output by the FPGA module 120 in the first simulator through the second enable line can synchronously reach all the second simulators, and then synchronously reach the output channel module 130 of each battery simulator, so that all output channel modules 130 can synchronously detect the change of the level from a high level to a low level, and then the rising edge of the subsequently detected clock signal can be the same rising edge, thereby achieving high synchronization.

[0093] The battery simulator synchronization method provided in the embodiment of the present application can be executed by a battery simulator synchronization device. In the embodiment of the present application, the battery simulator synchronization method executed by the battery simulator synchronization device is taken as an example to illustrate the battery simulator synchronization device provided in the embodiment of the present application.

[0094] refer to Figure 3 The embodiment of the present application further provides a battery simulator synchronization device, the battery simulator synchronization device comprising:

[0095] A setting data acquisition module, used to acquire setting data, the setting data including output adjustment parameters of multiple output channel modules 130 in each battery simulator;

[0096] A first data sending module, used for transmitting output adjustment parameters corresponding to the plurality of output channel modules 130 in the first simulator to the FPGA module 120 in the first simulator;

[0097] A second data sending module, used for transmitting the output adjustment parameters corresponding to the multiple output channels in each second simulator to the FPGA module 120 in the corresponding second simulator, so that the control module 110 in each second simulator feeds back the slave response signal to the control module 110 of the first simulator;

[0098] A first synchronization control module, configured to adjust the first enable line and each second enable line to a high level upon receiving a slave response signal returned by each second simulator, and transmit the output adjustment parameters corresponding to the multiple output channel modules 130 in each battery simulator to each output channel module 130, so that each output channel module 130 returns a channel response signal to the corresponding control module 110;

[0099] The second synchronization control module is used to adjust the first enable line and the second enable line to a low level when receiving a channel response signal transmitted and returned by each output channel in the first simulator, so that each output channel module 130, when detecting a falling edge signal in the corresponding first enable line or the second enable line, responds to the trigger edge signal in the corresponding first clock line or the second clock line and performs an output operation according to the received output adjustment parameters.

[0100] In addition, an embodiment of the present application also provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are executed by a processor or a control module, so that the above-mentioned processor can execute the battery simulator synchronization method in the above-mentioned embodiment, for example, execute the method described above.

[0101] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed methods above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium or a non-transitory medium and a communication medium or a temporary medium. As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk DVD or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0102] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A battery simulator synchronization method, characterized in that: Used to synchronize multiple battery simulators in a multi-channel battery simulator platform, each of the battery simulators includes a control module, an FPGA module, and multiple output channel modules, the control module is communicatively connected to the FPGA module, and a serial communication line, a first enable line, and a first clock line are connected between the FPGA module and each of the output channel modules; multiple battery simulators are arranged in sequence, and a second enable line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators; multiple FPGA modules output synchronized clock signals to the corresponding output channel modules through the first clock line and the second clock line; the control modules of multiple battery simulators are connected through a CAN bus or a CANFD bus; the battery simulator in the first position is the first simulator, and the remaining battery simulators are the second simulators; The battery simulator synchronization method, applied to the control module of the first simulator, comprises: Acquiring setting data, wherein the setting data includes output adjustment parameters of a plurality of output channel modules in each of the battery simulators; Transmitting output adjustment parameters corresponding to the plurality of output channel modules in the first simulator to the FPGA module in the first simulator; Transmitting the output adjustment parameters corresponding to the plurality of output channels in each of the second simulators to the FPGA module in the corresponding second simulator, so that the control module in each of the second simulators feeds back a slave response signal to the control module of the first simulator; In the case of receiving the slave response signal returned by each of the second simulators, adjusting the first enable line and each of the second enable lines to a high level, and transmitting the output adjustment parameters corresponding to the plurality of output channel modules in each of the battery simulators to each of the output channel modules, so that each of the output channel modules returns a channel response signal to the corresponding control module, wherein the high level output by the FPGA module in the first simulator through the second enable line synchronously reaches each of the second simulators; Upon receiving the channel response signal transmitted and returned by each of the output channels in the first simulator, the first enable line and the second enable line are adjusted to a low level, so that each of the output channel modules, upon detecting a falling edge signal in the corresponding first enable line or the second enable line, responds to a trigger edge signal in the corresponding first clock line or the second clock line, and performs an output operation according to the received output adjustment parameters, wherein the low level output by the FPGA module in the first simulator through the second enable line reaches each of the second simulators synchronously.

2. The battery simulator synchronization method according to claim 1, characterized in that: The step of transmitting the output adjustment parameters corresponding to the plurality of output channels in each of the second simulators to the FPGA module in the corresponding second simulator comprises: Transmitting the output adjustment parameters corresponding to the plurality of output channels in each of the second simulators to the corresponding control module in the second simulator, so that each control module in the second simulator transmits the received output adjustment parameters to the corresponding FPGA module, and after the FPGA module receives the output adjustment parameters, sends the slave response signal to the control module of the first simulator; When the first simulator receives the slave response signal returned by the second simulator, the first simulator sends the next output adjustment parameter corresponding to the second simulator.

3. The battery simulator synchronization method according to claim 2, characterized in that: The step of transmitting the output adjustment parameters corresponding to the plurality of output channels in each of the second simulators to a control module in the corresponding second simulator comprises: Generate a slave control data frame according to the output adjustment parameters corresponding to the plurality of output channel modules in each of the second simulators, the slave control data frame including the output adjustment parameters and register address data corresponding to the plurality of output channels in the second simulator, wherein each of the control modules in the second simulator includes a plurality of registers, and the register address data of the plurality of registers in the plurality of control modules are all different; The slave control data frame is transmitted to the control module in the second simulator of the register corresponding to the register address data through the CAN bus or the CANFD bus.

4. The battery simulator synchronization method according to claim 3, characterized in that: The control module in each of the second simulators transmits the received output adjustment parameters to the corresponding FPGA module through the following steps: In response to a data reception interrupt, parsing the slave control data frame to obtain the corresponding output adjustment parameter; The received output adjustment parameters are transmitted to the corresponding FPGA module.

5. The battery simulator synchronization method according to claim 3, characterized in that: The multiple registers of each control module include a synchronous control register and an independent control register; when the register address data in the slave control data frame indicates the synchronous control register, each battery simulator performs the output operation according to the received output adjustment parameter after responding to the trigger edge signal in the corresponding first clock line or the second clock line; The battery simulator synchronization method further includes: In the case where the register address data in the slave control data frame indicates the independent control register, parsing the slave control data frame to obtain the corresponding output adjustment parameter; Transmitting the corresponding output adjustment parameter to the corresponding output channel module; A plurality of the output channel modules are enabled to perform output operations according to the received output adjustment parameters.

6. The battery simulator synchronization method according to claim 1, characterized in that: The step of adjusting the first enable line and each of the second enable lines to a high level includes: Sending a write enable signal to the FPGA module in the first simulator, so that the FPGA module in the first simulator adjusts the first enable line to a high level and adjusts the second enable line connected to the adjacent FPGA module to a high level; Wherein, each FPGA module in the second simulator synchronously adjusts the second enable line connected to the next FPGA module to a high level.

7. The battery simulator synchronization method according to claim 1, characterized in that: The step of transmitting the output adjustment parameters corresponding to the plurality of output channel modules in each of the battery simulators to each of the output channel modules comprises: When the FPGA module in the first simulator adjusts the first enable line to a high level, the corresponding output adjustment parameter is sent to the corresponding output channel module; When the FPGA module in each of the second simulators detects a rising edge signal in the second enable line, the FPGA module in each of the second simulators sends the corresponding output adjustment parameter to the corresponding output channel module; After each of the output channel modules receives the corresponding output adjustment parameter, it returns the channel response signal to the corresponding control module through the corresponding FPGA module.

8. The battery simulator synchronization method according to claim 1, characterized in that: The step of adjusting the first enable line and the second enable line to a low level includes: Sending an output enable signal to the FPGA module in the first simulator, so that the FPGA module in the first simulator adjusts the first enable line corresponding to the output channel module to a low level, and adjusts the second enable line connected to the adjacent FPGA module to a low level; Among them, the FPGA module in each of the second simulators adjusts the second enable line connected to the next FPGA module to a low level.

9. A battery simulator synchronization device, characterized in that: Used to synchronize multiple battery simulators in a multi-channel battery simulator platform, each of the battery simulators includes a control module, an FPGA module, and multiple output channel modules, the control module is communicatively connected to the FPGA module, and a serial communication line, a first enable line, and a first clock line are connected between the FPGA module and each of the output channel modules; multiple battery simulators are arranged in sequence, and a second enable line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators; multiple FPGA modules output synchronized clock signals to the corresponding output channel modules through the first clock line and the second clock line; the control modules of multiple battery simulators are connected through a CAN bus or a CANFD bus; the battery simulator in the first position is the first simulator, and the remaining battery simulators are the second simulators; The battery simulator synchronization device, applied to the control module of the first simulator, comprises: A setting data acquisition module, used to acquire setting data, wherein the setting data includes output adjustment parameters of a plurality of output channel modules in each of the battery simulators; A first data sending module, used for transmitting output adjustment parameters corresponding to the plurality of output channel modules in the first simulator to the FPGA module in the first simulator; A second data sending module, used for transmitting the output adjustment parameters corresponding to the plurality of output channels in each of the second simulators to the FPGA module in the corresponding second simulator, so that the control module in each of the second simulators feeds back a slave response signal to the control module of the first simulator; a first synchronization control module, configured to adjust the first enable line and each of the second enable lines to a high level upon receiving the slave response signal returned by each of the second simulators, and transmit the output adjustment parameters corresponding to the plurality of output channel modules in each of the battery simulators to each of the output channel modules, so that each of the output channel modules returns a channel response signal to the corresponding control module, wherein the high level output by the FPGA module in the first simulator through the second enable line synchronously reaches each of the second simulators; A second synchronization control module is used to adjust the first enable line and the second enable line to a low level when receiving the channel response signal transmitted and returned by each of the output channels in the first simulator, so that each of the output channel modules, when detecting a falling edge signal in the corresponding first enable line or the second enable line, responds to the trigger edge signal in the corresponding first clock line or the second clock line, and performs an output operation according to the received output adjustment parameters, wherein the low level output by the FPGA module in the first simulator through the second enable line reaches each of the second simulators synchronously.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the battery simulator synchronization method as described in any one of claims 1 to 8.

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