Systolic array device

Abstract

A systolic array device according to an embodiment includes a plurality of processing units arranged in a matrix of M by N (M and N are natural numbers). Each of the processing units includes a processing element configured to perform a predetermined processing based on data received from a processing unit arranged adjacent to one side of the corresponding processing unit to output a result thereof, and a transmission portion configured to perform one of an operation of transmitting the received data to another processing unit arranged adjacent to the other side of the corresponding processing unit and an operation of transmitting the result.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a systolic array device. BACKGROUND

[0002] In a systolic array (SA) device, a plurality of processing elements (PEs) are adjacently arranged and connected to each other. Data such as input features and partial sums are transmitted between the adjacently arranged processing elements. At this time, the data can be transmitted in a vertical direction or a horizontal direction. For example, a partial sum can be transmitted in a vertical direction (from north to south) of the SA, and an input feature can be transmitted in a horizontal direction (from left to right).

[0003] In the SA, data such as input features are transmitted between the adjacently arranged processing elements to be reused, so that a bottleneck of a memory can not be caused. Also, in the SA, a connection between the processing elements is short, so that an ASIC or an FPGA having a relatively high clock frequency can be embodied.

[0004] Meanwhile, a multiplier and an adder can be included in each of a plurality of processing elements included in the SA, and each of the multiplier and the adder can be embodied by a plurality of transistors. If it is determined that any one of the transistors has a fault in a scan test performed after manufacturing of a semiconductor, the entire chip die needs to be discarded. This is because processing of input features and output features is performed in the plurality of processing elements by participating in lock-step. Therefore, there is a problem of low yield. Accordingly, a means for solving this yield problem is required. SUMMARY

[0005] TECHNICAL PROBLEM

[0006] A problem to be solved in the disclosure includes providing a means for utilizing the SA without discarding the entire chip when a fault is found in a manufacturing process of the SA.

[0007] Meanwhile, the problem to be solved in the disclosure is not limited to the above description. Another problem to be solved which is not described can be clearly understood by those skilled in the art according to the following description.

[0008] TECHNICAL SOLUTION TO THE PROBLEM

[0009] According to an embodiment of the present disclosure, there is provided a systolic array device including a plurality of processing units arranged in a matrix of M by N (M and N are natural numbers), wherein each of the processing units includes a processing element configured to perform predetermined processing based on data received from a processing unit arranged adjacent to one side of the corresponding processing unit to output a result thereof, and a transmission part configured to perform one of an operation of transmitting the received data to another processing unit arranged adjacent to the other side of the corresponding processing unit and an operation of transmitting the result.

[0010] Advantages of the Invention

[0011] According to an embodiment of the present disclosure, even if there is a failure in a part of processing units constituting a systolic array device, the systolic array device can be reused by bypassing data in each processing unit and a preliminarily provided processing unit, so that the yield of the systolic array device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 FIG. 1 is a schematic diagram illustrating a systolic array device according to a first embodiment of the present disclosure.

[0013] Figure 2 FIG. 2 is a schematic diagram illustrating a processing element (PE) applied in the first embodiment of the present disclosure.

[0014] Figure 3 FIG. 3 is a schematic diagram illustrating a processing element according to the first embodiment, a processing unit including the processing element according to the first embodiment, and an e-flash or an external ROM according to the first embodiment for controlling the processing unit in a case of being connected with the processing unit.

[0015] Figure 4 FIG. 4 is a conceptual diagram exemplarily illustrating a systolic array device including a plurality of processing units according to the first embodiment. Figure 3 FIG. 5 is a conceptual diagram illustrating a case where the systolic array device including the processing unit exemplified in FIG. 4 has a processing unit with a failure.

[0016] Figure 5 FIG. 6 is a conceptual diagram exemplarily illustrating a systolic array device including a plurality of processing units according to a second embodiment. Figure 4 FIG. 7 is a conceptual diagram illustrating a data flow in the systolic array device exemplified.

[0017] Figure 6 FIG. 8 is a schematic diagram illustrating a processing element according to the second embodiment, a processing unit including the processing element according to the second embodiment, and an e-flash or an external ROM according to the second embodiment for controlling the processing unit in a case of being connected with the processing unit.

[0018] Figure 7This exemplifies, by way of, including complex numbers. Figure 6 The pulsating array device of the processing unit illustrated in the figure includes a conceptual diagram of a processing unit with a fault.

[0019] Figure 8 This is an example of Figure 7 A conceptual diagram of the data flow in the illustrated pulsating array device.

[0020] Figure 9 This is an exemplary illustration of a processing element according to a third embodiment, a processing unit including a processing element according to a third embodiment, and an e-flash memory or external ROM according to a third embodiment for controlling the processing unit when connected to the processing unit.

[0021] Figure 10 This exemplifies, by way of, including complex numbers. Figure 9 The pulsating array device of the processing unit illustrated in the figure includes a conceptual diagram of a processing unit with a fault.

[0022] Figure 11 This is an example of Figure 10 A conceptual diagram of the data flow in the illustrated pulsating array device.

[0023] Figure 12 This is a schematic diagram illustrating a processing element with a structure for scanning faults.

[0024] Figure 13 This is a schematic diagram illustrating a processing unit for scanning faults according to one embodiment of the present disclosure. Detailed Implementation

[0025] The advantages and features of the embodiments, as well as the methods of implementing them, will become clear from the following description taken in conjunction with the accompanying drawings. However, the embodiments are not limited to those described, as they can be implemented in various forms. It should be noted that the present embodiments are provided to make a full disclosure and to allow those skilled in the art to understand the full scope of the embodiments. Therefore, the embodiments are defined only by the scope of the appended claims.

[0026] In describing embodiments of this disclosure, detailed descriptions of known components or functions will be omitted if they unnecessarily obscure the spirit of the disclosure. Furthermore, the terms to be described below are defined with reference to the functionality of embodiments of this disclosure and may vary depending on the intent or practice of the user or operator. Therefore, their definitions can be made on a consistent basis throughout this specification.

[0027] Figure 1is a block diagram illustrating a systolic array (SA) device 1000 according to a first embodiment of the present disclosure. The systolic array device 1000 can be utilized in various ways. For example, a processing accelerator is one of available examples. Referring to Figure 1 The systolic array device 1000 can include a processing element (PE) array 100, an input feature cache unit 200, a weight cache unit 300, a control unit 400, an integration unit 500, and an output feature cache unit 600. Each of the systolic array device 1000 and the components included in the systolic array device 1000 can be embodied by a microprocessor for running commands and a memory for storing commands programmed to be executed at the corresponding component. However, Figure 1 The illustrated block diagram is an example, and thus, the systolic array device 1000 can not include Figure 1 at least one of the illustrated components, or can include Figure 1 components not illustrated in FIG. 1.

[0028] The input feature cache unit 200 can be embodied by a cache for storing input features. Here, the input features can indicate information showing features such as a video or a voice.

[0029] The weight cache unit 300 can be embodied by a cache for storing weights. Here, the weights are a type of kernel data, and indicate information multiplied to the input features.

[0030] The processing element (PE) array 100 is configured to perform processing by matching with a synchronization signal (e.g., a clock signal). The processing element array 100 includes a plurality of processing units arranged in a matrix form of M by N (here, M and N are natural numbers). The processing unit itself will be described later.

[0031] Meanwhile, a part of the plurality of processing units is classified as a main processing unit and the remaining part is classified as a preliminary processing unit.

[0032] The main processing unit can include at least two processing units, and the at least two processing units can be arranged in a matrix form of P by Q (here, P is a natural number equal to or smaller than M, Q is a natural number equal to or smaller than N, and a sum of P and Q is smaller than a sum of M and N).

[0033] The preliminary processing unit indicates a processing unit having a form of at least one row or column added to the matrix form of P by Q formed by the mentioned main processing unit. The preliminary processing unit is provided to back up a processing unit having a failure among the main processing units, which will be described later.

[0034] The control unit 400 can use information about the main processing units and the preliminary processing units to control the systolic array device 1000 to work in various ways, for example, as a processing accelerator. The operation of the control unit 400 will be described later.

[0035] The integration unit 500 can integrate the partial sums when a plurality of partial sums are provided, and can generate an integration result as an output feature.

[0036] The output feature cache unit 600 can receive the output feature from the integration unit 500 and store the output feature.

[0037] Meanwhile, even if there is a failure in a part of the plurality of processing units included in the processing element array 100, the systolic array device 1000 according to the first embodiment of the disclosure can work according to the original purpose. Thus, the manufacturing yield of the systolic array device 1000 including the processing element array 100 can be improved. From now on, a specific configuration of the systolic array device 1000 that makes the above operation possible will be described.

[0038] The processing element array 100 included in the systolic array device 1000 can include a plurality of processing units as described above, and each processing unit can include Figure 2 The processing element 10 according to the first embodiment of the disclosure exemplified above.

[0039] More specifically, the processing element 10 can output a result by performing a predetermined process based on received data in a case where data is received from a processing unit adjacently arranged at its own side. Here, "its own" indicates a processing unit including the corresponding processing element 10. Further, "data" can include an input feature, a weight, or a partial sum as mentioned.

[0040] More specifically, referring to Figure 2 , the processing element 10 can include a REG1 13 as a register for storing an input feature and a REG2 14 as a register for storing a weight. Further, the processing element 10 can include a multiplier 11 for multiplying an input feature and a weight. In addition, the processing element 10 can include an adder 12, and in the adder 12, a partial sum transmitted from an adjacently arranged processing unit can be added to a multiplication result in the multiplier 11. Further, the processing element 10 can include a REG3 15 as a register for storing an addition result in the adder 12.

[0041] Simultaneously, processing element 10 may include a withdrawal route for bypassing information stored in each of REG1 13, REG2 14, and REG3 15 to a processing unit arranged adjacent to it on the other side. Also, if processing element 10 malfunctions, in some cases, the information stored in each of REG1 13, REG2 14, and REG3 15 may not be externally bypassed. Here, "malfunction" can mean an anomaly exists in the component included in processing element 10 or in the route.

[0042] Figure 3 This is a schematic diagram illustrating a processing element 10 according to a first embodiment, a processing unit 20 including the processing element 10 according to a first embodiment, and an e-flash memory or external ROM according to a first embodiment for controlling the processing unit 20 when connected to the processing unit 20.

[0043] Reference Figure 3 The processing unit 20 according to the first embodiment may include a processing element 10 and transmission sections 21 and 22, and may be connected to an e-flash memory or an external ROM 410 (including...). Figure 1 (Components in the control unit 400).

[0044] The description of processing element 10 is cited. Figure 2 The part explained in the text.

[0045] Then, each of the transmission sections 21 and 22 is configured to transmit one of the following to the processing unit 20, which is arranged adjacently on the other side of itself. At this time, the transmission section 21 can be designated as a first bypass transmission section 21, the transmission section 22 can be designated as a second bypass transmission section 22, and each of the transmission sections 21 and 22 can be implemented by a multiplexer.

[0046] - Data received from the processing unit 20 arranged on one side of itself

[0047] - The result processed and output by processing element 10

[0048] Here, the transmission units 21 and 22 transmit data received from the processing unit 20, which is arranged adjacent to it on one side, when there is a fault in the processing element 10. At the same time, the transmission units 21 and 22 transmit the results processed and output by the processing element 10 when there is no fault in the processing element 10.

[0049] The e-flash or external ROM 410 can provide information about whether there is a failure in the processing element 10 to each of the transmission sections 21, 22. Here, the information provided by the e-flash or external ROM 410 can be acquired by a previous scan test, which will be described in Figure 12 and Figure 13 in more detail.

[0050] Meanwhile, the number of the transmission sections 21, 22 is exemplified as two in Figure 3 , but this is only an example. According to an embodiment, the number of the transmission sections can be one or three or more. For example, the number of the transmission sections 21, 22 can be set to three in the processing unit 20 for each of the input features, weights, and sections.

[0051] Figure 4 is exemplified as a systolic array device including a complex number. Figure 3 The systolic array device of the processing unit 20 exemplified in Figure 4 is a block diagram of a case in which the processing unit includes a processing element having a failure. Here, the "processing unit having a failure" can indicate a processing unit including a processing element having a failure. Meanwhile, the processing unit having a failure can include a processing element having a failure. Figure 4 The exemplified case is an example, and the present disclosure is not limited to the exemplification of

[0052] In the case of Figure 4 , a systolic array device including nine main processing units in the form of a 3 by 3 matrix is assumed. Further, the preliminary processing units can be additionally arranged in the form of at least one row or at least one column to the 3 by 3 matrix. Figure 4 It is exemplified that the preliminary processing units are additionally arranged in the form of one row and one column to the 3 by 3 matrix.

[0053] If there is no failure in any one of the nine main processing units, the systolic array device can work as a processing accelerator by only the nine main processing units. In this case, the preliminary processing units can not work as a component of the processing accelerator.

[0054] Unlike this, depending on different cases, there can be a failure in at least one of the nine main processing units. For example, as exemplified in Figure 4 , two main processing units can have a failure. In Figure 4 , "failed" is exemplified in the processing unit having a failure.

[0055] In this case, the control unit 400 can determine whether there is a failure in the processing unit according to Figure 7 and Figure 8The illustrated method (described later) is used to identify information about two main processing units that are faulty among the nine main processing units. Based on the identified information, the e-flash or external ROM 410 included in the control unit 400 can control the transmission sections 21, 22 included in each processing unit and cause the following operations to be performed.

[0056] - In each processing unit included in the same row (or column) as the main processing unit with the fault, data controlled from the processing unit arranged adjacent to one side is bypassed to the processing unit arranged adjacent to the other side.

[0057] - In each main processing unit without faults, the results of control output from the processing elements included in the corresponding processing unit are transmitted to the processing units arranged adjacently in the same row (or column).

[0058] Reference Figure 4 The main processing unit arranged in (2,2) is faulty. Therefore, the control unit 400 can control each processing unit in the second row such that data transmitted from each processing unit adjacent to it in the first row is bypassed to the processing unit adjacent to it in the third row. Of course, with Figure 4 The examples are different, but each processing unit in the second column can be controlled in the same way.

[0059] In addition, refer to Figure 4 The main processing unit arranged in (3,3) is faulty. Therefore, the control unit 400 can control each processing unit in the third column such that data transmitted from each processing unit adjacent to it in the second column is bypassed to the processing unit adjacent to it in the fourth column. Of course, with Figure 4 The examples are different, but each processing unit in the third row can be controlled in the same way.

[0060] Based on this, we will refer to Figure 5 illustrate Figure 4 The data stream in the illustrated pulsating array device 1000. Figure 5 This is an example Figure 4 A block diagram of the data flow in the illustrated pulsating array device 1000.

[0061] After the systolic array device 1000 is manufactured, a boot loader can load a signal for controlling the transmission sections 21 and 22 from the e-flash included in the control unit 400 or the external ROM 410, and can cause the control unit 400 to be executed in the processing units in (2, 2) and (3, 3) having a fault. In addition, the boot loader can cause bypass work to be executed in all of the processing units in the second row and all of the processing units in the third column. The weight cache unit 300 can provide the weight to each of the processing units in (1, 1), (1, 2), and (1, 4). Further, the input feature cache unit 200 can provide the input feature to each of the processing units in (1, 1), (3, 1), and (4, 1).

[0062] Then, the processing unit arranged in (1, 1) can perform processing using the input feature and the weight, and then, can transmit the sum and the weight as a result of the processing to the processing unit arranged in (2, 1) and the input feature to the processing unit arranged in (1, 2).

[0063] Then, the processing unit arranged in (2, 1) can bypass the transmitted information to the processing unit arranged in (3, 1). The processing unit arranged in (3, 1) can perform processing in the same manner as the processing unit arranged in (1, 1) and process the processing result.

[0064] Meanwhile, the processing unit arranged in (1, 2) can perform processing in the same manner as the processing unit arranged in (1, 1) based on the information transmitted from the processing unit arranged in (1, 1), and then, can transmit the processing result to the processing unit arranged in (1, 3). Then, the processing unit arranged in (1, 3) can bypass the transmitted processing result to the processing unit arranged in (1, 4).

[0065] That is, in the first embodiment, even in the case where a part of the main processing units provided to constitute the systolic array device has a fault, the systolic array device can be operated by partially using the preliminary processing unit and the main processing unit having a fault. That is, even if one of the main processing units has a fault, the systolic array can not be discarded. Therefore, the yield of the systolic array device can be improved.

[0066] Meanwhile, each processing unit is configured to receive the same synchronization signal. Through the synchronization signal, each processing performed in the processing unit is synchronized. For example, a plurality of processing units arranged in the same row (or column) can perform processing at the same point in time, and transmit the processing result to the next row (or column) at the same timing. At this time, each of the input feature, the weight, and the partial sum can be periodically transmitted to the adjacent processing unit according to the synchronization signal. Unlike this, according to the embodiment, the weight can be first loaded at each processing unit regardless of the synchronization signal.

[0067] Hereinafter, a systolic array device according to a second embodiment of the disclosure will be explained. The systolic array device according to the second embodiment can have the same configuration as the systolic array device 1000 exemplified above, and can include a processing element 10 having the same configuration as the processing element 10 exemplified above. Figure 1 Figure 2 The processing element 10 exemplified above. Thus, in the second embodiment, the parts explained in Figure 1 and Figure 2 may be referred to, and the differences between the second embodiment and the first embodiment will be explained with reference to Figures 6 to 8

[0068] Figure 6 is a schematic diagram exemplifying a processing element 10 according to the second embodiment, a processing unit 30 according to the second embodiment including the processing element 10, and an e-flash or an external ROM 410 according to the second embodiment for controlling the processing unit in a state of being connected to the processing unit 30.

[0069] With reference to Figure 6 , the processing unit 30 according to the second embodiment can include the processing element 10 and the transmission parts 31 to 32, and can be connected to the e-flash or the external ROM 410. Meanwhile, since Figure 6 the configuration exemplified above is an example, the processing unit 30 can not include at least one of the components exemplified above. Unlike this, the processing unit 30 can include components not exemplified above. Figure 6 Figure 6

[0070] Here, the processing element 10 can receive input of first information (e.g., input feature) from a first direction (e.g., column direction) and receive input of second information (e.g., weight or partial sum) from a second direction (e.g., row direction). Then, the processing element 10 can perform processing based on the input information and output a result.

[0071] ​​​​Then, the transmission parts 31 to 33 can be configured to transmit one of the following to the processing unit adjacently arranged on the other side of itself or can be configured not to transmit anything. At this time, the transmission part 31 can refer to a bypass transmission part 31, the transmission parts 32, 33 can refer to direction control transmission parts 32 and 33, and each of the transmission parts 31 to 33 can be embodied by a multiplexer.

[0072] - data received from the processing unit adjacently arranged on the other side of itself

[0073] - a result processed and output by the processing element 10 of itself.

[0074] Here, the "processing unit adjacently arranged on the other side of itself" can refer to a processing unit adjacently arranged in the same row (or column) as itself or a processing unit adjacently arranged in a diagonal direction of itself. In addition, the "processing unit adjacently arranged on the other side of itself" can refer to a processing unit adjacently arranged in the same row (or column) as itself or a processing unit adjacently arranged in a diagonal direction of itself.

[0075] The description of the e-Flash or the external ROM 410 in the first embodiment can be referred to in the description.

[0076] Meanwhile, the number of the transmission parts 31 to 33 is exemplified as three in Figure 6 , but this is only an example and the number of transmission parts can be set to two or less or four or more. For example, the number of the transmission parts 31 to 33 can be set to one for input features, one for receiving each of the weight and partial sum, and one for transmitting each of the weight and partial sum. Thus, a total of five (1+2+2) transmission parts can be provided in the processing unit.

[0077] Figure 7 is a block diagram exemplifying a systolic array device including a complex number. Figure 6 The systolic array device of the processing unit 30 exemplified in Figure 7 The exemplified case is an example, and the present application is not limited to Figure 7 the exemplification.

[0078] In Figure 7 , it is conditioned on a systolic array device including nine main processing units in the form of a 3 by 3 matrix. In addition, preliminary processing units can be additionally arranged in the form of at least one row or at least one column to the 3 by 3 matrix. Figure 7 It is exemplified that the preliminary processing units are additionally arranged in the form of one column to the 3 by 3 matrix.

[0079] If there is no failure in any of the nine main processing units, the systolic array device can operate as a processing accelerator by only the nine main processing units. In this case, the preliminary processing unit can not operate as a component of the processing accelerator.

[0080] Unlike this, depending on the situation, there can be a failure in at least one of the nine main processing units. For example, as illustrated in FIG. 2, three main processing units can have a failure. In this case, the control unit 400 can recognize information about the main processing units having a failure among the nine main processing units. Based on the recognized information, the e-flash or the external ROM 410 included in the control unit 400 can control the transmission parts 31 to 33 included in each processing unit and cause the following operations to be performed. Figure 7 Figure 7

[0081] In this case, the control unit 400 can recognize information about the main processing units having a failure among the nine main processing units. Based on the recognized information, the e-flash or the external ROM 410 included in the control unit 400 can control the transmission parts 31 to 33 included in each processing unit and cause the following operations to be performed.

[0082] <Example of control performed by the bypass transmission part 31 in the processing unit having a failure>

[0083] - In the row direction (or the column direction), control is made such that data transmitted from the processing unit adjacently arranged on one side is bypassed to the processing unit adjacently arranged on the other side

[0084] <Example of control performed by the bypass transmission part 31 in the processing unit having a failure>

[0085] - The result output from the corresponding processing element 10 is transmitted to the processing unit adjacently arranged in the other direction

[0086] <Example of control performed by the bypass transmission part 31 in the processing unit having a failure>

[0087] - No data is provided to the corresponding processing element 10

[0088] <Example of control performed by the bypass transmission part 31 in the processing unit having a failure>

[0089] - In the column direction (row direction), data is received from one of the processing unit adjacently arranged in the same row (column) as itself and the processing unit adjacently arranged in the diagonal direction and is provided to the processing element 10

[0090] <Example of control performed by the bypass transmission part 31 in the processing unit having a failure>

[0091] ​​- the corresponding processing element 10 does not output any result, and therefore, the direction control transmission part 33 does not output any result in the column direction (row direction)

[0092] <Example of control performed by the direction control transmission part 33 in the processing unit without a fault>

[0093] - the result output by the corresponding processing element 10 is transmitted to one of the processing units adjacently arranged in the column direction (row direction) and in the diagonal direction from the same row (column) as itself

[0094] Based on this, referring to Figure 8 , the data flow in the illustrated systolic array device 1000 will be explained. Figure 7 Figure 8 is a block diagram illustrating Figure 7 the data flow in the illustrated systolic array device.

[0095] After the systolic array device 1000 is manufactured, when booting, a boot loader can load a signal for controlling the transmission parts 31 to 33 from the e-flash included in the control unit 400 or the external ROM 410 at the time of booting.

[0096] By the signal, in each of the processing units (1, 1), (2, 3), and (3, 2), the data transmitted from the processing unit adjacently arranged on one side in the row direction is transmitted to the processing unit adjacently arranged on the other side, and no data or result is transmitted in the column direction.

[0097] Further, by the signal, in each of at least a part of the processing units without a fault, the result output by the processing unit itself is transmitted to the processing unit adjacently arranged on the other side in the row direction. In the column direction, the data is supplied from one of the processing unit adjacently arranged on one side of the corresponding processing unit in the same column and the processing unit adjacently arranged diagonally to the corresponding processing unit, and the result output by the processing unit itself is transmitted to one of the processing unit adjacently arranged on the other side of the corresponding processing unit in the same column and the processing unit adjacently arranged diagonally to the corresponding processing unit.

[0098] For example, referring to Figure 8 , the weight transmitted to the processing unit (1, 2) by the weight cache unit 300 is transmitted to the processing unit (3, 1) by the processing unit (2, 1), the weight transmitted to the processing unit (1, 2) by the weight cache unit 300 is transmitted to the processing unit (3, 2) by the processing unit (2, 2), and the weight transmitted to the processing unit (1, 4) by the weight cache unit 300 is transmitted to the processing unit (3, 3) by the processing unit (2, 3). ​

[0099] Thus, the input features transferred to the processing unit (1,1) by the input feature cache unit 200 are transferred to the processing unit (1,2) by being immediately bypassed, and then transferred to the processing unit (1,4) through the processing unit (1,3). Further, the input features transferred to the processing unit (2,1) by the input feature cache unit 200 are transferred to the processing unit (2,2), and then transferred to the processing unit (2,4) by being bypassed in the processing unit (2,3). Further, the input features transferred to the processing unit (3,1) by the input feature cache unit 200 are transferred to the processing unit (3,3) by being bypassed in the processing unit (3,2), and then transferred to the processing unit (3,4).

[0100] That is, in the second embodiment, even in the case where there is a failure in the main processing units provided to constitute the systolic array device, the systolic array device can be operated by partially using the preliminary processing unit and the main processing unit having the failure. That is, even in the case where there is a failure in any one of the main processing units, the systolic array device does not need to be discarded. Thus, the yield of the systolic array device can be improved.

[0101] Meanwhile, each processing unit is configured to receive the same synchronization signal. Through the synchronization signal, the processes performed in the processing units are synchronized with each other. For example, the plurality of processing units arranged in the same row (or column) can perform processing at the same timing, and can transfer the result of performing the processing to the next row (or column) at the same timing. At this time, each of the input features and the partial sums can be periodically transferred to the adjacent processing unit according to the synchronization signal. Unlike this, according to the embodiment of the disclosure, the weights can be previously loaded at each processing unit regardless of the synchronization signal.

[0102] Hereinafter, the systolic array device according to the third embodiment will be explained. The systolic array device according to the third embodiment can have the same configuration as the systolic array device 1000 illustrated in Figure 1 and can include the processing element 10 having the same configuration as the processing element 10 illustrated in Figure 2 Thus, in the third embodiment, the parts explained in Figure 1 and Figure 2 may be referred to, and the third embodiment will be explained with reference to Figures 9 to 11 the differences between the third embodiment and the first embodiment will be explained.

[0103] Figure 9is a schematic diagram illustrating a processing element 10 according to the third embodiment, a processing unit 40 including the processing element 10 according to the third embodiment, and an e-flash or an external ROM for controlling the processing unit 40 in a case of being connected to the processing unit 40 according to the third embodiment.

[0104] Referring to Figure 9 , the processing unit 40 according to the third embodiment can include the processing element 10 and the transmission parts 41 to 43, and can be connected to the e-flash or the external ROM 410 (a component included in the control unit 400). Meanwhile, since Figure 9 the configuration illustrated is an example, the processing unit 40 can not include at least one of the components illustrated in Figure 9 . Unlike this, the processing unit 40 can include a component not illustrated in Figure 9 .

[0105] Here, the processing element 10 can receive an input of first information (for example, an input feature) from a first direction (for example, a column direction), receive an input of second information (for example, a weight or a partial sum) from a second direction (for example, a row direction), and then output a result after performing a process based on the input information.

[0106] Then, the transmission parts 41 to 43 can be configured to transmit one of the following to a processing unit adjacently arranged at the other side of itself or can be configured not to transmit anything. At this time, the transmission part 41 can refer to a bypass transmission part 41, the transmission parts 42 and 43 can refer to direction control transmission parts 42 and 43, and each of the transmission parts 41 to 43 can be embodied by a multiplexer.

[0107] - data received from a processing unit adjacently arranged at the side of itself

[0108] - a result processed and output by the processing element 10 of itself

[0109] Here, the "processing unit adjacently arranged at the side of itself" can refer to a processing unit adjacently arranged at the same row (or column) as itself or a processing unit adjacently arranged in a diagonal direction of itself. In addition, the "processing unit adjacently arranged at the other side of itself" can refer to a processing unit adjacently arranged at the same row (or column) as itself or a processing unit adjacently arranged in a diagonal direction of itself.

[0110] The description of the e-flash or the external ROM 410 in the first embodiment can be referred to in the description.

[0111] Meanwhile, the number of the transmission parts 41 to 43 is not limited to Figure 9The example is shown as three, but this is just an example and the number of transmission sections can be set to two or less or four or more. For example, the number of transmission sections 41 to 43 can be set to one for receiving input features, one for transmitting input features, and one for bypassing weights and each of the sections. Therefore, a total of four (1+1+1+1) transmission components can be provided in the processing unit.

[0112] Figure 10 It exemplifies including complex numbers. Figure 9 The pulse array device of the processing unit 40 illustrated here includes a conceptual diagram of a processing unit with a fault. Figure 10 The examples shown are merely illustrations, and the invention is not limited to these examples. Figure 10 of examples.

[0113] exist Figure 10 The configuration is based on a pulsed array device comprising nine main processing units in a 3x3 matrix. Furthermore, preliminary processing units may be additionally arranged in the 3x3 matrix in at least one row or at least one column. Figure 10 The example shows the preliminary processing units arranged in a row on a 3x3 matrix.

[0114] If there is no fault in any of the nine main processing units, the pulsating array device can operate as a processing accelerator using only the nine main processing units. In this case, the preliminary processing unit may not operate as a component of the processing accelerator.

[0115] In contrast, depending on the circumstances, a failure may occur in at least one of the nine main processing units. For example, as... Figure 10 The three main processing units illustrated may be faulty. Figure 11 In this context, "faulty" is listed in the processing unit that has a fault.

[0116] In this configuration, the control unit 400 can identify information about a faulty main processing unit among the nine main processing units. Based on the identified information, the e-flash or external ROM 410 included in the control unit 400 can control the transmission sections 41 to 43 included in each processing unit and cause the following operations to be performed.

[0117] <Example of control performed by bypass transmission section 41 in a faulty processing unit>

[0118] - In the row (or column) direction, the control causes data transmitted from processing units arranged adjacently on one side to be bypassed to processing units arranged adjacently on the other side.

[0119] <Example of control performed by bypass transmission section 41 in a fault-free processing unit>

[0120] The result output from the corresponding processing element 10 is transmitted to a processing unit arranged adjacently in another direction.

[0121] <Example of control executed by the direction control transmission section 42 in a processing unit with a fault>

[0122] - No data was provided to the corresponding processing element 10

[0123] <Example of control executed by the direction control transmission section 42 in a fault-free processing unit>

[0124] - In the column direction (row direction), data is received from one of the processing units arranged adjacent to it in the same row and one of the processing units arranged adjacent to it in the diagonal direction to provide the data to the processing element 10.

[0125] <Example of control performed by the direction control transmission section 43 in a processing unit with a fault>

[0126] - The corresponding processing element 10 does not output any results, and therefore, the direction control transmission section 43 does not output any results in the column direction (row direction).

[0127] <Example of control executed by the direction control transmission section 43 in a fault-free processing unit>

[0128] The output of the corresponding processing element 10 is transmitted to one of the processing units arranged adjacent to it in the same row (column) in the column direction (row direction) and one of the processing units arranged adjacent to it in the diagonal direction.

[0129] Based on this, refer to Figure 10 , will explain Figure 11 The data stream in the illustrated pulsating array device 1000. Figure 10 This is an example Figure 11 A block diagram of the data flow in the illustrated pulsating array device 1000.

[0130] After the pulsating array device 1000 is manufactured, when booting, the bootloader can load signals for controlling the transmission sections 41 to 43 from the e-flash memory included in the control unit 400 or the external ROM 410.

[0131] By the signal, in each of the processing units (4, 1), (1, 2), and (3, 3), data transmitted from the processing unit arranged adjacent to one side of the corresponding processing unit in the column direction is transmitted to the processing unit arranged adjacent to the other side of the corresponding processing unit in the column direction, and neither receives nor transmits any data or results in the row direction.

[0132] Further, by the signal, in each of at least a part of the processing units without a fault, the result output from the processing unit itself is transmitted to the processing unit arranged adjacent on the other side in the column direction. In the row direction, data is supplied from one of the processing unit arranged adjacent to one side of the corresponding processing unit in the same row and the processing unit arranged diagonally adjacent to the corresponding processing unit, and the result output from the processing unit itself is transmitted to one of the processing unit arranged adjacent to the other side of the corresponding processing unit in the same row as itself and the processing unit arranged diagonally adjacent to the corresponding processing unit.

[0133] For example, with reference to Figure 12 , the weight transmitted to the processing unit (1, 1) by the weight cache unit 300 is transmitted to the processing unit (3, 1) through the processing unit (2, 1), and then, bypassed to the processing unit (4, 1). Further, the weight transmitted to the processing unit (1, 2) by the weight cache unit 300 is transmitted to the processing unit (2, 2) through being bypassed, and then, transmitted to the processing unit (4, 2) through the processing unit (3, 2). Further, the weight transmitted to the processing unit (1, 3) by the weight cache unit 300 is transmitted to the processing unit (2, 3), and then, transmitted to the processing unit (4, 3) through being bypassed in the processing unit (3, 3).

[0134] Thus, the input feature transmitted to the processing unit (1, 1) by the input feature cache unit 200 is transmitted to the processing unit (1, 2), and then, to the processing unit (1, 3). Further, the input feature transmitted to the processing unit (2, 1) by the input feature cache unit 200 is transmitted to the processing unit (3, 2), and then, to the processing unit (2, 3). Further, the input feature transmitted to the processing unit (3, 1) by the input feature cache unit 200 is transmitted to the processing unit (4, 2), and then, to the processing unit (4, 3).

[0135] That is, in the third embodiment, even in the case where there is a fault in a part of the main processing units arranged to constitute the systolic array device, the systolic array device can be operated by partially utilizing the preliminary processing unit and the main processing unit with the fault. That is, even in the case where there is a fault in any one of the main processing units, the systolic array device does not need to be discarded. Therefore, the yield of the systolic array device can be improved.

[0136] Meanwhile, each processing unit is configured to receive the same synchronization signal. Through the synchronization signal, processes performed in the processing units are synchronized with each other. For example, a plurality of processing units arranged in the same row (or column) can perform processing at the same timing, and can transmit a result of performing the processing to the next row (or column) at the same timing. At this time, each of the input features and partial sums can be periodically transmitted to the adjacent processing unit according to the synchronization signal. Unlike this, according to an embodiment of the disclosure, weights can be previously loaded at each processing unit regardless of the synchronization signal.

[0137] Meanwhile, Figure 12 is an example diagram regarding a configuration that can be included in the processing element 10 to acquire a control signal from the e-Flash or the external ROM 410. Referring to Figure 2 , unlike Figure 13 , a scan FF (flip-flop) 15 is included instead of the REG3 15. Here, the scan FF 15 can be added instead of the REG3 15, i.e., a register for storing a partial sum.

[0138] Then, as ​ illustrated, only the scan FF 15 is chained. If a boundary scan test vector is given according to this chain, it is possible to confirm which processing element 10 or processing unit has a fault through a result value. Thus, an effect of area reduction can be achieved. The above description illustrates the technical idea of the disclosure, and those skilled in the art to which the disclosure pertains will understand that various changes and modifications can be made without departing from the scope of the essential characteristics of the disclosure. Therefore, the exemplary embodiments disclosed herein are not intended to limit the technical idea of the disclosure, but to illustrate the disclosure, and the scope of the technical idea of the disclosure is not limited by those embodiments. Therefore, the scope of protection of the disclosure should be understood as being interpreted as defined in the following claims, and all technical ideas falling within the technical idea of the disclosure are intended to be included in the scope of the claims of the disclosure.

[0139] Industrial applicability

[0140] According to an embodiment of the disclosure, the yield of a systolic array device can be improved.

Claims

1. A pulsating array device, the pulsating array device comprising: Multiple processing units are arranged in an M x N matrix, where M and N are natural numbers. Each of the processing units includes: A processing element configured to perform predetermined processing based on data received from a processing unit arranged adjacent to a corresponding processing unit on one side, to output a result of performing the predetermined processing; and The transmission section is configured to perform one of the following operations: transmitting the received data to another processing unit arranged adjacent to the other side of the corresponding processing unit, and transmitting the result. The processing unit includes: The main processing unit is arranged in the form of a P-Q matrix, where P is a natural number equal to or less than M, Q is a natural number equal to or less than N, and the sum of P and Q is less than the sum of M and N; and The preliminary processing unit is arranged in the form of at least one row or column added to a matrix of P multiplied by Q. The preliminary processing unit performs the predetermined processing operation based on data received from a processing unit arranged adjacent to one side of the preliminary processing unit, based on whether at least one of the main processing units has a fault.

2. The pulsating array device according to claim 1, wherein, Among the plurality of processing units, the first transmission section, including the fault handling unit previously identified as having a fault, performs the operation of transmitting the received data, and The operation of transmitting the results is performed by a second transmission section in a fault-free processing unit that has been previously confirmed to be fault-free.

3. The pulsating array device according to claim 1, wherein, The received data includes input features, weights, and a partial sum, which is the output of a process performed in the processing element of the processing unit arranged adjacent to one side of the corresponding processing unit. The transmission section is configured for each of the input features, the weights, and the sections.

4. The pulsating array device according to claim 1, wherein, The transmission portion includes at least one of the following: A first bypass transmission section is configured to receive data from one of the processing units arranged adjacent to the corresponding processing unit in the same row as the corresponding processing unit, and to bypass the data to another processing unit. as well as The second bypass transmission section is configured to receive data from one of the processing units arranged adjacent to the corresponding processing unit in the same column as the corresponding processing unit, and to bypass the data to another processing unit.

5. The pulsating array device according to claim 1, wherein, The transmission component includes: A bypass transmission section, configured to receive data from one of the processing units arranged adjacent to the corresponding processing unit in the same row as the corresponding processing unit, and to bypass the data to another processing unit; and The direction control transmission section is configured to receive data from one of the processing units arranged adjacent to the corresponding processing unit in the same column as the corresponding processing unit and the processing units diagonally adjacent to the corresponding processing unit, in order to transmit the data to another processing unit.

6. The pulsating array device according to claim 1, wherein, The transmission component includes: A bypass transmission section, configured to receive data from one of the processing units arranged adjacent to the corresponding processing unit in the same column as the corresponding processing unit, to bypass the data to another processing unit; and The direction control transmission section is configured to receive data from one of the processing units arranged adjacent to the corresponding processing unit in the same row as the corresponding processing unit and the processing units diagonally adjacent to the corresponding processing unit, in order to transmit the data to another processing unit.

Images