3D Flash Memory with Back Gate

Abstract

The present invention discloses a three-dimensional flash memory provided with a back gate. According to an embodiment, the three-dimensional flash memory of the present invention is characterized in that it includes: a plurality of word lines extending horizontally on a substrate and stacked in sequence; and a plurality of strings extending in one direction on the substrate by penetrating the plurality of word lines, each of the plurality of strings includes a channel layer and a charge storage layer, the channel layer extends in the one direction, the charge storage layer extends in the one direction in a manner surrounding the channel layer, the channel layer and the charge storage layer form a plurality of memory cells corresponding to the plurality of word lines, the channel layer includes: a back gate extending in the one direction in a state where at least a part thereof is surrounded by the channel layer; and an insulating film extending in the one direction between the back gate and the channel layer.

Description

Technical Field

[0001] The following embodiments relate to a three-dimensional flash memory. More specifically, the related art relates to a three-dimensional flash memory and a method of operating the same that structurally improve cell characteristics and reliability. Background Art

[0002] A flash memory device is an Electrically Erasable Programmable Read Only Memory (EEPROM), and its memory can be widely used in various aspects, such as computers, digital cameras, MP3 players, game systems, memory sticks, etc. Such a flash memory device electrically controls the input and output of data through Fowler-Nordheim tunneling or hot electron injection.

[0003] Specifically, referring to Figure 1 showing an array of a conventional three-dimensional flash memory, the array of the three-dimensional flash memory may include a common source line CSL, bit lines BL, and a plurality of cell strings CSTR disposed between the common source line CSL and the bit lines BL.

[0004] The plurality of bit lines are arranged in a two-bit manner and are respectively connected to the plurality of cell strings CSTR in parallel. The plurality of cell strings CSTR may be commonly connected to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines and one common source line CSL. In this case, there may be a plurality of common source lines CSL, and the plurality of common source lines CSL can be arranged in a two-bit manner. Among them, a voltage having the same voltage value may be applied to the plurality of common source lines CSL, or the plurality of common source lines CSL may also be individually controlled.

[0005] Each of the plurality of cell strings CSTR includes: a ground selection transistor GST connected to the common source line CSL; a string selection transistor SST connected to the bit line BL; and a plurality of memory cell transistors MCT disposed between the plurality of ground selection transistors GST and the plurality of string selection transistors SST. Moreover, the ground selection transistor GST, the string selection transistor SST, and the plurality of memory cell transistors MCT may be connected in series.

[0006] The common source line CSL can be commonly connected to the sources of a plurality of ground selection transistors GST. In addition, the ground selection line GSL, a plurality of word lines WL0-WL3, and a plurality of string selection lines SSL disposed between the common source line CSL and the bit line BL can be respectively used as electrode layers of the ground selection transistors GST, a plurality of memory cell transistors MCT, and the string selection transistors SST. Further, each of the plurality of memory cell transistors MCT includes a memory element. Hereinafter, the string selection line SSL can be referred to as an Upper Selection Line (USL), and the ground selection line LSL can be referred to as a Lower Selection Line (LSL).

[0007] On the other hand, in order to meet excellent performance and low price required by consumers, existing three-dimensional flash memories increase integration by vertically stacking cells.

[0008] For example, referring to Figure 2 showing the structure of an existing three-dimensional flash memory, the existing three-dimensional flash memory is manufactured in such a manner that an electrode structure 215 in which a plurality of interlayer insulating layers 211 and a plurality of horizontal structures 250 are alternately and repeatedly formed is disposed on a substrate 200. The plurality of interlayer insulating layers 211 and the plurality of horizontal structures 250 may extend along a first direction. As an example, the plurality of interlayer insulating layers 211 may be silicon oxide films, and the lowermost interlayer insulating layer 211a among the plurality of interlayer insulating layers 211 may be thinner than the remaining plurality of interlayer insulating layers 211. Each of the plurality of horizontal structures 250 may include a first barrier insulating film 242, a second barrier insulating film 243, and an electrode layer 245. A plurality of electrode structures 215 are provided, and the plurality of electrode structures 215 may be disposed to face each other along a second direction intersecting the first direction. The first direction and the second direction may be Figure 2 the x-axis and the y-axis in respectively. A plurality of trenches 240 for separating the plurality of electrode structures 215 may be formed to extend along the first direction between the plurality of electrode structures 215. In the substrate 200 exposed through the plurality of trenches 240, a common source line CSL may be configured by forming a plurality of impurity regions doped at a high concentration. Although not illustrated, a plurality of separation insulating films for filling the plurality of trenches 240 may also be configured.

[0009] A plurality of vertical structures 230 of the configurable through electrode structure 215. As an example, from a planar perspective, a plurality of vertical structures 230 may be arranged along a first direction and a second direction to be configured in a matrix form. In another example, a plurality of vertical structures 230 may be arranged along the second direction but configured in a zigzag form along the first direction. Each of the plurality of vertical structures 230 may include a protective film 224, a charge storage film 225, a channel insulating film 226, and a channel layer 227. As an example, the channel layer 227 may be configured in a hollow tube form, and in this case, a buried film 228 for filling the inside of the channel layer 227 may also be configured. A drain region D may be configured above the channel layer 227, and a conductive pattern 229 may be formed on the drain region D to be connected to the bit line BL. The bit line BL may extend along a direction intersecting the plurality of horizontal electrodes 250. For example, it may extend along the second direction. As an example, a plurality of vertical structures 230 arranged along the second direction may be connected to one bit line BL.

[0010] The first barrier insulating film 242, the second barrier insulating film 243 included in the plurality of horizontal structures 250, the charge storage film 225, and the channel insulating film 226 included in the plurality of vertical structures 230 may be defined as an oxide-nitride-oxide (ONO) layer that is an information storage element of the three-dimensional flash memory. That is, a part of the information storage element is included in the plurality of vertical structures 230, and the remaining part may be included in the plurality of horizontal structures 250. As an example, the charge storage film 225 and the channel insulating film 226 in the information storage element may be included in the plurality of vertical structures 230, and the first barrier insulating film 242 and the second barrier insulating film 243 may be included in the plurality of horizontal structures 250.

[0011] A plurality of epitaxial patterns 222 may be configured between the substrate 200 and the plurality of vertical structures 230. The plurality of epitaxial patterns 222 connect the substrate 200 and the plurality of vertical structures 230. The plurality of epitaxial patterns 222 may at least contact one layer of the plurality of horizontal structures 250. That is, the plurality of epitaxial patterns 222 may be configured to contact the lowermost horizontal structure 250a. According to another embodiment, the plurality of epitaxial patterns 222 may also be configured to contact a plurality of layers. For example, they may be configured to contact the plurality of horizontal structures 250 of two layers. On the other hand, when the plurality of epitaxial patterns 222 are configured to contact the lowermost horizontal structure 250a, the thickness of the lowermost horizontal structure 250a may be greater than the thickness of the remaining plurality of horizontal structures 250. The lowermost horizontal structure 250a in contact with the plurality of epitaxial patterns 222 may correspond to the reference Figure 1The ground selection line GSL of the described three-dimensional flash memory array and the remaining plurality of horizontal structures 250 in contact with the plurality of vertical structures 230 can correspond to the plurality of word lines WL0 - WL3.

[0012] Each of the plurality of epitaxial patterns 222 has an embedded sidewall 222a. Thus, the lowermost horizontal structure 250a in contact with the plurality of epitaxial patterns 222 can be arranged along the contour of the embedded sidewall 222a. That is, the lowermost horizontal structure 250a can be arranged in a shape protruding inward along the embedded sidewalls 222a of the plurality of epitaxial patterns 222.

[0013] In the existing three-dimensional flash memory with such a structure, there is a problem that an increase in the number of vertical memory cells leads to deterioration of cell characteristics and reliability.

[0014] Therefore, the following embodiments are for providing a technique for improving cell characteristics and reliability. Summary of the Invention

[0015] Technical Problem

[0016] In order to improve cell characteristics and reliability, an embodiment proposes a three-dimensional flash memory in which a back gate is formed by extending inside a channel layer structurally.

[0017] More specifically, an embodiment proposes a three-dimensional flash memory in which a back gate to which a pass voltage for forming a channel or reserving a channel layer in the channel layer is applied is provided therein.

[0018] Technical Solution

[0019] According to an embodiment, a three-dimensional flash memory is characterized by including: a plurality of word lines, which are formed by extending in a horizontal direction on a substrate and are stacked in sequence; and a plurality of strings, which penetrate the plurality of word lines and extend in one direction on the substrate. Each of the plurality of strings includes a channel layer and a charge storage layer. The channel layer extends in the one direction, and the charge storage layer extends in the one direction so as to surround the channel layer. The channel layer and the charge storage layer form a plurality of memory cells corresponding to the plurality of word lines. The channel layer includes: a back gate, which extends in the one direction in a state where at least a part thereof is surrounded by the channel layer; and an insulating film, which extends in the one direction between the back gate and the channel layer.

[0020] According to an embodiment, the present invention is characterized in that when a program operation related to an object memory cell is performed, a pass voltage for forming a channel or reserving the channel layer in the channel layer can be applied to the back gate.

[0021] According to another embodiment, the present invention is characterized in that in the channel layer included in the selected string corresponding to the object storage unit among the plurality of strings, a ground voltage can be applied to the bit line of the selected string, a program voltage can be applied to the word line corresponding to the object storage unit among the plurality of word lines, the through voltage can be applied to the back gate, and at the same time, the word lines corresponding to the remaining storage units other than the object storage unit among the plurality of word lines can be made floating, so that a channel for performing a program operation related to the object storage unit can be formed.

[0022] According to another embodiment, the present invention is characterized in that in the channel layer included in the non-selected string that does not correspond to the object storage unit among the plurality of strings, a power supply voltage can be applied to the bit line of the non-selected string, a power supply voltage can be applied to the string selection line of the non-selected string to make the non-selected string itself floating, and at the same time, the through voltage can be applied to the back gate for reservation, so as to prevent the storage units included in the non-selected string from being programmed due to the program voltage related to the object storage unit.

[0023] According to still another embodiment, the present invention is characterized in that a structure for preventing leakage current from being generated in the ground selection line can be formed in a region of the insulating film corresponding to the ground selection line disposed at the lower ends of the plurality of word lines or in a region of the channel layer corresponding to the ground selection line.

[0024] According to yet another embodiment, the present invention is characterized in that the back gate can be extended in such a way as to pass through the internal region of the channel layer corresponding to the plurality of word lines.

[0025] According to yet another embodiment, the present invention is characterized in that the back gate can be extended to a substrate for the back gate located below the substrate on which the plurality of strings are formed in a state of passing through the substrate on which the plurality of strings are formed, and the substrate for the back gate is used for dissipating heat from the plurality of strings.

[0026] According to yet another embodiment, the present invention is characterized in that wirings for the voltage applied to the back gate can be formed on one of the upper surface or the lower surface of the substrate for the back gate.

[0027] According to another embodiment, the present invention is characterized in that the back gate can be extended to a back gate plate disposed horizontally along the lower part of the substrate on which the plurality of strings are formed in a state of penetrating and extending through the substrate on which the plurality of strings are formed, and the back gate plate can function to prevent warpage of the substrate by alleviating film stress of the plurality of word lines between the plurality of word lines and the substrate.

[0028] According to another embodiment, the present invention is characterized in that when performing a read operation related to the plurality of memory cells, a program boost voltage for increasing a threshold voltage of the plurality of memory cells can be applied to the back gate to improve a program speed related to the plurality of memory cells.

[0029] According to another embodiment, the present invention is characterized in that when performing an erase operation, an erase voltage related to the memory cells included in the plurality of strings can be applied to the back gate.

[0030] According to another embodiment, the present invention is characterized in that when performing a program operation related to a target memory cell, a program enhancement voltage for forming inversion in the channel layer during the program operation and improving a program speed of the target memory cell can be applied to the back gate.

[0031] According to another embodiment, the present invention is characterized in that when performing an erase operation, a voltage for performing an erase operation related to the memory cells included in the plurality of strings in two steps can be applied to the back gate.

[0032] According to another embodiment, the present invention is characterized in that in a first step of the erase operation, as the plurality of word lines are floated, a ground voltage for generating holes can be applied to the back gate, and in a second step of the erase operation, as a ground voltage is applied to the plurality of word lines, the back gate will be floated for hole injection.

[0033] According to an embodiment, a method for manufacturing a three-dimensional flash memory includes the following steps: preparing a semiconductor structure including a plurality of word lines, a plurality of insulating layers, and a plurality of strings, the plurality of word lines extending horizontally on a substrate and stacked in sequence, the plurality of insulating layers being alternately stacked between the plurality of word lines, the plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings including a channel layer and a charge storage layer, the channel layer extending in the one direction, the charge storage layer extending in the one direction so as to surround the channel layer, in the semiconductor structure, forming a hole in the channel layer extending in the one direction; forming an insulating film having an internal hole extending in the one direction in the hole; and forming the back gate by extending a conductive material in the internal hole of the insulating film in the one direction.

[0034] According to an embodiment, the present invention is characterized in that the back gate is used to apply a passing voltage for forming a channel or reserving the channel layer in the channel layer.

[0035] According to another embodiment, the present invention is characterized in that the hole inside the channel layer extends to a substrate for the back gate located below the substrate where the plurality of strings are formed in a state of penetrating the substrate where the plurality of strings are formed.

[0036] According to still another embodiment, a method for manufacturing a three-dimensional flash memory includes the following steps: preparing a semiconductor structure including a plurality of word lines, a plurality of insulating layers, and a plurality of strings, the plurality of word lines extending horizontally on a substrate and stacked in sequence, the plurality of insulating layers being alternately stacked between the plurality of word lines, the plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings including a channel layer and a charge storage layer, the channel layer extending in the one direction, the charge storage layer extending in the one direction so as to surround the channel layer, in the semiconductor structure, forming a hole in the channel layer extending in the one direction; forming a second insulating film having an internal hole extending in the one direction in the hole; and forming the back gate by extending a conductive material in the internal hole of the second insulating film in the one direction.

[0037] According to another embodiment, a method for manufacturing a three-dimensional flash memory includes the following steps: preparing a semiconductor structure including a plurality of word lines, a plurality of insulating layers, and a plurality of strings, where the plurality of word lines extend horizontally on a substrate and are stacked in sequence, the plurality of insulating layers are alternately stacked between the plurality of word lines, the plurality of strings penetrate the plurality of word lines and extend in one direction on the substrate, the plurality of strings respectively include a channel layer and a charge storage layer, the channel layer extends in the one direction, and the charge storage layer extends in the one direction in a manner surrounding the channel layer; in the semiconductor structure, forming a first hole extending in the one direction in the channel layer; forming an insulating film extending in the one direction in the first hole; forming a second hole extending in the one direction in the insulating film; and using a conductive material to form a back gate extending in the one direction in the second hole.

[0038] According to still another embodiment, the method for manufacturing a three-dimensional flash memory according to the present invention is characterized in that it includes the following steps: preparing a semiconductor structure including a plurality of sacrificial layers, a plurality of insulating layers, and a plurality of strings, where the plurality of sacrificial layers extend horizontally on a substrate and are stacked in sequence, the plurality of insulating layers are alternately stacked between the plurality of sacrificial layers, the plurality of strings penetrate the plurality of sacrificial layers and extend in one direction on the substrate, the plurality of strings respectively include a channel layer and a charge storage layer, the channel layer extends in the one direction, and the charge storage layer extends in the one direction in a manner surrounding the channel layer; in the semiconductor structure, forming a hole extending in the one direction in the channel layer; removing the plurality of sacrificial layers through the hole in the channel layer; using a conductive material to form a plurality of word lines in the space where the plurality of sacrificial layers are removed; forming an insulating film having an internal hole extending in the one direction in the hole; and using the conductive material to form a back gate extending in the one direction in the internal hole of the insulating film.

[0039] According to one embodiment, the method for manufacturing the three-dimensional flash memory may further include the following steps: in the upper region of each of the plurality of strings, forming wiring required for a voltage applied to the back gate in a region corresponding to the back gate; and in the upper region of each of the plurality of strings, forming bit lines of each of the plurality of strings in a region corresponding to the channel layer.

[0040] According to another embodiment, a method for manufacturing a three-dimensional flash memory includes the following steps: preparing a lower semiconductor structure including a plurality of lower word lines, a plurality of lower insulating layers, and a plurality of lower strings, the plurality of lower word lines extending horizontally on a substrate and stacked in sequence, the plurality of lower insulating layers being alternately stacked between the plurality of lower word lines, the plurality of lower strings extending in one direction on the substrate through the plurality of lower word lines, the plurality of lower strings respectively including a lower channel layer and a lower charge storage layer, the lower channel layer extending in the one direction, the lower charge storage layer extending in the one direction so as to surround the lower channel layer, the lower channel layer including a lower back gate and a lower insulating film, the lower back gate extending in the one direction in a state where at least a part thereof is surrounded by the lower channel layer, and the lower insulating film extending in the one direction between the lower back gate and the lower channel layer; preparing an upper semiconductor structure including a plurality of upper word lines, a plurality of upper insulating layers, and a plurality of upper strings, the plurality of upper word lines being stacked in sequence, the plurality of upper insulating layers being alternately stacked between the plurality of upper word lines, the plurality of upper strings extending in one direction through the plurality of upper word lines, the plurality of upper strings respectively including an upper channel layer and an upper charge storage layer, the upper channel layer extending in the one direction, the upper charge storage layer extending in the one direction so as to surround the upper channel layer, the upper channel layer including an upper back gate and an upper insulating film, the upper back gate extending in the one direction in a state where at least a part thereof is surrounded by the upper channel layer, and the upper insulating film extending in the one direction between the upper back gate and the upper channel layer; and stacking the upper semiconductor structure on the upper portion of the lower semiconductor structure in such a manner that the cross section of the lower back gate is aligned with the cross section of the upper back gate.

[0041] According to an embodiment, the present invention provides a programming operation method for a three-dimensional flash memory, wherein the three-dimensional flash memory includes: a plurality of word lines extending horizontally on a substrate and stacked in sequence; and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings including a channel layer and a charge storage layer, the channel layer extending in the one direction, the charge storage layer extending in the one direction so as to surround the channel layer, the channel layer and the charge storage layer forming a plurality of memory cells corresponding to the plurality of word lines, the channel layer including: a back gate extending in the one direction in a state where at least a part thereof is surrounded by the channel layer so as to be capable of being applied with a voltage for forming a channel in the channel layer; and an insulating film extending in the one direction between the back gate and the channel layer, the programming operation method for the three-dimensional flash memory including the following steps: applying a passing voltage for forming a channel in the channel layer or reserving the channel layer to the back gate; applying a ground voltage to a bit line of a selected string corresponding to an object memory cell to be subjected to a programming operation among the plurality of strings, applying a program voltage to a word line corresponding to the object memory cell among the plurality of word lines, applying the passing voltage to the back gate, and at the same time floating word lines corresponding to remaining memory cells other than the object memory cell among the plurality of word lines, so as to form a channel for performing a programming operation related to the object memory cell in the channel layer included in the selected string; and applying a power supply voltage to a bit line of a non-selected string not corresponding to the object memory cell among the plurality of strings, applying a power supply voltage to a string selection line of the non-selected string to make the non-selected string itself float, and at the same time applying the passing voltage to the back gate to reserve the channel layer included in the non-selected string, so as to prevent memory cells included in the non-selected string from being programmed due to the program voltage related to the object memory cell.

[0042] According to an embodiment, the present invention provides a method for a read operation of a 3D flash memory. The 3D flash memory includes: a plurality of word lines extending in a horizontal direction on a substrate and stacked in sequence; and a plurality of strings extending in a direction on the substrate through the plurality of word lines. Each of the plurality of strings includes a channel layer and a charge storage layer. The channel layer extends in the one direction, and the charge storage layer extends in the one direction so as to surround the channel layer. The channel layer and the charge storage layer form a plurality of memory cells corresponding to the plurality of word lines. The channel layer includes: a back gate extending in the one direction in a state where at least a part thereof is surrounded by the channel layer so that a voltage for forming a channel in the channel layer can be applied; and an insulating film extending in the one direction between the back gate and the channel layer. The method for the read operation of the 3D flash memory includes the following steps: applying a program enhancement voltage to the back gate to increase a threshold voltage of the plurality of memory cells to improve a program speed related to the plurality of memory cells; and applying a power supply voltage to a bit line of a selected string corresponding to an object memory cell to be a read operation object among the plurality of strings, applying a verification voltage to a word line corresponding to the object memory cell among the plurality of word lines, and applying a pass voltage to word lines corresponding to remaining memory cells other than the object memory cell among the plurality of word lines, thereby performing a read operation related to the selected string.

[0043] According to an embodiment, the present invention provides a method for an erase operation of a 3D flash memory. The 3D flash memory includes: a plurality of word lines extending in a horizontal direction on a substrate and stacked in sequence; and a plurality of strings extending in a direction on the substrate through the plurality of word lines. Each of the plurality of strings includes a channel layer and a charge storage layer. The channel layer extends in the one direction, and the charge storage layer extends in the one direction so as to surround the channel layer. The channel layer and the charge storage layer form a plurality of memory cells corresponding to the plurality of word lines. The channel layer includes: a back gate extending in the one direction in a state where at least a part thereof is surrounded by the channel layer so that a voltage for forming a channel in the channel layer can be applied; and an insulating film extending in the one direction between the back gate and the channel layer. The method for the erase operation of the 3D flash memory includes the following step of applying an erase voltage related to the memory cells included in the plurality of strings to the back gate.

[0044] According to another embodiment, the present invention provides a programming operation method for a 3D flash memory, wherein the 3D flash memory includes: a plurality of word lines extending in a horizontal direction on a substrate and stacked in sequence; and a plurality of strings extending in a direction on the substrate through the plurality of word lines, each of the plurality of strings including a channel layer and a charge storage layer, the channel layer extending in the one direction, the charge storage layer extending in the one direction so as to surround the channel layer, the channel layer and the charge storage layer forming a plurality of memory cells corresponding to the plurality of word lines, the channel layer including: a back gate extending in the one direction in a state where at least a part thereof is surrounded by the channel layer so that a voltage for forming a channel in the channel layer can be applied; and an insulating film extending in the one direction between the back gate and the channel layer, the programming operation method for the 3D flash memory including the following steps: applying a programming enhancement voltage to the back gate for improving the programming speed of an object memory cell to be programmed; applying a pass voltage to the remaining word lines among the plurality of word lines except for the word line corresponding to the object memory cell; and forming an inversion in the channel layer included in a selected string corresponding to the object memory cell among the plurality of strings as the programming enhancement voltage is applied to the back gate.

[0045] According to another embodiment, the present invention provides an erasing operation method for a 3D flash memory, wherein the 3D flash memory includes: a plurality of word lines extending in a horizontal direction on a substrate and stacked in sequence; and a plurality of strings extending in a direction on the substrate through the plurality of word lines, each of the plurality of strings including a channel layer and a charge storage layer, the channel layer extending in the one direction, the charge storage layer extending in the one direction so as to surround the channel layer, the channel layer and the charge storage layer forming a plurality of memory cells corresponding to the plurality of word lines, the channel layer including: a back gate extending in the one direction in a state where at least a part thereof is surrounded by the channel layer so that a voltage for forming a channel in the channel layer can be applied; and an insulating film extending in the one direction between the back gate and the channel layer, the erasing operation method for the 3D flash memory including the following steps: in a first step of the erasing operation, applying a ground voltage for generating holes to the back gate as the plurality of word lines are floated; and in a second step of the erasing operation, floating the back gate as a ground voltage is applied to the plurality of word lines so as to achieve hole injection.

[0046] Technical effects

[0047] In order to improve cell characteristics and reliability, an embodiment of the present invention may propose a 3D flash memory in which a back gate is structurally formed to extend inside a channel layer.

[0048] More specifically, an embodiment of the present invention may provide a three-dimensional flash memory in which a back gate to which a pass voltage to be applied to form a channel or reserve a channel layer is provided therein. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic circuit diagram showing an array of a conventional three-dimensional flash memory;

[0050] Figure 2 A perspective view showing the structure of a conventional three-dimensional flash memory;

[0051] Figure 3a A Y-Z cross-sectional view showing a three-dimensional flash memory according to an embodiment;

[0052] Figure 3b To show Figure 3a An X-Y top view of an A-A' line cross-section of the three-dimensional flash memory shown;

[0053] Figures 4a to 4d A Y-Z cross-sectional view showing another example of a three-dimensional flash memory according to an embodiment;

[0054] Figures 5a to 5b A Y-Z cross-sectional view showing a three-dimensional flash memory according to another embodiment;

[0055] Figure 6 A flowchart showing a program operation of a three-dimensional flash memory according to an embodiment;

[0056] Figure 7 A Y-Z cross-sectional view for explaining a program operation of a three-dimensional flash memory according to an embodiment;

[0057] Figure 8 A flowchart showing a program operation of a three-dimensional flash memory according to another embodiment;

[0058] Figure 9 A Y-Z cross-sectional view for explaining a program operation of a three-dimensional flash memory according to another embodiment;

[0059] Figure 10 A flowchart showing a read operation of a three-dimensional flash memory according to an embodiment;

[0060] Figure 11 A flowchart showing an erase operation of a three-dimensional flash memory according to an embodiment;

[0061] Figure 12 A flowchart showing an erase operation of a three-dimensional flash memory according to another embodiment;

[0062] Figure 13Y-Z cross-sectional view for explaining the erasing operation of a 3D flash memory according to another embodiment;

[0063] Figure 14 Flowchart showing a method of manufacturing a 3D flash memory according to an embodiment;

[0064] Figures 15a to 15d For explaining the Figure 14 Y-Z cross-sectional view of a first example related to the method of manufacturing the 3D flash memory shown;

[0065] Figures 16a to 16b For explaining the Figure 14 Y-Z cross-sectional view of a second example related to the method of manufacturing the 3D flash memory shown;

[0066] Figure 17 Flowchart showing a method of manufacturing a 3D flash memory according to yet another embodiment;

[0067] Figures 18a to 18k For explaining the Figure 17 Y-Z cross-sectional view of an example related to the method of manufacturing the 3D flash memory shown;

[0068] Figure 19 Flowchart showing a method of manufacturing a 3D flash memory according to another embodiment;

[0069] Figures 20a to 20e For explaining the Figure 19 Y-Z cross-sectional view of an example related to the method of manufacturing the 3D flash memory shown;

[0070] Figure 21 Flowchart showing a method of manufacturing a 3D flash memory according to still another embodiment;

[0071] Figures 22a to 22b For explaining the Figure 21 Y-Z cross-sectional view of an example related to the method of manufacturing the 3D flash memory shown;

[0072] Figures 23a to 23g X-Y top view for explaining various structures of a back gate according to an embodiment;

[0073] Figure 24 Y-Z cross-sectional view for explaining the formation position of wiring required for the voltage applied to a back gate according to an embodiment. DETAILED DESCRIPTION

[0074] Hereinafter, a plurality of embodiments will be described in detail with reference to the drawings. However, the present invention is not limited or restricted to the following embodiments. Also, the same reference numerals in the respective drawings denote the same components.

[0075] Also, the terminology used in this specification is a terminology used for appropriately expressing the preferred embodiments of the present invention, which may vary depending on the intention of the user, the applier, or the convention in the technical field to which the present invention pertains. Therefore, the definitions of these terms should be based on the entire content of this specification.

[0076] Hereinafter, in a Y-Z cross-sectional view showing a three-dimensional flash memory, in terms of the three-dimensional flash memory, for ease of explanation, structural elements such as bit lines located above a plurality of strings and source lines located below a plurality of strings are omitted in the illustration and description. However, the three-dimensional flash memory described later is not limited or restricted thereto, and may further include additional structural elements on the basis of the structure of the existing three-dimensional flash memory shown. Figure 2 On the basis of the structure of the existing three-dimensional flash memory shown, additional structural elements are included.

[0077] Figure 3a FIG. is a Y-Z cross-sectional view showing a three-dimensional flash memory according to an embodiment. Figure 3b To show Figure 3a FIG. is an X-Y top view of a cross-section taken along line A-A' of the three-dimensional flash memory shown. Figures 4a to 4d FIG. is a Y-Z cross-sectional view showing another example of a three-dimensional flash memory according to an embodiment. Figures 5a to 5b FIG. is a Y-Z cross-sectional view showing a three-dimensional flash memory according to another embodiment.

[0078] Referring to Figures 3a to 3b , a three-dimensional flash memory 300 according to an embodiment includes a plurality of word lines 310 and a plurality of strings 320, 330.

[0079] The plurality of word lines 310 are sequentially stacked on the substrate 305 in a state of extending along the horizontal direction (e.g., the Y direction), and are respectively formed of a conductive material such as W, Ti, Ta, Cu, Mo, Ru, or Au (in addition to the metal materials described above, all metal materials capable of forming ALD are also included), and a storage operation (read operation, program operation, erase operation, etc.) can be performed by applying a voltage to the respective corresponding memory cells. A plurality of insulating layers 311 formed of an insulating material may be provided between such a plurality of word lines 310.

[0080] A string selection line may be disposed at the upper end of such a plurality of word lines 310, and a ground selection line may be disposed at the lower end.

[0081] A plurality of strings 320 and 330 penetrate through a plurality of word lines 310 and extend along a direction (e.g., the Z direction) on a substrate 305, and respectively include a channel layer 321, 331 and a charge storage layer 322, 332, so that a plurality of memory cells corresponding to the plurality of word lines 310 can be formed.

[0082] The charge storage layers 322 and 332 are structural elements that extend in a manner surrounding the channel layers 321 and 331 and trap charges or holes or maintain the charge state by means of the voltage applied through the plurality of word lines 310, and can function as data storage locations in the 3D flash memory 300. As an example, the charge storage layers 322 and 332 can use an oxide-nitride-oxide (ONO) layer or a ferroelectric layer.

[0083] The channel layers 321 and 331 are structural elements that perform a storage operation by means of the voltage applied through the plurality of word lines 310, string selection lines, ground selection lines, and bit lines, and can be formed of single-crystalline silicon or polycrystalline silicon. Also, the channel layers 321 and 331 can perform a storage operation by means of the voltage applied through back gates 323 and 333 described later. A detailed description thereof will be given later.

[0084] The channel layers 321 and 331 include: back gates 323 and 333, which extend along a direction (e.g., the Z direction) in a state where at least a part thereof is surrounded by the channel layers 321 and 331; and insulating films 324 and 334, which extend along a direction between the back gates 323 and 333 and the channel layers 321 and 331. Hereinafter, at least a part of the back gates 323 and 333 being surrounded by the channel layers 321 and 331 will include the case where the back gates 323 and 333 are included in at least a part of the channel layers 321 and 331 or penetrate through the channel layers 321 and 331.

[0085] Among them, the channel layers 321 and 331 can form a structure for preventing leakage current from occurring in the ground selection line. For example, a structure can be formed such that, for the regions of the channel layers 321 and 331 corresponding to the ground selection line disposed at the lower ends of the plurality of word lines 310, more boron (B) is introduced into the regions of the channel layers 321 and 331 corresponding to the ground selection line, thereby increasing the threshold voltage of the corresponding regions.

[0086] The back gates 323 and 333 can be formed of a conductive material such as W, Ti, Ta, Cu, Mo, Ru, or Au (in addition to the metal materials described above, all metal materials that can form ALD) or polysilicon doped with the conductive material as described above, and are formed in the channel layers 321 and 331 to extend through the internal region corresponding to the plurality of word lines 310 (the region from the ground selection line to the plurality of word lines 310). However, it is not limited or restricted thereto. As Figure 4a shown, it can be formed to extend through the internal region corresponding to the region from the ground selection line to the string selection line in the channel layers 321 and 331.

[0087] Moreover, the back gates 323 and 333 are formed to extend through the substrate 305 in which the plurality of strings 320 and 330 are formed in a penetrating manner and extend to the substrate 315 for the back gates 323 and 333 located below the substrate 305. That is, the three-dimensional flash memory 300 provided with the back gates 323 and 333 can form a double-substrate structure.

[0088] In the double-substrate structure, the lower substrate 315 can be used for dissipating heat from the plurality of strings 320 and 330. Since the heat dissipation path of the plurality of strings 320 and 330 is located in the substrate 315 separated from the substrate 305 in which the plurality of strings 320 and 330 are formed, the problem that the unit transistors are affected due to the formation of the heat dissipation path of the plurality of strings 320 and 330 in the substrate 305 in which the plurality of strings 320 and 330 are formed can be solved.

[0089] However, it is not limited or restricted thereto. As Figures 4b to 4d shown, the three-dimensional flash memory 300 provided with the back gates 323 and 333 can form a single-substrate structure. In this case, as Figure 4b shown, on the substrate 305 in which the plurality of strings 320 and 330 are formed, the back gates 323 and 333 are formed to extend through the internal region corresponding to the plurality of word lines 310 (the region from the ground selection line to the plurality of word lines 310) in the channel layers 321 and 331. As Figure 4c shown, on the substrate 305 in which the plurality of strings 320 and 330 are formed, the back gates 323 and 333 are formed to extend through the internal region corresponding to the region from the ground selection line to the string selection line in the channel layers 321 and 331.

[0090] Moreover, in the three-dimensional flash memory 300 provided with back gates 323 and 333, in a single substrate structure of a substrate 305 in which a plurality of word lines 310 are stacked and a plurality of strings 320 and 330 extend in one direction, a back gate plate 325 disposed horizontally along the lower portion of the substrate 305 in a state of penetrating the substrate 305 may further be included. Such a back gate plate 325 is formed of the same material as the back gates 323 and 333, and may function to prevent warpage of the substrate 305 by alleviating the film stress of the plurality of word lines 310. In such a structure, the back gates 323 and 333 may extend to the back gate plate 325.

[0091] As Figure 4a , Figure 4b and Figure 4d shown, in both the single substrate structure and the double substrate structure, wirings 340 required for voltages applied to the back gates 323 and 333 may be formed on the upper surfaces of the substrates 305 and 315 connected to the back gates 323 and 333. However, without being limited or restricted to the drawings, the wirings 340 required for voltages applied to the back gates 323 and 333 may be formed on the lower surfaces (not shown) of the substrates 305 and 315 connected to the back gates 323 and 333, or may also be formed on the upper portions of the back gates 323 and 333. Detailed descriptions related thereto will be described with reference to Figure 24 .

[0092] Voltages for operating the three-dimensional flash memory 300 may be applied to the back gates 323 and 333 as described above. For example, when a program operation is performed, a pass voltage for forming a channel or reserving the channel layers 321 and 331 may be applied to the back gates 323 and 333 in the channel layers 321 and 331. When a read operation is performed, a program boost voltage for increasing the threshold voltage of the memory cells may be applied to the back gates 323 and 333 to improve the program speed in the subsequent program operation. When an erase operation is performed, an erase voltage related to the memory cells may be applied to the back gates 323 and 333. Detailed descriptions related to applying the pass voltage for forming a channel or reserving the channel layers 321 and 331 to the back gates 323 and 333 when a program operation is performed will be described with reference to Figures 6 to 7 , and detailed descriptions related to applying the program boost voltage for increasing the threshold voltage of the memory cells to the back gates 323 and 333 when a read operation is performed will be described with reference to Figure 10 , and detailed descriptions related to applying the erase voltage for the memory cells to the back gates 323 and 333 when an erase operation is performed will be described with reference to Figure 11 .

[0093] In other examples, a program boost voltage for inverting the channel layers 321 and 331 and improving the program speed during a program operation may be applied to the back gates 323 and 333. When an erase operation is performed, a voltage for performing the erase operation in two steps may also be applied. A detailed description related to applying the program boost voltage for inverting the channel layers 321 and 331 and improving the program speed to the back gates 323 and 333 during a program operation will be described with reference to Figures 8 to 9 and a detailed description related to applying the voltage for performing the erase operation in two steps to the back gates 323 and 333 when an erase operation is performed will be described with reference to Figures 12 to 13 for description.

[0094] Moreover, the back gates 323 and 333 are used in the process of initially adjusting the threshold voltage of the memory cells in units of blocks formed by grouping the plurality of strings 320 and 330, whereby read operations, program operations, and erase operations can be performed in a manner not affected by the structural deviation of the strings in the block unit. For example, the 3D flash memory 300 can apply a fine adjustment voltage through the back gates 323 and 333 in consideration of the structural deviation of the strings in the block unit, thereby compensating the initial threshold voltage of the memory cells at the block level so as to adjust them uniformly or identically. As a more specific example, a voltage of -0.2V is applied to the back gate of the string included in block A, and a voltage of -0.1V is applied to the back gate of the string included in block B, whereby the initial threshold voltages of the memory cells of the strings included in block A and the initial threshold voltages of the memory cells of the strings included in block B can be set to be the same. As described above, the structure of the back gates 323 and 333 formed in such a way that different voltages can be applied in units of blocks formed by grouping the strings 320 and 330 has been described, but it is not limited or restricted thereto. The back gates 323 and 333 can also be formed in a structure electrically separated by string so that different voltages can be applied in units of strings to compensate and adjust the initial threshold voltage in units of strings.

[0095] The insulating films 324 and 334 may be formed of an insulating material to prevent the back gates 323 and 333 from directly contacting the channel layers 321 and 331. In particular, a structure for preventing leakage current from occurring in the ground selection line may be formed. For example, as Figures 5a to 5b shown, the regions 312 of the insulating films 324 and 334 corresponding to the ground selection lines disposed at the lower ends of the plurality of word lines 310 may have a greater thickness than the remaining regions in order to prevent leakage current from occurring in the ground selection line.

[0096] As described above, a structure in which the back gates 323 and 333 and the insulating films 324 and 334 are formed in the internal holes of the channel layers 321 and 331 and the channel layers 321 and 331 surround without gaps has been described, but it is not limited or restricted thereto, and a structure in which only at least a part is surrounded by the channel layers 321 and 331 may also be formed. A detailed description thereof will be given with reference to Figures 23a to 23g for description.

[0097] The storage operations described below are based on being performed by a 3D flash memory having a structure formed as described with reference to Figures 3a to 3b the structure described, and can similarly be performed in a 3D flash memory having a structure formed as described with reference to Figures 4a to 4d and Figures 5a to 5b the structure described.

[0098] Figure 6 FIG. is a flowchart showing the program operation of a 3D flash memory according to an embodiment, Figure 7 and FIG. is a Y-Z cross-sectional view for explaining the program operation of a 3D flash memory according to an embodiment. The program operations described below are based on applying a pass voltage for forming a channel or reserving a channel in the channel layer to the back gate.

[0099] Referring to Figure 6 , in step S610, a pass voltage for forming a channel or reserving the channel layers 731 and 741 in the channel layers 731 and 741 can be applied to the back gates 710 and 720 in the 3D flash memory.

[0100] More specifically, in step S610, as Figure 7 shown, in the 3D flash memory, for the selected string 730 corresponding to the target storage cell 750 that is the object of the program operation among the plurality of strings, a ground voltage (0V) is applied to the bit line of the selected string 730, a power supply voltage Vcc (for example, 3.3V) is applied to the string selection line, a ground voltage (0V) is applied to the ground selection line, and then a program voltage Vpgm is applied to the word line corresponding to the target storage cell 750 among the plurality of word lines, causing the word lines corresponding to the remaining storage cells other than the target storage cell 750 among the plurality of word lines to float, and at the same time, a pass voltage (for example, 6V) can be applied to the back gate 710.

[0101] Among them, the value of the pass voltage applied to the back gates 710 and 720 can be determined according to the thickness of the insulating films 711 and 721 surrounding the back gates 710 and 720. As an example, if the thickness of the insulating films 711 and 721 reaches 5 nm, the value of the pass voltage applied to the back gates 710 and 720 can be determined to be 3 V to 4 V. If the thickness of the insulating films 711 and 721 reaches 10 nm, the value of the pass voltage applied to the back gates 710 and 720 can be determined to be 5 V to 10 V. If the thickness of the insulating films 711 and 721 reaches 10 nm, the value of the pass voltage applied to the back gates 710 and 720 can be determined to be 7 V to 15 V.

[0102] In this case, in step S610, as Figure 7 shown, in the three-dimensional flash memory, for non-selected strings 740 in a plurality of strings that do not correspond to the target storage unit 750, a power supply voltage Vcc (e.g., 3.3 V) is applied to the bit lines of the non-selected strings 740, and a power supply voltage Vcc (e.g., 3.3 V) is applied to the string selection lines of the non-selected strings 740, thereby shutting off the string selection lines of the non-selected strings 740, so that the non-selected strings 740 can float. Similarly, a ground voltage (0 V) is applied to the ground selection lines of the non-selected strings 740, and a program voltage Vpgm is applied to the word lines corresponding to the target storage unit 750 among the plurality of word lines, so that the word lines corresponding to the remaining storage units except the target storage unit 750 among the plurality of word lines can float. And, since the back gate 720 of the non-selected string 740 and the back gate 710 of the selected string 730 are connected by a common wiring, a pass voltage same as the pass voltage applied to the back gate 710 of the selected string 730 (e.g., 6 V) can be applied to the back gate 720 of the non-selected string 740.

[0103] Next, in step S620, a ground voltage is applied to the bit lines of the selected string 730 in the three-dimensional flash memory, a program voltage is applied to the word lines corresponding to the target storage unit 750 among the plurality of word lines, and a pass voltage is applied to the back gate 710, while making the word lines corresponding to the remaining storage units except the target storage unit 750 among the plurality of word lines float, so that a channel for performing a program operation related to the target storage unit 750 can be formed in the channel layer 731 included in the selected string 730.

[0104] After that, in step S630, as a power supply voltage is applied to the bit lines of the non-selected strings 740 and a power supply voltage is applied to the string selection lines of the non-selected strings 740 to make the non-selected strings 740 themselves float, and a pass voltage is applied to the back gate 720, the manufacturing system reserves the channel layer 741 included in the non-selected strings 740, so that the storage units included in the non-selected strings 740 can be prevented from being programmed by the program voltage related to the target storage unit 750.

[0105] By performing program operations through steps S610 and S620 as described above, it is possible not to apply a pass voltage to the word lines corresponding to the remaining memory cells other than the target memory cell 750, which can prevent a disturbance phenomenon caused by applying a pass voltage from the target memory cell 750 to the word lines corresponding to the remaining memory cells. Therefore, due to the improvement of the program operation characteristics, the cell characteristics and reliability are also improved, and the speed of forming a channel in the channel layer 731 of the selected string 730 can be increased.

[0106] Moreover, by performing program operations through steps S610 and S630, it is possible not to apply a pass voltage to the word lines corresponding to the remaining memory cells other than the target memory cell 750, which can prevent a disturbance phenomenon caused by applying a pass voltage from the target memory cell 750 to the word lines corresponding to the remaining memory cells, and the speed of the channel layer 741 of the reserved non-selected string 740 can be increased.

[0107] In this case, leakage current generated in the ground selection line of the non-selected string 740 can be suppressed by making the thickness of the insulating film 721 of the non-selected string 740 greater than that of other regions. Alternatively, a structure can also be adopted in which more boron (B) is introduced into the region corresponding to the ground selection line in the channel layer 741 of the non-selected string 740 to increase the threshold voltage of the corresponding region, thereby suppressing leakage current generated in the ground selection line of the non-selected string 740.

[0108] Furthermore, since a pass voltage was previously applied to the word lines in the non-selected string that do not correspond to the target memory cell, there was a problem of a sharp increase in the step difference in reserving the channels of the word lines that do not correspond to the target memory cell and the channels of the word lines that correspond to the target memory cell. However, in the program operations performed through steps S610 and S630 described above, since the entire channel layer 741 of the non-selected string 740 can be reserved simultaneously, the channel potential of the channel layer 741 is improved during reservation, so that the electric field profile in the channel slopes slowly along the periphery of the position of the word line corresponding to the target memory cell.

[0109] As described above, program operations are performed based on the method of applying a pass voltage for forming or reserving channels in the channel layers 731 and 741 through the back gates 710 and 720, thereby replacing the method of applying through the word lines. However, this is not limited or restricted thereto. Program operations can also be performed by additionally applying a separate voltage to the back gates 710 and 720 on the premise of applying a pass voltage for forming or reserving channels in the channel layers 731 and 741 through the word lines. A detailed description thereof will be provided by referring to Figure 8 andFigure 9 be described.

[0110] Figure 8 FIG. is a flowchart showing the program operation of a three-dimensional flash memory according to another embodiment. Figure 9 FIG. is a Y-Z cross-sectional view for explaining the program operation of a three-dimensional flash memory according to another embodiment. The program operation described below is based on applying a program enhancement voltage to the back gate to form an inversion in the channel layer during the program operation and improve the program speed of the target memory cell.

[0111] Refer to Figure 8 , in step S810, a program enhancement voltage for improving the program speed of the target memory cell 930 that is the object of the program operation can be applied to the back gates 910, 920 in the three-dimensional flash memory.

[0112] More specifically, in step S810, as Figure 9 shown, in the three-dimensional flash memory, a program enhancement voltage can be applied to the back gate 910 of the selected string 940 corresponding to the target memory cell 930 among the multiple strings. The back gates 920 of the non-selected strings 950 and the back gate 910 of the selected string 940 are connected by a common wiring, so a program enhancement voltage identical to the program enhancement voltage applied to the back gate 910 of the selected string 940 can also be applied to the back gate 920 of the non-selected strings 950.

[0113] Herein, the value of the program enhancement voltage applied to the back gates 910, 920 can be determined according to the thickness of the insulating films 911, 921 surrounding the back gates 910, 920.

[0114] Next, in step S820, in the three-dimensional flash memory, a pass voltage can be applied to the remaining word lines among the multiple word lines except for the word line corresponding to the target memory cell 930.

[0115] Specifically, in step S820, as Figure 9 shown, in the three-dimensional flash memory, for the selected string 940 corresponding to the target memory cell 930 that is the object of the program operation among the multiple strings, a ground voltage (0V) can be applied to the bit line of the selected string 940, a power supply voltage Vcc (e.g., 3.3V) can be applied to the string selection line, a ground voltage (0V) can be applied to the ground selection line, and then a program voltage Vpgm can be applied to the word line corresponding to the target memory cell 930 among the multiple word lines, and a pass voltage (e.g., 5V) can be applied to the word lines corresponding to the remaining memory cells except for the target memory cell 930.

[0116] In this case, in step S820, as Figure 9As shown, in a 3D flash memory, for non-selected strings 950 in multiple strings that do not correspond to the target memory cell 930, a power supply voltage Vcc (e.g., 3.3V) can be applied to the bit lines of the non-selected strings 950. Similarly, a power supply voltage Vcc (e.g., 3.3V) can be applied to the string selection lines of the non-selected strings 950, a ground voltage (0V) can be applied to the ground selection lines, a program voltage Vpgm can be applied to the word lines corresponding to the target memory cell 930 among the multiple word lines, and a pass voltage (e.g., 5V) can be applied to the word lines corresponding to the remaining memory cells other than the target memory cell 930 among the multiple word lines.

[0117] After that, in step S830, as a program intensifying voltage is applied to the back gates 910, 920, the manufacturing system can invert the channel layer 941 included in the selected string 940.

[0118] By performing the program operation through steps S810 and S830 as described above, the channel layer 911 can be inverted as the program intensifying voltage is applied to the back gates 910, 920. Based on this, the value of the pass voltage applied to the word lines corresponding to the remaining memory cells other than the target memory cell 930 can be made lower, thereby preventing an interference phenomenon from occurring in the target memory cell 930. Thus, the cell characteristics and reliability can also be improved by improving the program operation characteristics, and the speed at which the channel layer 941 of the selected string 940 forms a channel can be increased.

[0119] Figure 10 A flowchart showing the read operation of a 3D flash memory according to an embodiment.

[0120] Refer to Figure 10 In step S1010, a program enhancing voltage can be applied to the back gate in the 3D flash memory. Among them, the program enhancing voltage is a voltage used to improve the speed of the program operation performed after the read operation, and can be a voltage formed as a negative value to increase the threshold voltages of multiple memory cells.

[0121] That is, step S1010 is a step required for the subsequent program operation. After first performing step S1010 of applying the program enhancing voltage to the back gate, a normal read operation such as step S1020 can be performed.

[0122] Moreover, in step S1010, the 3D flash memory can apply a voltage for performing a normal read operation.

[0123] More specifically, in a three-dimensional flash memory, a power supply voltage can be applied to the bit lines of the selected strings corresponding to the target memory cells to be read among the multiple strings, a verification voltage (Vverify) can be applied to the word lines corresponding to the target memory cells among the multiple word lines, and a pass voltage can be applied to the word lines corresponding to the remaining memory cells other than the target memory cells among the multiple word lines.

[0124] After that, in step S1020, a power supply voltage can be applied to the bit lines of the selected strings in the three-dimensional flash memory, a verification voltage can be applied to the word lines corresponding to the target memory cells among the multiple word lines, and a pass voltage can be applied to the word lines corresponding to the remaining memory cells other than the target memory cells among the multiple word lines, thereby enabling a read operation related to the selected strings to be performed.

[0125] In this way, by performing step S1010 for improving the speed of subsequent programming operations during the read operation, the threshold voltage of the memory cells can be increased and thereby the programming operation speed can be improved.

[0126] Moreover, by performing the read operation through steps S1010 and S1020, when the three-dimensional flash memory controls the back gate in units of blocks formed by grouping multiple strings, the back gate can be used to improve channel reservation for non-selected blocks including non-selected strings, and the back gate can be used to improve channel reservation for non-selected strings in the selected blocks including the selected strings. Interference phenomena caused by applying a pass voltage from the target memory cells of the selected strings to the word lines corresponding to the remaining memory cells can be prevented. As a result, cell characteristics and reliability can be improved.

[0127] Furthermore, as a program boost voltage is applied to the back gate in step S1010, the voltage electric field formed along the back gate direction from the word lines is uniformly distributed, thereby preventing accidental lateral diffusion of electrons. For example, a three-dimensional flash memory with an existing structure without a back gate has the following problem: due to the electric fields of the pass voltages applied to the corresponding word lines and the pass voltages applied to adjacent word lines, lateral diffusion of electrons occurs, resulting in deteriorated cell characteristics. However, the three-dimensional flash memory according to an embodiment can make the voltage electric field uniformly distributed along the direction from the word lines towards the back gate by applying a program boost voltage to the back gate in step S1010 described above, thereby preventing accidental lateral diffusion of electrons and thus solving the problem of deteriorated cell characteristics.

[0128] Figure 11 The flowchart shows the erase operation of a three-dimensional flash memory according to an embodiment.

[0129] Refer to Figure 11, the 3D flash memory can perform a body erasure method based on the back gate by applying an erasure voltage related to the memory cells included in a plurality of strings to the back gate in step S1110.

[0130] Compared with the body erasure method, this back-gate-based erasure method can improve the erasure operation speed by making the movement of holes easier.

[0131] Figure 12 The flowchart shows the erasure operation of the 3D flash memory according to another embodiment. Figure 13 The Y-Z cross-sectional view is used to illustrate the erasure operation of the 3D flash memory according to another embodiment. The feature of the following description is that when performing the erasure operation, a voltage for performing the erasure operation related to the memory cells in two steps (the first step and the second step) is applied to the back gate. For the sake of convenience in explanation, in Figure 13 a specific memory cell to be erased in the 3D flash memory is enlarged and shown.

[0132] Refer to Figure 12 , in step S1210, the 3D flash memory floats a plurality of word lines and applies an erasure voltage (e.g., 10V) to the channel body in the first step of the erasure operation as shown in 1310 in Figure 13 , so that a ground voltage (e.g., 10V) for generating holes can be applied to the back gate. Thus, a channel can be formed in the channel layer by generating holes.

[0133] After that, in step S1220, the 3D flash memory applies a ground voltage to the plurality of word lines and applies an erasure voltage (e.g., 10V) to the channel body in the second step of the erasure operation as shown in 1320 in Figure 13 , so that the back gate floats for hole injection. Thus, hole injection can be performed on the charge storage layer.

[0134] Hereinafter, the manufacturing method of the 3D flash memory described will be premised on being executed by a manufacturing system that realizes automation and mechanization, which means a method for manufacturing the 3D flash memory described with reference to Figures 3a to 3b , but is not limited or restricted thereto, and can also be used as a method for manufacturing the 3D flash memory whose structure is described with reference to Figures 4a to 4d , Figures 5a to 5b .

[0135] Moreover, for the sake of convenience in explanation, in the drawings related to the manufacturing method of the 3D flash memory described below, a plurality of strings are shown in the form of one string.

[0136] Figure 14 The flowchart shows the manufacturing method of the 3D flash memory according to an embodiment. Figures 15a to 15d For the purpose of illustrationFigure 14 A Y-Z cross-sectional view of a first example related to a method of manufacturing the three-dimensional flash memory shown Figures 16a to 16b For the purpose of illustration in connection with Figure 14 A Y-Z cross-sectional view of a second example related to a method of manufacturing the three-dimensional flash memory shown

[0137] Referring to Figure 14 In step S1410, the manufacturing system may prepare a semiconductor structure

[0138] For example, as Figure 15a shown, the manufacturing system may prepare a semiconductor structure including: a plurality of word lines 1520, extending along a horizontal direction on a substrate 1510 and stacked in sequence; a plurality of insulating layers 1530, alternately stacked between the plurality of word lines 1520; and a plurality of strings 1540, extending through the plurality of insulating layers 1530 and the plurality of word lines 1520 to extend in a direction (e.g., the Z direction) on the substrate 1510

[0139] In this case, in the semiconductor structure, each of the plurality of strings 1540 may include: a channel layer 1541, extending in a direction (e.g., the Z direction); and a charge storage layer 1542, extending in a direction (e.g., the Z direction) so as to surround the channel layer 1541, and holes 1543 may be formed in the channel layer 1541 extending in a direction (e.g., the Z direction)

[0140] Moreover, in the semiconductor structure, a substrate 1515 for a back gate 1560 may be included below the substrate 1510 in which the plurality of strings 1540 are formed. Thus, the holes 1543 of the channel layer 1541 can extend to the substrate 1515 for the back gate 1560 in a state of penetrating the substrate 1510 in which the plurality of strings 1540 are formed

[0141] Next, as Figure 15b shown, in step S1420, the manufacturing system may cause an insulating film 1550 having internal holes 1551 to extend in a direction within the holes 1543

[0142] Next, in step S1430, the manufacturing system may use a conductive material or polysilicon doped with a conductive material to form a back gate 1560 extending in a direction within the internal holes 1551 of the insulating film 1550. Among them, the back gate 1560 may be a structural element required to apply a pass voltage for forming a channel or reserving a channel layer 1541 in the channel layer 1541

[0143] As Figure 15cAs shown, in step S1430, the back gate 1560 extends inside the channel layer 1541 in a state where at least a part of it is surrounded by the channel layer 1541 to the region of the multiple word lines 1520 that reach the lower end of the string selection line, but is not limited or restricted thereto. As Figure 15d shown, it can extend inside the channel layer 1541 to the region of the string selection line.

[0144] Although not shown in Figure 14 as a separate step, the manufacturing system can form a drain region on top of the multiple strings 1540 after step S1430.

[0145] In this way, the manufacturing method of the three-dimensional flash memory of one embodiment is by using a semiconductor structure in which holes 1543 extend in the channel layer 1541. As Figures 16a to 16b shown, the semiconductor structure used can be manufactured in advance. For example, the manufacturing system can prepare the semiconductor structure in step S1410 by sequentially stacking the prepared lower semiconductor structure and upper semiconductor structure as Figure 16b shown. Figure 16a shown.

[0146] In the above description, a channel layer with holes inside is used in step S1420, and an insulating film with holes inside is used in step S1430. However, the manufacturing method of the three-dimensional flash memory can prepare a channel layer without holes inside in step S1410 and form an insulating film without holes inside in step S1420, so that the hole formation step of the channel layer and the hole formation step of the insulating film can be performed as additional separate processes. In this case, the manufacturing method of the three-dimensional flash memory can include: a first step of preparing a semiconductor structure, the semiconductor structure including multiple word lines, multiple insulating layers, and multiple strings, the multiple word lines extending horizontally on a substrate and being sequentially stacked, the multiple insulating layers being alternately stacked between the multiple word lines, the multiple strings passing through the multiple insulating layers and the multiple word lines to extend on the substrate in one direction (for example, the Z direction), the multiple strings respectively including a channel layer and a charge storage layer, the channel layer extending in one direction, the charge storage layer extending in one direction (for example, the Z direction) in a manner surrounding the channel layer, and no holes being formed in the channel layer; a second step of causing a first hole to extend in the channel layer in one direction; a third step of causing an insulating film to extend in the first hole in one direction; a fourth step of causing a second hole to extend in the insulating film in one direction; and a fifth step of using a conductive material to extend and form a back gate in the second hole in one direction.

[0147] Figure 17 To show the flowchart of the manufacturing method of the three-dimensional flash memory of another embodiment, Figures 18a to 18kFor explaining an example related to the manufacturing method of the three-dimensional flash memory shown in Figure 17 a Y-Z cross-sectional view.

[0148] Referring to Figure 17 , in step S1710, the manufacturing system may prepare a semiconductor structure.

[0149] For example, as Figure 18a shown, the manufacturing system may prepare a semiconductor structure including: a plurality of word lines 1820, which are formed to extend in a horizontal direction on a substrate 1810 and are stacked in sequence; a plurality of insulating layers 1830, which are alternately stacked between the plurality of word lines 1820; and a plurality of strings 1840, which penetrate through the plurality of insulating layers 1830 and the plurality of word lines 1820 to extend in a direction (e.g., the Z direction) on the substrate 1810.

[0150] In this case, in the semiconductor structure, each of the plurality of strings 1840 may include: a channel layer 1841, which extends in a direction (e.g., the Z direction); and a charge storage layer 1842, which extends in a direction (e.g., the Z direction) so as to surround the channel layer 1841, and holes 1843 may be formed to extend in a direction (e.g., the Z direction) in the channel layer 1841.

[0151] In particular, a first insulating film 1844 may be formed in a region 1843-1 of the inner wall of the hole 1843 corresponding to the ground selection line. Furthermore, as Figure 18b shown, the cross-section of the region of the channel layer 1841 corresponding to the ground selection line may be larger than the cross-section of the remaining region. The following description of the manufacturing method of the three-dimensional flash memory will be made by manufacturing a three-dimensional flash memory in which the cross-section of the region of the channel layer 1841 corresponding to the ground selection line is larger than the cross-section of the remaining region in terms of structure.

[0152] The semiconductor structure as described above may be prepared through the process shown in Figures 18c to 18i .

[0153] Moreover, the semiconductor structure may further include a substrate 1815 for a back gate 1860 located below the substrate 1810 where the plurality of strings 1840 are formed to extend. Thus, the holes 1843 of the channel layer 1841 can extend to the substrate 1815 for the back gate 1860 in a state of penetrating through the substrate 1810 where the plurality of strings 1840 are formed to extend.

[0154] Next, as Figure 18j shown, in step S1720, the manufacturing system may cause a second insulating film 1850 having an internal hole 1851 to extend in the hole 1843 in a direction.

[0155] After that, asFigure 18k As shown, in step S1730, the manufacturing system may use a conductive material or polysilicon doped with a conductive material to form a back gate 1860 extending along a direction in the internal holes 1851 of the second insulating film 1850. Among them, the back gate 1860 may be a structural element required to apply a pass voltage for forming a channel in the channel layer 1841 or reserving the channel layer 1841.

[0156] In the above description, in step S1730, the back gate 1860 is formed to extend inside the channel layer 1841 in a state where at least a part thereof is surrounded by the channel layer 1841 to the region of the plurality of word lines 1820 at the lower end of the string selection line, but it is not limited or restricted thereto, and it can also be formed to extend inside the channel layer 1841 to the region of the string selection line in the above-described manner.

[0157] And, a drain region may be formed on the upper part of the plurality of strings 1840 in step S1730.

[0158] In this way, the manufacturing method of the three-dimensional flash memory of another embodiment is a method for manufacturing a structure in which the thickness of the region corresponding to the ground selection line in the insulating film region is greater than that of other regions. The semiconductor structure used in this method (more precisely, the semiconductor structure in step S1710) can be prepared through Figures 18c to 18j the processes shown.

[0159] Figure 19 FIG. is a flowchart showing a manufacturing method of a three-dimensional flash memory of another embodiment. Figures 20a to 20e It is for explaining Figure 19 a Y-Z cross-sectional view of an example related to the manufacturing method of the three-dimensional flash memory shown.

[0160] Referring to Figure 19 , in step S1910, the manufacturing system may prepare a semiconductor structure.

[0161] For example, as Figure 20a shown, the manufacturing system may prepare the following semiconductor structure, which includes: a plurality of sacrificial layers 2020, which are formed to extend horizontally on the substrate 2010 and are stacked in sequence; a plurality of insulating layers 2030, which are alternately stacked between the plurality of sacrificial layers 2020; and a plurality of strings 2040, which penetrate the plurality of insulating layers 2030 and the plurality of sacrificial layers 2020 to extend on the substrate 2010 along a direction (for example, the Z direction).

[0162] In this case, in the semiconductor structure, multiple strings 2040 may each include: a channel layer 2041 extending along a direction (e.g., the Z direction); and a charge storage layer 2042 extending along a direction (e.g., the Z direction) so as to surround the channel layer 2041, such that holes 2043 are formed in the channel layer 2041 along a direction (e.g., the Z direction).

[0163] Moreover, in the semiconductor structure, a substrate 2015 for a back gate 2060 may also be included below the substrate 2010 in which the multiple strings 2040 are formed. Thus, the holes 2043 inside the channel layer 2041 can extend through the substrate 2010 in which the multiple strings 2040 are formed and extend to the substrate 2015 for the back gate 2060.

[0164] Next, as Figure 20b shown, in step S1920, the manufacturing system can remove the multiple sacrificial layers 2020 through the holes 2043 of the channel layer 2041.

[0165] Next, as Figure 20c shown, in step S1930, the manufacturing system can use a conductive material to form multiple word lines 2022 in the space 2021 where the multiple sacrificial layers 2020 are removed.

[0166] Next, as Figure 20d shown, in step S1940, the manufacturing system can cause the insulating film 2050 having internal holes 2051 to extend along a direction inside the holes 2043.

[0167] After that, as Figure 20e shown, in step S1950, the manufacturing system can use a conductive material to form a back gate 2060 along a direction in the internal holes 2051 of the insulating film 2050.

[0168] Among them, the back gate 2060 can be a structural element required to apply a pass voltage for forming a channel or reserving a channel in the channel layer 2041.

[0169] In the above description, in step S1950, the back gate 2060 is formed to extend inside the channel layer 2041 to the region of the multiple word lines 2022 at the lower end of the string selection line in a state where at least a part is surrounded by the channel layer 2041, but it is not limited or restricted thereto, and it can extend inside the channel layer 2041 to the region of the string selection line in the above-described manner.

[0170] Moreover, a drain region can be formed above the multiple strings 2040 in step S1950.

[0171] Like this, as described in steps S1920 to S1930, a method for manufacturing a three-dimensional flash memory according to another embodiment is characterized in that the space (holes 2043 in the channel layer 2041) for forming the back gate 2060 and the insulating film 2050 is used in the process of forming a plurality of word lines 2022. Other processes may be the same as those of the method for manufacturing a three-dimensional flash memory with reference to Figure 14 described.

[0172] Figure 21 FIG. is a flowchart showing a method for manufacturing a three-dimensional flash memory according to still another embodiment. Figures 22a to 22b For explaining Figure 21 a Y-Z cross-sectional view of an example related to the method for manufacturing a three-dimensional flash memory shown.

[0173] With reference to Figure 21 , in step S2110, the manufacturing system may prepare a lower semiconductor structure.

[0174] For example, as Figure 22a shown, the manufacturing system may prepare a semiconductor structure including: a plurality of lower word lines 2220, which are formed to extend in the horizontal direction on the substrate 2210 and are stacked in sequence; a plurality of lower insulating layers 2230, which are alternately stacked between the plurality of lower word lines 2220; and a plurality of lower strings 2240, which penetrate the plurality of lower insulating layers 2230 and the plurality of lower word lines 2220 to extend in one direction (e.g., the Z direction) on the substrate 2210.

[0175] In this case, in the semiconductor structure, each of the plurality of lower strings 2240 may include: a lower channel layer 2241, which is formed to extend in one direction (e.g., the Z direction); and a lower charge storage layer 2242, which is formed to extend in one direction (e.g., the Z direction) so as to surround the lower channel layer 2241. In particular, the lower channel layer 2241 may include: a lower back gate 2243, which is formed to extend in one direction (e.g., the Z direction) in a state where at least a part of it is surrounded by the lower channel layer 2241; and a lower insulating film 2244, which is formed to extend in one direction (e.g., the Z direction) between the lower back gate 2243 and the lower channel layer 2241.

[0176] Moreover, the lower semiconductor structure may further include a substrate 2215 for the lower back gate 2243 located below the substrate 2210 where the plurality of lower strings 2240 are formed in an extending manner. Thus, the lower back gate 2243 and the lower insulating film 2244 of the lower channel layer 2241 can be formed to extend to the substrate 2215 for the lower back gate 2243 in a state of the substrate 2210 where the plurality of strings 2240 are formed in an extending manner.

[0177] Next, in step S2120, the manufacturing system can prepare the upper semiconductor structure.

[0178] For example, as Figure 22a shown, the manufacturing system can prepare a semiconductor structure including: a plurality of upper word lines 2250, extending along the horizontal direction and stacked in sequence; a plurality of upper insulating layers 2260, alternately stacked between the plurality of upper word lines 2250; and a plurality of upper strings 2270, extending along one direction (e.g., the Z direction) through the plurality of upper insulating layers 2260 and the plurality of upper word lines 2250.

[0179] In this case, in the semiconductor structure, the plurality of upper strings 2270 may each include: an upper channel layer 2271, extending along one direction (e.g., the Z direction); and an upper charge storage layer 2272, extending along one direction (e.g., the Z direction) so as to surround the upper channel layer 2271. In particular, the upper channel layer 2271 may include: an upper back gate 2273, extending along one direction (e.g., the Z direction) in a state where at least a part is surrounded by the upper channel layer 2271; and an upper insulating film 2274, extending along one direction (e.g., the Z direction) between the upper back gate 2273 and the upper channel layer 2271.

[0180] After that, as Figure 22b shown, in step S2130, the manufacturing system can stack the upper semiconductor structure on the upper part of the lower semiconductor structure in such a way that the cross-section of the lower back gate 2243 and the cross-section of the upper back gate 2273 are aligned.

[0181] In this way, a manufacturing method of a three-dimensional flash memory according to another embodiment is a method using a plurality of semiconductor structures (lower semiconductor structure and upper semiconductor structure) in which both the lower back gate 2243 and the upper back gate 2273 are already formed.

[0182] Figures 23a to 23g It is an X-Y top view for illustrating various structures of a back gate according to an embodiment.

[0183] Hereinafter, for the sake of convenience of explanation, only the structural elements of the back gate 2310, the insulating film 2320, and the channel layer 2330 except for the charge storage layer are shown in the drawings.

[0184] Referring to Figures 23a to 23g , it is characterized in that only a part of the back gate 2310 and the insulating film 2320 is surrounded by the channel layer 2330. This is to solve the disadvantage that the formation process becomes complicated when the back gate 2310 and the insulating film 2320 are surrounded by the channel layer 2330 without gaps, and an additional effect of improving the integration degree can also be achieved.

[0185] The channel layer 2330 only surrounds a portion of the back gate 2310 and the insulating film 2320 , which means that the back gate 2310 and the insulating film 2320 are included in at least a portion of the channel layer 2330 or penetrate the channel layer 2330 .

[0186] In more detail, Figure 23a As shown in 23b, the channel layer 2330 surrounds the back gate 2310 and a portion of the insulating film 2320, and at the same time forms a structure divided by the back gate 2310 and the insulating film 2320, so that the channel layer 2330 can be divided into 4 units and the 4 units can be used separately, which can improve the integration of the storage unit in the three-dimensional flash memory 2300.

[0187] The shape of the back gate 2310 and the insulating film 2320 and the number of the channel layer 2330 divided by the back gate 2310 and the insulating film 2320 are not limited or restricted to Figure 23a as well as Figure 23b The method shown can be adopted as follows Figures 23c to 23g In this case, the channel layer 2330 can also be formed into various shapes, from a circle to a quadrilateral, according to the different structures and shapes of the back gate 2310 and the insulating film 2320.

[0188] That is, the three-dimensional flash memory is characterized in that the back gate 2310 and the insulating film 2320 are included in at least a portion of the channel layer 2330 while forming the channel layer 2330 , the back gate 2310 , and the insulating film 2320 into various shapes.

[0189] Furthermore, the back gate 2310 may be formed in a shape shared by a plurality of strings, instead of being formed separately in each string. Figures 23e to 23g As shown, a structure penetrating the sides of multiple strings can be formed by the back gate 2310 so as to be shared by multiple strings.

[0190] Figure 24 2 is a YZ cross-sectional view for explaining the formation position of wiring required for applying a voltage to the back gate of one embodiment. The three-dimensional flash memory 2400 described below can be formed similar to the reference Figures 3a to 3b The structure is the same as the three-dimensional flash memory 300 described above, but the difference between the three-dimensional flash memory 300 and that of the three-dimensional flash memory 300 is that a wiring 2412 required for applying a voltage to the back gate 2411 is formed on the upper part of the back gate 2411 .

[0191] More specifically, the wiring 2412 for applying a voltage to the back gate 2411 may be formed in a position corresponding to the back gate 2411 in the upper region of the string 2410 including the back gate 2411. Accordingly, the bit lines 2413 of the string 2410 may be formed in a position corresponding to the channel layer 2414 other than the back gate 2411 in the upper region of the string 2410.

[0192] The processes required to form the wiring 2412 in the upper region of the string 2410 in a region corresponding to the back gate 2411 as described above and the processes required to form the bit lines 2413 of the string 241 in the upper region of the string 2410 in a region corresponding to the channel layer 2413 other than the back gate 2411 may be performed after each step included in the manufacturing method described with reference to Figure 14 、 Figures 15a to 15d the preparation method described, the manufacturing method described with reference to Figures 16a to 16b the manufacturing method described, the manufacturing method described with reference to Figure 17 、 Figures 18a to 18k the manufacturing method described, the manufacturing method described with reference to Figure 19 、 Figures 20a to 20e the manufacturing method described, the manufacturing method described with reference to Figure 21 、 Figures 22a to 22b the manufacturing method described is appended and executed.

[0193] For example, after performing the step S1430 of forming the extended back gate described with reference to Figure 14 、 Figures 15a to 15d the step of forming the wiring required to apply a voltage to the back gate (the step of connecting the wiring and the back gate) in the region corresponding to the back gate in the upper region of each of the plurality of strings and the step of forming the bit lines of each of the plurality of strings in the region corresponding to the channel layer in the upper region of each of the plurality of strings (the step of connecting the channel layer and the bit lines) may be appended and executed, thereby completing the manufacturing of the wiring and the bit lines required to apply a voltage to the back gate.

[0194] As described above, although a plurality of embodiments have been described with reference to limited embodiments and drawings, those of ordinary skill in the technical field to which the present invention pertains can make various modifications and variations based on the above description. For example, even if the described techniques are executed in an order different from the order in the described method and / or the plurality of structural elements of the described system, structure, device, circuit, etc. are combined or assembled in a form different from the described method, or are replaced or substituted by other structural elements or equivalent technical solutions, appropriate effects can still be achieved.

[0195] Therefore, a plurality of other examples, a plurality of other embodiments, and embodiments equivalent to the scope of the invention claimed also fall within the scope of the invention claimed in the present invention.

Claims

1. A three-dimensional flash memory, characterized in that, Comprising: A plurality of word lines, which are formed by extending along the horizontal direction on a substrate and are stacked in sequence; And A plurality of strings, which are formed by penetrating the plurality of word lines and extending along a direction on the substrate. The plurality of strings respectively include a channel layer and a charge storage layer. The channel layer extends along the direction, and the charge storage layer extends along the direction in a manner of surrounding the channel layer. The channel layer and the charge storage layer form a plurality of memory cells corresponding to the plurality of word lines, The channel layer includes: A back gate, which extends along the direction in a state where at least a part thereof is surrounded by the channel layer; and An insulating film, which extends along the direction between the back gate and the channel layer; Wherein, when a program operation related to a target memory cell is performed, a pass voltage for forming a channel or reserving the channel layer is applied to the back gate.

2. The three-dimensional flash memory according to claim 1, wherein In the channel layer included in the selected string corresponding to the target memory cell among the plurality of strings, a ground voltage is applied to the bit line of the selected string, a program voltage is applied to the word line corresponding to the target memory cell among the plurality of word lines, the pass voltage is applied to the back gate, and at the same time, the word lines corresponding to the remaining memory cells other than the target memory cell among the plurality of word lines are floated, so as to form a channel for performing the program operation related to the target memory cell.

3. The 3D flash memory according to claim 1, characterized in that, In the channel layer included in the non-selected string not corresponding to the target memory cell among the plurality of strings, a power supply voltage is applied to the bit line of the non-selected string, a power supply voltage is applied to the string selection line of the non-selected string to float the non-selected string itself, and at the same time, the pass voltage is applied to the back gate to reserve, so as to prevent the memory cells included in the non-selected string from being programmed due to the program voltage related to the target memory cell.

4. The three-dimensional flash memory according to claim 1, wherein A structure for preventing leakage current from being generated in the ground selection line is formed in the region of the insulating film corresponding to the ground selection line arranged at the lower end of the plurality of word lines or in the region of the channel layer corresponding to the ground selection line.

5. The three-dimensional flash memory according to claim 1, wherein The back gate extends in a manner of passing through the internal region of the channel layer corresponding to the plurality of word lines.

6. The three-dimensional flash memory according to claim 5, wherein The back gate extends to a substrate for the back gate located below the substrate on which the plurality of strings are formed in a state of penetrating the substrate on which the plurality of strings are formed, The substrate for the back gate is used for dissipating heat from the plurality of strings.

7. The three-dimensional flash memory according to claim 5, wherein The back gate extends to a back gate plate arranged along the horizontal direction below the substrate on which the plurality of strings are formed in a state of penetrating the substrate on which the plurality of strings are formed, The back gate plate functions to prevent the substrate from warping by relieving the film stress of the plurality of word lines between the plurality of word lines and the substrate.

8. The three-dimensional flash memory according to claim 1, wherein When performing a program operation related to an object storage cell, a program strengthening voltage for forming an inversion in the channel layer during the program operation and improving the program speed of the object storage cell is applied to the back gate.

9. The three-dimensional flash memory according to claim 1, wherein When performing an erase operation, a voltage for performing an erase operation related to the storage cells included in the plurality of strings in two steps is applied to the back gate.

10. A three-dimensional flash memory, characterized in that, Comprising: A plurality of word lines extending in a horizontal direction on a substrate and stacked in sequence; And A plurality of strings extending in one direction on the substrate through the plurality of word lines. Each of the plurality of strings includes a channel layer and a charge storage layer. The channel layer extends in the one direction, and the charge storage layer extends in the one direction so as to surround the channel layer. The channel layer and the charge storage layer form a plurality of storage cells corresponding to the plurality of word lines. The channel layer includes: A back gate extending in the one direction with at least a part thereof surrounded by the channel layer; and An insulating film extending in the one direction between the back gate and the channel layer; Wherein, when performing a read operation related to the plurality of storage cells, a program enhancement voltage for increasing the threshold voltage of the plurality of storage cells is applied to the back gate to improve the program speed related to the plurality of storage cells.

11. A three-dimensional flash memory, characterized in that, Comprising: A plurality of word lines extending in a horizontal direction on a substrate and stacked in sequence; And A plurality of strings extending in one direction on the substrate through the plurality of word lines. Each of the plurality of strings includes a channel layer and a charge storage layer. The channel layer extends in the one direction, and the charge storage layer extends in the one direction so as to surround the channel layer. The channel layer and the charge storage layer form a plurality of storage cells corresponding to the plurality of word lines. The channel layer includes: A back gate extending in the one direction with at least a part thereof surrounded by the channel layer; and An insulating film extending in the one direction between the back gate and the channel layer; Wherein, when performing an erase operation, an erase voltage related to the storage cells included in the plurality of strings is applied to the back gate.

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