Multiplication-accumulation operation device and multiplication-accumulation operation method

Abstract

The present disclosure provides a multiplication-accumulation operation device and a multiplication-accumulation operation method. The device includes a multiplier, an adder and a first register group connected in sequence, the first register group includes multiple first registers; it also includes a second register group, including at least one second register, which is used to extend the multiplication-accumulation operation result by at least one clock cycle in timing; multiple first registers are used to receive the multiplication-accumulation operation results in sequence according to the interval of the extended clock cycle. By setting the second register group, the circuit delay of multiple first registers can be balanced. It can also make the combinational logic depth before and after the second register group is inserted more balanced, effectively reduce the depth of the original combinational logic, so that the circuit can work at a higher frequency under the same voltage, and improve performance. It can also reduce the circuit working low voltage to effectively reduce the dynamic power consumption of the circuit without changing the performance.

Description

Technical Field

[0001] The present invention belongs to the technical field of multiplication-accumulation operation, and in particular relates to a multiplication-accumulation operation device and a multiplication-accumulation operation method. Background Art

[0002] Multiplication and accumulation are common operations in matrix operations. The performance of multiplication and accumulation has a great impact on the performance of matrix operations. How to improve the performance of multiplication and accumulation operations while reducing their power consumption is an important research direction in the implementation of matrix operations.

[0003] Traditionally, such as Figure 1 As shown, in the process of matrix multiplication and accumulation, the multiplier multiplies the input data, and the output result is sent to the adder. After the adder completes the addition, it is sent to the timing device register. The output of the register is fed back to another input of the adder, thereby realizing the accumulation of the multiplication results. One multiplication and addition calculation is completed in each clock cycle.

[0004] However, multiplication, especially floating-point multiplication, is a relatively complex operation, so the input data needs to pass through many levels of logic to reach the register input through the multiplier and adder, resulting in a relatively large circuit delay, which affects the operating frequency of the circuit. In addition, due to the large logic depth, the circuit glitch transmission effect is more obvious, and the glitch propagation increases the dynamic power consumption of the circuit. Summary of the invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art and to provide a multiplication-accumulation-addition operation device and a multiplication-accumulation-addition operation method.

[0006] In one aspect of the present disclosure, there is provided a multiplication-accumulation operation device, the device comprising a multiplier, an adder and a first register group connected in sequence;

[0007] The first register group includes a plurality of first registers;

[0008] The device further comprises a second register group, the second register group comprises at least one second register, and the at least one second register is used to extend the multiplication and accumulation operation result by at least one clock cycle in timing;

[0009] The plurality of first registers are used to sequentially receive multiplication-accumulation operation results according to the extended clock cycle intervals, so that the circuit delays of the plurality of first registers are balanced.

[0010] In some optional implementations, the second register group includes a plurality of second registers; wherein,

[0011] At least one of the plurality of second registers is disposed in the multiplier; and

[0012] The remaining second registers of the plurality of second registers are arranged in the adder.

[0013] In some optional implementations, the at least one second register is arranged in the adder.

[0014] In some optional implementations, the number of the first registers is one more than the number of the second registers provided in the adder.

[0015] In some optional implementation modes, a second register is set in the adder;

[0016] The number of the plurality of first registers is two, namely an odd register and an even register; the odd register receives a multiplication-accumulation operation result of an odd clock cycle; and the even register receives a multiplication-accumulation operation result of an even clock cycle.

[0017] In some optional implementations, the device further comprises a logic controller, the input end of the logic controller is respectively connected to the output ends of the plurality of first registers, and the output end of the logic controller is connected to the adder;

[0018] The logic controller is used to sequentially send the multiplication and accumulation operation results of the multiple first registers to the adder.

[0019] Another aspect of the present disclosure provides a multiplication-accumulation-addition method, comprising:

[0020] Extend the result of the multiplication and accumulation operation by at least one clock cycle in timing;

[0021] The plurality of first registers receive the multiplication-accumulation operation results in sequence according to the extended clock cycle interval, so that the circuit delays of the plurality of first registers are balanced.

[0022] In some optional implementations, the number of the plurality of first registers is two, namely an odd register and an even register, and the plurality of first registers sequentially receive multiplication-accumulation operation results according to the extended clock cycle interval, including:

[0023] The odd register receives the multiplication and accumulation operation result of the odd clock cycle;

[0024] The even register receives the multiplication and accumulation operation result of the even clock cycle.

[0025] Another aspect of the present disclosure provides a computing core including at least one of the above-mentioned multiplication and accumulation devices.

[0026] Another aspect of the present disclosure provides a chip including at least one of the above-mentioned computing cores.

[0027] Another aspect of the present disclosure provides an electronic device, including:

[0028] one or more processors;

[0029] A storage unit is used to store one or more programs, and when the one or more programs are executed by the one or more processors, the one or more processors can implement the method described above.

[0030] Another aspect of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program can implement the method described above when executed by a processor.

[0031] Another aspect of the present disclosure provides a computer program, which can implement the method described above when executed by a processor.

[0032] The multiplication-accumulation operation device and multiplication-accumulation operation method disclosed in the present invention can make the circuit delay of the adder result output to each first register in the first register group balanced by setting the second register group. In addition, the depth of the combinational logic before and after the insertion of the second register group is relatively balanced, thereby effectively reducing the depth of the original combinational logic, so that the circuit can operate at a higher frequency under the same voltage, thereby improving performance. At the same time, by reducing the circuit working low voltage, it can effectively reduce the dynamic power consumption of the circuit under the premise of unchanged performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of the structure of a traditional multiplication and accumulation operation device;

[0034] Figure 2 A schematic block diagram of the composition of an electronic device according to an embodiment of the present disclosure;

[0035] Figure 3 A schematic diagram of the structure of a multiplication-accumulation operation device according to another embodiment of the present disclosure;

[0036] Figure 4 It is the timing diagram of the traditional multiplication and accumulation operation;

[0037] Figure 5 is a timing diagram of multiplication and accumulation operations of another embodiment of the present disclosure;

[0038] Figure 6 The figure is a flowchart of a multiplication-accumulation method according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0040] First, refer to Figure 2 An example electronic device for implementing the multiplication-accumulation operation device and the multiplication-accumulation operation method of the embodiments of the present disclosure is described.

[0041] like Figure 2 As shown, the electronic device 200 includes one or more processors 210, one or more storage devices 220, one or more input devices 230, one or more output devices 240, etc. These components are interconnected through a bus system 250 and / or other forms of connection mechanisms. It should be noted that Figure 2 The components and structures of the electronic device shown are merely exemplary and non-limiting. The electronic device may also have other components and structures as required.

[0042] The processor 210 may be a central processing unit (CPU), or may be composed of multiple processing cores, or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 200 to perform desired functions.

[0043] The storage device 220 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may run the program instructions to implement the client functions (implemented by the processor) and / or other desired functions in the embodiments of the present disclosure described below. Various applications and various data may also be stored in the computer-readable storage medium, such as various data used and / or generated by the application, etc.

[0044] The input device 230 may be a device used by a user to input instructions, and may include one or more of a keyboard, a mouse, a microphone, a touch screen, and the like.

[0045] The output device 240 may output various information (eg, images or sounds) to the outside (eg, a user), and may include one or more of a display, a speaker, and the like.

[0046] Next, we will refer to Figure 3 A multiplication-accumulation-addition operation device according to an embodiment of the present disclosure is described.

[0047] like Figure 3 As shown, a multiplication-accumulation operation device 100 includes a multiplier 110, an adder 120, and a first register group 130 connected in sequence, wherein the first register group 130 includes a plurality of first registers. The device 100 also includes a second register group 140, wherein the second register group 140 includes at least one second register. The at least one second register is used to extend the multiplication-accumulation operation result by at least one clock cycle in timing. The plurality of first registers are used to sequentially receive the multiplication-accumulation operation result according to the interval of the extended clock cycle, so that the circuit delay of the plurality of first registers is balanced.

[0048] Specifically, if Figure 3 As shown, the input end of the multiplier 110 receives input data to be executed for the multiplication-accumulation operation, the output end of the multiplier 110 is connected to the first input end of the adder 120, and the output end of the adder 120 is connected to the input end of the first register group 130. The first output end of the first register group 130 is connected to the second input end of the adder 120, and the second output end of the first register group 130 is used to output the final result of the multiplication-accumulation operation.

[0049] Continue to refer Figure 3 When the multiplication-accumulation-addition operation device 100 according to the embodiment of the present disclosure is used to perform a multiplication-accumulation-addition operation, the second register group 140 exists, so the behaviors of the multiplier 110 and the adder 120 can be changed. Specifically, since there is at least one second register in the second register group 140, the timing of obtaining the calculation result from the adder is extended by at least one clock cycle, and the specific number of extended clock cycles depends on the number of second registers in the second register group 140. Exemplarily, if there are two second registers in the second register group 140, the output result of the adder 120 is extended by two clock cycles.

[0050] like Figure 3 As shown, a second register Re_2 is configured in the adder 120. Since calculations are performed in each clock cycle, two first registers need to be configured in the first register group 130 to store the calculation results of the adder in adjacent clock cycles. The specific storage process is as follows: the calculation results of the odd clock cycles can be saved to one of the first registers, and the calculation results of the even clock cycles can be saved to the other first register. Finally, the results of the two first registers are added to obtain the final multiplication and accumulation result.

[0051] In addition, if there are three second registers in the second register group 140, assuming that one second register is set in the multiplier and two second registers are set in the adder, for the adder, since calculation is performed in each clock cycle, three first registers need to be configured in the first register group 130. Due to the existence of three second registers, the output result of the entire adder will be extended by three clock cycles, and the three first registers will respectively save data in three adjacent clock cycles. The specific saving process is as follows: one of the first registers receives the operation results of the 0th, 3rd, 6th... clock cycles, another first register receives the operation results of the 1st, 4th, 7th... clock cycles, and the last first register receives the operation results of the 2nd, 5th, 8th... clock cycles, and the results of the last three first registers are added to obtain the final multiplication and accumulation operation result.

[0052] The multiplication-accumulation operation device of the disclosed embodiment can make the circuit delay of the adder result output to each first register in the first register group balanced by setting the second register group. In addition, the depth of the combinational logic before and after the insertion of the second register group is relatively balanced, thereby effectively reducing the depth of the original combinational logic, so that the circuit can operate at a higher frequency under the same voltage, thereby improving performance. At the same time, by reducing the circuit working low voltage, it can effectively reduce the dynamic power consumption of the circuit without changing the performance.

[0053] Specifically, Figure 3 As shown, the second register group 140 includes two second registers, namely the second register Re_1 and the second register Re_2, and the first register group 130 includes two first registers, namely the odd register 131 and the even register 132. The second register Re_1 is arranged in the multiplier 110, and the multiplier 110 is divided into the front part 111 of the multiplier and the rear part 112 of the multiplier. The second register Re_2 is arranged in the adder 120, and the adder 120 is divided into the front part 121 of the adder and the rear part 122 of the adder, and the rear part 122 of the adder is respectively connected to the odd register 131 and the even register 132. In this way, since the multiplier 110 is inserted with a second register Re_1, and the adder 120 is inserted with a second register Re_2, the data passing through the register will generate a time delay of one clock cycle. Therefore, for the multiplication and accumulation calculation device with the second register inserted, the calculation result output from the adder 120 is extended by two clock cycles in timing.

[0054] Since the adder performs calculations in each clock cycle, in order to ensure that the adder performs normal calculations and accumulation in each clock cycle, the data output from the adder in the odd clock cycle is sent to the odd register 131, and the data output from the adder in the even clock cycle is sent to the even register 132, so that the circuit delays of the odd register 131 and the even register 132 can be balanced.

[0055] It should be noted that the number and configuration positions of the second registers included in the second register group 140 are not limited to the following: Figure 3 The configuration results shown, for example, the second registers in the second register group 140 can be configured only in the adder, or at least one second register in the second register group 140 is configured in the multiplier, and the remaining second registers are configured in the adder, etc., can be determined according to actual needs, and the embodiments of the present disclosure are not limited to this.

[0056] It should be understood that the number of first registers included in the first register group 130 is not limited to Figure 3 As shown in the two, as the number of second registers included in the second register group changes, the number of first registers included in the first register group also changes. For example, when one second register is set in the adder, the multiplication and accumulation device needs to divide the original clock cycle into two sub-clock cycles for normal operation, so two first registers need to be configured behind the adder; when two second registers are set in the adder, the multiplication and accumulation device needs to divide the original clock cycle into three sub-clock cycles for normal operation, so three first registers need to be configured behind the adder, that is, the number of first registers is 1 more than the number of second registers set in the adder.

[0057] For example, Figure 3 As shown, the multiplication-accumulation operation device 100 may also include a logic controller 150, wherein the input end of the logic controller 150 is respectively connected to the output end of the odd register 131 and the even register 132, and the output end of the logic controller 150 is connected to the adder front part 121 of the adder 120, and the logic controller 150 is used to sequentially send the multiplication-accumulation operation results of the odd register 131 and the even register 132 to the adder.

[0058] The following is a specific example to describe the operation process of the multiplication and accumulation operation device of the embodiment of the present disclosure:

[0059] Take 16 sets of input data as an example:

[0060] The data timing flow of the original multiplication and accumulation device when performing multiplication and accumulation is as follows: Figure 4 As shown: a, b are the multiplier inputs, m is the multiplier output, and s is the adder output.

[0061] s0=a0*b0

[0062] s1=a0*b0+a1*b1

[0063] s2=a0*b0+a1*b1+a2*b2

[0064] s3=a0*b0+a1*b1+a2*b2+a3*b3 ...

[0066] For the same input data, the data timing process executed by the multiplication and accumulation device of the embodiment of the present disclosure is as follows: Figure 5 As shown in the figure: Since the multiplier is inserted into the register, the multiplier takes one clock cycle longer to get the result. Similarly, the adder takes two clock cycles longer to get the result of the multiplication.

[0067] sa0=a0*b0

[0068] sb1=a1*b1

[0069] sa2=a0*b0+a2*b2

[0070] sb3=a1*b1+a3*b3

[0071] sa4=a0*b0+a2*b2+a4*b4

[0072] sb5=a1*b1+a3*b3+a5*b5

[0073] …

[0074] Finally, sa14 is the result of the multiplication and accumulation of all even inputs, and sb15 is the result of the multiplication and accumulation of all odd inputs. The sum of the two results is the multiplication and accumulation result of all inputs.

[0075] The multiplication-accumulation operation device of the disclosed embodiment inserts a second register in the multiplier and the adder, thereby reducing the logic depth between the registers and improving the operating frequency of the circuit. In addition, due to the reduction in logic depth, the circuit can reduce the operating voltage without changing the performance, thereby saving power consumption. Finally, because the second register is inserted, the propagation of the burr is effectively interrupted, further reducing dynamic power consumption.

[0076] Next, we will refer to Figure 6 A multiplication-accumulation-addition method according to another embodiment of the present disclosure is described. The multiplication-accumulation-addition method can adopt the multiplication-accumulation-addition device 100 described above. The specific structure of the multiplication-accumulation-addition device 100 can refer to the relevant description above and will not be repeated here.

[0077] like Figure 6 As shown, a multiplication-accumulation operation method S100 includes:

[0078] S110, extending the multiplication-accumulation operation result by at least one clock cycle in terms of timing;

[0079] S120 , a plurality of first registers receive the multiplication-accumulation operation results in sequence according to the extended clock cycle interval, so that the circuit delays of the plurality of first registers are balanced.

[0080] The multiplication-accumulation operation method of the disclosed embodiment adopts the multiplication-accumulation operation device described above, and by setting the second register group, the circuit delay of the adder result output to each first register in the first register group can be balanced. In addition, the depth of the combinational logic before and after the insertion of the second register group is relatively balanced, thereby effectively reducing the depth of the original combinational logic, so that the circuit can operate at a higher frequency under the same voltage, improving performance. At the same time, by reducing the circuit working low voltage, it can effectively reduce the dynamic power consumption of the circuit without changing the performance.

[0081] In some optional implementations, the number of the plurality of first registers is two, namely an odd register and an even register, and the plurality of first registers sequentially receive multiplication-accumulation operation results according to the extended clock cycle interval, including:

[0082] The odd register receives the multiplication and accumulation operation result of the odd clock cycle;

[0083] The even register receives the multiplication and accumulation operation result of the even clock cycle.

[0084] Another aspect of the present disclosure provides a computing core including at least one of the above-mentioned multiplication and accumulation devices.

[0085] Another aspect of the present disclosure provides a chip including at least one of the above-mentioned computing cores.

[0086] Another aspect of the present disclosure provides an electronic device, including:

[0087] one or more processors;

[0088] A storage unit is used to store one or more programs, and when the one or more programs are executed by the one or more processors, the one or more processors can implement the method described above.

[0089] Another aspect of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program can implement the method described above when executed by a processor.

[0090] The computer-readable medium may be included in the apparatus, device, or system of the present disclosure, or may exist independently.

[0091] Among them, computer-readable storage media can be any tangible media that contains or stores a program, which can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment. More specific examples include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, an optical fiber, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0092] The computer-readable storage medium may also include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code, specific examples of which include but are not limited to electromagnetic signals, optical signals, or any suitable combination thereof.

[0093] Another aspect of the present disclosure provides a computer program, which can implement the method described above when executed by a processor.

[0094] It is understandable that a computer program can be stored in a computer storage medium, such as the random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), etc. mentioned above.

[0095] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A multiplication-accumulation operation device, It is characterized in that include: A multiplier, an adder and a first register group connected in sequence; The first register group includes a plurality of first registers; The device further comprises a second register group, the second register group comprises at least one second register, and the at least one second register is used to extend the multiplication and accumulation operation result by at least one clock cycle in timing; The plurality of first registers are used to sequentially receive the multiplication-accumulation operation results according to the interval of the extended clock cycle, so that the circuit delays of the plurality of first registers are balanced; The second register group includes a plurality of second registers; wherein, At least one of the plurality of second registers is disposed in the multiplier; and The remaining second registers of the plurality of second registers are arranged in the adder.

2. The device according to claim 1, It is characterized in that The at least one second register is arranged in the adder.

3. The device according to claim 2, It is characterized in that The number of the first registers is greater than the number of the second registers provided in the adder by one.

4. The device according to claim 2, It is characterized in that The adder is provided with a second register; The number of the plurality of first registers is two, namely an odd register and an even register; the odd register receives a multiplication-accumulation operation result in an odd clock cycle; and the even register receives a multiplication-accumulation operation result in an even clock cycle.

5. The device according to any one of claims 1 to 4, It is characterized in that The device further comprises a logic controller, wherein an input end of the logic controller is respectively connected to output ends of the plurality of first registers, and an output end of the logic controller is connected to the adder; The logic controller is used to sequentially send the multiplication and accumulation operation results of the multiple first registers to the adder.

6. A multiplication and accumulation method, It is characterized in that Using the multiplication-accumulation-addition operation device according to any one of claims 1 to 5, the multiplication-accumulation-addition operation method comprises: Extend the result of the multiplication and accumulation operation by at least one clock cycle in timing; The plurality of first registers receive the multiplication-accumulation operation results in sequence according to the extended clock cycle interval, so that the circuit delays of the plurality of first registers are balanced.

7. The method according to claim 6, It is characterized in that The number of the plurality of first registers is two, namely an odd register and an even register, and the plurality of first registers sequentially receive multiplication and accumulation operation results according to the interval of the extended clock cycle, including: The odd register receives the multiplication and accumulation operation result of the odd clock cycle; The even register receives the multiplication and accumulation operation result of the even clock cycle.

8. An electronic device, It is characterized in that include: one or more processors; A storage unit, used to store one or more programs, which, when executed by the one or more processors, enable the one or more processors to implement the method according to claim 6 or 7.

9. A computer-readable storage medium having a computer program stored thereon, It is characterized in that When the computer program is executed by a processor, the method according to claim 6 or 7 can be implemented.

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