Data processing method and apparatus for system on chip performance monitoring

Abstract

The embodiment of the present disclosure provides a data processing method and device for system chip performance monitoring. In the case that a first transaction request is detected, a first label of the first transaction request is acquired. Information of the first transaction request is stored into a first linked list based on the first label of the first transaction request. The first linked list includes at least one node for storing information of a transaction request with the first label.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of chip design, and in particular, to a data processing method and device for system chip performance monitoring. BACKGROUND

[0002] In the process of system chip design, various subsystems are connected through a data path to realize the function of the whole chip system. The data path is realized in a bus mode, and one subsystem can send a transaction request to another subsystem through the data path, and the other subsystem can respond to the transaction request. The information of each transaction request is counted through a system bus performance monitoring module, however, the traditional system bus performance monitoring module randomly stores the information of each transaction request into a storage space as soon as it detects a transaction request, and when monitoring the performance of the chip system, a large number of arithmetic operations and logical operations are required to determine the storage location of the information of each transaction request from the storage space, resulting in a high complexity of the system bus performance monitoring module. SUMMARY

[0003] The present disclosure provides a data processing method and device for system chip performance monitoring.

[0004] According to a first aspect of an embodiment of the present disclosure, a data processing method for system chip performance monitoring is provided, the method comprising: in the case of detecting a first transaction request, acquiring a first tag of the first transaction request; storing the information of the first transaction request into a first linked list based on the first tag of the first transaction request; wherein the first linked list comprises at least one node for storing the information of the transaction request with the first tag.

[0005] In some embodiments, the information of multiple transaction requests with the first tag is stored into each node of the first linked list in turn according to the time when the multiple transaction requests are detected; and / or the information of multiple transaction requests with the first tag is extracted in turn according to the order of the multiple transaction requests in the first linked list.

[0006] In some embodiments, the number of nodes currently included in the first linked list is the number of currently unresponded transaction requests with the first tag; and / or the information of multiple transaction requests with different tags is stored in different linked lists; and / or the nodes of at least two linked lists share multiple storage units; wherein each storage unit is used to store a node of a linked list.

[0007] In some embodiments, the method further comprises: after storing the information of the first transaction request into the first linked list, allocating storage units for the node corresponding to the first transaction request, so that the number of storage units allocated to the first linked list matches the number of nodes currently included in the first linked list.

[0008] In some embodiments, storing the information of the first transaction request into the first linked list based on the first tag of the first transaction request comprises: creating a new node for the first transaction request; and linking the created node to a current tail node of the first linked list.

[0009] In some embodiments, linking the created node to the current tail node of the first linked list comprises: updating fourth indication information corresponding to the current tail node of the first linked list as information of the created node, wherein the fourth indication information is used to indicate a next node of the corresponding node; and / or updating second indication information corresponding to the current tail node of the first linked list as a first indication state, wherein the first indication state of the second indication information is used to indicate that the corresponding node is not a tail node of the linked list; and / or setting second indication information corresponding to the created node as a second indication state, wherein the second indication state of the second indication information is used to indicate that the corresponding node is a tail node of the linked list.

[0010] In some embodiments, the method further comprises: after extracting the information of the transaction request stored in the current head node of the first linked list, performing at least one of the following: updating first indication information corresponding to the current head node, wherein the first indication information is used to indicate whether the corresponding node contains valid information; updating third indication information corresponding to the current head node as a third indication state, wherein the third indication state of the third indication information is used to indicate that the corresponding node is not a head node of the linked list; and updating third indication information corresponding to a next node of the current head node of the first linked list as a fourth indication state, wherein the fourth indication state of the third indication information is used to indicate that the corresponding node is a head node of the linked list.

[0011] In some embodiments, the storage units allocated for the nodes of the first linked list store at least one of the following indication information: first indication information used to indicate whether the storage unit is a valid storage unit, second indication information used to indicate whether the node is a tail node of the first linked list, third indication information used to indicate whether the node is a head node of the first linked list, and fourth indication information used to indicate a storage unit used to store a next node of the node.

[0012] In some embodiments, the method further comprises: querying the first indication information, the second indication information and the tag information stored in each of the plurality of storage units in parallel to determine the current tail node of the first linked list; and / or querying the first indication information, the third indication information and the tag information stored in each of the plurality of storage units in parallel to determine the current head node of the first linked list.

[0013] In some embodiments, each storage unit is configured to store a node of a linked list, and the method further comprises: storing the node corresponding to the first transaction request into an invalid storage unit of the plurality of storage units.

[0014] In some embodiments, the storing of the node corresponding to the first transaction request into an invalid storage unit of the plurality of storage units comprises: querying the first indication information stored in each of the plurality of storage units respectively to determine the invalid storage unit from the plurality of storage units, the first indication information of the storage unit being configured to indicate whether the storage unit is a valid storage unit.

[0015] According to a second aspect of embodiments of the present disclosure, a data processing method for system chip performance monitoring is provided, the method comprising: in the case of detecting a first transaction request, creating a first node for the first transaction request in a first linked list; storing information of the first transaction request into a storage unit allocated for the first node; wherein nodes of at least two linked lists share a plurality of storage units.

[0016] In some embodiments, each storage unit is configured to store a node of a linked list, and the number of storage units allocated for the first linked list matches the number of nodes currently included in the first linked list.

[0017] In some embodiments, the storage unit allocated for the first node stores at least one of the following indication information: first indication information configured to indicate whether the storage unit is a valid storage unit, second indication information configured to indicate whether the first node is a tail node of the first linked list, third indication information configured to indicate whether the first node is a head node of the first linked list, and fourth indication information configured to indicate a storage unit used to store a next node of the first node.

[0018] In some embodiments, the method further comprises: querying the first indication information, the second indication information and the tag information stored in each of the plurality of storage units in parallel to determine the current tail node of the first linked list; and / or querying the first indication information, the third indication information and the tag information stored in each of the plurality of storage units in parallel to determine the current head node of the first linked list.

[0019] In some embodiments, the method further comprises: allocating, based on the first indication information stored in the plurality of storage units, an invalid storage unit in the plurality of storage units to the first node.

[0020] According to a third aspect of the embodiments of the present disclosure, a data processing apparatus for system chip performance monitoring is provided, the apparatus comprising: an acquisition module configured to acquire a first tag of a first transaction request when the first transaction request is detected; and a first storage module configured to store information of the first transaction request into a first linked list based on the first tag of the first transaction request; wherein the first linked list comprises at least one node configured to store information of a transaction request having the first tag.

[0021] In some embodiments, information of a plurality of transaction requests having the first tag is stored into each node of the first linked list in turn according to a time when the plurality of transaction requests are detected; and / or information of the plurality of transaction requests having the first tag is extracted in turn according to an order of the plurality of transaction requests in the first linked list.

[0022] In some embodiments, a number of nodes currently included in the first linked list is a number of transaction requests having the first tag which are currently un-answered; and / or information of a plurality of transaction requests having different tags is stored in different linked lists; and / or nodes of at least two linked lists share a plurality of storage units; wherein each storage unit is configured to store one node of a linked list.

[0023] In some embodiments, the apparatus further comprises: an allocation module configured to allocate, after the information of the first transaction request is stored into the first linked list, a storage unit to a node corresponding to the first transaction request, so that a number of storage units allocated to the first linked list matches a number of nodes currently included in the first linked list.

[0024] In some embodiments, the first storage module comprises: a creation unit configured to create a new node for the first transaction request; and a linking unit configured to link the created node to a tail node of the first linked list currently.

[0025] In some embodiments, the linking unit is configured to: update fourth indication information corresponding to the current tail node of the first chain table to information of the created node, wherein the fourth indication information is used to indicate a next node corresponding to the node; and / or update second indication information corresponding to the current tail node of the first chain table to a first indication state, wherein the first indication state of the second indication information is used to indicate that the corresponding node is not a tail node of the chain table; and / or set second indication information corresponding to the created node to a second indication state, wherein the second indication state of the second indication information is used to indicate that the corresponding node is a tail node of the chain table.

[0026] In some embodiments, the device further comprises at least one of: a first updating module configured to update first indication information corresponding to the current head node, wherein the first indication information is used to indicate whether the corresponding node contains valid information; a second updating module configured to update third indication information corresponding to the current head node to a third indication state, wherein the third indication state of the third indication information is used to indicate that the corresponding node is not a head node of the chain table; and / or a third updating module configured to update third indication information corresponding to a next node of the current head node of the first chain table to a fourth indication state, wherein the fourth indication state of the third indication information is used to indicate that the corresponding node is a head node of the chain table.

[0027] In some embodiments, the storage unit allocated for the node of the first chain table stores at least one of the following indication information: first indication information used to indicate whether the storage unit is a valid storage unit, second indication information used to indicate whether the node is a tail node of the first chain table, third indication information used to indicate whether the node is a head node of the first chain table, and fourth indication information used to indicate a storage unit used to store a next node of the node.

[0028] In some embodiments, the device further comprises: a first querying module configured to query, in parallel, first indication information, second indication information and tag information stored in each of the plurality of storage units to determine the current tail node of the first chain table; and / or a second querying module configured to query, in parallel, first indication information, third indication information and tag information stored in each of the plurality of storage units to determine the current head node of the first chain table.

[0029] In some embodiments, each storage unit is used to store a node of a chain table, and the device further comprises a third storage module configured to store the node corresponding to the first transaction request into an invalid storage unit of the plurality of storage units.

[0030] In some embodiments, the third storage module is configured to: query first indication information stored in each of the plurality of storage units respectively, to determine invalid storage units from the plurality of storage units, the first indication information of the storage unit being configured to indicate whether the storage unit is a valid storage unit.

[0031] According to a fourth aspect of the embodiments of the present disclosure, a data processing apparatus for system chip performance monitoring is provided, the apparatus comprising: a creation module configured to create a first node for a first transaction request in a first linked list upon detecting the first transaction request; and a second storage module configured to store information of the first transaction request into a storage unit allocated for the first node; wherein nodes of at least two linked lists share a plurality of storage units.

[0032] In some embodiments, each storage unit is configured to store one node of a linked list, and the number of storage units allocated for the first linked list matches the number of nodes currently included in the first linked list.

[0033] In some embodiments, the storage unit allocated for the first node stores at least one of the following indication information: first indication information configured to indicate whether the storage unit is a valid storage unit, second indication information configured to indicate whether the first node is a tail node of the first linked list, third indication information configured to indicate whether the first node is a head node of the first linked list, and fourth indication information configured to indicate a storage unit storing a next node of the first node.

[0034] In some embodiments, the apparatus further comprises: a third query module configured to query the first indication information, the second indication information and the tag information stored in each of the plurality of storage units in parallel, to determine a current tail node of the first linked list; and / or a fourth query module configured to query the first indication information, the third indication information and the tag information stored in each of the plurality of storage units in parallel, to determine a current head node of the first linked list.

[0035] In some embodiments, the apparatus further comprises: an allocation module configured to allocate, based on the first indication information stored in the plurality of storage units, an invalid storage unit from the plurality of storage units for the first node.

[0036] According to a fifth aspect of the embodiments of the present disclosure, a computer readable storage medium is provided, having stored thereon a computer program, the program being executed by a processor to implement the method according to any of the embodiments.

[0037] According to a sixth aspect of the embodiments of the present disclosure, a computer device is provided, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the method according to any of the embodiments when executing the program.

[0038] According to the embodiments of the present disclosure, the information of the transaction request is stored into the linked list based on the label of the transaction request, wherein the information of multiple transaction requests with the same label is stored in multiple nodes of the same linked list, so that the information of the transaction request with the same label can be read from the same linked list without complex arithmetic and logical operations, which reduces the complexity of the system bus performance monitoring module and the demand for storage space, and improves the efficiency of the system bus performance monitoring.

[0039] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0040] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the technical solutions of the present disclosure.

[0041] Figure 1 is a flowchart of the data processing method for system chip performance monitoring according to the embodiments of the present disclosure.

[0042] Figure 2 is a schematic diagram of the linked list structure according to the embodiments of the present disclosure.

[0043] Figure 3 is a schematic diagram of the insertion and extraction process of the transaction request according to the embodiments of the present disclosure.

[0044] Figure 4 is a schematic diagram of the tail node polling of the linked list according to the embodiments of the present disclosure.

[0045] Figure 5 is a flowchart of the data processing method for system chip performance monitoring according to another embodiment of the present disclosure.

[0046] Figure 6 is a block diagram of the data processing device for system chip performance monitoring according to the embodiments of the present disclosure.

[0047] Figure 7 is a block diagram of the data processing device for system chip performance monitoring according to another embodiment of the present disclosure.

[0048] Figure 8 is a structural schematic diagram of the computer device according to the embodiments of the present disclosure. DETAILED DESCRIPTION

[0049] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description herein relates to the drawings, in which the same numbers represent the same or similar elements throughout several figures. The implementations described in the following exemplary embodiments are not meant to represent all implementations consistent with the present disclosure. Rather, they are merely examples that are consistent with some aspects of the present disclosure as detailed in the appended claims.

[0050] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. In addition, the term "at least one of' as used herein means any one of or any combination of two or more of the items in the non- limiting list.

[0051] It should be understood that although the terms first, second, third, etc. can be used herein to describe various information, the information should not be limited to these terms. These terms are only used to distinguish one piece of information from another. For example, a first information can also be termed a second information without departing from the scope of the present disclosure, similarly, a second information can also be termed a first information. Depending on the context, the word "if' as used herein can be interpreted as meaning "when" or "in response to determining."

[0052] In order to make the technical solutions in the embodiments of the present disclosure better understood, and to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more apparent and easy to understand, the technical solutions in the embodiments of the present disclosure will be further described in detail below with reference to the drawings.

[0053] In the process of system chip design, a system bus performance monitoring module is often used to monitor the performance of the chip system. Each subsystem in the chip system generates a transaction request when working, and the information of each transaction request is stored in a storage unit every time a transaction request is generated. The system bus performance monitoring module reads the information of the transaction request from the storage unit and performs statistics on the information in a specific manner, thereby monitoring the performance of the chip system. Each transaction request corresponds to a tag, which is used to identify the transaction request. In the case that a transaction request cannot be responded in time, the same transaction request can be generated and sent repeatedly. In the case that the chip system uses different protocols, the maximum number of unresponded transaction requests supported by the chip system is also different. The unresponded transaction requests described above can be transaction requests of the same tag, or can include transaction requests of multiple different tags. The following describes the scheme of the embodiments of the present disclosure taking the maximum number of unresponded transaction requests as 128 for example. Those skilled in the art can understand that the number is only an exemplary description and is not used to limit the present disclosure.

[0054] The conventional system bus performance monitoring module randomly stores the information of each transaction request in the storage space when monitoring the transaction request. When monitoring the performance of the chip system, a large number of arithmetic operations and logical operations are required to determine the storage location of the information of each transaction request in the storage space, resulting in low monitoring efficiency. For example, when the delay between the response time and the generation time of the transaction request of the same tag is counted, the first transaction request of the same tag needs to be determined. The conventional system bus performance monitoring module generally determines the order of generation of the transaction request according to the time stamp of each transaction request of the same tag. Therefore, the type of the transaction request generated first needs to be determined based on the time stamp of all valid transaction requests of the same tag in the storage space. In the worst case, the transaction request with the smallest time stamp needs to be selected from 128 transaction requests, that is, 127 comparison operations need to be performed.

[0055] Based on this, the embodiments of the present disclosure provide a data processing method for system chip performance monitoring, as shown in Figure 1 The method comprises the following steps:

[0056] Step 101: In the case that a first transaction request is detected, a first tag of the first transaction request is acquired.

[0057] Step 102: Based on the first tag of the first transaction request, the information of the first transaction request is stored in a first linked list; wherein the first linked list comprises at least one node, and is used to store the information of the transaction request with the first tag.

[0058] The method of the embodiments of the present disclosure can be applied to a system bus performance monitoring module. The design of the module focuses on the transmission of large amounts of data, and various bus protocols are considered in the design, including all bus protocols containing a tag (TAG ID, abbreviated as xID) type, and the bus protocols support out-of-order requests and responses of different xID transactions and in-order requests and responses of the same xID transaction. Among them, the out-of-order requests and responses of different xID transactions refer to that the response order of different xID transactions can be different from the request order. The in-order requests and responses of the same xID transaction refer to that multiple transaction requests of the same xID are sequentially responded according to the order in which the requests are generated.

[0059] For example, the transaction requests of xID 1 include transaction request 1, transaction request 2 and transaction request 3. In the generation process of the above three transaction requests, transaction requests of xID 2 can also be generated, for example, including transaction request 4 and transaction request 5. The generation process of transaction requests of different xIDs can be independent of each other. Assuming that the generation order of the above transaction requests from early to late is: transaction request 1, transaction request 4, transaction request 2, transaction request 3 and transaction request 5, the transaction requests of the same xID need to be sequentially responded in order, for example, the response time of transaction request 1 should be earlier than that of transaction request 2, the response time of transaction request 2 should be earlier than that of transaction request 3, and the response time of transaction request 4 should be earlier than that of transaction request 5. The response time of transaction requests of different xIDs can be in any order, for example, the response time of transaction request 4 can be earlier than that of transaction request 1, or later than that of transaction request 2. Therefore, the response order of the above transaction requests can be: transaction request 1, transaction request 2, transaction request 4, transaction request 5 and transaction request 3, or transaction request 4, transaction request 5, transaction request 1, transaction request 2 and transaction request 3, and the like.

[0060] Each received transaction request can store information of the transaction request in a node of a linked list. The linked list is a non-continuous and non-sequential storage structure on a physical storage unit, and the logical order of data elements is realized by the pointer link order in the linked list. Each node in a linked list is used to store information of multiple transaction requests of the same tag. The information can include, but is not limited to, at least one of the type, tag and generation time of the transaction request. By storing the information of each transaction request of the same tag in different nodes of the same linked list, since each node of the linked list is linked to each other through a pointer, when the performance of the system chip is monitored, it is not necessary to compare the tags of each transaction request one by one, but only to find the linked list corresponding to the transaction request and then find the information from each node of the linked list, thereby improving the monitoring efficiency. Further, the information of multiple transaction requests with different tags can be stored in different linked lists.

[0061] In some embodiments, to facilitate the searching of information from the linked list, information of multiple transaction requests of the same label can be stored in the nodes of the linked list in a certain order. The certain order can be the order of the time when the multiple transaction requests are detected. For example, information of the transaction request detected first is stored in the node close to the head of the linked list, and information of the transaction request detected last is stored in the node close to the tail of the linked list. Similarly, to facilitate the extraction of information from the linked list, information of the multiple transaction requests with the first label is extracted in the order of the multiple transaction requests in the first linked list. For example, information of the transaction request is extracted from the head node of the first linked list first, and information of the transaction request is extracted from the next node of the head node second, and so on.

[0062] In the case where only information of transaction requests of one label is stored in each linked list, the depth of each linked list of the embodiments of the present disclosure (i.e., the number of nodes included in the linked list) can be the same or different. In some embodiments, upon detection of a transaction request, information of the transaction request is stored in the linked list, and upon detection of a response to the transaction request, information of the transaction request is extracted from the linked list, and thus the linked list can store information of transaction requests that are currently unresponded.

[0063] In some embodiments, each node in the linked list can be used to store information of one or more transaction requests, and in the case where each node is used to store information of one transaction request, the number of nodes currently included in the first linked list can be equal to the number of transaction requests with the first label that are currently unresponded. For example, there are 4 transaction requests with xID 1 that are currently unresponded, and thus the depth of the linked list corresponding to the transaction requests with xID 1 is 4, i.e., the linked list includes 4 nodes. For another example, there are 5 transaction requests with xID 2 that are currently unresponded, and thus the depth of the linked list corresponding to the transaction requests with xID 2 is 5.

[0064] In a chip system design, a communication bus is usually allowed to support a maximum of 128 un-responded transaction requests, which can be transaction requests of the same xID, transaction requests of 128 different xIDs, or transaction requests of less than 128 xIDs. When a linked list structure is used to store the transaction requests, in the case of 128 transaction requests being transaction requests of the same xID, each linked list is required to support a maximum of 128 nodes; in the case of 128 transaction requests being transaction requests of different xIDs, a maximum of 128 linked lists are required to be supported. If a storage unit with a fixed depth of 128 nodes is designed for each xID transaction request, 128*128 storage units are required to be designed to solve the sequential request and response of the same xID transaction and the out-of-order request and response of different xID transactions. The storage unit can be a flip-flop storage array row. In this case, the number of xIDs contained in the un-responded transaction requests is between 1 and 128, and the depth of each link is between 128 and 1, and 128*128 flip-flop storage array rows are used, and the remaining (128-1)*128 flip-flop storage array rows are empty, but the distribution of the (128-1)*128 flip-flop storage array rows is not determined. For example, the 128 flip-flop storage array rows can store a linked list of 128 transaction requests of the same xID, or a linked list of 128 xID transaction requests.

[0065] In some embodiments, in order to further save storage units, at least two nodes of linked lists can share a plurality of storage units, and each storage unit is used to store a node of a linked list. That is, the plurality of storage units can be allocated to nodes of a linked list with xID 1, or to nodes of a linked list with xID 2, or to nodes in different linked lists respectively. Specifically, after storing the information of the first transaction request in the first linked list, a storage unit can be allocated to the node corresponding to the first transaction request, so that the number of storage units allocated to the first linked list matches the number of nodes currently included in the first linked list. A linked list includes several nodes, and several storage units are allocated to the linked list. The total number of storage units allocated to each linked list is equal to the maximum number of un-responded transaction requests.

[0066] In the embodiments of the present disclosure, in the case that a new node is created in a linked list, a storage unit can be allocated to the new node, and in the case that the information of a transaction request included in a node in a linked list is extracted, the storage unit allocated to the node can be recycled, for example, by setting indication information in the storage unit to indicate that the storage unit is invalid, so that the storage unit can be allocated to other nodes if necessary.

[0067] The present disclosure adopts multiple linked lists, the linked list depth allocated to hardware is not fixed, is dynamically allocated based on an xID transaction request, and the linked list depth supports a range of 1 to 128. Meanwhile, the bus system supports a maximum of 128 unresponded transaction requests, is allocated with a maximum of 128 xID linked lists, and the nodes corresponding to different xID transaction requests share a storage space, the size of the shared storage space is a trigger storage array row of 128, and the sequential request and response of a transaction and the out-of-order request and response of a transaction are completed through a linked list. In this way, sufficient storage units can be allocated for different linked lists, and the idle storage units can be reduced, and the utilization rate of the storage units is improved. This shared storage based multiple linked list structure is referred to as a shared storage based multiple linked list structure.

[0068] In the case where the information of a transaction request is not stored in a linked list structure, such as 128 trigger storage array rows (referred to as array rows) storing the information of all xID transaction requests, when the information of a transaction request is extracted, the valid rows are extracted from the 128 trigger storage array rows, the xIDs corresponding to the transaction requests in each valid row are screened, and finally the array row corresponding to the minimum timestamp value is selected from the screened array rows. In this process, a large number of arithmetic operations are introduced, and 128 cases need to be considered at each step (including extracting valid rows, selecting array rows corresponding to the minimum timestamp value, etc.), the logic design is very complex, and the amount of calculation is very large.

[0069] In some embodiments of the present disclosure, the nodes in the linked list can be dynamically adjusted. In the case where the first transaction request is detected, a new node can be created for the first transaction request, and the created node is linked to the current tail node of the first linked list. That is, a new node is created for each detected transaction request in the corresponding linked list, and the created new node is linked to the tail node of the corresponding linked list to become the new tail node of the linked list. In this way, the transaction requests corresponding to each node in the linked list are arranged in the order of the detected time, and when the information of a transaction request is extracted, the trigger storage array row of the head node of the linked list can be directly extracted as a valid row, without the need for complex arithmetic operations and logical operations, thereby improving the processing efficiency.

[0070] In some embodiments, upon detecting a transaction response, based on a tag contained in the transaction response, a corresponding chain table of a transaction request to which the transaction response is directed is determined, and information of the transaction request is extracted from a head node of the corresponding chain table. For example, the generation time of the transaction request with the tag xIDn can be extracted from the head node of the chain table, and the time interval between the response time of the transaction response with the tag xIDn and the generation time of the transaction request with the tag xIDn is calculated, so as to calculate the delay between the transaction request with the tag xIDn and the transaction response with the tag xIDn. In actual applications, the delay between each transaction request and transaction response can be calculated, or the average delay between each tag transaction request and corresponding tag transaction response generated in a period of time can be calculated. Those skilled in the art can understand that according to the information of the transaction request included in the chain table, other parameters can also be calculated, which will not be described here.

[0071] In some embodiments, the storage unit allocated for the node of the first chain table stores at least one indication information, including first indication information for indicating whether the storage unit is a valid storage unit, second indication information for indicating whether the node is a tail node of the first chain table, third indication information for indicating whether the node is a head node of the first chain table, and fourth indication information for indicating a storage unit for storing a next node of the node.

[0072] The at least one indication information can be carried in the node of the chain table. The chain table structure of some embodiments is as shown in FIG. 2. In order to flexibly use the 128 flip-flop storage array rows, the flip-flop storage array row of the shared storage multi-chain table structure is used to store the information, and the area in the box in the figure is the information space required to be stored by the transaction request, and the rest is the extension field. Figure 2

[0073] ​The information space can include a label xID corresponding to the node and information AXI INFO of a system bus transaction request. The xID can be an identifier of the 16-bit transaction request, and is any xID value supported by the bus. The width of the AXI INFO is determined according to design requirements, and generally includes a time stamp (TIMESLOT) when the transaction request is generated, a type of the bus, a granularity of burst transmission (BURST SIZE), a type of burst transmission (BURST TYPE), a protection type (PROT), a cache type (CACHE), a request address (ADDRESS), and the like. Among them, the granularity of burst transmission is used to determine the size of the transaction request transmitted in one burst transmission process; the type of burst transmission is used to indicate the attribute of the transaction request transmitted in one burst transmission process; the protection type is used to indicate the security mode and level of transaction access in the system chip; the cache type is used to indicate the storage mode of the transaction request, whether to store in the cache first and then store from the cache to the storage unit, or directly store to the storage unit; and the request address is used to indicate the starting storage position of the transaction request of the burst transmission.

[0074] The extension field can include any one of a V field, a T field, an H field, and a pointer (Next Pointer, NPTR) field. Among them, the first indication information is included in the V field of the node, the second indication information is included in the T field of the node, the third indication information is included in the H field of the node, and the fourth indication information is included in the pointer field of the node.

[0075] In some embodiments, the V field can be represented by 1 bit, for example, "0" represents that the storage unit is invalid, and "1" represents that the storage unit is valid. In the case that the information stored in the storage unit is extracted, the storage unit is an invalid storage unit, and in the case that the storage unit is allocated to a node and the information stored in the storage unit is not extracted, the storage unit is a valid storage unit. In some embodiments, the node corresponding to the first transaction request can be stored in at most one invalid storage unit in the plurality of storage units. In some embodiments, the node can be randomly stored in any one of the plurality of invalid storage units; in other embodiments, the node can be stored in the invalid storage unit with the smallest number. The T field can also be represented by 1 bit, for example, "0" represents that it is not a tail node of the list, and "1" represents that it is a tail node of the list. The H field can also be represented by 1 bit, for example, "0" represents that it is not a head node of the list, and "1" represents that it is a head node of the list. The width of the NPTR field is determined by the depth of the storage unit shared by each list. For example, in the case that the total number of available storage space is 128, the length of the fourth indication information can be 7 bits. In the case that the node is a tail node of the list, the content of the NPTR field in the node is not concerned. After a new node is linked to the current tail node of the list, the NPTR field of the current tail node can be updated based on the address of the storage unit storing the new node.

[0076] Through the above extension, a basis is provided for storing transaction requests into a list, and when a new transaction request needs to be stored, the current tail node or head node of the first list can be determined according to the information stored in the storage unit. In the case of determining the tail node, the first indication information, the second indication information and the tag information stored in each of the plurality of storage units can be queried in parallel to determine the current tail node of the first list.

[0077] Optionally, whether each storage unit is a valid storage unit can be determined according to the first indication information stored in the storage unit, then the nodes with the same tag as the first transaction request are screened out from the valid storage units, and finally the tail node is determined from the screened nodes.

[0078] After the tail node is determined, the created node can be linked to the current tail node of the first list in the following way. For example, the fourth indication information corresponding to the current tail node of the first list can be updated to the information of the created node.

[0079] For example, the second indication information corresponding to the current tail node of the first linked list can be updated to the first indication state. Assuming that the first linked list currently includes N nodes, and node N is the current tail node of the first linked list, after the created node is linked to the tail node of the first linked list, node N is no longer the tail node of the first linked list, and therefore, the second indication information corresponding to node N can be updated to the first indication state.

[0080] For another example, the second indication information corresponding to the created node can be set to the second indication state. Assuming that the first linked list currently includes N nodes, and node N is the current tail node of the first linked list, after the created node is linked to the tail node of the first linked list, the created node becomes the tail node of the first linked list, and therefore, the second indication information corresponding to the created node can be updated to the second indication state.

[0081] In the above manner, each transaction request can be stored in each node of the linked list in the detected order, so that when the information of the transaction request is extracted, the information of the transaction request can be extracted from the head node of the linked list by finding the head node of the linked list.

[0082] The specific execution process of determining the tail and linking the node to the tail node is as follows:

[0083] (1) Based on the V field in the trigger storage array row, the position where the first transaction request with the label xIDn needs to be stored is determined by the low (high) bit priority decoding method.

[0084] (2) Based on the parallel polling method, the tail node of the linked list corresponding to xIDn is found.

[0085] (3) The NPTR field of the tail node of the xIDn transaction request is updated to the storage unit storing the node corresponding to the first transaction request, and the V field of the current tail node is set to 0.

[0086] (4) Based on the information of the first transaction request, the content of the corresponding storage unit is updated, the V field of the node corresponding to the first transaction request is set to 1, the T field is set to 1, and the NPTR field is not updated.

[0087] In practical applications, the above step (1) and step (2) can be realized by the following way: the first indication information, the second indication information and the label of each node and the label of the first transaction request are subjected to AND operation to obtain an operation result, the position of "1" in the operation result is determined, and the tail node is determined according to the position of "1". Specifically, the first indication information corresponding to each node can be generated as a one-dimensional array V, the length of the one-dimensional array V is 128, and each element in the array is 1 or 0, which is used to indicate whether the storage unit storing the corresponding node is a valid storage unit or not. Similarly, the second indication information corresponding to each node can be generated as a one-dimensional array T, the length of the one-dimensional array T is 128, and each element in the array is 1 or 0, which is used to indicate whether the corresponding node is a tail node or not. The label carried in each node is subjected to AND operation with the label of the transaction request, the one-dimensional array V and the one-dimensional array T, and the tail node can be determined according to the position of "1" in the operation result of the AND operation. In the case where the chain table corresponding to the transaction request exists, the operation result is a 128-bit one-hot code, the position of "1" in the one-hot code is at most 127 and at least 0; in the case where the chain table corresponding to the transaction request does not exist, the operation result is a value of all 0, and the one-hot code can be represented by a 7-bit pointer. The process of obtaining the 7-bit pointer through arithmetic operation is as follows:

[0088] (1) The operation result of the AND operation is subtracted by 1 to obtain a first operation result. In the first operation result, the values corresponding to the position of "1" in the original one-hot code and the values higher than the position are all 0, and the values lower than the position of "1" in the original one-hot code are all 1.

[0089] (2) The positions of "1" in the original one-hot code are obtained by summing up each bit in the first operation result.

[0090] (3) If the operation result is not a one-hot code but a 0 value, the first operation result is a 128-bit all-1 value, and the sum of 128 "1"s is 128. For a 7-bit pointer, the high bit overflows, and the 7 bits are 0. Since the first operation result of the one-hot code 000...01 minus 1 is 0, the case of high bit overflow will conflict with the first operation result corresponding to the one-hot code 000...01, so when filling the chain table, the original one-hot code corresponding to the all-0 value needs to be compared with the 128-bit 0. If they are different, it is determined that the node indicated by the all-0 value is the node corresponding to the one-hot code 000...01. The number of bits where "1" is located is the position of the storage unit where the tail node is located. For example, "1" is at the 28th bit, which indicates that the 28th storage unit stores the tail node of the first target chain table.

[0091] Similarly, when the transaction information of xIDn needs to be extracted, the first indication information, the third indication information and the label information stored in each of the plurality of storage units can be queried in parallel to determine the current head node of the first linked list. The specific execution process is as follows:

[0092] (1) Based on the parallel polling method, find the storage unit where the head node of the first linked list of the transaction request with the label xIDn is located.

[0093] (2) Extract the information of the transaction request with the label xIDn from the storage unit, and obtain the position of the next node through the NPTR field, and set the V field of the head node of the extracted information to 0.

[0094] (3) Update the H field of the next node to 1, indicating that the next node is the head node of the linked list corresponding to xIDn.

[0095] In practical applications, steps (1) and (2) can be implemented by the following method: performing an AND operation on the first indication information, the third indication information and the label of each node and the label of the first transaction request, obtaining an operation result, determining the position of "1" in the operation result, and determining the head node according to the position of "1". The head node can be determined in the same way as the tail node, which will not be described here.

[0096] According to the head node of the linked list, the earliest timestamp of the transaction request corresponding to xIDn (xID is n transaction label) is determined, avoiding obtaining the earliest timestamp of the transaction request corresponding to xIDn by comparing the value of the real-time counter, and saving a large amount of operation logic.

[0097] The insertion and extraction process of the transaction request is as shown in Figure 3 Based on the design and implementation of the shared storage multi-linked list structure, it mainly consists of a storage unit and two parallel polling modules, including an insertion polling module for inserting the detected transaction request into the linked list, and a deletion polling module for extracting the information of the transaction request from the linked list. Among them, the deletion polling module is used to execute the method for extracting the information of the transaction request from the linked list in any of the above embodiments, and the insertion polling module is used to execute the method for inserting the information of the transaction request into the linked list in any of the above embodiments. The specific insertion and extraction methods are described in the above embodiments, which will not be described here.

[0098] The storage space of the embodiment of the present disclosure can be implemented by using a flip-flop storage array, the depth of the storage space can be 128, and the width is defined according to the bus protocol and statistical requirements. By designing the peripheral circuit of the storage array, the states of part or all of the V domain, the H domain, the xID domain and the T domain of the flip-flop are accessed in a parallel polling manner, so as to determine the current tail node or head node of the first linked list. For the transaction request writing the linked list corresponding to the xID (or creating a new linked list corresponding to the xID), and the transaction response reading the linked list corresponding to the xID, a parallel polling manner is adopted, and the logical design is as shown in Figure 4 The input is a 128-bit V domain one-dimensional array, that is, V[0:127], a 128-bit node xID, that is, xID[0:127], and a 128-bit T domain one-dimensional array or a 128-bit H domain one-dimensional array, that is, T[0:127] or H[0:127]. The judgment process is as follows (i is valued from 0 to 127):

[0099] (1) Determine whether the data in the i-th row of the storage array is valid by V[i].

[0100] (2) Determine whether the data in the i-th row of the storage array belongs to the linked list corresponding to xIDn by comparing whether the transaction request label xIDn is equal to the node xID[i].

[0101] (3) Determine whether the data in the i-th row of the storage array is the tail node of the linked list by T[i], or determine whether the data in the i-th row of the storage array is the head node of the linked list by H[i].

[0102] (4) After the above three steps, a 128-bit one-hot code or all-0 value is obtained, and each bit is respectively recorded as Bit[0], Bit[1], …, Bit

[127] . At the same time, the position of 1, that is, the tail node of the linked list to be inserted or the head node of the linked list to be extracted.

[0103] (5) Based on the 128-bit one-hot code or 0 value, a minus 1 operation is performed, and the obtained 128-bit Bit[0]’, Bit[1]’, …, Bit

[127] ’ is accumulated, that is, a 7-bit head pointer or tail pointer PTR[6:0] of the linked list is obtained, and the value of the pointer ranges from 0 to 127.

[0104] Based on the design and implementation of the method, the delay information of different xIDs can be supported, the statistics of different types of transaction requests can be supported, the storage demand of the hardware design is small, and the operation amount of the calculation delay is also small.

[0105] As shown in Figure 5 The embodiment of the present disclosure also provides a data processing method for system chip performance monitoring, the method comprising:

[0106] Step 501: in the case of detecting a first transaction request, creating a first node for the first transaction request in a first linked list;

[0107] Step 502: storing information of the first transaction request into a storage unit allocated for the first node; wherein nodes of at least two linked lists share a plurality of storage units.

[0108] In some embodiments, each storage unit is used to store a node of a linked list, and the number of storage units allocated for the first linked list matches the number of nodes currently included in the first linked list.

[0109] In some embodiments, the storage unit allocated for the first node stores at least one of the following indication information: first indication information for indicating whether the storage unit is a valid storage unit, second indication information for indicating whether the first node is a tail node of the first linked list, third indication information for indicating whether the first node is a head node of the first linked list, and fourth indication information for indicating a storage unit storing a next node of the first node.

[0110] In some embodiments, the method further comprises: querying the first indication information, the second indication information and the tag information stored in each of the plurality of storage units in parallel to determine the current tail node of the first linked list; and / or querying the first indication information, the third indication information and the tag information stored in each of the plurality of storage units in parallel to determine the current head node of the first linked list.

[0111] In some embodiments, the method further comprises: based on the first indication information stored in the plurality of storage units, allocating an invalid storage unit in the plurality of storage units for the first node.

[0112] In some embodiments, the method further comprises: respectively querying the first indication information stored in the plurality of storage units to determine invalid storage units from the plurality of storage units, the first indication information of the storage unit being used to indicate whether the storage unit is a valid storage unit.

[0113] In some embodiments, each linked list includes at least one node for storing information of a transaction request with one or more tags. For example, linked list 1 is used to store information of a transaction request with a tag of xID1, and linked list 2 is used to store information of transaction requests with tags of xID2 and xID3. For ease of processing, each linked list can also include only information of transaction requests with the same tag, and information of transaction requests with different tags is stored in different linked lists.

[0114] In some embodiments, the information of the plurality of transaction requests with the first label is sequentially stored into the nodes of the first linked list according to the time when the plurality of transaction requests are detected; and / or the information of the plurality of transaction requests with the first label is sequentially extracted according to the order of the plurality of transaction requests in the first linked list.

[0115] In some embodiments, the number of nodes currently included in the first linked list is the number of transaction requests with the first label that are currently unresponded.

[0116] In some embodiments, the creating the first node for the first transaction request in the first linked list comprises: creating a new node for the first transaction request; and linking the created node to a current tail node of the first linked list.

[0117] In some embodiments, the linking the created node to the current tail node of the first linked list comprises: updating fourth indication information corresponding to the current tail node of the first linked list as information of the created node, wherein the fourth indication information is used to indicate the next node of the corresponding node; and / or updating second indication information corresponding to the current tail node of the first linked list as a first indication state, wherein the first indication state of the second indication information is used to represent that the corresponding node is not a tail node of the linked list; and / or setting second indication information corresponding to the created node as a second indication state, wherein the second indication state of the second indication information is used to represent that the corresponding node is a tail node of the linked list.

[0118] In some embodiments, the method further comprises: after extracting the information of the transaction request stored in the current head node of the first linked list, performing at least one of the following: updating first indication information corresponding to the current head node, wherein the first indication information is used to represent whether the corresponding node contains valid information; updating third indication information corresponding to the current head node as a third indication state, wherein the third indication state of the third indication information is used to represent that the corresponding node is not a head node of the linked list; and updating third indication information corresponding to the next node of the current head node of the first linked list as a fourth indication state, wherein the fourth indication state of the third indication information is used to represent that the corresponding node is a head node of the linked list.

[0119] The details of each step in the method embodiments are described in the foregoing method embodiments, which will not be repeated here.

[0120] Those skilled in the art can understand that, in the above method of the specific embodiments, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process, and the specific execution order of each step should be determined by its function and possible internal logic.

[0121] As Figure 6 shown, the present disclosure also provides a data processing apparatus for system chip performance monitoring, the apparatus comprising:

[0122] an obtaining module 601 configured to, in a case where a first transaction request is detected, obtain a first tag of the first transaction request;

[0123] a first storage module 602 configured to, based on the first tag of the first transaction request, store information of the first transaction request into a first linked list; wherein the first linked list comprises at least one node for storing information of transaction requests with the first tag.

[0124] In some embodiments, information of multiple transaction requests with the first tag is sequentially stored into respective nodes of the first linked list according to a time when the multiple transaction requests are detected; and / or information of the multiple transaction requests with the first tag is sequentially extracted according to an order of the multiple transaction requests in the first linked list.

[0125] In some embodiments, a number of nodes currently included in the first linked list is a number of currently un-answered transaction requests with the first tag; and / or information of multiple transaction requests with different tags is stored in different linked lists; and / or nodes of at least two linked lists share a plurality of storage units; wherein each storage unit is used for storing one node of a linked list.

[0126] In some embodiments, the apparatus further comprises an allocating module configured to, after storing the information of the first transaction request into the first linked list, allocate a storage unit for a node corresponding to the first transaction request, so that a number of storage units allocated to the first linked list matches a number of nodes currently included in the first linked list.

[0127] In some embodiments, the first storage module comprises a creating unit configured to create a new node for the first transaction request; and a linking unit configured to link the created node to a current tail node of the first linked list.

[0128] In some embodiments, the linking unit is configured to: update fourth indication information corresponding to the current tail node of the first linked list as information of the created node, wherein the fourth indication information is used for indicating a next node of a corresponding node; and / or update second indication information corresponding to the current tail node of the first linked list as a first indication state, wherein the first indication state of the second indication information is used for representing that the corresponding node is not a tail node of a linked list to which the corresponding node belongs; and / or set second indication information corresponding to the created node as a second indication state, wherein the second indication state of the second indication information is used for representing that the corresponding node is a tail node of a linked list to which the corresponding node belongs.

[0129] In some embodiments, the apparatus further comprises at least one of: a first updating module configured to update first indication information corresponding to the current head node of the first chain table, the first indication information being used to indicate whether the corresponding node contains valid information; a second updating module configured to update third indication information corresponding to the current head node of the first chain table to a third indication state, wherein the third indication state of the third indication information is used to indicate that the corresponding node is not the head node of the corresponding chain table; and a third updating module configured to update third indication information corresponding to the next node of the current head node of the first chain table to a fourth indication state, wherein the fourth indication state of the third indication information is used to indicate that the corresponding node is the head node of the corresponding chain table.

[0130] In some embodiments, the storage unit allocated for the node of the first chain table stores at least one of the following indication information: first indication information used to indicate whether the storage unit is a valid storage unit, second indication information used to indicate whether the node is the tail node of the first chain table, third indication information used to indicate whether the node is the head node of the first chain table, and fourth indication information used to indicate the storage unit storing the next node of the node.

[0131] In some embodiments, the apparatus further comprises: a first querying module configured to query, in parallel, the first indication information, the second indication information and the tag information stored in each of the plurality of storage units to determine the current tail node of the first chain table; and / or a second querying module configured to query, in parallel, the first indication information, the third indication information and the tag information stored in each of the plurality of storage units to determine the current head node of the first chain table.

[0132] In some embodiments, each storage unit is used to store a node of a chain table, and the apparatus further comprises a third storing module configured to store the node corresponding to the first transaction request into an invalid storage unit of the plurality of storage units.

[0133] In some embodiments, the third storing module is configured to query the first indication information stored in each of the plurality of storage units respectively to determine the invalid storage unit from the plurality of storage units, wherein the first indication information of the storage unit is used to indicate whether the storage unit is a valid storage unit.

[0134] As shown in Figure 7 The present disclosure further provides a data processing apparatus for system chip performance monitoring, the apparatus comprising:

[0135] a creating module 701 configured to create a first node for the first transaction request in a first chain table when the first transaction request is detected;

[0136] The second storage module 702 is configured to store information of the first transaction request into a storage unit allocated to the first node; wherein the nodes of the at least two linked lists share a plurality of storage units.

[0137] In some embodiments, each storage unit is configured to store a node of a linked list, and the number of storage units allocated to the first linked list matches the number of nodes currently included in the first linked list.

[0138] In some embodiments, the storage unit allocated to the first node stores at least one of the following indication information: first indication information for indicating whether the storage unit is a valid storage unit, second indication information for indicating whether the first node is a tail node of the first linked list, third indication information for indicating whether the first node is a head node of the first linked list, and fourth indication information for indicating a storage unit storing a next node of the first node.

[0139] In some embodiments, the apparatus further comprises: a third query module configured to query, in parallel, the first indication information, the second indication information and the tag information stored in each of the plurality of storage units to determine the current tail node of the first linked list; and / or a fourth query module configured to query, in parallel, the first indication information, the third indication information and the tag information stored in each of the plurality of storage units to determine the current head node of the first linked list.

[0140] In some embodiments, the apparatus further comprises an allocation module configured to allocate, based on the first indication information stored in the plurality of storage units, an invalid storage unit in the plurality of storage units to the first node.

[0141] In some embodiments, the apparatus provided by the embodiments of the present disclosure has the functions or includes the modules described above, which can be used to execute the methods described in the above method embodiments. For brevity, the specific implementation details are not described here again.

[0142] The embodiments of the present disclosure further provide a computer device, which includes at least a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the method of any of the above embodiments when executing the program.

[0143] Figure 8A more specific computer device hardware structure diagram provided by the embodiments of the present specification is shown, which can include a processor 801, a memory 802, an input / output interface 803, a communication interface 804 and a bus 805. The processor 801, the memory 802, the input / output interface 803 and the communication interface 804 are connected to each other through the bus 805 for internal communication connection.

[0144] The processor 801 can be implemented in the form of a general-purpose CPU (Central Processing Unit), a microprocessor, an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits, etc., for executing related programs to implement the technical solutions provided by the embodiments of the present specification.

[0145] The memory 802 can be implemented in the form of a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, etc. The memory 802 can store an operating system and other application programs, and when the technical solutions provided by the embodiments of the present specification are implemented by software or firmware, the related program codes are stored in the memory 802 and called and executed by the processor 801.

[0146] The input / output interface 803 is used to connect input / output modules to realize information input and output. The input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. The input device can include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device can include a display, a speaker, a vibrator, an indicator light, etc.

[0147] The communication interface 804 is used to connect a communication module (not shown in the figure) to realize the communication interaction between the present device and other devices. The communication module can realize communication through wired means (such as USB, network cable, etc.) or through wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0148] The bus 805 includes a channel for transmitting information between various components (such as the processor 801, the memory 802, the input / output interface 803 and the communication interface 804) of the device.

[0149] It should be noted that although the above device only shows the processor 801, the memory 802, the input / output interface 803, the communication interface 804 and the bus 805, in the specific implementation process, the device can also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above device can also only contain components necessary to implement the embodiments of the present specification, and does not necessarily contain all the components shown in the figure.

[0150] The embodiments of the present disclosure also provide a computer readable storage medium, which stores a computer program, and the program is executed by a processor to implement the method of any of the preceding embodiments.

[0151] The computer readable medium includes permanent and non-permanent, removable and non-removable media, which can be implemented by any method or technology to store information. The information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device. According to the definition in this paper, computer readable medium does not include transitory computer readable medium, such as modulated data signal and carrier wave.

[0152] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments of the present specification can be realized by means of software and necessary general hardware platforms. Based on such understanding, the technical solutions of the embodiments of the present specification can be embodied in the form of a software product, which can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including a number of instructions to make a computer device (which can be a personal computer, server, or network device, etc.) execute the methods described in various embodiments or some parts of the embodiments of the present specification.

[0153] The systems, apparatuses, modules, or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, and the specific forms of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0154] The various embodiments described in the specification are progressive, and the same or similar parts among the various embodiments can be mutually referred to. Each embodiment focuses on the differences from other embodiments. In particular, the device embodiments are described more simply because they are basically similar to the method embodiments, and the relevant parts can be referred to the part of the method embodiments. The device embodiments described above are merely illustrative, and the modules described as separate components can or can not be physically separated, and the functions of each module can be implemented in one or more software and / or hardware in the implementation of the embodiments of the specification. Some or all of the modules can be selected to achieve the purpose of the embodiments of the specification according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0155] The above is only a specific implementation of the embodiments of the specification, and it should be noted that those skilled in the art can make several improvements and refinements without departing from the principles of the embodiments of the specification, and these improvements and refinements should also be considered within the protection scope of the embodiments of the specification.

Claims

1. A data processing method for system on chip performance monitoring, characterized in that, Each subsystem in a chip system can generate a transaction request, the same transaction request can be repeatedly generated and sent in case that the transaction request fails to be responded, information of the transaction request is used for monitoring performance of the chip system, the performance of the chip system includes delay between response time and generation time of the same transaction request with the same tag; the method comprises: In case that a first transaction request is detected, a first tag of the first transaction request is acquired; each transaction request corresponds to a tag, the tag is used for identifying the transaction request, information of multiple transaction requests with the same tag is stored in multiple nodes of a same linked list; the first tag of the transaction request is xID of the transaction request; Information of the first transaction request is stored into a first linked list based on the first tag of the first transaction request; wherein the first linked list comprises at least one node, the node is used for storing information of the transaction request with the first tag, the information of the transaction request is used for monitoring performance of the chip system, the information of the transaction request comprises tag and generation time of the transaction request; information of multiple transaction requests with the first tag is sequentially stored into each node of the first linked list according to time when the multiple transaction requests are detected; delay between generation time and response time of the transaction request with any tag is determined based on the following manner: Generation time of the transaction request with the tag is extracted from a head node of the linked list; Time interval between the generation time of the transaction request with the tag and generation time of the transaction request with the tag is calculated; The time interval is determined as delay between the generation time and response time of the transaction request with the tag.

2. The method of claim 1, wherein, Information of the multiple transaction requests with the first tag is sequentially extracted according to order of the multiple transaction requests in the first linked list.

3. The method of claim 1, wherein, Number of nodes currently included in the first linked list is number of transaction requests with the first tag which are currently unresponded; and / or Information of multiple transaction requests with different tags is stored in different linked lists; And / or Multiple storage units are shared by nodes of at least two linked lists; wherein each storage unit is used for storing a node of a linked list.

4. The method of claim 1, wherein, The method further comprises: After information of the first transaction request is stored into the first linked list, storage unit is allocated for the node corresponding to the first transaction request, so that number of storage units allocated to the first linked list matches number of nodes currently included in the first linked list.

5. The method of claim 1, wherein, The storing information of the first transaction request into the first linked list based on the first tag of the first transaction request comprises: A new node is created for the first transaction request; The created node is linked to a current tail node of the first linked list.

6. The method of claim 5, wherein, The linking the created node to the current tail node of the first linked list comprises: Fourth indication information corresponding to the current tail node of the first linked list is updated as information of the created node, wherein the fourth indication information is used for indicating next node of the corresponding node; and / or updating second indication information corresponding to the current tail node of the first linked list to a first indication state, wherein the first indication state of the second indication information is used to indicate that the corresponding node is not a tail node of the linked list; and / or setting second indication information corresponding to the created node to a second indication state, wherein the second indication state of the second indication information is used to indicate that the corresponding node is a tail node of the linked list.

7. The method of claim 1, wherein, The method further comprises: after extracting the information of the transaction request stored in the current head node of the first linked list, performing at least one of the following: updating first indication information corresponding to the current head node, wherein the first indication information is used to indicate whether the corresponding node contains valid information; updating third indication information corresponding to the current head node to a third indication state, wherein the third indication state of the third indication information is used to indicate that the corresponding node is not a head node of the linked list; updating third indication information corresponding to the next node of the current head node of the first linked list to a fourth indication state, wherein the fourth indication state of the third indication information is used to indicate that the corresponding node is a head node of the linked list.

8. The method of claim 1, wherein, The storage unit allocated for the node of the first linked list stores at least one of the following indication information: first indication information used to indicate whether the storage unit is a valid storage unit, second indication information used to indicate whether the node is a tail node of the first linked list, third indication information used to indicate whether the node is a head node of the first linked list, fourth indication information used to indicate a storage unit used to store the next node of the node.

9. The method of claim 8, wherein, The method further comprises: parallelly querying the first indication information, the second indication information and the tag information stored in each of the plurality of storage units to determine the current tail node of the first linked list; and / or parallelly querying the first indication information, the third indication information and the tag information stored in each of the plurality of storage units to determine the current head node of the first linked list.

10. The method of claim 1, wherein, Each storage unit is used to store a node of a linked list, and the method further comprises: storing the node corresponding to the first transaction request into an invalid storage unit of the plurality of storage units.

11. The method of claim 10, wherein, The storing of the node corresponding to the first transaction request into an invalid storage unit of the plurality of storage units comprises: respectively querying the first indication information stored in the plurality of storage units to determine invalid storage units from the plurality of storage units, wherein the first indication information of the storage unit is used to indicate whether the storage unit is a valid storage unit.

12. A data processing method for system on chip performance monitoring, characterized in that, Each subsystem in a chip system can generate a transaction request, and the same transaction request can be repeatedly generated and sent multiple times in the case that the transaction request fails to be responded, the maximum number of unresponded transaction requests supported by the chip system is N, N is a positive integer, and the N unresponded transaction requests include transaction requests of the same tag and / or transaction requests of different tags; The method comprises: In the case of detecting a first transaction request, a first node is created for the first transaction request in a first linked list; the first linked list is used to store information of transaction requests with a first label, and the first label of a transaction request is an xID of the transaction request; Information of the first transaction request is stored in a storage unit allocated for the first node; wherein nodes of at least two linked lists share a plurality of storage units, the information of the first transaction request is used to monitor performance of the system chip, and the information of the first transaction request includes a label and a generation time of the first transaction request; information of a plurality of transaction requests with the same label is stored in a plurality of nodes of the same linked list; Each storage unit is used to store a node of a linked list, and the number of storage units allocated for the first linked list matches the number of nodes currently included in the first linked list; Wherein, information of a plurality of transaction requests with the first label is sequentially stored in each node of the first linked list according to the time when the plurality of transaction requests are detected; the delay between the generation time and the response time of a transaction request with any label is determined based on the following way: Extracting the generation time of the transaction request with the label from the head node of the linked list; Calculating the time interval between the generation time of the transaction request with the label and the generation time of the transaction request with the label; Determining the time interval as the delay between the generation time and the response time of the transaction request with the label.

13. The method of claim 12, wherein, The storage unit allocated for the first node stores at least one of the following indication information: First indication information for indicating whether the storage unit is a valid storage unit, Second indication information for indicating whether the first node is a tail node of the first linked list, Third indication information for indicating whether the first node is a head node of the first linked list, Fourth indication information for indicating a storage unit for storing a next node of the first node.

14. The method of claim 13, wherein, The method further comprises: Parallelly querying the first indication information, the second indication information and the label information stored in each storage unit of the plurality of storage units to determine the current tail node of the first linked list; and / or Parallelly querying the first indication information, the third indication information and the label information stored in each storage unit of the plurality of storage units to determine the current head node of the first linked list.

15. The method of claim 13, wherein, The method further comprises: Based on the first indication information stored in the plurality of storage units, allocating an invalid storage unit in the plurality of storage units for the first node.

16. A data processing device for system on chip performance monitoring, the device comprising: Each subsystem in a chip system can generate a transaction request, and the same transaction request can be repeatedly generated and sent multiple times in the case that the transaction request fails to be responded, information of the transaction request is used to monitor performance of the chip system, and the performance of the chip system includes a delay between the response time and the generation time of a transaction request with the same label; the device comprises: The acquisition module is configured to acquire a first tag of the first transaction request when the first transaction request is detected; each transaction request corresponds to a tag, which is used to identify the transaction request; information of multiple transaction requests with the same tag is stored in multiple nodes of the same linked list; the first tag of the transaction request is an xID of the transaction request; The first storage module is configured to store information of the first transaction request into a first linked list based on the first tag of the first transaction request; the first linked list includes at least one node, which is used to store information of a transaction request with the first tag; the information of the transaction request is used to monitor performance of the system chip; the information of the transaction request includes a tag and a generation time of the transaction request; information of multiple transaction requests with the first tag is sequentially stored into each node of the first linked list according to a time when the multiple transaction requests are detected; a delay between the generation time and a response time of a transaction request with any tag is determined based on the following manner: The generation time of the transaction request with the tag is extracted from a head node of the linked list; A time interval between the generation time of the transaction request with the tag and the generation time of the transaction request with the tag is calculated; The time interval is determined as the delay between the generation time and the response time of the transaction request with the tag.

17. A data processing device for system on chip performance monitoring, the device comprising: Each subsystem in a chip system can generate a transaction request; in a case where the transaction request fails to be responded, the same transaction request can be repeatedly generated and sent for multiple times; the chip system supports a maximum number N of unresponded transaction requests, N is a positive integer, and the N unresponded transaction requests include transaction requests with the same tag and / or transaction requests with different tags; The apparatus includes: The creation module is configured to create a first node for the first transaction request in the first linked list when the first transaction request is detected; the first linked list is used to store information of a transaction request with a first tag; the first tag of the transaction request is an xID of the transaction request; The second storage module is configured to store the information of the first transaction request into a storage unit allocated for the first node; nodes of at least two linked lists share multiple storage units; the information of the first transaction request is used to monitor performance of the system chip; the information of the first transaction request includes a tag and a generation time of the first transaction request; information of multiple transaction requests with the same tag is stored in multiple nodes of the same linked list; Each storage unit is used to store a node of a linked list; a number of storage units allocated for the first linked list matches a number of nodes currently included in the first linked list; In which, information of multiple transaction requests with the first tag is sequentially stored into each node of the first linked list according to a time when the multiple transaction requests are detected; a delay between the generation time and the response time of a transaction request with any tag is determined based on the following manner: The generation time of the transaction request with the tag is extracted from a head node of the linked list; A time interval between the generation time of the transaction request with the tag and the generation time of the transaction request with the tag is calculated; The time interval is determined as the delay between the generation time and the response time of the transaction request with the tag. The time interval is determined as a delay between a time of generation and a time of response of a transaction request of the tag.

18. A computer readable storage medium having stored thereon a computer program, characterized in that, The program, when executed by the processor, implements the method of any one of claims 1 to 15.

19. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the computer program comprises the steps of: The processor implements the method of any one of claims 1 to 15 when executing the program.

Images