All-flash array storage device and data processing method

Abstract

The present invention relates to an all-flash array storage device and a data processing method. The all-flash array storage device includes a flash memory array and a microprocessor. The flash memory array includes a plurality of flash memories, the flash memories correspond to a plurality of logical aggregation units, each logical aggregation unit includes a plurality of stripes, each stripe includes a plurality of storage units, and the storage units include data units and parity units. When the microprocessor detects that one of the flash memories is removed from the flash memory array, a repair operation is sequentially performed on the stripes included in one or more logical aggregation units to which data has been written. In the repair operation corresponding to a stripe, the microprocessor recalculates the protection information corresponding to the stripe based on the content stored in a portion of the data units of the stripe, and rewrites the recalculated protection information into one or more storage units of the stripe.

Description

Technical Field

[0001] The present invention relates to a data processing method for an all-flash array storage device, and more particularly to a data processing method that can efficiently restore the original data protection capability when a disk is lost in the all-flash array storage device. Background Art

[0002] All Flash Array (AFA) is a storage device architecture whose basic architecture is to use several flash memory disks to form a storage array to greatly increase the storage space of the storage device. All Flash Array is usually used in network-side servers to store large amounts of data from multiple users. In order to avoid the problem of data loss in the storage device due to damage or removal of one or more flash memory disks in the storage array, the storage device can use the error protection mechanism used in the Redundant Array of Independent Disks (RAID) technology to protect data. In the error protection mechanism used by RAID, the storage device can calculate protection information based on the data being written. When valid data is found to be lost, the protection information can be used to reversely deduce the content of the lost valid data.

[0003] For example, the storage device can calculate M pieces of protection information based on the data being written, so that the storage device can have a protection capability of +M. The +M means that even when M flash memory disks are damaged or removed, the storage device can still use the remaining data to perform data repair and deduce the data stored in the damaged or removed M flash memory disks.

[0004] However, for a storage device with +M protection capability, when a flash memory disk in the storage array is damaged or removed, the data protection capability will be reduced to +(M-1). When the number of damaged or removed flash memory disks is equal to M, the storage device will no longer have data protection capability.

[0005] In order to solve the above problems, a novel data processing method is needed to enable the storage device to recover the original data protection capability after a lost disk (including the above-mentioned flash memory disk being damaged or removed) occurs, while avoiding the situation where too many write operations are introduced to perform related operations to recover the original data protection capability, resulting in a significant decrease in the performance of the storage device. When a flash array storage device loses a disk, the original data protection capability can be efficiently recovered. Summary of the invention

[0006] An object of the present invention is to efficiently restore the original data protection capability when a flash array storage device fails.

[0007] According to one embodiment of the present invention, a full flash array storage device includes a flash memory array and a microprocessor. The flash memory array includes a plurality of flash memories, the flash memories correspond to a plurality of logical aggregation units, each logical aggregation unit includes a plurality of stripes, each stripe includes a plurality of storage units, and the storage unit includes a plurality of data units for storing data and at least one parity unit for storing protection information. The microprocessor is coupled to the flash memory array to detect a state of the flash memory. When the microprocessor detects that one of the flash memories is removed from the flash memory array, a repair operation is sequentially performed on the stripes included in one or more logical aggregation units to which data has been written. In the repair operation corresponding to a stripe, the microprocessor recalculates the protection information corresponding to the stripe according to the content stored in a portion of the data units of the stripe, and rewrites the recalculated protection information into one or more of the storage units of the stripe, and the number of the portion of the data units of the stripe is less than the number of all the data units included in the stripe.

[0008] According to an embodiment of the present invention, a data processing method for an all-flash array storage device is provided, wherein the all-flash array storage device includes a flash memory array, the flash memory array includes a plurality of flash memories, the flash memories correspond to a plurality of logical aggregation units, each logical aggregation unit includes a plurality of stripes, each stripe includes a plurality of storage units, the storage unit includes a plurality of data units for storing data and at least one parity unit for storing protection information, the data processing method includes: in response to a detection result indicating that one of the flash memories is removed from the flash memory array, sequentially performing a repair operation on the stripes included in one or more logical aggregation units to which data has been written. The step of sequentially performing a repair operation on the stripes included in one or more logical aggregation units to which data has been written also includes: recalculating the protection information corresponding to the stripe based on the content stored in a portion of the data units of a stripe; and rewriting the protection information corresponding to the recalculated stripe into one or more of the storage units of the stripe, wherein a number of the portion of the data units of the stripe is less than a number of all the data units included in the stripe.

[0009] According to an embodiment of the present invention, a full flash array controller includes a memory device and a microprocessor. The microprocessor is coupled to the memory device and a flash memory array, and is used to manage the flash memory array according to data stored in the memory device, wherein the flash memory array includes a plurality of logical aggregation units, each of which includes a plurality of stripes, each of which includes a plurality of storage units, and the storage unit includes a plurality of data units for storing data and at least one parity unit for storing protection information. When the microprocessor detects that a disk is lost in the flash memory array, a repair operation is sequentially performed on the stripes included in one or more logical aggregation units to which data has been written, and wherein in the repair operation corresponding to a stripe, the microprocessor recalculates the protection information corresponding to the stripe according to the content stored in a portion of the data units of the stripe, and rewrites the protection information corresponding to the recalculated stripe into one or more of the storage units of the stripe, wherein a number of the partial data units of the stripe is less than a number of all the data units included in the stripe. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 FIG. 4 is a schematic diagram showing the appearance of an all-flash array storage device according to an embodiment of the present invention.

[0011] Figure 2 FIG. 4 is a block diagram showing an example of a full flash array storage device according to an embodiment of the present invention.

[0012] Figure 3 FIG. 4 is a diagram showing a software architecture for managing a flash memory array according to an embodiment of the present invention.

[0013] Figure 4 It is a schematic diagram showing a logical aggregation unit according to an embodiment of the present invention.

[0014] Figure 5 The flowchart shows a data processing method of an all-flash array storage device according to an embodiment of the present invention.

[0015] Figure 6 FIG. 2 is a diagram showing an example of executing a repair operation according to an embodiment of the present invention.

[0016] Figure 7 FIG. 2 is another example of executing the repair operation according to an embodiment of the present invention.

[0017] Figure 8 It is a detailed flow chart showing a data processing method applicable to an all-flash array storage device according to an embodiment of the present invention.

[0018]

Explanation of symbols

[0019] 100,200: Full flash array storage device

[0020] 110-1,110-n,110-N,Drive_1,Drive_N: Flash memory disk

[0021] 200: All flash array storage device

[0022] 210: All-flash array controller

[0023] 220: Microprocessor

[0024] 230: Memory device

[0025] 240: Flash memory array

[0026] 310: Volume Management Module

[0027] 320: Flash array control module

[0028] 601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,701,702,703,704,705,706,707,708,709,710,711,712,713,714,715,716,717,718,719,720: Storage unit

[0029] D1~D32,Dh:Data

[0030] DLBA: Disk Logical Block Address

[0031] P,P',P",P1,P2,P3,P4,PM1,PM2,Q,Q',Q",Q1,Q2,Q3,Q4,QM1,QM2: Protection Information

[0032] User_Write: Write instruction

[0033] LAU: Logical Aggregation Unit

[0034] LBA1~LBA16: Logical Block Address

[0035] SLBA: Storage Pool Logical Block Address

[0036] Stripe_1, Stripe_K: Stripe

[0037] VVLBA: Virtual Volume Logical Block Address DETAILED DESCRIPTION

[0038] In the following, many specific details are described to provide a thorough understanding of the embodiments of the present invention. However, those skilled in the art will still understand how to implement the present invention in the absence of one or more specific details or relying on other methods, elements or materials. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the main concepts of the present invention.

[0039] References throughout this specification to "one embodiment," "an embodiment," "one example," or "an example" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment or example is included in at least one of the multiple embodiments of the present invention. Thus, the phrases "in one embodiment," "in an embodiment," "in an example," or "in an example" appearing in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples.

[0040] In addition, in order to make the purpose, features and advantages of the present invention more clearly understood, the following specific embodiments of the present invention are specifically cited and described in detail with the accompanying drawings. The purpose is to illustrate the spirit of the present invention rather than to limit the scope of protection of the present invention. It should be understood that the following embodiments can be implemented via software, hardware, firmware, or any combination thereof.

[0041] The present invention relates to a full flash array storage device and a data processing method of the full flash array storage device. According to an embodiment of the present invention, the full flash array storage device may include a plurality of flash memory disks, each of which may include at least one flash memory, and the flash memories included in the flash memory disks may form a flash memory array.

[0042] Figure 1 is a schematic diagram showing the appearance of a full flash array storage device according to an embodiment of the present invention. Figure 1 In the illustrated embodiment, the full flash array storage device 100 may include N flash memory disks, for example, the flash memory disks 110-1 to 110-N shown in the figure, where N is a positive integer greater than 1, and each flash memory disk includes a flash memory. Therefore, the full flash array storage device 100 may include a flash memory array composed of N flash memories.

[0043] When a flash array storage device loses a disk, for example, one of the flash memory disks (for example, the flash memory disk 110-n, where n is a positive integer) is removed from the full flash array storage device 100, or the disk is damaged or cannot be recognized, the data stored in the flash memory disk 110-n is lost, and the data protection capability of the full flash array storage device 100 is correspondingly reduced. In order to repair the lost data and enable the full flash array storage device 100 to restore the original data protection capability after the disk is lost, the full flash array storage device 100 needs to perform a corresponding repair operation to deduce the lost data and restore the original data protection capability of the full flash array storage device 100. In the embodiment of the present invention, by using the data processing method proposed by the present invention, the original data protection capability can be efficiently restored with a very small number of write operations.

[0044] Figure 2 2 is a block diagram showing an example of a full flash array storage device according to an embodiment of the present invention. According to an embodiment of the present invention, the full flash array storage device 200 may include a full flash array controller 210 and a flash memory array 240 formed by flash memories included in a plurality of flash memory disks. The full flash array controller 210 may include a microprocessor 220 and a memory device 230. The microprocessor 220 is coupled to the memory device 230 and the flash memory array 240 to manage the flash memory array 240 according to the data stored in the memory device 230. According to an embodiment of the present invention, the flash memory array 240 may include a plurality of flash memories, each of which may correspond to a flash memory disk, and the microprocessor 220 may continuously detect a state of each flash memory disk or flash memory. For example, the microprocessor 220 may continuously send a polling signal to poll the state of the flash memory disk or the flash memory. When the microprocessor 220 cannot receive a response from the flash memory disk or flash memory within a predetermined time, or the received response shows an abnormal state, or the microprocessor 220 can no longer identify the flash memory disk or flash memory, the microprocessor 220 can determine that a disk drop has occurred in the full flash array storage device 200 or the flash memory array 240. Since a disk drop may include different situations caused by a variety of different reasons, and these situations will all lead to the loss of data stored in this flash memory, therefore, in order to simplify the description, the following paragraphs will uniformly use the situation where the flash memory is removed from the flash memory array 240 as a representative of the various situations included in the disk drop. It can be understood that the data processing method proposed in the present invention is not limited to the situation where the flash memory is removed, but can be applied to any situation that will eventually lead to the loss of data in a portion of the flash memory included in the flash memory array and the inability to continue to use the portion of the flash memory included in the flash memory array.

[0045] Figure 3 1 is a diagram showing a software architecture for managing a flash memory array according to an embodiment of the present invention, for illustrating the addressing operation inside a full flash array storage device. According to an embodiment of the present invention, the microprocessor 220 may include one or more internal memory devices for storing data and program codes required for managing the flash memory array. The microprocessor 220 may generate a plurality of modules for managing the flash memory array by executing the program codes, and each module may perform a corresponding operation. For example, the software modules generated by the microprocessor 220 by executing the program codes may include a volume management module 310 and a flash array control module 320. In response to a write instruction User_Write for writing data corresponding to a virtual volume logical block address (Virtual Volume Logic Block Address, abbreviated as VVLBA) into the flash memory array, the volume management module 310 may first convert the virtual volume logical block address VVLBA into a storage pool logical block address (Storage pool Logic Block Address, abbreviated as SLBA) used inside another microprocessor 220, and inform the flash array control module 320 to write the data into the storage pool logical block address SLBA. Then, the flash array control module 320 converts the storage pool logical block address SLBA into a disk logical block address (Disk Logical Block Address, abbreviated as DLBA) of the flash memory array, and performs a corresponding write operation to write the received data (i.e., the data corresponding to the storage pool logical block address SLBA, which is also the data corresponding to the aforementioned virtual volume logical block address VVLBA) into the corresponding disk logical block address DLBA.

[0046] More specifically, in response to a write instruction User_Write for writing user data DATA_A corresponding to a virtual volume logical block address VVLBA_1 into the flash memory array, the microprocessor 220 of the full flash array controller 210 may perform two address conversion operations, first converting the virtual volume logical block address VVLBA_1 into another internally used storage pool logical block address SLBA_1, and then converting the storage pool logical block address SLBA_1 into the disk logical block address DLBA_1. Then, the microprocessor 220 may issue a write instruction to one or more flash memory disks to write the data DATA_A into the storage unit addressed by the disk logical block address DLBA_1 in the flash memory array.

[0047] It should be noted that in the embodiment of the present invention, the aforementioned storage unit is a storage unit in the full flash array storage device, that is, a storage unit viewed by the full flash array controller 210, which may not correspond to a physical storage unit inside each flash memory.

[0048] In addition, it should be noted that, in the embodiment of the present invention, the size of the "block" in the block address may not be equal to the size of the physical "memory block" contained in the flash memory. For example, in one embodiment of the present invention, the "block" in the physical block address or the logical block address may be a write unit of 4K bytes, so a disk logical block address DLBA may address a storage unit with a size of 4KB in the flash memory array. The size of a physical "memory block" contained in the flash memory may depend on the physical configuration of the flash memory.

[0049] In addition, it should be noted that since the flash memory array is composed of flash memories included in a plurality of flash memory disks, and each flash memory disk may further include a memory controller for controlling the access operation of the corresponding flash memory, therefore, when the memory controller in each flash memory disk writes the received data into the corresponding flash memory according to the received disk logical block address DLBA (or, when the memory controller reads data from the corresponding flash memory according to the received logical address), it will still perform another address conversion operation to convert the received logical address into a physical address that can be addressed to one or more physical storage units of the corresponding flash memory, and this physical address (i.e., the physical address viewed by the memory controller in each flash memory disk) is the address that actually corresponds to the physical storage unit.

[0050] Continuing with the previous example, when a flash memory disk including a storage unit of a full flash array storage device pointed to by a disk logical block address DLBA_1 receives a write instruction including data DATA_A and related information such as the disk logical block address DLBA_1, the memory controller of the flash memory disk can further convert the disk logical block address DLBA_1 into a physical block address PBA_1 actually used internally, wherein the physical block address PBA_1 indicates the memory block and data page in the flash memory disk that are actually arranged to store the data DATA_A, and the memory controller stores the data DATA_A in the memory block and data page addressed by the physical block address PBA_1.

[0051] According to an embodiment of the present invention, a flash memory array may include a plurality of flash memories, the flash memories correspond to a plurality of logical aggregation units (LAUs), each logical aggregation unit includes a plurality of stripes, each stripe includes a plurality of storage units. A plurality of storage units in the same stripe of a full flash array storage device may actually be distributed in a plurality of flash memories, and these storage units may include a plurality of data units for storing data and at least one parity unit for storing protection information.

[0052] Figure 4 1 is a schematic diagram showing a logical aggregation unit according to an embodiment of the present invention. In this example, the full flash array storage device may include a plurality of flash memory disks Drive_1 to Drive_N, where N is a positive integer. The flash memory array composed of the flash memories included in the flash memory disks Drive_1 to Drive_N may form / correspond to a plurality of logical aggregation units, such as one of the logical aggregation units LAU framed by the dotted line in the figure. Each logical aggregation unit corresponds to a portion of the flash memory disks Drive_1 to Drive_N, for example, a memory space of 64KB.

[0053] Figure 4 The right side of the diagram shows the data content stored in a logical aggregation unit LAU. Each logical aggregation unit includes multiple stripes, such as the stripes Stripe_1 to Stripe_K shown in the figure, where K is a positive integer. Each stripe includes multiple storage units, and the size of a storage unit can be designed to be the size of a write unit (for example, 4KB). The storage units located in the same stripe can correspond to different flash memory disks respectively. The storage unit can include or be further divided into multiple data units for storing data (for example, data D1 to D32) and multiple parity units for storing protection information (for example, protection information P1 to P4 and Q1 to Q4).

[0054] At Figure 4In the example shown, N=10, and the flash memory array is designed to have a protection capability of +2. Therefore, as shown in the figure, stripe Stripe_1 may include 10 storage units corresponding to different flash memories, 8 of which may be configured as data units for storing data, and the remaining 2 storage units may be configured as parity units for storing protection information. The microprocessor 220 may calculate the corresponding protection information (e.g., protection information P1 and Q1) based on the data content stored in the data unit (e.g., data D1 to D8 stored in the data unit of stripe Stripe_1), and store the protection information in the parity unit of this stripe to protect the data stored in this stripe. The data stored in the data unit described herein is the aforementioned user data.

[0055] In addition to storing user data, one or more stripes of a logical aggregation unit LAU can be used to store the meta data of the logical aggregation unit LAU, wherein the meta data may at least include the mapping information of the multiple stripes of the logical aggregation unit LAU from the disk to the storage pool (abbreviated as D2S). Figure 4 In the example shown, the stripe for storing the original data (e.g., stripes Stripe_(K-1) and Stripe_K) can record a plurality of logical block addresses, such as the logical block addresses LBA1 to LBA16 shown in the figure, wherein a data unit of the stripe for storing the original data can be used to store the logical block address corresponding to the data stored in a data unit of the stripe for storing the user data (e.g., stripe Stripe_1). That is, the logical block address recorded in a data unit of the stripe for storing the original data can be the logical block address corresponding to the data stored in a data unit of the stripe for storing the user data (e.g., the aforementioned storage pool logical block address SLBA). In addition, in order to protect the D2S mapping information, the microprocessor 220 can calculate the corresponding protection information (e.g., protection information PM1 and QM1) according to the data content stored in the data unit of the stripe for storing the original data (e.g., logical block addresses LBA1 to LBA8), and store the protection information in the parity unit of this stripe.

[0056] In an embodiment of the present invention, the logical block addresses LBA1 - LBA16 may be the aforementioned storage pool logical block addresses SLBA, and the number of stripes used to store original data in a logical aggregation unit LAU may be equal to the number of stripes used to store user data.

[0057] Reference Figure 2According to an embodiment of the present invention, when the microprocessor 220 detects that one of the flash memories is removed from the flash memory array 240, the microprocessor 220 may perform a repair operation so that the flash memory array 240 can restore the predetermined data protection capability. The predetermined data protection capability may be the original data protection capability of the flash memory array 240, that is, the protection capability originally set. For example, assuming that the microprocessor 220 calculates two corresponding protection information (for example, Figure 4 When the microprocessor 220 detects that one of the flash memories is removed from the flash memory array 240, the protection capability of the flash memory array 240 will be reduced to only have a protection capability of +1. Therefore, in the embodiment of the present invention, the microprocessor 220 can perform a repair operation so that the flash memory array 240 can restore the predetermined data protection capability of +2. It should be noted that, for the sake of simplicity, two pieces of protection information and a data protection capability of +2 are used as an illustrative example in the embodiment of the present invention, but the present invention is not limited thereto. The flash memory array can provide different data protection capabilities using different amounts of protection information.

[0058] Figure 5 2 is a flow chart showing a data processing method of an all-flash array storage device according to an embodiment of the present invention. According to an embodiment of the present invention, as described above, in the data processing method of an all-flash array storage device proposed by the present invention, in response to a detection result indicating that one of the flash memories is removed from the flash memory array, the microprocessor 220 can sequentially perform a repair operation on a plurality of stripes included in one or more logical aggregation units to which data has been written, so that the flash memory array can resume providing a predetermined data protection capability.

[0059] In the embodiment of the present invention, the repair operation is repeatedly performed on each stripe included in the logical aggregation unit to which data has been written, until the repair operations of all the logical aggregation units to which data has been written are completed.

[0060] In an embodiment of the present invention, the repair operation sequentially performed on the stripes included in one or more logical aggregation units to which data has been written may include the following steps:

[0061] Step S502: recalculate the protection information corresponding to a stripe according to the contents stored in a portion of data units in a stripe included in a logical aggregation unit to which data has been written. It should be noted that, in the embodiment of the present invention, no matter the storage units in a stripe corresponding to the removed flash memory are data units or parity units, the number of the portion of data units used to recalculate the protection information in step S502 will be less than the number of all data units included in the stripe.

[0062] Step S504: rewrite the recalculated protection information corresponding to the stripe into one or more of the storage units of the stripe. For example, if the microprocessor 220 wants to enable the flash memory array to provide +2 data protection capability, the microprocessor 220 can recalculate two corresponding protection information based on the data content stored in some data units of a stripe, and rewrite the recalculated protection information into two storage units to replace the previously stored content.

[0063] Figure 6 An example of an execution of a repair operation according to an embodiment of the present invention is shown to illustrate the repair operation when the storage unit corresponding to the removed flash memory in a stripe is a data unit. In this example, a stripe may include 10 storage units corresponding to different flash memories, such as storage units 601-610 shown in the figure, where storage units 601-608 are data units, respectively used to store data D1-D8, and storage units 609-610 are parity units, respectively used to store protection information P and Q corresponding to the data D1-D8 stored in this stripe.

[0064] Assuming that the storage unit 605 corresponding to the removed flash memory in this stripe is a data unit, during the repair operation, the microprocessor 220 can determine whether this data unit 605 stores valid data. If the data unit 605 does not store valid data, that is, the data D5 is invalid data, the microprocessor 220 can directly discard the data D5, and recalculate the protection information corresponding to this stripe according to the contents stored in the remaining data units other than the storage unit corresponding to the removed flash memory in this stripe (for example, recalculate the protection information P' and Q' corresponding to this stripe according to the data D1~D4 and D6~D8 shown in the figure), and the microprocessor 220 can write the recalculated protection information into the parity unit of this stripe to replace the content originally stored in the parity unit (for example, store the recalculated protection information P' and Q' in the storage units 609~610 of this stripe to replace the previous protection information P and Q). It should be noted that for the microprocessor 220, the recalculated protection information is written to the same disk logical block address DLBA (eg, the address of storage units 609-610), and for the memory controller in the corresponding flash memory disk, the recalculated protection information is updated data of the same logical address.

[0065] On the other hand, if the data unit 605 still stores valid data, the microprocessor 220 needs to perform data recovery and data migration operations, reversely deduce the data stored in the data unit 605 based on the content stored in this stripe, and move the restored data to other storage units. More specifically, the microprocessor 220 can deduce the valid data stored in the storage unit 605 based on the content stored in the remaining storage units in this stripe. After obtaining the valid data stored in the data unit 605 (for example, the data D5 shown in the figure), the microprocessor 220 writes the derived valid data D5 into a storage unit of an active logical aggregation unit (for example, the storage unit 611 shown in the figure), and the active logical aggregation unit refers to the logical aggregation unit that is being configured to receive user data (for example, the data Dh shown in the figure). After the data units in the currently used logical aggregation unit (for example, storage units 611~618) are full, the microprocessor 220 can calculate two corresponding protection information (for example, P" and Q" shown in the figure) according to the data content stored in the data unit and write them into the corresponding parity units (for example, storage units 619~620).

[0066] In addition, the microprocessor 220 updates the mapping information of the logical address (e.g., storage pool logical block address SLBA) corresponding to the valid data in a mapping table (e.g., a storage pool to disk (abbreviated as S2D) mapping table) according to an address (e.g., disk logical block address DLBA) of a data unit (e.g., storage unit 611 shown in the figure) used to store the derived (restored) valid data in the current logical aggregation unit. For example, the S2D mapping information of the storage pool logical block address SLBA corresponding to the valid data in the S2D mapping table is modified to the disk logical block address DLBA of the storage unit 611.

[0067] According to one embodiment of the present invention, the microprocessor 220 can establish the aforementioned S2D mapping table for the flash memory array 240 to record the disk logical block address DLBA corresponding to each storage pool logical block address SLBA, and store this S2D mapping table in the memory device 230, wherein the disk logical block address DLBA corresponding to a storage pool logical block address SLBA indicates the disk logical block address DLBA that stores the data corresponding to this storage pool logical block address SLBA.

[0068] The microprocessor 220 can determine whether the data stored in a data unit is valid data by comparing the S2D mapping information recorded in the S2D mapping table with the D2S mapping information recorded in the logical aggregation unit LAU. More specifically, the S2D mapping table can include a plurality of fields, one field corresponding to a storage pool logical block address SLBA, for recording which disk logical block address DLBA of the flash memory array 240 the data of the storage pool logical block address SLBA is actually stored in. The number of fields included in the S2D mapping table can be equal to the total number of logical block addresses or storage units viewed by the volume management module 310 and / or the flash array control module 320.

[0069] In addition, as described above, one or more stripes used to store original data in a logical aggregation unit LAU may record the D2S information of multiple stripes in the logical aggregation unit LAU. When determining whether the data stored in a data unit (e.g., data unit DU_a) is valid data, the microprocessor 220 may first check the original data of the data unit recorded in the logical aggregation unit LAU containing the data unit to obtain the D2S mapping information of the data unit, for example, to obtain the storage pool logical block address SLBA_a corresponding to the data unit DU_a (i.e., to know that the data currently stored in the data unit corresponds to the storage pool logical block address SLBA_a). Next, the microprocessor 220 can check the content recorded in the S2D mapping table stored in the memory device 230 corresponding to the storage pool logical block address SLBA_a to obtain the S2D mapping information of the storage pool logical block address SLBA_a, for example, to obtain the disk logical block address DLBA_a currently corresponding to the storage pool logical block address SLBA_a (i.e., to obtain the data of the storage pool logical block address SLBA_a is currently stored in the disk logical block address DLBA_a). If the disk logical block address DLBA_a is equal to the disk logical block address of the data unit DU_a, it means that the data stored in the data unit DU_a is valid data. If the disk logical block address DLBA_a is not equal to the disk logical block address of the data unit DU_a, it means that the data of the storage pool logical block address SLBA_a has been updated and stored in other data units, so the data stored in the data unit DU_a is invalid data.

[0070] In addition, as described above, in the embodiment of the present invention, for the microprocessor 220, although the aforementioned operation is to rewrite the recalculated protection information P' and Q' to the same disk logical block address DLBA to replace the previous protection information P and Q, for the memory controller in the corresponding flash memory disk, this operation is actually to write the recalculated protection information P' and Q' to a new physical address respectively. In addition, the memory controller can also establish and maintain a corresponding logical to physical (Logical to Physical, abbreviated as L2P) mapping table for the corresponding flash memory, and modify the L2P mapping information of the logical address (for example, the disk logical block address of storage units 609-610) for this flash memory disk to the physical address of the actual storage protection information P' and Q'. By this operation, the previous protection information P and Q can be made invalid data.

[0071] Figure 7FIG. 1 is another example of the repair operation according to an embodiment of the present invention, which is used to illustrate the repair operation when the storage unit corresponding to the removed flash memory in a stripe is a parity unit. In this example, a stripe may correspond to 10 storage units of different flash memories, such as storage units 701-710 shown in the figure, where storage units 701-708 are data units, respectively used to store data D1-D8, and storage units 709-710 are parity units, respectively used to store protection information P and Q corresponding to the data D1-D8 stored in this stripe.

[0072] Assuming that the storage unit 709 in this stripe corresponding to the removed flash memory is a co-location unit, during the repair operation, the microprocessor 220 may select one of the data units from the same stripe, for example but not limited to, selecting the storage unit 708 that is closest to the storage unit 709, and recalculating the protection information corresponding to this stripe according to the contents stored in the remaining data units other than the selected data unit in this stripe (for example, recalculating the protection information P' and Q' corresponding to this stripe according to the data D1 to D7 shown in the figure), and the microprocessor 220 may write the recalculated protection information into the selected storage unit to replace the contents originally stored in the storage unit (for example, storing the protection information P' in the storage unit 708 to replace the previously stored data D8), and write the recalculated protection information into the co-location unit that has not been removed in this stripe to replace the contents originally stored in the co-location unit (for example, storing the protection information Q' in the storage unit 710 to replace the previous protection information Q).

[0073] In addition, the microprocessor 220 can determine whether the selected storage unit stores valid data. If the data D8 stored in the selected storage unit 708 is invalid data, the microprocessor 220 can directly discard the data D8. If the data D8 stored in the selected storage unit 708 is still valid data, the microprocessor 220 can move (write) the data D8 to a data unit of an active logical aggregation unit (for example, the storage unit 711 shown in the figure). After the data units in the active logical aggregation unit (for example, storage units 711~718) are full, the microprocessor 220 can calculate two corresponding protection information (for example, P" and Q" shown in the figure) according to the data content stored in the data unit and write them into the corresponding parity units (for example, storage units 719~720).

[0074] In addition, the microprocessor 220 updates the mapping information of a logical address (e.g., storage pool logical block address SLBA) corresponding to the valid data in a mapping table (e.g., S2D mapping table) according to an address (e.g., disk logical block address DLBA) of a data unit (e.g., storage unit 711 shown in the figure) used to store the moved valid data (e.g., data D8 shown in the figure) in the current logical aggregation unit. For example, the S2D mapping information of the storage pool logical block address SLBA corresponding to the valid data in the S2D mapping table is modified to the disk logical block address DLBA of the storage unit 711.

[0075] Similarly, in the embodiment of the present invention, for the microprocessor 220, although the aforementioned operation is to rewrite the recalculated protection information P" and Q" to the same disk logical block address DLBA to replace the previously stored user data and protection information, for the memory controller in the corresponding flash memory disk, this operation is actually to write the recalculated protection information P" and Q" to a new physical address respectively. The memory controller can further modify the L2P mapping information of the logical address for the flash memory disk (for example, the disk logical block address DLBA of the storage units 708 and 710) in the L2P mapping table maintained internally to the physical address where the protection information P" and Q" are actually stored. By this operation, the previously stored user data and protection information can be made invalid data.

[0076] It should be noted that in the embodiment of the present invention, no matter the storage unit corresponding to the removed flash memory is a data unit or a parity unit, in a repair operation of a band, only three write operations need to be performed at most. Figure 6 In the illustrated embodiment, if the data D5 is still valid data, the write operation to be performed in the repair operation includes the write operation of writing the data D5 into the storage unit 611 and the write operation of writing the recalculated protection information P' and Q' into the storage units 609 and 610. On the other hand, when the data D5 is invalid data, only two write operations need to be performed in the repair operation, including the write operation of writing the recalculated protection information P' and Q' into the storage units 609 and 610.

[0077] Similarly, Figure 7 In the illustrated embodiment, if the data D8 is still valid data, the write operation to be performed in the repair operation includes the write operation of writing the data D8 into the storage unit 711 and the write operation of writing the recalculated protection information P' and Q' into the storage units 708 and 710. On the other hand, when the data D8 is invalid data, only two write operations need to be performed in the repair operation, including the write operation of writing the recalculated protection information P' and Q' into the storage units 708 and 710.

[0078] In the prior art, in the repair operation of a stripe, at least N write operations need to be performed, where N is the total number of flash memory disks or flash memories included in the full flash array storage device. Therefore, when N is a large number, a large number of write operations will cause the performance of the storage device to drop significantly. Compared with the prior art, in the data processing method of the present invention, at most three write operations need to be performed in the repair operation of a stripe. In this way, the problem that a large number of write operations are introduced in order to perform related operations to restore the original data protection capability in the prior art, resulting in a significant drop in the performance of the storage device, can be effectively solved.

[0079] Figure 8 Detailed flow chart of a data processing method for a full flash array storage device according to an embodiment of the present invention. The data processing method may start when one of the flash memory disks is detected to be removed, and includes the following steps:

[0080] Step S802: The microprocessor 220 may select a logical aggregation unit to which data has been written, and read the original data stored in the logical aggregation unit to obtain the D2S mapping information of the multiple storage units included in the logical aggregation unit.

[0081] Step S804: The microprocessor 220 selects a stripe in the logical aggregation unit. For example, the microprocessor 220 may select stripes included in the logical aggregation unit in sequence from the first stripe according to the stripe number or index value.

[0082] Step S806: The microprocessor 220 may determine whether a storage unit in the stripe corresponding to the removed flash memory / flash memory disk (or the removed storage unit for simplified explanation) is a data unit. If not, step S808 is executed. If yes, step S810 is executed. It is worth noting that the determination of "whether the removed storage unit is a data unit" in step S806 may also be replaced by the determination of "whether the removed storage unit is a parity unit". Under this determination, if yes, step S808 is executed. If no, step S810 is executed.

[0083] Step S808: The microprocessor 220 may select a data unit from the stripe and determine whether the selected data unit stores valid data. If not, step S812 is executed. If yes, step S814 is executed.

[0084] Step S810: The microprocessor 220 may determine whether the removed data unit stores valid data. If not, step S822 is executed. If yes, step S826 is executed.

[0085] Step S812: The microprocessor 220 may read the contents stored in the remaining data units in the stripe except the selected data unit.

[0086] Step S814: The microprocessor 220 may read the contents stored in all data units in the stripe.

[0087] Step S816: The microprocessor 220 may write the content stored in the selected data unit into an currently used logical aggregation unit.

[0088] Step S818: The microprocessor 220 may update the S2D mapping table maintained by the microprocessor 220 for the flash memory array 240 according to the write operation of step S816. Figure 7 Update operations described.

[0089] Step S820: The microprocessor 220 may recalculate the protection information corresponding to the stripe according to the contents stored in the remaining data units except the selected data unit in the stripe, and store the recalculated protection information. As described above, when the protection information corresponding to the stripe includes more than one piece of protection information, the protection information may be written into the disk logical block address DLBA of the selected data unit in the stripe and the disk logical block address DLBA of the same unit that has not been removed, to replace the previously stored contents. It is worth noting that the "read contents" in the text "recalculate and store the protection information corresponding to the stripe according to the read contents" in step S820 in the figure refers to the contents stored in the remaining data units except the selected data unit read in step S812, or the contents stored in the remaining data units except the selected data unit read in step S814.

[0090] Step S822: The microprocessor 220 may read the contents stored in the remaining data units in the stripe except for the removed storage unit.

[0091] Step S824: The microprocessor 220 can recalculate the protection information corresponding to this stripe according to the contents stored in the remaining data units in this stripe except the removed storage unit, and store the recalculated protection information. As described above, when the protection information corresponding to this stripe includes more than one piece of protection information, the protection information can be written into the disk logical block address DLBA of each co-location unit to replace the previously stored protection information. It is worth noting that the "read content" in the text "recalculate and store the protection information corresponding to this stripe according to the read content" in step S824 in the figure refers to the contents stored in the remaining data units in this stripe except the removed data unit, which are taken out in step S822, or the contents stored in the remaining data units in this stripe except the removed data unit, which are read in step S826.

[0092] Step S826: The microprocessor 220 may read the contents stored in the data units and parity units that have not been removed in the stripe.

[0093] Step S828: The microprocessor 220 derives the valid data stored in the removed storage unit according to the read content, and writes the derived valid data into an currently used logical aggregation unit.

[0094] Step S830: The microprocessor 220 may update the S2D mapping table maintained by the microprocessor 220 for the flash memory array 240 according to the write operation of step S828. Figure 6 Update operations described.

[0095] Step S832: The microprocessor 220 may determine whether the currently processed stripe is the last stripe in the LAU. If so, it means that the repair operations of all stripes of the currently selected LAU have been completed, and the process proceeds to step S834. If not, the process returns to step S804 and selects the next stripe that has not been processed.

[0096] Step S834: The microprocessor 220 may determine whether the currently processed LAU is the last LAU to which data has been written. If so, it means that the repair operations corresponding to all LAUs affected by the disk removal have been completed. If not, the process returns to step S802 to select the next LAU that has not been processed.

[0097] In summary, in the data processing method of the present invention, only three write operations need to be performed at most during the repair operation of each stripe. With the improvement of the present invention, the write operation introduced by the repair operation is no longer related to the total amount of flash memory disks or flash memories included in the full flash array storage device. In this way, the original data protection capability can be restored very efficiently, and the problem of introducing a large number of write operations in order to perform related operations to restore the original data protection capability in the prior art can be effectively solved, which leads to a significant decrease in the performance of the storage device.

[0098] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. An all-flash array storage device, comprising: A flash memory array, wherein the flash memory array includes a plurality of flash memories corresponding to a plurality of logical aggregation units, each logical aggregation unit includes a plurality of stripes, each stripe includes a plurality of storage units, and the storage units include a plurality of data units for storing data and at least one parity unit for storing protection information; as well as a microprocessor coupled to the flash memory array for detecting a state of the flash memories, wherein when the microprocessor detects that one of the flash memories is removed from the flash memory array, a repair operation is sequentially performed on the stripes included in one or more logical aggregation units to which data has been written, and In the repair operation corresponding to a stripe, the microprocessor recalculates the protection information corresponding to the stripe according to the contents stored in a portion of the data units of the stripe, and rewrites the recalculated protection information corresponding to the stripe into one or more of the storage units of the stripe. The quantity of the portion of data units in the stripe is less than the quantity of all data units included in the stripe.

2. The all-flash array storage device as claimed in claim 1, wherein: In the repair operation corresponding to a stripe, the microprocessor also determines whether a storage unit in the stripe corresponding to the removed flash memory is a parity unit, and when the storage unit in the stripe corresponding to the removed flash memory is a parity unit, the microprocessor selects a data unit from the stripe, recalculates the protection information corresponding to the stripe based on the contents stored in the remaining data units in the stripe other than the selected data unit, and stores the recalculated protection information corresponding to the stripe in the selected data unit to replace the contents stored in the selected data unit.

3. The all-flash array storage device as claimed in claim 2, wherein: In the repair operation corresponding to the stripe, the microprocessor also determines whether the selected data unit stores valid data, and when the selected data unit stores valid data, the microprocessor reads the valid data stored in the selected data unit, writes the valid data into a data unit of an currently used logical aggregation unit, and updates the mapping information of a logical address corresponding to the valid data in a mapping table according to an address of the data unit of the currently used logical aggregation unit.

4. The all-flash array storage device as claimed in claim 1, wherein: In the repair operation corresponding to a stripe, the microprocessor also determines whether a storage unit in the stripe corresponding to the removed flash memory is a data unit, and when the storage unit in the stripe corresponding to the removed flash memory is a data unit, the microprocessor recalculates the protection information corresponding to the stripe based on the contents stored in the remaining data units in the stripe other than the storage unit corresponding to the removed flash memory, and stores the recalculated protection information corresponding to the stripe in the parity unit of the stripe to replace the contents stored in the parity unit.

5. The all-flash array storage device as claimed in claim 4, wherein: In the repair operation corresponding to the stripe, the microprocessor also determines whether the storage unit corresponding to the removed flash memory in the stripe stores valid data, and when the storage unit corresponding to the removed flash memory stores valid data, the microprocessor reads the contents stored in the remaining storage units in the stripe other than the storage unit corresponding to the removed flash memory, derives the valid data stored in the storage unit corresponding to the removed flash memory based on the read contents, writes the derived valid data into a data unit of an currently used logical aggregation unit, and updates the mapping information of a logical address corresponding to the valid data in a mapping table based on an address of the data unit of the currently used logical aggregation unit.

6. A data processing method, applicable to an all-flash array storage device, the all-flash array storage device comprising a flash memory array, the flash memory array comprising a plurality of flash memories, the flash memories corresponding to a plurality of logical aggregation units, each logical aggregation unit comprising a plurality of stripes, each stripe comprising a plurality of storage units, the storage units comprising a plurality of data units for storing data and at least one parity unit for storing protection information, the data processing method comprising: In response to a detection result indicating that one of the flash memories is removed from the flash memory array, a repair operation is sequentially performed on the stripes included in one or more logical aggregation units to which data has been written, The step of sequentially performing the repair operation on the stripes included in the one or more logical aggregation units to which data has been written further includes: Recalculating the protection information corresponding to a stripe according to the contents stored in a portion of data units of the stripe; and re-write the protection information corresponding to the recalculated stripe into one or more of the storage units of the stripe, The quantity of the portion of data units in the stripe is less than the quantity of all data units included in the stripe.

7. The data processing method according to claim 6, characterized in that: The step of sequentially performing the repair operation on the stripes included in the one or more logical aggregation units to which data has been written further includes: determining whether a storage unit in the stripe corresponding to the removed flash memory is a parity unit; and When the storage unit in the stripe corresponding to the removed flash memory is a co-location unit, a data unit is selected from the stripe, the protection information corresponding to the stripe is recalculated based on the contents stored in the remaining data units in the stripe other than the selected data unit, and the recalculated protection information corresponding to the stripe is stored in the selected data unit to replace the contents stored in the selected data unit.

8. The data processing method according to claim 7, characterized in that: The step of sequentially performing the repair operation on the stripes included in the one or more logical aggregation units to which data has been written further includes: Determining whether the selected data unit stores valid data; and When the selected data unit stores valid data, the valid data stored in the selected data unit is read, the valid data is written into a data unit of an currently used logical aggregation unit, and mapping information corresponding to a logical address of the valid data in a mapping table is updated according to an address of the data unit of the currently used logical aggregation unit.

9. The data processing method according to claim 6, characterized in that: The step of sequentially performing the repair operation on the stripes included in the one or more logical aggregation units to which data has been written further includes: determining whether a storage unit in the stripe corresponding to the removed flash memory is a data unit; and When the storage unit in the stripe corresponding to the removed flash memory is a data unit, the protection information corresponding to the stripe is recalculated based on the contents stored in the remaining data units in the stripe other than the storage unit corresponding to the removed flash memory, and the recalculated protection information corresponding to the stripe is stored in the parity unit of the stripe to replace the contents stored in the parity unit.

10. The data processing method according to claim 9, characterized in that: The step of sequentially performing the repair operation on the stripes included in the one or more logical aggregation units to which data has been written further includes: determining whether the storage unit in the stripe corresponding to the removed flash memory stores valid data; and When the storage unit corresponding to the removed flash memory stores valid data, the contents stored in the remaining storage units in the stripe other than the storage unit corresponding to the removed flash memory are read, the valid data stored in the storage unit corresponding to the removed flash memory is derived based on the read contents, the derived valid data is written into a data unit of an currently used logical aggregation unit, and mapping information of a logical address corresponding to the valid data in a mapping table is updated based on an address of the data unit of the currently used logical aggregation unit.

11. An all-flash array controller, comprising: a memory device; as well as a microprocessor coupled to the memory device and a flash memory array for managing the flash memory array according to data stored in the memory device, wherein the flash memory array includes a plurality of logical aggregation units, each of the logical aggregation units includes a plurality of stripes, each of the stripes includes a plurality of storage units, and the storage units include a plurality of data units for storing data and at least one parity unit for storing protection information, When the microprocessor detects that a disk is lost in the flash memory array, a repair operation is performed sequentially on the stripes included in one or more logical aggregation units to which data has been written, and In the repair operation corresponding to a stripe, the microprocessor recalculates the protection information corresponding to the stripe according to the contents stored in a portion of the data units of the stripe, and rewrites the recalculated protection information corresponding to the stripe into one or more of the storage units of the stripe. The quantity of the portion of data units in the stripe is less than the quantity of all data units included in the stripe.

12. The all-flash array controller according to claim 11, wherein: In the repair operation corresponding to a stripe, the microprocessor also determines whether a storage unit in the stripe corresponding to a removed flash memory is a parity unit, and when the storage unit in the stripe corresponding to the removed flash memory is a parity unit, the microprocessor selects a data unit from the stripe, recalculates the protection information corresponding to the stripe based on the contents stored in the remaining data units in the stripe other than the selected data unit, and stores the recalculated protection information corresponding to the stripe in the selected data unit to replace the contents stored in the selected data unit.

13. The all-flash array controller according to claim 12, wherein: In the repair operation corresponding to the stripe, the microprocessor also determines whether the selected data unit stores valid data, and when the selected data unit stores valid data, the microprocessor reads the valid data stored in the selected data unit, writes the valid data into a data unit of an currently used logical aggregation unit, and updates the mapping information of a logical address corresponding to the valid data in a mapping table according to an address of the data unit of the currently used logical aggregation unit.

14. The all-flash array controller according to claim 11, wherein: In the repair operation corresponding to a stripe, the microprocessor also determines whether a storage unit in the stripe corresponding to a removed flash memory is a data unit, and when the storage unit in the stripe corresponding to the removed flash memory is a data unit, the microprocessor recalculates the protection information corresponding to the stripe based on the contents stored in the remaining data units in the stripe other than the storage unit corresponding to the removed flash memory, and stores the recalculated protection information corresponding to the stripe in the parity unit of the stripe to replace the contents stored in the parity unit.

15. The all-flash array controller according to claim 14, wherein: In the repair operation corresponding to the stripe, the microprocessor also determines whether the storage unit corresponding to the removed flash memory in the stripe stores valid data, and when the storage unit corresponding to the removed flash memory stores valid data, the microprocessor reads the contents stored in the remaining storage units in the stripe other than the storage unit corresponding to the removed flash memory, derives the valid data stored in the storage unit corresponding to the removed flash memory based on the read contents, writes the derived valid data into a data unit of an currently used logical aggregation unit, and updates the mapping information of a logical address corresponding to the valid data in a mapping table based on an address of the data unit of the currently used logical aggregation unit.

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