Dynamic L2P cache

Abstract

The present application relates to dynamic L2P caches. In some examples, methods, systems, and machine-readable media are disclosed for dynamically adjusting the size of an L2P cache in a memory device in response to observed operating conditions. The L2P cache can borrow memory space from donor memory locations, such as read or write buffers. For example, if the system observes a high number of read requests, the system can increase the size of the L2P cache at the expense of the write buffer (which can be reduced). Similarly, if the system observes a high number of write requests, the system can increase the size of the L2P cache at the expense of the read buffer (which can be reduced).

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with application number 201880078171.2, application date October 9, 2018, and invention name “Dynamic L2P Cache”.

[0003] Priority application

[0004] This application claims the benefit of priority to U.S. Application Serial No. 15 / 797,812, filed October 30, 2017, which is incorporated herein by reference in its entirety. Background Art

[0005] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are several different types of memory, including volatile memory and non-volatile memory.

[0006] Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), among others.

[0007] Non-volatile memory can retain stored data even when power is not supplied, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistance variable memory (such as phase-change random access memory (PCRAM)), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or 3D XPoint™ memory, etc.

[0008] Flash memory is used as non-volatile memory in a wide range of electronic applications. A flash memory device typically includes one or more groups of single-transistor, floating-gate, or charge-trapping memory cells that allow for high memory density, high reliability, and low power consumption.

[0009] Two common types of flash memory array architectures include the NAND and NOR architectures, named after the logical form in which their basic memory cell configurations are arranged. The memory cells of a memory array are typically arranged in a matrix. In one example, the gate of each floating gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a string of the array is coupled together in series, source-to-drain, between a source line and a bit line.

[0010] Both NOR and NAND architecture semiconductor memory arrays are accessed by activating a decoder of a specific memory cell by selecting a word line coupled to the gate of the specific memory cell. In a NOR architecture semiconductor memory array, once activated, the selected memory cell can place its data value on the bit line, causing different currents to flow depending on the state of the programmed specific cell. In a NAND architecture semiconductor memory array, a high bias voltage is applied to the drain-side select gate (SGD) line. The word line coupled to the gates of the unselected memory cells of each group is driven with a specified pass voltage (e.g., Vpass) to operate the unselected memory cells of each group as pass transistors (e.g., pass current in a manner unrestricted by the data value stored in them). Current then flows from the source line to the bit line through each series-coupled group, limited only by the selected memory cells of each group, to place the current-encoded data value of the selected memory cell on the bit line.

[0011] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be individually or collectively programmed to one or more programming states. For example, a single-level cell (SLC) can represent one of two programming states (e.g., 1 or 0) (representing one data bit).

[0012] However, flash memory cells can also represent one of more than two programmed states, allowing for the fabrication of higher density memories without increasing the number of memory cells, since each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In certain examples, an MLC may refer to a memory cell that can store two bits of data per cell (e.g., one of four programmed states), a three-level cell (TLC) may refer to a memory cell that can store three bits of data per cell (e.g., one of eight programmed states), and a four-level cell (QLC) may store four bits of data per cell. MLC is used herein in its broader context to refer to any memory cell that can store more than one bit of data per cell (i.e., can represent more than two programmed states).

[0013] Conventional memory arrays are two-dimensional (2D) structures arranged on the surface of a semiconductor. To increase memory capacity for a given area and reduce costs, the size of individual memory cells has been reduced. However, there are technical limitations to reducing the size of individual memory cells, and therefore the memory density of 2D memory arrays. In response, three-dimensional (3D) memory structures, such as 3D NAND architecture semiconductor memory devices, are being developed to further increase memory density and reduce memory costs.

[0014] Such 3D NAND devices typically include a string of memory cells coupled in series (e.g., drain-to-source) between one or more source-side select gates (SGS) near the source and one or more drain-side select gates (SGD) near the bit lines. In some examples, the SGS or SGD may include one or more field-effect transistors (FETs) or metal-oxide-semiconductor (MOS) structure devices, among others. In some examples, the string will extend vertically through multiple vertical spacer layers containing corresponding word lines. A semiconductor structure (e.g., a polysilicon structure) may extend adjacent to a string of memory cells to form a channel for the memory cells of the string. In the example of a vertical string, the polysilicon structure may be in the form of a vertically extending column. In some examples, the string may be "folded" and thus arranged relative to a U-shaped column. In other examples, multiple vertical structures may be stacked on top of each other to form a stacked array of memory cell strings.

[0015] Memory arrays or devices can be combined together to form the storage volume of a memory system, such as a solid-state drive (SSD), universal flash storage (UFS), or a storage medium. TM ) devices, Multimedia Card (MMC) solid-state storage devices, embedded MMC devices (eMMC TM ), etc. SSDs are particularly useful as primary storage devices for computers, having advantages over traditional hard drives with moving parts in terms of, for example, performance, size, weight, durability, operating temperature range, and power consumption. For example, SSDs may have reduced seek times, latency, or other delays (e.g., electromechanical delays, etc.) associated with magnetic disk drives. SSDs use non-volatile memory cells (e.g., flash memory cells) to eliminate the need for an internal battery supply, thereby allowing the drives to be more versatile and compact.

[0016] An SSD may include several memory devices (including several dies or logical units (e.g., logical unit numbers or LUNs)) and may include one or more processors or other controllers that perform the logic functions required to operate the memory devices or interface with external systems. Such an SSD may include one or more flash memory dies, including several memory arrays and peripheral circuitry thereon. The flash memory arrays may include several blocks of memory cells organized into several physical pages. In many examples, the SSD will also include DRAM or SRAM (or other forms of memory dies or other memory structures). The SSD may receive commands from the host associated with memory operations, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory device and the host, or erase operations to erase data from the memory device. Summary of the Invention

[0017] The present application relates to a method performed by a controller of a NAND memory device, the controller in communication with a volatile memory, the method comprising: determining a command queue depth of the NAND memory device; determining that the command queue depth exceeds a determined threshold number of commands and a ratio of read commands to write commands exceeds a determined threshold ratio; in response to determining that the command queue depth exceeds the determined threshold number of commands and the ratio of read commands to write commands exceeds the determined threshold ratio, reallocating an amount of volatile memory allocated to a donor memory location to a logical-to-physical L2P cache; and storing additional L2P table entries in the L2P cache in a region of the volatile memory previously allocated to the donor memory location and now allocated to the L2P cache as a result of increasing the L2P cache. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate the various embodiments discussed in this document by way of example and not by way of limitation.

[0019] Figure 1 An example of an environment including a memory device is described.

[0020] Figures 2 to 3 A schematic diagram illustrating an example of a 3D NAND architecture semiconductor memory array.

[0021] Figure 4 An example block diagram illustrating a memory module.

[0022] Figure 5 L2P cache resizing according to some examples of the present invention is described.

[0023] Figure 6 A flowchart showing a method of adjusting L2P cache size based on operating conditions according to some examples of the present invention is shown.

[0024] Figure 7 A schematic diagram showing a memory controller according to some examples of the present invention is shown.

[0025] Figure 8 is a block diagram illustrating an example of a machine upon which one or more embodiments may be implemented. DETAILED DESCRIPTION

[0026] In some examples, methods, systems, and machine-readable media are disclosed for dynamically adjusting the size of an L2P cache in a memory device in response to observed operating conditions. The L2P cache can reallocate memory space from donor memory locations (e.g., a read buffer, a write buffer, or both). For example, if the system observes a high volume of read requests, the system can increase the size of the L2P cache at the expense of the write buffer (which can be reduced). Thus, volatile memory assigned by firmware to the write buffer (or read buffer) can be reallocated to the L2P cache instead. Similarly, if the system observes a high volume of write requests, the system can increase the size of the L2P cache at the expense of the read buffer (which can be reduced). In some examples, the increase can be temporary, and the L2P cache can return to its normal size in response to changing operating conditions. By increasing the size of the L2P cache, a NAND device can increase the probability of a cache hit and improve performance.

[0027] Electronic devices, such as mobile electronic devices (e.g., smart phones, tablet computers, etc.), electronic devices used in automotive applications (e.g., automotive sensors, control components, driver assistance systems, passenger safety or comfort systems, etc.), and Internet-connected devices or devices (e.g., Internet of Things (IoT) devices, etc.) have varying storage requirements depending, among other things, on the type of electronic device, usage environment, performance expectations, etc.

[0028] An electronic device can be divided into several major components: a processor (e.g., a central processing unit (CPU) or other main processor); a memory (e.g., one or more volatile or non-volatile random access memory (RAM) memory devices, such as dynamic RAM (DRAM), mobile or low-power double data rate synchronous DRAM (DDR SDRAM), etc.); and a storage device (e.g., a non-volatile memory (NVM) device, such as flash memory, read-only memory (ROM), SSD, MMC, or other memory card structure or assembly, etc.). In some examples, an electronic device may include a user interface (e.g., a display, a touch screen, a keyboard, one or more buttons, etc.), a graphics processing unit (GPU), power management circuitry, a baseband processor, or one or more transceiver circuits, etc.

[0029] Figure 1An example of an environment 100 is described that includes a host device 105 and a memory device 110 configured to communicate via a communication interface. The host device 105 or the memory device 110 can be included in various products 150, such as Internet of Things (IoT) devices (e.g., refrigerators or other appliances, sensors, engines or actuators, mobile communication devices, cars, drones, etc.) to support processing, communication, or control of the product 150.

[0030] Memory device 110 includes a memory controller 115 and a memory array 120 that, for example, includes several individual memory dies (e.g., a stack of three-dimensional (3D) NAND dies). In 3D architecture semiconductor memory technology, vertical structures are stacked, thereby increasing the number of levels, physical pages, and correspondingly increasing the density of memory devices (e.g., storage devices). In one example, memory device 110 may be a discrete memory or storage device component of host device 105. In other examples, memory device 110 may be part of an integrated circuit (e.g., a system on a chip (SOC)) that is stacked or otherwise included with one or more other components of host device 105.

[0031] One or more communication interfaces may be used to transfer data between the memory device 110 and one or more other components of the host device 105, such as a Serial Advanced Attachment Technology (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC™ interface, or one or more other connectors or interfaces. The host device 105 may include a host system, an electronic device, a processor, a memory card reader, or one or more other electronic devices external to the memory device 110. In some examples, the host 105 may be a host computer with a reference Figure 8 The machine 800 may include some or all of the components discussed above.

[0032] The memory controller 115 may receive instructions from the host 105 and may communicate with the memory array, for example, to transfer (e.g., write or erase) data to or from (e.g., read) data in one or more of the memory cells, planes, sub-blocks, blocks, or pages of the memory array. The memory controller 115 may include, among other things, circuitry or firmware (including one or more components or integrated circuits). For example, the memory controller 115 may include one or more memory control components, circuits, or elements configured to control access across the memory array 120 and provide a translation layer between the host 105 and the memory device 110. The memory controller 115 may include one or more input / output (I / O) circuits, lines, or interfaces to transfer data to or from the memory array 120. The memory controller 115 may include a memory manager 125 and an array controller 135.

[0033] The memory manager 125 may include, among other things, circuitry or firmware, such as several components or integrated circuits associated with various memory management functions. For purposes of this description, example memory operation and management functions will be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operation or management functions. Such NAND management functions include wear leveling (e.g., garbage collection or recycling), error detection or correction, block retirement, or one or more other memory management functions. The memory manager 125 may parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with the operation of a memory array, etc.), or generate device commands for the array controller 135 or one or more other components of the memory device 110 (e.g., to perform various memory management functions).

[0034] The memory manager 125 may include a set of management tables 130 configured to maintain various information associated with one or more components of the memory device 110 (e.g., various information associated with a memory array or one or more memory cells coupled to the memory controller 115). For example, the management tables 130 may include information about the block age, block erase count, error history, or one or more error counts (e.g., a write operation error count, a read bit error count, a read operation error count, an erase error count, etc.) of one or more blocks of memory cells coupled to the memory controller 115. In some examples, a bit error may be referred to as an uncorrectable bit error if the number of detected errors in one or more of the error counts is above a threshold. The management tables 130 may, in particular, maintain counts of correctable or uncorrectable bit errors.

[0035] The array controller 135 may include, among other things, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory operations may be based on host commands received, for example, from the host 105 or generated internally by the memory manager 125 (e.g., associated with wear leveling, error detection or correction, etc.).

[0036] The array controller 135 may include an error correction code (ECC) component 140, which may include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of a memory device 110 coupled to the memory controller 115. The memory controller 115 may be configured to actively detect and recover from error occurrences (e.g., bit errors, operational errors, etc.) associated with various operations or storage of data while maintaining the integrity of data transferred between the host 105 and the memory device 110, or maintaining the integrity of stored data (e.g., using redundant RAID storage, etc.), and may remove (e.g., retire) failed memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.

[0037] Memory array 120 may include a number of memory cells arranged into, for example, a number of devices, planes, sub-blocks, blocks, or pages. As one example, a 48GB TLC NAND memory device may include 18,592 data bytes (B) per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32GB MLC memory device (storing two data bits per cell (i.e., 4 programmable states)) may include 18,592 data bytes (B) per page (16,384 + 2208 bytes), 1024 pages per block, 548 blocks per plane, and 4 planes per device, but with half the required write time and twice the program / erase (P / E) cycles of a corresponding TLC memory device. Other examples may include other numbers or arrangements. In some examples, a memory device, or a portion thereof, can selectively operate in an SLC mode or in a desired MLC mode (eg, TLC, QLC, etc.).

[0038] In operation, data is typically written to or read from the NAND memory device 110 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) can be performed on larger or smaller groups of memory cells as needed. The data transfer size of the NAND memory device 110 is typically referred to as a page, while the data transfer size of the host is typically referred to as a sector.

[0039] Although a data page may include several bytes of user data (e.g., a data payload including several data sectors) and its corresponding metadata, the size of the page generally refers only to the number of bytes used to store the user data. As an example, a data page with a 4KB page size may include 4KB of user data (e.g., 8 sectors exhibiting a 512B sector size) and several bytes (e.g., 32B, 54B, 224B, etc.) of metadata corresponding to the user data, such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0040] Different types of memory cells or memory arrays 120 may provide different page sizes or may require different amounts of metadata associated therewith. For example, different memory device types may have different bit error rates, which may result in different amounts of metadata required to ensure the integrity of the page data (e.g., a memory device with a higher bit error rate may require more bytes of error correction code data than a memory device with a lower bit error rate). As an example, a multi-level cell (MLC) NAND flash device may have a higher bit error rate than a corresponding single-level cell (SLC) NAND flash device. Thus, an MLC device may require more bytes of metadata for error data than a corresponding SLC device.

[0041] Figure 2 The illustration includes organization into blocks (e.g., block A 201A, block B 201B, etc.) and sub-blocks (e.g., sub-block A0 201A0, sub-block A n 201A n , sub-block B0 201B0, sub-block B n 201B n etc.) of the number string memory cells (eg, the first to third A0 memory strings 205A0 to 207A0, the first to third A n Memory string 205A n To 207A n , first to third B0 memory strings 205B0 to 207B0, first to third B n Memory string 205B n To 207B nMemory array 200 represents a portion of a larger number of similar structures that would typically be found in a block, device, or other component of a memory device.

[0042] Each memory cell string includes a source line (SRC) 235 or a source side select gate (SGS) (eg, first to third A0 SGS 231A0 to 233A0, first to third A0 SGS 231A0 to 233A0, and second to third A0 SGS 231A0 to 233A0) stacked from source to drain along the Z direction. n SGS 231A n To 233A n 、First to third B0 SGS 231B0 to 233B0、First to third B n SGS 231B n To 233B n , etc.) and the drain side select gate (SGD) (eg, first to third A0 SGD 226A0 to 228A0, first to third A n SGD 226A n To 228A n , 1st to 3rd B0 SGD 226B0 to 228B0, 1st to 3rd B n SGD 226B n To 228B n Each string of memory cells in a 3D memory array may be arranged as a data line (e.g., bit lines (BL) BL0 through BL2 220 through 222) along the X direction and as a physical page along the Y direction.

[0043] Within a physical page, each level represents a row of memory cells, and each string of memory cells represents a column. A sub-block can represent one or more physical pages. A block can include a number of sub-blocks (or physical pages) (e.g., 128, 256, 384, etc.). Although illustrated herein as having two blocks, each with two sub-blocks, each sub-block having a single physical page, each physical page having three strings of memory cells, and each string having eight levels of memory cells, in other examples, memory array 200 can include more or fewer blocks, sub-blocks, physical pages, strings of memory cells, memory cells, or levels. For example, each string of memory cells can include more or fewer levels (e.g., 16, 32, 64, 128, etc.), as desired, as well as one or more additional levels of semiconductor material above or below the charge storage transistors (e.g., select gates, data lines, etc.). As an example, a 48GB TLC NAND memory device can include 18,592 bytes of data (B) per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device.

[0044] Each memory cell in the memory array 200 includes a control gate (CG) coupled to (e.g., electrically connected to or otherwise operably connected to) an access line (e.g., word lines (WL) WL00 through WL70 210A through 217A, WL01 through WL71 210B through 217B, etc.), which optionally couples the control gates (CG) across a particular tier or portion of a tier in common. A particular tier in the 3D memory array, and correspondingly, a particular memory cell in a string, can be accessed or controlled using a corresponding access line. Groups of select gates can be accessed using various select lines. For example, the first through third A0 SGDs 226A0 through 228A0 can be accessed using A0 SGD line SGDA0 225A0, and the first through third A0 SGDs 226A0 through 228A0 can be accessed using A0 SGD line SGDA0 225A0. n SGD 226A n To 228A n A n SGD Line SGDA n 225A n The first to third B0 SGD 226B0 to 228B0 can be accessed using the B0 SGD line SGDB0 225B0, and the first to third B n SGD 226B n To 228B n Can use B n SGD line SGDB n 225B n Access. First to third A0 SGS 231A0 to 233A0 and first to third A n SGS 231A nTo 233A n The gate select line SGS0 230A can be used to access the first to third B0 SGS231B0 to 233B0 and the first to third B n SGS 231B n To 233B n Access is possible using gate select line SGS1 230B.

[0045] In an example, the memory array 200 may include several levels of semiconductor material (e.g., polysilicon, etc.) configured to couple the control gate (CG) or select gate (or a portion of the CG or select gate) of each memory cell of a corresponding level of the array. A particular string of memory cells in the array may be accessed, selected, or controlled using a combination of bit lines (BLs) and select gates, etc., and particular memory cells at one or more levels in the particular string may be accessed, selected, or controlled using one or more access lines (e.g., word lines).

[0046] Figure 3 An example schematic diagram illustrating a portion of a NAND architecture semiconductor memory array 300 including a plurality of memory cells 302 and sense amplifiers or devices 360 arranged in a two-dimensional array of strings (e.g., first through third strings 305-307) and levels (e.g., illustrated as respective word lines (WLs) WL0-WL7 310-317, drain side select gate (SGD) lines 325, source side select gate (SGS) lines 330, etc.). For example, the memory array 300 may illustrate, for example, Figure 2 Schematic diagram of an example of a portion of one physical page of memory cells of a 3D NAND architecture semiconductor memory device illustrated in FIG.

[0047] Each memory cell string is coupled to a source line (SRC) using a respective source-side select gate (SGS) (e.g., first to third SGS 331 to 333) and to a respective data line (e.g., first to third bit lines (BL) BL0 to BL2 320 to 322) using a respective drain-side select gate (SGD) (e.g., first to third SGD 326 to 328). Figure 3 The example of is illustrated as having eight levels (eg, using word lines (WL) WL0 through WL7 310-317) and three data lines (BL0 through BL2 320-322), but other examples may include strings of memory cells with more or fewer levels or data lines as desired.

[0048] In a NAND architecture semiconductor memory array (such as example memory array 300), the state of a selected memory cell 302 can be accessed by sensing a change in current or voltage associated with a particular data line containing the selected memory cell. Memory array 300 can be accessed (e.g., by control circuitry, one or more processors, digital logic, etc.) using one or more drivers. In one example, the one or more drivers can activate a particular memory cell or set of memory cells by driving a particular potential to one or more data lines (e.g., bit lines BL0 to BL2), access lines (e.g., word lines WL0 to WL7), or select gates, depending on the type of operation that needs to be performed on the particular memory cell or set of memory cells.

[0049] To program or write data to a memory cell, a programming voltage (Vpgm) (e.g., one or more programming pulses) may be applied to a selected word line (e.g., WL4) and, therefore, to the control gates of each memory cell coupled to the selected word line (e.g., the first to third control gates (CG) 341 to 343 of the memory cells coupled to WL4). The programming pulses may, for example, begin at or near 15V and, in some instances, increase in magnitude during each application of the programming pulses. When the programming voltage is applied to the selected word line, a potential (e.g., ground potential (e.g., Vss)) may be applied to the data line (e.g., bit line) and the substrate (and, therefore, the channel between the source and drain) of the memory cell designated for programming, resulting in charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the channel to the floating gate of the designated memory cell.

[0050] In contrast, a pass voltage (Vpass) can be applied to one or more word lines having memory cells not designated for programming, or an inhibit voltage (e.g., Vcc) can be applied to data lines (e.g., bit lines) having memory cells not designated for programming, for example, to inhibit charge transfer from the channel to the floating gates of such undesignated memory cells. The pass voltage can vary, for example, depending on the proximity of the applied pass voltage to the word lines designated for programming. The inhibit voltage can include a supply voltage (Vcc) relative to a ground potential (e.g., Vss), such as a voltage from an external source or supply (e.g., a battery, an AC-to-DC converter, etc.).

[0051] As an example, if a programming voltage (e.g., 15V or greater) is applied to a particular word line (e.g., WL4), a pass voltage of 10V may be applied to one or more other word lines (e.g., WL3, WL5, etc.) to inhibit programming of non-calibrated memory cells or to preserve the values ​​stored on such memory cells that have not been calibrated for programming. As the distance between the applied programming voltage and the non-calibrated memory cells increases, the pass voltage required to inhibit programming of the non-calibrated memory cells may decrease. For example, if a programming voltage of 15V is applied to WL4, a pass voltage of 10V may be applied to WL3 and WL5, a pass voltage of 8V may be applied to WL2 and WL6, a pass voltage of 7V may be applied to WL1 and WL7, and so on. In other examples, the pass voltages, the number of word lines, etc. may be higher or lower, or more or fewer.

[0052] A sense amplifier 360 coupled to one or more of the data lines, such as the first, second, or third bit lines (BL0-BL2) 320-322, can detect the state of each memory cell in the respective data line by sensing the voltage or current on the particular data line.

[0053] Between applying one or more programming pulses (e.g., Vpgm), a verify operation can be performed to determine whether the selected memory cell has reached its intended programming state. If the selected memory cell has reached its intended programming state, it can be inhibited from further programming. If the selected memory cell has not yet reached its intended programming state, additional programming pulses can be applied. If the selected memory cell does not reach its intended programming state after a certain number (e.g., a maximum number) of programming pulses, the selected memory cell or the string, block, or page associated with the selected memory cell can be marked as defective.

[0054] To erase a memory cell or a group of memory cells (e.g., erasure is typically performed in blocks or sub-blocks), an erase voltage (Vers) (e.g., typically Vpgm) may be applied to the substrate (and therefore the channel between the source and drain) of the memory cells designated for erasure (e.g., using one or more bit lines, select gates, etc.), while the word lines of the designated memory cells are held at a potential (e.g., ground potential (e.g., Vss)), thereby causing charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the floating gates of the designated memory cells to the channel.

[0055] Figure 4An example block diagram illustrating a memory device 400 including a memory array 402 having a plurality of memory cells 404 and one or more circuits or components to provide communication with or perform one or more memory operations on the memory array 402. The memory device 400 may include a row decoder 412, a column decoder 414, sense amplifiers 420, a page buffer 422, a selector 424, input / output (I / O) circuitry 426, and a memory control unit 430.

[0056] The memory cells 404 of the memory array 402 may be arranged into blocks (e.g., a first block 402A and a second block 402B). Each block may include sub-blocks. For example, the first block 402A may include a first sub-block 402A0 and a second sub-block 402A n , and the second block 402B may include a first sub-block 402B0 and a second sub-block 402B n Each sub-block may include a number of physical pages, each page including a number of memory cells 404. Although illustrated herein as having two blocks, each block having two sub-blocks, and each sub-block having a number of memory cells 404, in other examples, the memory array 402 may include more or fewer blocks, sub-blocks, memory cells, etc. In other examples, the memory cells 404 may be arranged into a number of rows, columns, pages, sub-blocks, blocks, etc., and accessed using, for example, an access line 406, a first data line 410, or one or more select gates, source lines, etc.

[0057] The memory control unit 430 may control the memory operations of the memory device 400 according to one or more signals or instructions received on the control line 432 (e.g., including one or more clock signals or control signals indicating a desired operation (e.g., write, read, erase, etc.)) or address signals (A0 to AX) received on one or more address lines 416. One or more devices external to the memory device 400 may control the value of the control signal on the control line 432 or the address signal on the address line 416. Examples of devices external to the memory device 400 may include, but are not limited to, Figure 4 A host, memory controller, processor, or one or more circuits or components not described in the specification.

[0058] The memory device 400 may use access lines 406 and first data lines 410 to transfer (e.g., write or erase) data to or from (e.g., read) one or more of the memory cells 404. Row decoders 412 and column decoders 414 may receive and decode address signals (A0 through AX) from address lines 416, may determine which memory cell 404 should be accessed, and may provide signals to one or more of the access lines 406 (e.g., one or more of the plurality of word lines (WL0 through WLm)) or first data lines 410 (e.g., one or more of the plurality of bit lines (BL0 through BLn)) described above.

[0059] The memory device 400 may include sensing circuitry (e.g., sense amplifiers 420) configured to determine the value of data on a memory cell 404 (e.g., read) or determine the value of data written to the memory cell 404 using the first data line 410. For example, in a selected string of memory cells 404, one or more of the sense amplifiers 420 may read the logic level in the selected memory cell 404 in response to a read current flowing through the selected string in the memory array 402 to the data line 410.

[0060] One or more devices external to memory device 400 can communicate with memory device 400 using I / O lines (DQ0 to DQN) 408, address lines 416 (A0 to AX), or control lines 432. Input / output (I / O) circuitry 426 can use I / O lines 408 to transfer data values ​​into or out of memory device 400 (e.g., into or out of page buffer 422 or memory array 402) in accordance with, for example, control lines 432 and address lines 416. Page buffer 422 can store data received from one or more devices external to memory device 400 before the data is programmed into the relevant portion of memory array 402, or can store data read from memory array 402 before the data is transmitted to one or more devices external to memory device 400.

[0061] The column decoder 414 can receive the address signals (A0 to AX) and decode them into one or more column select signals (CSEL1 to CSELn). A selector 424 (e.g., a selection circuit) can receive the column select signals (CSEL1 to CSELn) and select data in the page buffer 422 representing the value of the data to be read from or programmed into the memory cell 404. The selected data can be transferred between the page buffer 422 and the I / O circuit 426 using the second data line 418.

[0062] The memory control unit 430 may receive positive and negative supply signals, such as a supply voltage (Vcc) 434 and a negative supply source (Vss) 436 (e.g., ground potential), from an external source or supply (e.g., an internal or external battery, an AC-to-DC converter, etc.). In some examples, the memory control unit 430 may include a regulator 428 that internally provides the positive or negative supply signals.

[0063] Host software wishing to read, write, or erase data from a memory device issues a command specifying one or more logical block addresses (LBAs) addressing one or more memory locations (e.g., memory pages) for the read, write, or erase. In contrast to magnetic memory, in NAND devices, these do not correspond to actual physical locations in the memory device. Instead, the NAND uses a logical-to-physical (L2P) table to map these LBAs to one or more physical pages of NAND memory cells. The reason for this mapping is that the NAND cannot modify values ​​in the NAND; that is, it must erase the value and then write a new value. Complicating this is that the NAND can only erase a block of memory (which has many pages) at a time. If a delete or modify request is for less than one block of memory, then to satisfy the request and preserve the data that should not be erased, the NAND must move all valid pages to another block and then erase the old block (a process known as garbage collection). This solution is slow and also shortens the lifespan of the NAND, as NAND memory cells have only a limited number of program and erase cycles before they can no longer hold a charge.

[0064] Thus, upon receiving a delete request or a request to modify a value in memory, the NAND simply marks the old location as invalid and, in the case of a modification, writes the new value to a new physical location (one or more pages) on the memory device. For a modification request, the NAND then updates its mapping of the LBA to the new physical location so that subsequent requests involving that LBA point to the correct physical location.

[0065] Finally, the NAND frees up the previously marked invalid pages to maintain the advertised storage level. As previously mentioned, NAND erases only blocks of data at a time. Therefore, the NAND device first performs a garbage collection, which copies the data from the valid pages of the block to be erased to new pages in other blocks. Once the data has been copied, the pages of the block to be erased can be marked as invalid and the block can be erased.

[0066] The L2P table used to map logical addresses to physical addresses takes up a lot of memory resources. For example, a NAND with 2 gigabytes (GB) of memory may have a 2 megabyte (MB) L2P table, and a 128GB NAND may be mapped with a 128MB L2P table. A NAND memory device may have a controller (e.g., a CPU) that has internal memory that can be divided into multiple memory banks (e.g., 1MB to 2MB). One memory bank is tightly coupled to the processor and accessed in a single clock cycle. This tightly coupled RAM may be approximately 256K bytes and stores firmware and data used by the firmware. Other memory banks (referred to as multi-bank SRAM configuration MRAM) are slower to access. MRAM is typically 1 to 2 megabytes and slower than tightly coupled memory.

[0067] As can be appreciated, the L2P table does not fit neatly into tightly coupled memory or MRAM. While NAND memory devices can increase the amount of tightly coupled memory or MRAM, this increases complexity, size, and cost. Another approach is to have an area of ​​MRAM (or, in some instances, tightly coupled memory) that serves as a cache for the L2P table. This cache may indicate the physical addresses of the most frequently or recently accessed logical blocks. Requests from the host for logical addresses in the cache are serviced using the cache. If the L2P cache does not contain the physical address for a given logical address, the NAND device must load that portion of the L2P table from the NAND. This is called a cache miss and increases the amount of time it takes the NAND to service a request. The problem with caches is that they are relatively small, ranging in size from approximately 32K bytes to 128K bytes. A cache miss converts a host operation into two NAND operations: one to retrieve the L2P information needed to service the host request and a second to actually service the request. Therefore, techniques that increase the number of cache hits have a measurable effect on performance.

[0068] In some examples, methods, systems, and machine-readable media are disclosed for dynamically adjusting the size of an L2P cache in a memory device in response to observed NAND operating conditions. The L2P cache can borrow memory space from donor memory locations, such as a read buffer or a write buffer. For example, if the system observes a high number of read requests, the system can increase the size of the L2P cache at the expense of the write buffer (which can be reduced). Similarly, if the system observes a high number of write requests, the system can increase the size of the L2P cache at the expense of the read buffer (which can be reduced). In some examples, the increase can be temporary, and the L2P cache can return to its normal size in response to changing operating conditions, for example, in response to a lack of conditions that would have prompted the increase. By increasing the size of the L2P cache, a NAND device can increase the probability of a cache hit and reduce the probability that a single NAND operation will require a second NAND operation to load L2P table information from the NAND.

[0069] In some examples, an L2P cache profile may specify cache behavior based on one or more NAND operating conditions. For example, the L2P cache profile may include one or more rules that describe under what operating conditions the cache is increased from a default size, decreased back to the default size, the amount of change, the speed at which the size change occurs, and from which other memory location (e.g., read, write, or other buffer) used for the L2P cache is changed. For example, one or more rules in the L2P cache profile may specify when the cache size is increased from the default size and when the cache size is returned to the default size.

[0070] The L2P cache profile may be static, i.e., it may be loaded onto the NAND at manufacturing time and persist (as a data structure on the NAND or volatile operating memory). In other examples, a default L2P cache profile may be loaded onto the NAND at manufacturing time but may be modified later (e.g., by the NAND's firmware, the host device's operating system (e.g., by sending changes through a host interface such as UFS), etc.). In some examples, the rules of the L2P cache profile may be instantiated as part of firmware instructions.

[0071] Example operating conditions that may trigger a change in L2P cache size may include one or more of the following: host command queue depth size, types of commands in the queue (e.g., read, write, erase, and other commands), ratios between different types of commands in the queue (e.g., read / write ratio, write / read ratio), L2P cache hit percentage, L2P cache miss percentage, etc. A rule may have the following form: if [operating condition] [greater than, equal to, less than] [determined value] then [increase / decrease] L2P cache by [amount] from the [write or read] buffer.

[0072] In some examples, cache increases are performed immediately, i.e., data in donor memory can be immediately allocated to the L2P cache. In other examples, the system can wait until donor memory (e.g., write and / or read buffers) is empty before performing an L2P cache increase. In still other examples, the NAND can be accelerated in an effort to free up donor memory. In still other examples, the L2P cache can be increased gradually over time. For example, at time t, the L2P cache can be increased by X KB, and at time t+1, it can be increased by another X KB (for a total increase of 2X KB over time t-1).

[0073] As an example, an L2P cache rule in a configuration file may be: when the queue depth exceeds 5 commands (where the majority (e.g., a read / write ratio of greater than 50%) of the commands are read commands), increase the L2P cache by 10%, up to 25%, for each read command within the 5 commands by borrowing space from the write buffer. Another cache increase rule may be: when the queue depth exceeds 5 commands (where the majority of the commands are read commands), increase the L2P cache by 10%, up to 25%, for each command within the 5 commands by borrowing space from both the read buffer and the write buffer in a ratio based on the ratio of read commands to write commands in the queue. Yet another example rule may be: if the L2P cache hit percentage is less than a predetermined value, increase the L2P cache by taking space from either the read buffer or the write buffer.

[0074] Multiple rules can be defined and can be stacked, i.e., if the operating conditions satisfy one or more increase rules, then the cache can be increased for both of those rules. This can be the case if the operating conditions are such that multiple rules can be triggered. For example, given an L2P cache profile with the following rules:

[0075] Queue depth exceeds 5 commands, where the majority (e.g., more than 50% read / write ratio) of the commands are read commands, increase the L2P cache by 10% for each read command within the 5 commands, up to a maximum of 25% by borrowing space from the write buffer;

[0076] If the L2P cache hit % is less than a predetermined value, then increase the L2P cache by occupying from the read buffer;

[0077] If the NAND queue depth exceeds 5 commands and more than 50% of the commands in the queue buffer are read commands, the L2P cache can be increased at the expense of the write buffer. Meanwhile, if the L2P cache hit percentage is less than a predetermined value, the L2P cache can be further increased. Similarly, rules can partially or completely offset each other, for example, if operating conditions are such that one rule indicates an increase in the L2P cache and another rule indicates a decrease in the L2P cache. In this case, the L2P cache can increase or decrease in size (which is the sum of the rules). A rule can even cause the L2P cache to decrease below the default size (at least temporarily).

[0078] The donor memory location may include a read buffer for buffering host read commands, a write buffer for buffering write data from the host, etc. A donor memory location may be any memory location of non-volatile memory that has not been allocated for use as an L2P cache.

[0079] Cache size rules can be defined that limit the amount taken from each donor memory location, for example, to prevent the L2P cache from taking too much memory from the read or write buffers, thereby degrading performance. In some examples, the rules can specify that if the donor memory buffer utilization % is above a predetermined threshold percentage, some or all of any memory loaned to the L2P cache will be returned. In certain examples, this prevents the L2P cache from transferring memory from the read / write buffers and degrading performance.

[0080] As mentioned, L2P cache rules can also specify under what circumstances the L2P cache can revert to a default size. An example rule can specify that once the queue depth returns to a level below a predetermined threshold, the L2P cache can revert to the default value. In other examples, an example rule can specify that a reduction can occur over time. That is, the initial L2P cache increase can decay over time until the L2P cache returns to its default size.

[0081] In some examples, L2P cache increases or decreases (e.g., reallocations) can be accomplished simply by moving pointers marking the boundaries of the L2P cache and donor memory locations (e.g., read buffers or write buffers). Because write commands change the logical-to-physical mapping, these changes can be stored in an update list in a memory location distinct from the L2P cache. That is, a host write can first check the L2P table for the L2P mapping, then check the update list to see if the L2P mapping has been updated. As a result, L2P cache entries can always be "clean," i.e., unmodified. Consequently, when an L2P cache entry is evicted due to a "snapback" of L2P cache size, the entry is not lost but remains on the NAND or in the update list.

[0082] Figure 5 L2P cache resizing according to some examples of the present invention is described. Operational memory 530 may be non-volatile memory (e.g., SRAM, DDR RAM, etc.) that can store data structures, code, variables, etc. for the controller. Operational memory 530 may be tightly coupled, MRAM, etc. Operational memory 530 may store one or more data structures, such as a read buffer 532, an L2P cache 534, a write buffer 536, and other structures, code, command queues, etc. (other items not shown for clarity). Read buffer 532 may be used to store one or more pages read from memory until the host is ready to consume them. Write buffer 536 may be used by the host to write data to a NAND. The NAND may buffer data before it is written to the NAND. L2P cache 534 is at a first size at time 510. An operational condition may be detected, and operational memory 530 may be reconfigured 517 such that L2P cache 534 increases in size at the expense of read buffer 532, as shown at 515. In other examples, the write buffer 536 may be reduced to accommodate the larger size of the L2P cache 534. In still other examples, both the read buffer 532 and the write buffer 536 may be reduced to accommodate the L2P cache 534.

[0083] Now go to Figure 6, a flowchart of a method 600 for adjusting the L2P cache size based on operating conditions according to some examples of the present invention is shown. At operation 605, the controller may determine one or more operating conditions of the NAND. For example, the controller may determine one or more of each of the following, or a combination thereof: command queue depth, command type of commands in the queue (e.g., write vs. read vs. erase), cache statistics (e.g., cache hit or miss ratio), etc. At operation 610, the controller may determine whether the L2P cache should be adjusted based on the operating characteristics. For example, one or more rules based on a cache profile may be used to determine whether the L2P cache should be increased or decreased based on the one or more operating conditions. If the cache is not to be adjusted, the system may return to operation 605. For example, an operating condition may be determined and the rules may be checked later, another operating condition may be determined and whether the operating condition indicates a change in the L2P cache size, etc. If the L2P cache is to be adjusted, the L2P cache may be resized at operation 620, for example, by reducing the size of the donor memory region of the operating memory. In other examples, the size of the L2P cache may be reduced by returning the donor memory.The memory region to be increased or decreased may be specified by a cache rule of a cache profile.

[0084] Figure 7 A schematic diagram of a memory controller 115 is shown according to some embodiments of the present invention. Figure 1 In addition to the components shown in FIG. 1 , in some examples, the memory controller 115 may also have additional components. For example, the controller 135 may include an L2P cache manager 750, which may manage the size of the L2P cache, manage entries in the L2P cache of the L2P table, etc. For example, the L2P cache manager 750 may execute Figure 6 , to increase or decrease the size of the L2P cache based on one or more NAND operating conditions. The L2P cache, read buffer, and write buffer may be stored in the operating memory 745. For example, the operating memory 745 may be an embodiment of the operating memory 530. The operating memory 745 may be a volatile memory that stores code, buffers, L2P cache, machine-readable firmware instructions, etc. The operating memory 745 may be tightly coupled or MRAM.

[0085] Figure 8A block diagram illustrates an example machine 800 on which any one or more of the techniques (e.g., methodologies) discussed herein may be performed. In alternative embodiments, the machine 800 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 800 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, the machine 800 may function as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 800 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, an IoT device, an automotive system, or any machine capable of executing (sequentially or otherwise) instructions specifying actions to be taken by the machine. Furthermore, while a single machine is illustrated, the term "machine" shall also be construed to include any collection of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methodologies discussed herein (e.g., cloud computing, software as a service (SaaS), or other computer cluster configurations).

[0086] As described herein, examples may include or be operable through logic, components, devices, packages, or mechanisms. A circuit system is a collection of circuits (e.g., a group of circuits) implemented in a tangible entity comprising hardware (e.g., simple circuits, gates, logic, etc.). Circuit system membership can be flexible over time and with the variability of the underlying hardware. A circuit system includes components that, when in operation, can perform specific tasks individually or in combination. In an example, the hardware of a circuit system may be permanently designed to perform a specific operation (e.g., hard-wired). In an example, the hardware of a circuit system may include variably connected physical components (e.g., actuators, transistors, simple circuits, etc.) and a computer-readable medium that is physically modified (e.g., magnetic, electrical, removably positioned particles of constant mass, etc.) to encode instructions for the specific operation. In connecting the physical components, the underlying electrical properties of the hardware components change, for example, from insulators to conductors or vice versa. The instructions enable participating hardware (e.g., actuators or load mechanisms) to generate components of the circuit system in the hardware through variable connections to perform portions of a specific task in operation. Thus, when the device is operating, the computer-readable medium is communicatively coupled to other components of the circuit system. In an example, any one of the physical components can be used in more than one member of more than one circuit system. For example, during operation, an execution component can be used in a first circuit in a first circuit system at one point in time and reused at a different time by a second circuit in the first circuit system or by a third circuit in the second circuit system.

[0087] A machine (e.g., a computer system) 800 (e.g., host device 105, memory device 110, etc.) may include a hardware processor 802 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, such as memory controller 115, etc.), a main memory 804, and a static memory 806, some or all of which may communicate with each other via an interconnect (e.g., a bus) 808. The machine 800 may further include a display component 810, an alphanumeric input device 812 (e.g., a keyboard), and a user interface (UI) navigation device 814 (e.g., a mouse). In an example, the display component 810, the input device 812, and the UI navigation device 814 may be a touch screen display. The machine 800 may additionally include a storage device (e.g., a drive component) 821, a signal generating device 818 (e.g., a speaker), a network interface device 820, and one or more sensors 816 (e.g., a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors). The machine 800 may include an output controller 828, such as a serial (e.g., Universal Serial Bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection for communicating with or controlling one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0088] The storage device 821 may include a machine-readable medium 822 having stored thereon one or more sets of data structures or instructions 824 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 824 may also reside, completely or at least partially, within the main memory 804, within the static memory 806, or within the hardware processor 802 during execution of the instructions by the machine 800. In an example, one or any combination of the hardware processor 802, the main memory 804, the static memory 806, or the storage device 821 may constitute the machine-readable medium 822.

[0089] Although machine-readable medium 822 is illustrated as a single medium, the term “machine-readable medium” may include a single medium or multiple media (eg, a centralized or distributed database or associated caches and servers) configured to store one or more instructions 824 .

[0090] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions that are executed by the machine 800 and cause the machine 800 to perform any one or more of the techniques of the present invention, or capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory and optical and magnetic media. In an example, massed machine-readable media includes a plurality of particles having a constant (e.g., stationary) mass. Thus, massed machine-readable media is not a transitory propagating signal. Specific examples of massed machine-readable media may include: nonvolatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable magnetic disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0091] Instructions 824 (e.g., software, programs, operating systems (OS), etc.) or other data are stored on storage device 821 and can be accessed by memory 804 for use by processor 802. Memory 804 (e.g., DRAM) is typically fast but volatile, and therefore, unlike storage devices 821 (e.g., SSDs), storage devices 821 are suitable for long-term storage (including when powered off). Instructions 824 or data used by a user or machine 800 are typically loaded into memory 804 for use by processor 802. When memory 804 is full, virtual space from storage device 821 can be allocated to supplement memory 804. However, because storage device 821 is generally slower than memory 804, with write speeds typically at least half the read speed, using virtual memory can significantly reduce the user experience due to storage device latency (compared to memory 804, e.g., DRAM). Furthermore, using storage device 821 for virtual memory can significantly reduce the usable lifespan of storage device 821.

[0092] Compared to virtual memory, virtual memory compression (e.g. A kernel feature ("ZRAM") uses portions of memory as compressed block memory to avoid paging to storage 821. Paging occurs in compressed blocks until the data must be written to storage 821. Virtual memory compression increases the available size of memory 804 while reducing wear on storage 821.

[0093] Storage devices optimized for mobile electronic devices or mobile storage typically include MMC solid-state storage devices (e.g., micro Secure Digital (microSD) TM) card, etc.). An MMC device includes several parallel interfaces (e.g., 8-bit parallel interfaces) with a host device and is typically a component that can be removed and separated from the host device. In contrast, an eMMC TM The device is attached to the circuit board and is considered a component of the host device with features comparable to those based on Serial ATA. TM The read speeds of SSD devices based on Serial AT (Advanced Technology) Attachment, or SATA, have been significantly improved. However, the demand for performance in mobile devices continues to increase, for example, to fully enable virtual or augmented reality devices, take advantage of increased network speeds, and so on. In response to this demand, storage devices have transitioned from parallel to serial communication interfaces. Universal Flash Storage (UFS) devices (including controllers and firmware) use a low-voltage differential signaling (LVDS) serial interface with dedicated read / write paths to communicate with host devices, further increasing read / write speeds.

[0094] The instructions 824 may be further transmitted or received over a communication network 826 using a transmission medium via a network interface device 820 that utilizes any of a number of transmission protocols, such as frame relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc. Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards (known as ), IEEE 802.16 series standards (called ), IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, etc.). In an example, network interface device 820 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to communication network 826. In an example, network interface device 820 may include multiple antennas to enable wireless communication using at least one of single-input, multiple-output (SIMO), multiple-input, multiple-output (MIMO), or multiple-input, single-output (MISO) technology. The term "transmission media" shall be taken to include any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 800, and includes digital or analog communication signals or other intangible media that facilitate communication of such software.

[0095] The above embodiments include references to the accompanying drawings that form a part of the embodiments. The drawings show, by way of illustration, specific embodiments in which the present invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements other than those shown or described. However, the present inventors also contemplate examples in which only those shown or described elements are provided. Furthermore, the present inventors also contemplate examples (or one or more aspects thereof) using any combination or arrangement of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0096] In this document, the term "a" or "an" is often used in patent documents to include one or more, independent of any other examples or uses of "at least one" or "one or more." In this document, the term "or" is used to refer to a non-exclusive "or" so that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain English equivalents of the respective terms "comprising" and "wherein." Furthermore, in the appended claims, the terms "including" and "comprising" are open-ended, that is, a system, apparatus, object, or process that includes elements in addition to those listed after the term in a claim is still considered to be within the scope of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0097] In various examples, the components, controllers, processors, parts, engines, or tables described herein may include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit (including a group of processors or a multi-core device).

[0098] As used in this document, the term "horizontal" is defined as a plane parallel to the conventional plane or surface of a substrate (e.g., the plane underlying a wafer or die), regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to horizontal, as defined above. Prepositions such as "on," "above," and "below" are defined as referring to the top or exposed surface of a substrate relative to a conventional plane or surface, regardless of the substrate's orientation; while "on" is intended to indicate direct contact of one structure relative to another structure "above" the structure (absent an explicit indication to the contrary); the terms "above" and "below" are expressly intended to identify the relative placement of structures (or layers, features, etc.), which explicitly includes (but is not limited to) direct contact between the identified structures, unless explicitly identified otherwise. Similarly, the terms "above" and "below" are not limited to a horizontal orientation, as a structure may be "above" a reference structure if, at a certain point in time, it is the outermost portion of the structure in question, even if such structure extends vertically, rather than horizontally, relative to the reference structure.

[0099] The terms "wafer" and "substrate" are generally used herein to refer to any structure on which an integrated circuit is formed, and also to such structures during the various stages of integrated circuit fabrication. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0100] Various embodiments according to the present invention and described herein include memories utilizing a vertical structure of memory cells (e.g., a string of NAND memory cells). As used herein, directional adjectives will be considered relative to the surface of the substrate on which the memory cells are formed (i.e., a vertical structure will be considered to extend away from the substrate surface, the bottom end of the vertical structure will be considered to be the end closest to the substrate surface, and the top end of the vertical structure will be considered to be the end farthest from the substrate surface).

[0101] As used herein, directional adjectives (e.g., horizontal, vertical, normal, parallel, perpendicular, etc.) may refer to relative orientations and, unless otherwise specified, are not intended to require strict adherence to specific geometric properties. For example, as used herein, a vertical structure need not be strictly perpendicular to the surface of a substrate, but may instead be substantially perpendicular to the surface of the substrate and may form an acute angle (e.g., between 60 and 120 degrees, etc.) with the surface of the substrate.

[0102] In some embodiments described herein, different doping configurations may be applied to a source-side select gate (SGS), a control gate (CG), and a drain-side select gate (SGD), each of which, in this example, may be formed of or at least include polysilicon. This results in these layers (e.g., polysilicon, etc.) exhibiting different etch rates when exposed to an etching solution. For example, during the formation of a monolithic pillar in a 3D semiconductor device, the SGS and CG may form a recess, while the SGD may remain less recessed or even not recessed at all. These doping configurations can thus enable selective etching into different layers (e.g., the SGS, CG, and SGD) in the 3D semiconductor device using an etching solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0103] As used herein, operating a memory cell includes reading from, writing to, or erasing the memory cell. The operation of placing a memory cell in a desired state is referred to herein as "programming" and can include both writing to and erasing the memory cell (e.g., the memory cell can be programmed to an erased state).

[0104] According to one or more embodiments of the present invention, a memory controller (e.g., a processor, controller, firmware, etc.) located within or external to a memory device is capable of determining (e.g., selecting, setting, adjusting, calculating, changing, clearing, communicating, adapting, deriving, defining, utilizing, modifying, applying, etc.) a number of wear cycles or a wear state (e.g., recording wear cycles, counting operations of the memory device as they occur, tracking operations of the memory device from which they originate, evaluating characteristics of the memory device corresponding to the wear state, etc.).

[0105] According to one or more embodiments of the present invention, a memory access device may be configured to provide wear cycle information to a memory device with each memory operation. Memory device control circuitry (e.g., control logic) may be programmed to compensate for memory device performance variations corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0106] It will be understood that when an element is referred to as being “on,” “connected to,” or “coupled to” another element, it can be directly on, connected to, or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element, there are no intervening elements or layers present. Unless otherwise indicated, if two elements are shown in a drawing with a line connecting the two elements, the two elements may be coupled or directly coupled.

[0107] The method examples described herein may be at least partially machine or computer-implemented. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform the methods described in the examples above. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, and the like. This code may include computer-readable instructions for performing the various methods. The code may form part of a computer program product. Furthermore, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media (e.g., during execution or at other times). Examples of such tangible computer-readable media may include, but are not limited to: a hard disk, a removable magnetic disk, a removable optical disk (e.g., a compact disk and a digital video disk), a magnetic cassette, a memory card or stick, random access memory (RAM), read-only memory (ROM), a solid-state drive (SSD), a universal flash storage (UFS) device, an embedded MMC (eMMC) device, and the like.

[0108] The above description is intended to be illustrative rather than restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with each other. After reviewing the above description, for example, a person of ordinary skill in the art may use other embodiments. It is claimed that it is not intended to explain or limit the scope or meaning of the claims. Moreover, in the above embodiments, various features may be grouped together to simplify the present invention. This should not be interpreted as expecting that unclaimed disclosed features are the key to any claim. Rather, the subject matter of the present invention may be less than all the features of a particular disclosed embodiment. Therefore, the appended claims are incorporated into the embodiments herein, with each claim itself serving as a separate embodiment, and it is expected that such embodiments can be combined with each other in various combinations or permutations. The scope of the embodiments should be determined with reference to the appended claims together with the full scope of equivalents authorized by such claims.

[0109] Other notes and examples

[0110] Example 1 is a method performed by a controller of a NAND memory device, the controller in communication with a volatile memory, the method comprising: determining a first operating condition of the NAND device; determining, based on the first operating condition, that an amount of volatile memory allocated to a logical-to-physical (L2P) cache should be increased; in response to determining that the amount of volatile memory allocated to the L2P cache should be increased, reallocating an amount of volatile memory allocated to a donor memory location to the L2P cache; and storing an additional L2P table entry in the L2P cache in a region of the volatile memory previously allocated to the donor memory location and now allocated to the L2P cache as a result of increasing the L2P cache.

[0111] In example 2, the subject matter of example 1 optionally includes wherein the first operating condition is a command queue depth.

[0112] In Example 3, the subject matter of Example 2 optionally includes that the PD cache should be increased comprises determining that the command queue depth exceeds a determined threshold number of commands.

[0113] In Example 4, the subject matter of any one or more of Examples 2-3 optionally includes: the PD cache should be increased comprising determining that the command queue depth exceeds a determined threshold number of commands and a ratio of read commands to write commands exceeds a determined threshold ratio.

[0114] In Example 5, the subject matter of Example 4 optionally includes wherein the donor memory location is a read buffer.

[0115] In Example 6, the subject matter of any one or more of Examples 2-5 optionally includes: the PD cache should be increased comprising determining that the command queue depth exceeds a determined threshold number of commands and a ratio of write commands to read commands exceeds a determined threshold ratio.

[0116] In Example 7, the subject matter of Example 6 optionally includes wherein the donor memory location is a write buffer.

[0117] In Example 8, the subject matter of any one or more of Examples 1-7 optionally includes wherein the donor memory location is part of both a read buffer and a write buffer.

[0118] Example 9 is a NAND memory device comprising: a volatile memory; and a controller that executes instructions to: determine a first operating condition of the NAND memory device; determine, based on the first operating condition, that an amount of volatile memory allocated to a logical-to-physical (L2P) cache should be increased; in response to determining that the amount of volatile memory allocated to the L2P cache should be increased, reallocate an amount of volatile memory allocated to a donor memory location to the L2P cache; and store an additional L2P table entry in the L2P cache in a region of the volatile memory that was previously allocated to the donor memory location and that is now allocated to the L2P cache as a result of increasing the L2P cache.

[0119] In Example 10, the subject matter of Example 9 optionally includes wherein the first operating condition is a command queue depth.

[0120] In Example 11, the subject matter of Example 10 optionally includes that the PD cache should be increased comprises determining that the command queue depth exceeds a determined threshold number of commands.

[0121] In Example 12, the subject matter of any one or more of Examples 10-11 optionally includes that the PD cache should be increased comprises determining that the command queue depth exceeds a determined threshold number of commands and a ratio of read commands to write commands exceeds a determined threshold ratio.

[0122] In Example 13, the subject matter of Example 12 optionally includes wherein the donor memory location is a read buffer.

[0123] In Example 14, the subject matter of any one or more of Examples 10-13 optionally includes that the PD cache should be increased comprises determining that the command queue depth exceeds a determined threshold number of commands and a ratio of write commands to read commands exceeds a determined threshold ratio.

[0124] In Example 15, the subject matter of Example 14 optionally includes wherein the donor memory location is a write buffer.

[0125] In Example 16, the subject matter of any one or more of Examples 9-15 optionally includes wherein the donor memory location is part of both a read buffer and a write buffer.

[0126] Example 17 is a machine-readable medium comprising instructions that, when executed by a machine, cause the machine to perform operations comprising each of: determining a first operating condition of a NAND memory device; determining, based on the first operating condition, that an amount of volatile memory allocated to a logical-to-physical (L2P) cache should be increased; in response to determining that the amount of volatile memory allocated to the L2P cache should be increased, reallocating an amount of volatile memory allocated to a donor memory location to the L2P cache; and storing an additional L2P table entry in the L2P cache in a region of the volatile memory previously allocated to the donor memory location and now allocated to the L2P cache as a result of increasing the L2P cache.

[0127] In Example 18, the subject matter of Example 17 optionally includes wherein the first operating condition is a command queue depth.

[0128] In Example 19, the subject matter of Example 18 optionally includes that the PD cache should be increased comprises determining that the command queue depth exceeds a determined threshold number of commands.

[0129] In Example 20, the subject matter of any one or more of Examples 18-19 optionally includes that the PD cache should be increased comprises determining that the command queue depth exceeds a determined threshold number of commands and a ratio of read commands to write commands exceeds a determined threshold ratio.

[0130] In Example 21, the subject matter of Example 20 optionally includes wherein the donor memory location is a read buffer.

[0131] In Example 22, the subject matter of any one or more of Examples 18-21 optionally includes that the PD cache should be increased comprises determining that the command queue depth exceeds a determined threshold number of commands and a ratio of write commands to read commands exceeds a determined threshold ratio.

[0132] In Example 23, the subject matter of Example 22 optionally includes wherein the donor memory location is a write buffer.

[0133] In Example 24, the subject matter of any one or more of Examples 17-23 optionally includes wherein the donor memory location is part of both a read buffer and a write buffer.

[0134] Example 25 is a device comprising: means for determining a first operating condition of a NAND device; means for determining, based on the first operating condition, that an amount of volatile memory allocated to a logical-to-physical (L2P) cache should be increased; means for reallocating an amount of volatile memory allocated to a donor memory location to the L2P cache in response to determining that the amount of volatile memory allocated to the L2P cache should be increased; and means for storing additional L2P table entries in the L2P cache in a region of the volatile memory previously allocated to the donor memory location and now allocated to the L2P cache as a result of increasing the L2P cache.

[0135] In Example 26, the subject matter of Example 25 optionally includes wherein the first operating condition is a command queue depth.

[0136] In Example 27, the subject matter of Example 26 optionally includes that the PD cache should be increased including means for determining that the command queue depth exceeds a determined threshold number of commands.

[0137] In Example 28, the subject matter of any one or more of Examples 26-27 optionally includes: the cache should be increased (P) including means for determining that the command queue depth exceeds a determined threshold number of commands and a ratio of read commands to write commands exceeds a determined threshold ratio.

[0138] In Example 29, the subject matter of Example 28 optionally includes wherein the donor memory location is a read buffer.

[0139] In Example 30, the subject matter of any one or more of Examples 26-29 optionally includes: the cache including means for determining that the command queue depth exceeds a determined threshold number of commands and a ratio of write commands to read commands exceeds a determined threshold ratio.

[0140] In Example 31, the subject matter of Example 30 optionally includes wherein the donor memory location is a write buffer.

[0141] In Example 32, the subject matter of any one or more of Examples 25-31 optionally includes wherein the donor memory location is part of both a read buffer and a write buffer.

Claims

1. A NAND memory device comprising: Controller; a volatile memory storing instructions that, when executed by the controller, cause the controller to perform the following operations: determining a command queue depth of a command queue of the NAND memory device; determining whether an amount of volatile memory allocated to a logical-to-physical L2P cache should be increased based on the command queue depth of the command queue exceeding a threshold number of commands in the command queue; In response to determining that the amount of volatile memory allocated to the L2P cache should be increased: selecting a donor memory location from a read buffer, a write buffer, or one of the read buffer and the write buffer based on the command in the command queue; reallocating a volatile memory region allocated to the selected donor memory location to the L2P cache; as well as Additional L2P entries in the L2P cache are stored at least in part in the volatile memory region previously allocated to the donor memory location.

2. The NAND memory device according to claim 1, wherein: Determining whether the amount of volatile memory allocated to the L2P cache should be increased includes determining whether the amount of volatile memory allocated to the L2P cache should be increased based on the command queue depth of the command queue and a ratio of command types in the command queue.

3. The NAND memory device according to claim 1 , wherein: Determining whether the amount of volatile memory allocated to the L2P cache should be increased includes determining whether the amount of volatile memory allocated to the L2P cache should be increased based on the command queue depth and an L2P cache hit or L2P cache miss percentage of the command queue.

4. The NAND memory device according to claim 1 , wherein: The operations of determining whether the amount of volatile memory allocated to the L2P cache should be increased based on the command queue depth of the command queue include comparing the command queue depth to a threshold depth, and wherein the operations further include: After storing the additional L2P entry: determining whether the command queue depth of the command queue no longer exceeds the threshold depth; and In response to determining that the command queue depth no longer exceeds the threshold depth, the size of the L2P cache is reduced by reallocating at least a portion of the volatile memory region back to the donor memory location.

5. The NAND memory device according to claim 1, wherein The operation of reallocating the volatile memory region allocated to the donor memory location to the L2P cache comprises: reallocating, at a first time, a first portion of the volatile memory region allocated to the donor memory location; and A second portion of the volatile memory region allocated to the donor memory location is reallocated at a second time after the first time.

6. The NAND memory device of claim 1 , wherein the operations further comprise: receiving a host write command from a host device, the host write command including a logical address; checking a portion of a logical-to-physical L2P mapping table stored in the L2P cache to identify whether the mapping of the logical address to the physical address exists in the L2P cache; checking a volatile memory location not assigned to the L2P cache to identify whether an updated mapping of the logical address to a second physical address exists; and In response to determining that an updated mapping of the logical address to a second physical address exists, the host write command is executed using the second physical address.

7. The NAND memory device of claim 1 , wherein the operations further comprise: The updated logical-to-physical allocation record is stored in the donor memory location. The volatile memory region allocated to the donor memory location is reassigned back to the donor memory location by moving a pointer marking a boundary between the L2P cache and the donor memory location.

8. The NAND memory device of claim 1 , further comprising: Reallocation of the volatile memory region allocated to the donor memory location to the L2P cache is delayed until the volatile memory allocated to the donor memory location is unused.

9. The NAND memory device according to claim 1, wherein: Reallocating the volatile memory region allocated to the donor memory location to the L2P cache includes incrementally reallocating the volatile memory region by reallocating a specified amount of the volatile memory region per unit time until all of the volatile memory region is reallocated.

10. A NAND memory device comprising: Controller; a volatile memory storing instructions that, when executed by the controller, cause the controller to perform the following operations: determining that a ratio of first-type commands to second-type commands in a host command queue exceeds a threshold; responsive to determining that the ratio of the first type of commands to the second type of commands exceeds the threshold, incrementally reallocating, over a defined time period, a volatile memory region of a buffer of the NAND memory device that services the second type of commands for use as an L2P cache; as well as Additional L2P entries in the L2P cache are stored at least in part in the volatile memory region previously allocated to servicing the second type of commands.

11. The NAND memory device according to claim 10, wherein: Incrementally reallocating the volatile memory region of the buffer allocated to the NAND memory device that services the second type of commands for use as the L2P cache over a defined time period includes reallocating a predetermined amount of memory to the L2P cache per defined time period.

12. The NAND memory device of claim 10, wherein the operations further comprise: After completing the incremental reallocation, determining that the ratio of the first type of commands to the second type of commands no longer exceeds the threshold; and In response to determining that the ratio of the first type of commands to the second type of commands no longer exceeds the threshold, reducing the size of the L2P cache by reallocating a volatile memory region of the L2P cache allocated to the NAND memory device for servicing the second type of commands.

13. The NAND memory device of claim 10, wherein the operations further comprise: A size of the volatile memory region reallocated to the L2P cache is calculated based on the ratio.

14. The NAND memory device of claim 13, wherein the operations further comprise: The size is limited to a predetermined size.

15. The NAND memory device of claim 10, wherein the operations further comprise: After the incremental reallocation is completed, the volatile memory region reallocated from the volatile memory previously allocated for servicing the second type of commands is reallocated back to servicing the second type of commands within a time period.

16. The NAND memory device according to claim 10, wherein: Incrementally reallocating, within the defined time period, the region of the volatile memory allocated for servicing the second type of commands to the L2P cache includes incrementally moving a memory pointer that marks a boundary between the volatile memory allocated to the L2P cache and the volatile memory allocated for servicing the second type of commands.

17. The NAND memory device of claim 10, wherein the operations further comprise: receiving a write command, the write command changing the contents of an L2P table stored in the L2P cache; and The changed contents of the L2P table are stored in an update list stored in the volatile memory area previously allocated to servicing the second type of commands.

18. The NAND memory device of claim 10, further comprising receiving L2P cache rules from a host device, the L2P cache rules including the threshold.

19. The NAND memory device of claim 10, wherein the first type of command is a read command and the second type of command is a write command.

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