A multi-interface compatible expansion system and communication method based on SRIO bus

Abstract

The present application belongs to the field of data processing technology, and particularly relates to a multi-interface compatible expansion system and communication method based on SRIO bus. The system includes a processor CPU and an FPGA chip, wherein the CPU and the FPGA are connected via an SRIO interface, and multiple external devices are connected to the pins of the FPGA via an interface bus; the CPU includes at least one OUTBOUND space, in which multiple interface intervals are divided, and each interface interval corresponds to a register list, in which the protocol parameters for bus communication between the FPGA and each external device are recorded, and the FPGA allocates information according to the interface interval of the OUTBOUND space, maps the control data to the corresponding external device interface IP, and each interface IP core completes the register configuration and data transmission and reception control of various bus interfaces according to the control data. The present application reduces the interface resource requirements of the target CPU, broadens the selection range of the CPU, and utilizes FPGA logic development to greatly meet the requirements of the radar information processing system for different interfaces, thereby improving the development efficiency of the radar processing module.

Description

Technical Field

[0001] The present application belongs to the field of data processing technology, and in particular relates to a multi-interface compatible expansion system and a communication method based on an SRIO bus. Background Art

[0002] Radar is the eyes of the aircraft. Whether it is a civil aviation system or a military device, the radar system is required to have fast information processing speed, high accuracy, and good real-time performance in terms of safety, reliability, rapid response, and precise counterattack. Therefore, choosing a high-performance CPU, a high-speed data communication bus, and a highly reliable communication node is an important design consideration for technical experts.

[0003] At present, the computing speed, operating power consumption and interface types of Freescale's PowerPC series CPU, TI's DSP and domestic Loongson, Feiteng and other CPUs have greatly promoted the development of embedded products, but the interfaces of these CPUs are usually relatively simple and cannot meet the requirements of various types of interfaces and bus protocols for radar information processing. On the other hand, the rapid development of programmable logic devices (FPGAs), such as Xilinx and Guowei Electronics, has provided a large number of general IOs and high-speed GTPs for design, which can be used for compatible design of multiple interfaces, but their logic writing is complex and the software process control is difficult, which also brings certain troubles to engineering implementation.

[0004] In the prior art, the CPU is usually connected to external devices through a local bus, or connected to an FPGA through a local bus. The FPGA pre-processes the radar data of the external device and then transmits it to the CPU through the local bus. However, when connecting external devices or FPGAs through a local bus, the local bus also needs to change as the external device is replaced. During the radar signal processing process, as the number of external devices increases, it is usually necessary to add 20 to 30 local buses, making subsequent interface compatibility expansion increasingly difficult. Summary of the invention

[0005] In order to solve at least one of the above technical problems, the present application provides a multi-interface compatible expansion system and communication method based on SRIO bus. The present application connects the CPU and FPGA through a high-speed bus for expansion design, which can not only meet the radar's design requirements for different interfaces, but also greatly facilitate the flexible development of system control software.

[0006] The first aspect of the present application provides a multi-interface compatible expansion system based on the SRIO bus, including a processor CPU and an FPGA chip, wherein the processor CPU is connected to the FPGA chip via an SRIO interface, and multiple external devices are connected to the pins of the FPGA chip via an interface bus; the processor CPU includes at least one OUTBOUND space, wherein the OUTBOUND space is divided into multiple interface intervals, each interface interval corresponds to a register list, and the register list records the protocol parameters for bus communication between the FPGA and each external device, and the FPGA chip is configured to map control data to the corresponding external device interface IP according to the interface interval allocation information of the OUTBOUND space, and each interface IP core completes the register configuration and data transmission and reception control of various bus interfaces according to the control data.

[0007] Preferably, the size of the interface interval is 1MB to 4MB.

[0008] Preferably, the processor CPU performs SRIO communication with the FPGA chip through OUTBOUND address mapping, applying a write operation NWRITE, a stream write operation SWRITE or a read operation NREAD.

[0009] Preferably, the FPGA chip performs data communication with an external bus interface of an external device through its GPIO pins.

[0010] Preferably, the FPGA chip performs data communication with an external bus interface of an external device through its GTP pin.

[0011] Preferably, the external devices include SRIO devices, PCIe devices, PLB devices, SPI devices, IIC devices, and UART devices. The FPGA chip communicates with the SRIO devices via the SRIO bus, communicates with the PLB devices via the PLB bus, communicates with the SPI devices via the SPI bus, communicates with the IIC devices via the IIC bus, and communicates with the UART devices via the UART bus. Correspondingly, the OUTBOUND space of the processor CPU is provided with an SRIO interface interval, a PCIe interface interval, a PLB interface interval, a SPI interface interval, an IIC interface interval, and a UART interface interval. The register list in the SRIO interface interval records the configuration parameters and transceiver control parameters of SRIO bus communication, the register list in the PCIe interface interval records the configuration parameters and transceiver control parameters of PCIe bus communication, the register list in the PLB interface interval records the configuration parameters and transceiver control parameters of PLB bus communication, the register list in the SPI interface interval records the configuration parameters and transceiver control parameters of SPI bus communication, the register list in the IIC interface interval records the configuration parameters and transceiver control parameters of IIC bus communication, and the register list in the UART interface interval records the configuration parameters and transceiver control parameters of UART bus communication.

[0012] A second aspect of the present application provides a communication method of a multi-interface compatible expansion system based on an SRIO bus, wherein the multi-interface compatible expansion system based on the SRIO bus as described above is used for communication, and the communication method includes:

[0013] Determine the external device and interface bus that need to communicate, and write the interface configuration data associated with the interface bus into the corresponding address of the OUTBOUND space of the processor CPU to form SRIO data;

[0014] By sending the SRIO data of the corresponding address to the FPGA chip;

[0015] After the FPGA chip receives the SRIO data from the processor CPU, it maps it into control instructions and data read and write instructions for various interfaces according to the protocol, and controls the corresponding interface IP core in the FPGA to complete interface initialization;

[0016] The IP core sends instructions and data to each interface through the interface bus protocol, thereby controlling the external device to perform read and write operations.

[0017] Preferably, the FPGA chip is configured to complete the development and packaging of various types of interface bus protocol IP cores.

[0018] The multi-interface compatible expansion method based on SRIO bus designed by this application reduces the interface resource requirements of the target CPU, broadens the selection range of the CPU, and improves the development efficiency of the CPU. At the same time, the use of FPGA logic development greatly meets the requirements of the radar information processing system for different interfaces, improves the development efficiency of the radar processing module, and is conducive to the advancement of the three-dimensional work of the radar processing platform. This application can be applied to the hardware interface compatible expansion of various systems and can be applied to the three-dimensional integration of various processing platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a system block diagram of a preferred embodiment of the multi-interface compatible expansion system based on the SRIO bus of the present application.

[0020] Figure 2 For this application Figure 1 The schematic diagram of the OUTBOUND space division and the correspondence with various interface bus protocol IP cores of the illustrated embodiment. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical scheme and advantages of the implementation of this application clearer, the technical scheme in the implementation of this application will be described in more detail in combination with the drawings in the implementation of this application. In the drawings, the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The described implementation is a part of the implementation of this application, not all of the implementations. The implementation described below with reference to the drawings is exemplary and is intended to be used to explain this application, and cannot be understood as a limitation on this application. Based on the implementation in this application, all other implementations obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. The implementation of this application is described in detail below in combination with the drawings.

[0022] The first aspect of the present application provides a multi-interface compatible expansion system based on the SRIO bus, including a processor CPU and an FPGA chip, wherein the processor CPU is connected to the FPGA chip via an SRIO interface, and multiple external devices are connected to the pins of the FPGA chip via an interface bus; the processor CPU includes at least one OUTBOUND space, wherein the OUTBOUND space is divided into multiple interface intervals, each interface interval corresponds to a register list, and the register list records the protocol parameters for bus communication between the FPGA and each external device, and the FPGA chip is configured to map control data to the corresponding external device interface IP according to the interface interval allocation information of the OUTBOUND space, and each interface IP core completes the register configuration and data transmission and reception control of various bus interfaces according to the control data.

[0023] This application consists of a CPU chip, an FPGA chip and various bus interface devices. The CPU sends and receives data with external bus interface devices through the SRIO bus, completes the initialization configuration of each interface, software protocol transmission and device control processing. The CPU and FPGA are connected through the SRIO bus. The CPU controls the IP core in the FPGA to complete interface initialization, interface data transmission and reception by sending SRIO data of the corresponding address according to the divided interface space. The FPGA completes the development and packaging of various interface bus protocol IP cores. After receiving the SRIO data from the CPU, the FPGA maps it into control instructions and data read and write instructions for various interfaces according to the protocol, and sends instructions and data to each interface through the interface bus protocol IP core. The FPGA is compatible with various interfaces at the same time, and the number of each interface device can be expanded.

[0024] For example, the CPU's 0x300000~0x3FFFFF interface range corresponds to the SPI bus register list. The first data in the register represents the design of the SPI bus baud rate, and the second data is the data to be sent to the SPI bus. According to the prior agreement, the FPGA reads the first data at the starting address of 0x200000, and will update the baud rate in the SPI bus interface protocol. When it reads the second data, it will send the second data to the SPI bus interface at the above baud rate. In another embodiment, the CPU's 0x500000 to 0x5FFFFF interface interval corresponds to a register list of the UART bus, the first data in the register is 1, indicating communication via the RS422 serial port, the second data in the register is 1, indicating communication via the RS485 serial port, the third data in the register is 1, indicating communication via the RS232 serial port, and the fourth data is the data to be sent to the UART bus. According to the prior agreement, FPGA assumes that the first three data read from the starting address of 0x500000 are 010, then the serial port in the UART bus interface protocol will be set to RS485. After reading the fourth data, the fourth data will be sent to the UART bus interface based on the RS485 serial port.

[0025] In some optional implementations, the size of the interface interval is 1MB to 4MB, which can be customized according to specific needs. Figure 2As shown in the figure, each interface is allocated 1MB of space (SRIO access space is allocated in 0~0x0FFFFF, PCIe access space is allocated in 0x100000~0x1FFFFF, ...), each interface is allocated a register list according to the standard bus protocol, and can occupy multiple OUTBOUND spaces according to the number and type of ports. It is also possible to allocate only one interface in a certain OUTBOUND space or allocate multiple bus interfaces in the same OUTBOUND space as needed.

[0026] In some optional implementations, the processor CPU performs SRIO communication with the FPGA chip through OUTBOUND address mapping, applying a write operation NWRITE, a stream write operation SWRITE, or a read operation NREAD.

[0027] In some optional implementations, the FPGA chip communicates data with an external bus interface of an external device through its GPIO pins.

[0028] In some optional implementations, the FPGA chip communicates data with an external bus interface of an external device through its GTP pin.

[0029] In this example, external devices are connected to the FPGA via an external bus. Various bus types and quantities can be flexibly configured and adjusted according to system requirements. Various bus interfaces are compatible and there is no conflict.

[0030] In some optional implementations, the external device includes an SRIO device, a PCIe device, a PLB device, an SPI device, an IIC device, and a UART device. The FPGA chip communicates with the SRIO device through the SRIO bus, communicates with the PLB device through the PLB bus, communicates with the SPI device through the SPI bus, communicates with the IIC device through the IIC bus, and communicates with the UART device through the UART bus. Correspondingly, the OUTBOUND space of the processor CPU is provided with an SRIO interface interval, a PCIe interface interval, a PLB interface interval, a SPI interface interval, an IIC interface interval, and a UART interface interval. The register list in the SRIO interface interval records the configuration parameters and transceiver control parameters of the SRIO bus communication, the register list in the PCIe interface interval records the configuration parameters and transceiver control parameters of the PCIe bus communication, the register list in the PLB interface interval records the configuration parameters and transceiver control parameters of the PLB bus communication, the register list in the SPI interface interval records the configuration parameters and transceiver control parameters of the SPI bus communication, the register list in the IIC interface interval records the configuration parameters and transceiver control parameters of the IIC bus communication, and the register list in the UART interface interval records the configuration parameters and transceiver control parameters of the UART bus communication.

[0031] The bus interface types of this application include SRIO bus interface, PCIE bus interface, PLB bus interface, SPI bus interface, IIC bus interface, UART bus interface and other commonly used interfaces for radar signal processing. Each interface is connected to the GPIO or GTP pin of the FPGA without interfering with each other.

[0032] A second aspect of the present application provides a communication method of a multi-interface compatible expansion system based on an SRIO bus, wherein the multi-interface compatible expansion system based on the SRIO bus as described above is used for communication, and the communication method includes:

[0033] Determine the external device and interface bus that need to communicate, and write the interface configuration data associated with the interface bus into the corresponding address of the OUTBOUND space of the processor CPU to form SRIO data;

[0034] By sending the SRIO data of the corresponding address to the FPGA chip;

[0035] After the FPGA chip receives the SRIO data from the processor CPU, it maps it into control instructions and data read and write instructions for various interfaces according to the protocol, and controls the corresponding interface IP core in the FPGA to complete interface initialization;

[0036] The IP core sends instructions and data to each interface through the interface bus protocol, thereby controlling the external device to perform read and write operations.

[0037] In some optional implementations, the FPGA chip is configured to complete the development and packaging of various types of interface bus protocol IP cores.

[0038] This application reduces the interface resource requirements of the target CPU, broadens the selection range of the CPU, and utilizes FPGA logic development to greatly meet the radar information processing system's requirements for different interfaces, thereby improving the development efficiency of the radar processing module.

[0039] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A multi-interface compatible expansion system based on SRIO bus, characterized in that: It includes a processor CPU and an FPGA chip, the processor CPU is connected to the FPGA chip through an SRIO interface, and multiple external devices are connected to the pins of the FPGA chip through an interface bus; the processor CPU includes at least one OUTBOUND space, the OUTBOUND space is divided into multiple interface intervals, each interface interval corresponds to a register list, and the register list records the protocol parameters for bus communication between the FPGA and each external device. The FPGA chip is configured to map control data to the corresponding external device interface IP according to the interface interval allocation information of the OUTBOUND space, and each interface IP core completes the register configuration and data transmission and reception control of various bus interfaces according to the control data.

2. The multi-interface compatible expansion system based on SRIO bus as claimed in claim 1, characterized in that: The size of the interface interval is 1MB to 4MB.

3. The multi-interface compatible expansion system based on SRIO bus as claimed in claim 1, characterized in that: The processor CPU performs SRIO communication with the FPGA chip through OUTBOUND address mapping, and applies a write operation NWRITE, a stream write operation SWRITE or a read operation NREAD.

4. The multi-interface compatible expansion system based on SRIO bus as claimed in claim 1, characterized in that: The FPGA chip performs data communication with the external bus interface of the external device through its GPIO pins.

5. The multi-interface compatible expansion system based on SRIO bus as claimed in claim 1, characterized in that: The FPGA chip performs data communication with the external bus interface of the external device through its GTP pin.

6. The multi-interface compatible expansion system based on SRIO bus as claimed in claim 1, characterized in that: The external devices include SRIO devices, PCIe devices, PLB devices, SPI devices, IIC devices, and UART devices. The FPGA chip communicates with the SRIO devices through the SRIO bus, communicates with the PLB devices through the PLB bus, communicates with the SPI devices through the SPI bus, communicates with the IIC devices through the IIC bus, and communicates with the UART devices through the UART bus. Correspondingly, the OUTBOUND space of the processor CPU is provided with an SRIO interface interval, a PCIe interface interval, a PLB interface interval, a SPI interface interval, an IIC interface interval, and a UART interface interval. The register list in the RIO interface interval records the configuration parameters and transceiver control parameters of SRIO bus communication, the register list in the PCIe interface interval records the configuration parameters and transceiver control parameters of PCIe bus communication, the register list in the PLB interface interval records the configuration parameters and transceiver control parameters of PLB bus communication, the register list in the SPI interface interval records the configuration parameters and transceiver control parameters of SPI bus communication, the register list in the IIC interface interval records the configuration parameters and transceiver control parameters of IIC bus communication, and the register list in the UART interface interval records the configuration parameters and transceiver control parameters of UART bus communication.

7. A communication method for a multi-interface compatible expansion system based on SRIO bus, characterized in that: The multi-interface compatible expansion system based on the SRIO bus as claimed in claim 1 is used for communication, and the communication method comprises: Determine the external device and interface bus that need to communicate, and write the interface configuration data associated with the interface bus into the corresponding address of the OUTBOUND space of the processor CPU to form SRIO data; By sending the SRIO data of the corresponding address to the FPGA chip; After the FPGA chip receives the SRIO data from the processor CPU, it maps it into control instructions and data read and write instructions for various interfaces according to the protocol, and controls the corresponding interface IP core in the FPGA to complete interface initialization; The IP core sends instructions and data to each interface through the interface bus protocol, thereby controlling the external device to perform read and write operations.

8. The communication method of the multi-interface compatible expansion system based on the SRIO bus as claimed in claim 7, characterized in that: The FPGA chip is configured to complete the development and packaging of various interface bus protocol IP cores.

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