Accelerator device, data processing system, and method of operation of an accelerator device

Abstract

The present disclosure relates to an acceleration device including an accelerator. The accelerator processes a computation by using a computation method selected based on at least one of a batch size and a sequence size and by controlling an input path of first input data and second input data to a processing element array according to the selected computation method. The computation method includes a first computation method and a second computation method, and the first input data and the second input data are input into the processing element array based on the batch size according to the first computation method, and the first input data is input into the processing element array based on the sequence size according to the second computation method.

Description

[0001] Cross-references to related applications

[0002] This patent document claims priority and benefit to Korean application No. 10-2020-0108437, filed on August 27, 2020, which is incorporated herein by reference in its entirety as part of the disclosure of this patent document. Technical Field

[0003] The technology and implementation scheme disclosed in this patent document generally relate to a semiconductor device. Background Technology

[0004] An artificial intelligence (AI) accelerator is a hardware accelerator or computer system designed to accelerate artificial intelligence applications such as artificial neural networks. AI accelerators can speed up processes associated with artificial intelligence applications such as multilayer perceptrons (MLPs), long short-term memory (LSTMs), and convolutional neural networks (CNNs) while reducing the burden on host resources.

[0005] Long Short-Term Memory (LSTM) is an artificial recurrent neural network architecture used in the field of deep learning, and computations associated with LSTM operations can be performed by computing input data based on sequence information and the output value of the current unit in an accelerator.

[0006] Since the speed improvement of the above calculations is directly related to the performance of the accelerator, various technologies, including new ways to accelerate processes within the accelerator, are being discussed. Summary of the Invention

[0007] The technology disclosed in this patent document can be implemented in various embodiments to provide an acceleration device, a data storage device, a data processing system, and a method of operating the acceleration device with improved computational input data capabilities.

[0008] In an embodiment, an acceleration device may include: an accelerator communicating with an array of processing elements of an artificial neural network, and configured to perform computation by using a computation method selected based on at least one of batch size and sequence size, and by controlling the input paths of first input data and second input data to the array of processing elements according to the selected computation method, wherein the batch size corresponds to the size of data that the array of processing elements can process simultaneously, and the sequence size corresponds to the length of data that is sequentially input to the array of processing elements, wherein the computation method includes a first computation method and a second computation method, and the first input data and the second input data are input to the array of processing elements based on the batch size according to the first computation method, and the first input data is input to the array of processing elements based on the sequence size according to the second computation method.

[0009] In an embodiment, a data storage apparatus can include: a processing element array configured to perform a computation associated with input data; and an accelerator in communication with the processing element array and configured to perform the computation by using a computation method selected based on at least one of a batch size and a sequence size and by controlling an input path of first input data and second input data to the processing element array according to the selected computation method, the batch size corresponding to a size of data simultaneously processable by the processing element array, the sequence size corresponding to a length of data sequentially input to the processing element array, wherein the computation method includes a first computation method and a second computation method, and the first input data and the second input data are input into the processing element array based on the batch size according to the first computation method, and the first input data is input into the processing element array based on the sequence size according to the second computation method.

[0010] In an embodiment, a data processing system can include a host apparatus and a data storage apparatus. The host apparatus can determine a computation method and a method of inputting first input data and second input data to a processing element array based on at least one of a comparison between a batch size and a batch reference value, a comparison between a sequence size and a sequence reference value, or a combination of these comparisons; and the data storage apparatus is configured to control an input path of the first input data and the second input data to the processing element array according to the determined computation method, wherein the computation method includes a first computation method and a second computation method, and the first input data and the second input data are input into the processing element array based on the batch size according to the first computation method, and the first input data is input into the processing element array based on the sequence size according to the second computation method.

[0011] In an embodiment, an operation method of an acceleration apparatus can include: receiving a batch size corresponding to a size of data simultaneously processable and a sequence size corresponding to a length of data sequentially input; selecting one of a first computation method and a second computation method as a computation method and selecting a method of inputting first input data and second input data to a processing element array based on at least one of a comparison between the batch size and a batch reference value, a comparison between the sequence size and a sequence reference value, or a combination of these comparisons; when it is determined that the computation method is the first computation method, inputting the first input data or the second input data corresponding to the batch size in a first direction to the processing element array; when it is determined that the computation method is the second computation method, inputting the first input data corresponding to the sequence size in the first direction to the processing element array; and obtaining a state value of a current cell and an output value of the current cell by performing a computation process using the first input data, the second input data, and weight values for the first input data and the second input data, respectively.

[0012] In an embodiment, an acceleration device can include: a processing element array including a plurality of processing elements and configured to output a first calculation result value, a second calculation result value, and a third calculation result value, the first calculation result value being a result of a calculation on a first input data and a third input data corresponding to a weight value of the first input data, and the second calculation result value being a result of a calculation on a second input data and a fourth input data corresponding to a weight value of the second input data; an IO buffer block configured to provide the first input data and the second input data to the processing element array in a first direction; a weight buffer block configured to provide the third input data and the fourth input data to the processing element array in a second direction; and a processing element controller configured to select one of a first calculation method and a second calculation method as a calculation method and select a method of inputting the first input data and the second input data to the processing element array based on at least one of a comparison between a batch size and a batch reference value, a comparison between a sequence size and a sequence reference value, or a combination of the comparisons, wherein the first input data and the second input data are input to the processing element array based on the batch size according to the first calculation method, and the first input data is input to the processing element array based on the sequence size according to the second calculation method.

[0013] In some embodiments of the disclosed technology, a calculation method can be determined based on a batch size and a sequence size of data to be input, and according to the determined calculation method, data input can be adjusted and calculation can be processed. Accordingly, it can be desirable to have an effect of improving calculation efficiency on input data.

[0014] In some embodiments of the disclosed technology, data input can be processed in reference to a sequence. Accordingly, it can be desirable to have an effect of improving calculation speed on data. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 FIG. 1 is a diagram illustrating an example of an external server and a data processing system in communication with the external server based on some embodiments of the disclosed technology.

[0016] Figure 2 FIG. 2 is a diagram illustrating an example of a data processing system based on some embodiments of the disclosed technology.

[0017] Figure 3 FIG. 3 is a diagram illustrating a calculation method based on some embodiments of the disclosed technology.

[0018] Figure 4 FIG. 4 is a diagram illustrating an example of an acceleration device based on some embodiments of the disclosed technology.

[0019] Figure 5is a diagram illustrating an example of a first computing method based on some embodiments of the disclosed technology.

[0020] Figure 6 and Figure 7 is a diagram illustrating an example of a second computing method based on some embodiments of the disclosed technology.

[0021] Figure 8 is a diagram illustrating an example of a gate buffer block based on some embodiments of the disclosed technology.

[0022] Figure 9 illustrates example operations of a gate buffer block based on some embodiments of the disclosed technology.

[0023] Figure 10 illustrates example operations of a gate buffer block based on some embodiments of the disclosed technology.

[0024] Figure 11 is a diagram illustrating example operations of a gate buffer block based on some embodiments of the disclosed technology.

[0025] Figure 12 is a diagram illustrating an example of a data processing system based on some embodiments of the disclosed technology.

[0026] Figure 13 is a flowchart illustrating example operations of an acceleration device based on some embodiments of the disclosed technology.

[0027] Figure 14 is a flowchart illustrating a portion of the operations of the acceleration device shown in Figure 13 .

[0028] Figure 15 is a diagram illustrating an example of an acceleration device based on some embodiments of the disclosed technology.

[0029] Figure 16 is a diagram illustrating a configuration of a state buffer block shown in Figure 15 . DETAILED DESCRIPTION

[0030] The technology disclosed in this patent document can be implemented in various embodiments to speed up processes associated with artificial intelligence applications such as long short-term memory (LSTM). Figure 1 is a diagram illustrating a connection relationship between an external server and a data processing system based on some embodiments of the disclosed technology. Figure 2 is a diagram illustrating a configuration of a data processing system based on some embodiments of the disclosed technology.

[0031] Reference is made to Figure 1The data processing system 20 can be coupled to the external server 10 through a communication network to receive data. The data can have a batch size and a sequence size or sequence length, which will be described later. The deep learning algorithm / artificial neural network algorithm can process one "batch" of data at a time.

[0032] In some embodiments, the batch size can indicate a number of training samples utilized in one iteration. For example, if the batch size is set to 100 samples, the algorithm will take 100 samples from the training data set and train the network. In some embodiments, the batch size can indicate a size of a data set that the data processing system 20 can process at a time. Because the data processing system 20 cannot process the entire data set at a time, the data processing system divides the data set into multiple batches and processes one batch at a time. For example, when the first input data is picture images, a number of picture images that can be processed at once can be a batch size of the first input data. For example, assume that the batch size is ten (10), the first input data can include ten picture images. For example, multiply and accumulate (MAC) calculations can be performed on the ten picture images of the first input data based on weights of the first input data. Here, the weights can indicate a number of picture images in the first input data.

[0033] The larger the batch size of the first input data, the higher the utilization of MACs within the range that a processing element (PE) array can handle. If the batch size of the first input data is too small for the range that the PE array can handle, the resources of the MACs will be wasted. Accordingly, the disclosed technology can be implemented in some embodiments to improve the processing speed of calculations by performing calculations on the first input data input to the PE array in parallel when the batch size of the first input data is smaller or different from the batch size that the PE array can handle.

[0034] In some embodiments, the sequence size or sequence length can indicate a length of data that is sequentially fed into the deep learning algorithm. In some embodiments, the sequence can include time-based data of the same batch. The batch can be a set of data that can be processed by the data storage device 200 (or the accelerator 400 described later) at the same time. The sequence size can be a length of data that is sequentially input to the data storage device 200 (or the accelerator 400).

[0035] For example, in a case of natural language processing (NLP) mainly using an LSTM, the number of sentences can be a batch size, and the length of each sentence can be a sequence size. For example, in the sentence "Can I help you", the batch size can be one (1), and the sequence size can be four (4). For example, in the sentence "It is beautiful", the batch size can be one (1), and the sequence size can be three (3).

[0036] The data processing system 20 can include a host device 100 and a data storage device 200.

[0037] Referring to Figure 2 The host device 100 can include an application (Appl.) 110, a software firmware (SW / FW) 120, and an application programming interface (API) 130.

[0038] The software firmware 120 of the host device 100 can determine a calculation method within the accelerator 400 based on at least one or more between a batch size and a sequence size. The calculation method can be determined by the data storage device 200 as well as the host device 100.

[0039] Although not shown, the host device 100 can perform a compilation operation based on network model information including hardware architecture information such as network information and processing near memory (PNM) architecture information. Here, the host device 100 can perform a compilation operation for processing near memory (PNM).

[0040] According to the above-described PNM, a data signal is coupled to the logic die 300. Accordingly, the PNM can generate a faster speed than a data pin structure of high bandwidth memory (HBM). This is because a speed limitation of an off-chip connection is removed.

[0041] The network can include a convolutional neural network (CNN), a multi-layer perceptron (MLP), a long short-term memory (LSTM), etc. As described above, the network can be a neural network, and is not limited thereto.

[0042] Referring to Figure 2 The data storage device 200 can include a memory controller 310, an accelerator 400, and a plurality of memory dies 210. The memory controller (MC) 310 and the accelerator 400 can be included in the logic die 300. The data storage device 200 can be processing near memory (PNM).

[0043] The data storage device 200 can communicate with the host device 100 through a serial deserializer interface (Serdes Interface) protocol. Without being limited thereto, the data storage device 200 can support any protocol capable of communicating with the host device 100 and protocols such as Peripheral Component Interconnect Express (PCI-E), Universal Serial Bus (USB), Universal Flash Storage (UFS), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), and Peripheral Component Interconnect (PCI).

[0044] Figure 3 is a diagram briefly illustrating a computing method based on some embodiments of the disclosed technology.

[0045] Figure 2 The data storage device 200 shown in FIG. 1 can determine a computing method by itself based on at least one or more of a computing method provided from the host device 100 and a batch size and a sequence size provided from the host device 100.

[0046] In an embodiment, the data storage device 200 can perform a computation on an input value "x t " that is an input value of a current cell, perform a computation on an output value "h t-1 " that is an output value of a previous cell, and perform a bias computation. Then, the data storage device 200 can perform addition on a result value of the computation of the input value "x t ", a result value of the computation of the output value "h t-1 ", and a result value of the bias computation. Then, the data storage device 200 can perform the remaining operations such as an activation function process.

[0047] The computation on the input value "x t " can indicate a computation on the input value "x t " (first input data described later) and a weight value of the input value "x t " (third input data described later). The computation on the output value "h t-1 " can indicate a computation on the output value "h t-1 " (second input data described later) and a weight value of the output value "h t-1 " (fourth input data described later).

[0048] Referring to Figure 3 , when the input value "x t " is needed to obtain "f t ", "i t ", "o t ", and "g th t ", but "h t-1 " as an output value of a previous cell. Thus, it is impossible to perform a calculation on "x t " and "h t " at the same time.

[0049] In an embodiment, a calculation on an input value "x t ", a calculation on an output value "h t-1 ", and a bias calculation can be performed separately, and then the remaining operations including an activation function process can be performed.

[0050] Referring to Figure 3 , the data storage apparatus 200 can obtain a first calculation result value in an LSTM in which a plurality of separate cells are coupled to each other, by a calculation (“(1)” in Figure 3 ) on an input value “x t ” as an input value of a current cell and weight values “W xh_f ”, “W xh_i ”, “W xh_o ”, and “W xh_g ” as weight values of the input value “x t ”.

[0051] Also, the data storage apparatus 200 can obtain a second calculation result value by a calculation (“(3)” in Figure 3 ) on an output value “h t-1 ” as an output value of a previous cell and weight values “W hh_f ”, “W hh_i ”, “W hh_o ”, and “W hh_g ” as weight values of “h t-1 ”.

[0052] Further, the data storage apparatus 200 can obtain third calculation result values “b h_f ”, “b h_i ”, “b h_o ”, and “b h_g ” by a bias calculation (“(2)” in Figure 3 ).

[0053] Still further, the data storage apparatus 200 can perform addition (“(4)” in Figure 3 ) on the first calculation result value, the second calculation result value, and the third calculation result value.

[0054] Thereafter, the data storage apparatus 200 can perform the remaining operations such as an activation function process based on a result of the addition operation to obtain a forget gate value “f t ”, an input gate value “it and an output gate value "o t ", and obtains a state value "g t " of a new cell through a hyperbolic tangent (tanh) function. Finally, the data storage device 200 can obtain a state value "c t " of a current cell and an output value "h t " of the current cell. In Figure 3 , "σ" can indicate an activation function, and "c t-1 " can indicate a state value of a previous cell.

[0055] Figure 4 is a diagram illustrating a configuration of an acceleration device based on some embodiments of the disclosed technology.

[0056] Hereinafter, a first calculation method based on some embodiments of the disclosed technology will be described with reference to Figure 5 illustrating an example of the first calculation method, and a second calculation method based on some embodiments of the disclosed technology will be described with reference to Figure 6 and Figure 7 illustrating an example of the second calculation method.

[0057] Referring to Figure 4 , the acceleration device 40 can include an accelerator 400 configured to process a calculation by determining at least one or more calculation methods based on a batch size and a sequence size and by controlling an input path of the first input data and the second input data to a processing element (PE) array 410 according to the determined calculation method.

[0058] The calculation method can include a first calculation method and a second calculation method. According to the first calculation method, the first input data and the second input data are input to the PE array 410 based on the batch size. According to the second calculation method, the first input data is input to the PE array 410 based on the sequence size.

[0059] For example, according to the first calculation method, when there are a plurality of batches within a range that the PE array 410 can handle, a plurality of input data segments (for example, "xt") of the same sequence can be utilized as input to the PE array 410.

[0060] According to the second calculation method, "x" input data "xt-1", "xt", "xt+1", etc. of different sequences can be utilized as input to the PE array 410. The calculation can be performed by increasing the parallelism as many as the number of sequences of the "x" input data. Since the weights of the "x" input data can be utilized to "N" rows ( Figure 4 ) of the "N", the utilization rate of the MAC can also be increased.

[0061] The accelerator 400 may include a PE array 410, an IO buffer block 420, a weight buffer block 430, a gate buffer block 440, an excitation function unit 450, a specific function unit 460, a state buffer block 470, a PE controller 480, and a data transmission unit 490.

[0062] PE array 410 may include multiple PEs.

[0063] The PE array 410 can output a first calculation result value, a second calculation result value, and a third calculation result value. The first calculation result value can be the result calculated using the first input data and the third input data, which serves as the weight value for the first input data. The second calculation result value can be the result calculated using the second input data and the fourth input data, which serves as the weight value for the second input data.

[0064] The third calculation result can indicate the result of the deviation calculation.

[0065] The PE array 410 can be a pulsating array. The PE array 410 can receive input data and weights, and can perform calculations that multiply the input data and weights and add previously stored data.

[0066] The array structure of the PE array 410 can be varied depending on the area of ​​the system being implemented.

[0067] IO buffer 420 can transmit the first input data and the second input data along a first direction (i.e., Figure 4 The direction ①) is provided to the PE array 410. The first input data can be the input data of the current cell, and can be... Figure 3 The "xt" is the second input data. The second input data can be the output data of the previous unit, and can be... Figure 3 The output value is "ht-1".

[0068] The IO buffer 420 can receive a first calculation result value, a second calculation result value, and a third calculation result value provided from the PE array 410. The first calculation result value can be the result of calculation on the first input data and the third input data as the weight value of the first input data. The second calculation result value can be the result of calculation on the second input data and the fourth input data as the weight value of the second input data. The third calculation result value can indicate the result value of the deviation calculation.

[0069] If data is provided directly from PE array 410 to gate buffer 440, the transmission of the first, second, and third calculated values ​​from IO buffer 420 to gate buffer 440 can be omitted.

[0070] The weight buffer block 430 can provide the third input data and the fourth input data to the PE array 410 in a second direction (i.e., direction ② in FIG. 11). Figure 4 The third input data can be a weight value of the first input data. The fourth input data can be a weight value of the second input data.

[0071] The PE controller 480 can be configured to control the entire operation of the accelerator 400 and determine one of the first calculation method and the second calculation method as the calculation method based on at least one or more of a result value of comparing the batch size with the batch reference value, a result value of comparing the sequence size with the sequence reference value, and a combination of the result values.

[0072] According to the first calculation method, the first input data and the second input data can be input to the PE array 410 based on the batch size. According to the second calculation method, the first input data can be input to the PE array 410 based on the sequence size.

[0073] It is also possible to determine one of the first calculation method and the second calculation method by the host device 100, not by the accelerator 400, which will be described later.

[0074] If the first calculation method is determined as the calculation method, the PE controller 480 can control the first input data or the second input data corresponding to the batch size to be input to the PE array 410 in the first direction.

[0075] For example, referring to Figure 5 If the batch size of the input data is "1" and the sequence size of the input data is "5", the PE controller 480 can input the first input data to the PE array 410 through the IO buffer block 420. Here, the PE controller 480 can input the first input data "xt0t-1", "xt0t", "xt0t+1", "xt0t+2", and "xt0t+3" by repeating 1 / N Util( Figure 5 in "A") 5 times. In the symbol "xt0t-1", "0" indicates a batch and "t-1" indicates a sequence.

[0076] Also, when the second input data (for example, "h0t-1") is input to the PE array 410 through the IO buffer block 420, the PE controller 480 can repeat 1 / N Util( Figure 5 in "A") 5 times.

[0077] In Figure 5In the example, when it takes accelerator 400 time "2t" to perform a calculation on the first and second input data, it may take accelerator 400 time "10t" to perform a calculation using 1 / N Util. Figure 5 (A in the example). Here, time "2t" can be "1t" calculated from "xt" or "1t" calculated from "ht-1".

[0078] If the second calculation method is determined to be this calculation method, the PE controller 480 can control the first input data corresponding to the sequence size to be input into the PE array 410 along the first direction.

[0079] For example, refer to Figure 6 If the batch size of the input data is "1" and the sequence size of the input data is "10", then the PE controller 480 can use the IO buffer block 420 to process the first input data (e.g., "x") at a time. t 0 t-1 “x” t 0 t “x” t 0 t+1 “x” t 0 t+2 “x” t 0 t+3 “x” t 0 t+4 “x” t 0 t+5 “x” t 0 t+6 “x” t 0 t+7 " and "x t 0 t+8 The signal is input to the PE array 410 along the first direction.

[0080] That is, the PE controller 480 can input all the first input data corresponding to the sequence size "10" into the PE array 410 at once. Here, in the symbol "x t 0 t-1 “x” t 0 t “x” t 0t+1”, “x” t 0 t+2 “x” t 0 t+3 “x” t 0 t+4 “x” t 0 t+5 “x” t 0 t+6 “x” t 0t+7 and "x t 0 t+8 In the above Equation 1, "t-1", "t", "t+1", "t+2", "t+3", "t+4", "t+5", "t+6", "t+7", and "t+8" can represent sequences. The calculation can be performed by inputting first input data of different sequences into the PE array 410. In the above Equation 1, the calculation can be performed by inputting the first input data of the sequence "t" into the PE array 410. Figure 6 In the above Equation 2, "N" can be "10". Because "N" is "10", 100% of Util Figure 6 ("B") in the above Equation 2 can be utilized.

[0081] Referring to Figure 7 , when second input data (e.g., h t-1 0 t-1 , h t-1 0 t ,...) is input into the PE array 410 through the IO buffer block 420, the PE controller 480 can repeat 1 / N Util Figure 7 ("C") in the above Equation 2 ten times.

[0082] Referring to Figure 6 and Figure 7 , for the calculation of "x t ", 10 / N Util is utilized once ("1t"), and for the calculation of "h t-1 ", 1 / N Util is utilized ten times ("10t"). Thus, the first input data and the calculation operation on the first input data can be completed in the PE array 410 within a total amount of time 11t.

[0083] Figure 8 is a diagram illustrating a configuration of a gate buffer block based on some embodiments of the disclosed technology.

[0084] The gate buffer block 440 can perform addition processing on the first, second, and third calculation result values provided from the PE array 410, and can store related data. Here, the data provided from the PE array 410 can also be transferred through the IO buffer block 420. That is, the gate buffer block 440 can receive the data provided from the PE array 410 directly from the PE array 410 or through the IO buffer block 420.

[0085] Referring to Figure 8 , the gate buffer block 440 can include a multiplexer (MUX) 443, a gate controller 444, an adder 445, a gate buffer 446, and a gate buffer controller 447.

[0086] The multiplexer 443 can be configured to process data as well as inputs of a first calculation result value, a second calculation result value, and a third calculation result value. Here, the third calculation result value can be input together with the first calculation result value or input separately from the first calculation result value.

[0087] Multiplexer 443 may include a first multiplexer 441 and a second multiplexer 442. The first multiplexer 441 may selectively input at least one or more of a first calculation result value, a second calculation result value, and a third calculation result value provided from PE array 410 into adder 445. The second multiplexer 442 may selectively input one of the data "0" and the data fed back from gate buffer 446 into adder 445.

[0088] The door controller 444 can be configured as an input of control data.

[0089] Adder 445 can perform addition on the first calculation result value, the second calculation result value, and the third calculation result value.

[0090] The gate buffer 446 can be configured to store at least one or more of the first, second, and third computed values ​​provided from the PE array 410, and the result of adding the first, second, and third computed values.

[0091] like Figure 8 As shown, the gate buffer 446 may include multiple data storage areas (e.g., Figure 8 The data storage areas are "Gate_i", "Gate_f", "Gate_o", and "Gate_g" in the code, and the calculated results can be stored separately in each data storage area under the control of the gate buffer controller 447. It is obvious here that the data storage areas are not limited to "Gate_i", "Gate_f", "Gate_o", and "Gate_g", but can be expanded or reduced according to the operator.

[0092] The gate buffer controller 447 can be configured to control all operations of the gate buffer block 440.

[0093] Figure 9 This is a diagram illustrating the operation of a gate buffer block based on some embodiments of the disclosed technology.

[0094] Figure 9 The operation of gate buffer 440 is shown when the batch size of the input data is "6". An example of the first computation method applied to PE array 410 will be described below.

[0095] Reference Figure 9The gate buffer controller 447 can receive the first calculation result values in the order along the paths "i_GB_nn" (i.e., the path "i_GB_1", the path "i_GB_2",..., the path "i_GB_6") and the second calculation result values in the order along the paths "i_GB_nn" (i.e., the path "i_GB_1", the path "i_GB_2",..., the path "i_GB_6") through the multiplexer 443.

[0096] At the time point "t0", the gate buffer controller 447 can receive the first calculation result values "B0S0_xt", "B1S0_xt", "B2S0_xt", "B3S0_xt", "B4S0_xt", and "B5S0_xt" through the multiplexer 443. In the notation "B0S0_xt", "B" can denote a batch identification, and "S" can denote a sequence identification. That is, the first calculation result value "B0S0_xt" can be batch 0 and sequence 0.

[0097] At the time point "t1", the gate buffer controller 447 can receive the second calculation result values "B0S0_ht-1", "B1S0_ht-1", "B2S0_ht-1", "B3S0_ht-1", "B4S0_ht-1", and "B5S0_ht-1" through the multiplexer 443. Thereafter, the gate buffer controller 447 can receive the first calculation result values and the second calculation result values in a similar manner to the above.

[0098] Figure 10 is a diagram illustrating the operation of the gate buffer block based on some embodiments of the disclosed technology.

[0099] Figure 10 The operation of the gate buffer block 440 when the batch size of the input data is "1" is illustrated. Hereinafter, an example of a first calculation method applied to the PE array 410 will be described.

[0100] Referring to Figure 10 The gate buffer controller 447 can receive the first calculation result values through only the path "i_GB_1" and the second calculation result values through only the path "i_GB_1" through the multiplexer 443.

[0101] At the time point "t0", the gate buffer controller 447 can receive the first calculation result values only for "B0S0_xt" through the multiplexer 443. In the notation "B0S0_xt", "B" can denote a batch identification, and "S" can denote a sequence identification. That is, the first calculation result value "B0S0_xt" can be batch 0 and sequence 0.

[0102] At the time point "t1", the gate buffer controller 447 can receive the second calculation result value only for "B0S0_ht-1" through the multiplexer 443. Thereafter, the gate buffer controller 447 can receive the first calculation result value or the second calculation result value only through the path "i_GB_1" in a similar manner as described above. According to the sequence size of the input data, the gate buffer controller 447 can repeat the input processing of the calculation result value by utilizing the path "i_GB_1".

[0103] Figure 11 is a diagram illustrating the operation of the gate buffer block based on some embodiments of the disclosed technology.

[0104] Figure 11 The operation of the gate buffer block 440 when the batch size of the input data is "1" and the sequence size is "6" is illustrated. Hereinafter, an example of the second calculation method applied to the PE array 410 will be described.

[0105] Referring to Figure 11 , the gate buffer controller 447 can receive the first calculation result value through the multiplexer 443 along the order of the paths "i_GB_nn" (i.e., the path "i_GB_1", the path "i_GB_2",..., the path "i_GB_6").

[0106] At the time point "t0", the gate buffer controller 447 can receive the first calculation result values "B0S0_xt", "B0S1_xt", "B0S2_xt", "B0S3_xt", "B0S4_xt", and "B0S5_xt" through the multiplexer 443. In the notation "B0S0_xt", "B" can denote a batch identification, and "S" can denote a sequence identification. That is, the first calculation result value "B0S0_xt" can be batch 0 and sequence 0.

[0107] The gate buffer controller 447 can sequentially receive the second calculation result values through the multiplexer 443. The gate buffer controller 447 can receive the second calculation result value for batch 0 and sequence 0 through the path "i_GB_1" Figure 11 in "③". The gate buffer controller 447 can receive the second calculation result value for batch 0 and sequence 1 through the path "i_GB_2". The gate buffer controller 447 can receive the second calculation result value for batch 0 and sequence 2 through the path "i_GB_3". The gate buffer controller 447 can receive the second calculation result value for batch 0 and sequence 3 through the path "i_GB_4". The gate buffer controller 447 can receive the second calculation result value for batch 0 and sequence 4 through the path "i_GB_5". The gate buffer controller 447 can receive the second calculation result value for batch 0 and sequence 5 through the path "i_GB_6".

[0108] At time point "t1", the gate buffer controller 447 can receive the second calculation result value "B0S0_ht-1" through the multiplexer 443. At time point "t2", the gate buffer controller 447 can receive the second calculation result value "B0S1_ht-1" through the multiplexer 443. At time point "t3", the gate buffer controller 447 can receive the second calculation result value "B0S2_ht-1" through the multiplexer 443. At time point "t4", the gate buffer controller 447 can receive the second calculation result value "B0S3_ht-1" through the multiplexer 443. At time point "t5", the gate buffer controller 447 can receive the second calculation result value "B0S4_ht-1" through the multiplexer 443. At time point "t6", the gate buffer controller 447 can receive the second calculation result value "B0S5_ht-1" through the multiplexer 443.

[0109] The gate buffer controller 447 can separately store the first calculation result values and the second calculation result values provided through the multiplexer 443 in the gate buffers 446 according to the respective sequences.

[0110] For example, the gate buffer controller 447 can separately store the first calculation result values and the second calculation result values in the respective gate buffers "Gate Buffer 1", "Gate Buffer 2", "Gate Buffer 3", "Gate Buffer 4", "Gate Buffer 5", and "Gate Buffer 6". It is obvious that the second calculation result values can also be separately stored.

[0111] Further, the gate buffer controller 447 can separately store the first to third calculation result values in the respective gate buffers "Gate Buffer 1", "Gate Buffer 2", "Gate Buffer 3", "Gate Buffer 4", "Gate Buffer 5", and "Gate Buffer 6". In each of the gate buffers "Gate Buffer 1", "Gate Buffer 2", "Gate Buffer 3", "Gate Buffer 4", "Gate Buffer 5", and "Gate Buffer 6", the gate buffer controller 447 can further separately store the first to third calculation result values in the respective data storage areas "Gate_i", "Gate_f", "Gate_o", and "Gate_g".

[0112] Referring back to Figure 8 , the gate buffer block 440 can include at least one or more groups each including the multiplexer 443, the gate controller 444, the adder 445, and the gate buffer 446, the number of groups being as many as the number (e.g., "N") of PEs arranged along the second direction (i.e., the direction "②" in Figure 4 ).

[0113] The activation function unit 450 can be configured to perform an activation function process on data obtained by performing calculations and provided from the gate buffer block 440.

[0114] The specific function unit 460 can be configured to perform a specific calculation other than the excitation function processing on the data obtained by performing the excitation function processing to obtain the state value of the current cell and the output value of the current cell.

[0115] The state buffer block 470 can be configured to store the state value of the current cell and the output value of the current cell provided from the excitation function unit 450 and provide the state value of the current cell and the output value of the current cell.

[0116] The data transfer unit 490 can be coupled to each of the IO buffer block 420 and the state buffer block 470. The data transfer unit 490 can transfer data provided from the host device 100 (see Figure 2 ) to the IO buffer block 420. The data transfer unit 490 can transfer data provided from the state buffer block 470 to the host device 100. That is, the PE controller 480 can provide and receive a control signal to and from the host device 100, and the data transfer unit 490 can provide and receive data to and from the host device 100.

[0117] Figure 12 is a diagram illustrating a configuration of a data processing system based on some embodiments of the disclosed technology.

[0118] Referring to Figure 12 , the data processing system 20 can include a host device 100 and a data storage device 200.

[0119] The host device 100 can determine a calculation method and the following method of inputting the first input data and the second input data to the PE (Processing Element) array 410 based on at least one or more among a result value of comparing the batch size with the batch reference value, a result value of comparing the sequence size with the sequence reference value, and a combination of the result values.

[0120] Referring to Figure 12 , the data storage device 200 can include a host interface (IF) block 401, a memory controller 310, an accelerator 400, and a plurality of memory dies 210. Here, the memory controller 310 and the accelerator 400 can be included in a logic die 300 (see Figure 2 ).

[0121] The host IF block 401 can be configured to perform communication between the accelerator 400 and the host device 100.

[0122] The host IF block 401 can serve as an interface between the host device 100 and the data storage device 200 according to a protocol of the host device 100. For example, the host IF block 401 can communicate with the host device 100 through a serial-parallel converter interface protocol. Without being limited thereto, the host IF block 401 can support any protocol capable of communicating with the host device 100 and protocols such as Peripheral Component Interconnect Express (PCI-E), Universal Serial Bus (USB), Universal Flash Storage (UFS), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), and Peripheral Component Interconnect (PCI).

[0123] The memory controller 310 can receive data from an external memory (e.g., a plurality of memory dies 210) to transfer the received data to the accelerator 400.

[0124] The data storage device 200, which will be described later, can receive a computation method from the host device 100 and can determine the computation method by itself by receiving a batch size and a sequence size from the host device 100.

[0125] In an embodiment, the data storage device 200 can include the accelerator 400 configured to control input paths of the first input data and the second input data to the PE array 410 according to a computation method provided from the host device 100. The computation method can include a first computation method and a second computation method. According to the first computation method, the first input data and the second input data are input to the PE array 410 based on a batch size. According to the second computation method, the first input data is input to the PE array 410 based on a sequence size.

[0126] In an embodiment, the data storage device 200 can include the accelerator 400 configured to determine a computation method based on at least one or more between a batch size and a sequence size provided from the host device 100 and to control input paths of the first input data and the second input data to the PE array 410 according to the determined computation method to process a computation. The computation method can include a first computation method and a second computation method. According to the first computation method, the first input data and the second input data are input to the PE array 410 based on a batch size. According to the second computation method, the first input data is input to the PE array 410 based on a sequence size.

[0127] In both cases described above, the accelerator 400, which will be described later, can be applicable to the data storage device 200.

[0128] The accelerator 400 can include a PE array 410, an IO buffer block 420, a weight buffer block 430, a gate buffer block 440, an activation function unit 450, a specific function unit 460, a state buffer block 470, a PE controller 480, and a data transfer unit 490.

[0129] The PE array 410 can include a plurality of PEs.

[0130] The IO buffer block 420 can provide the first input data and the second input data to the PE array 410 in a first direction.

[0131] Also, the IO buffer block 420 can receive the first calculation result value, the second calculation result value, and the third calculation result value provided from the PE array 410 to transfer the first calculation result value, the second calculation result value, and the third calculation result value to the gate buffer block 440. The first calculation result value can be a result of calculating the first input data and the third input data which is a weight value of the first input data. The second calculation result value can be a result of calculating the second input data and the fourth input data which is a weight value of the second input data. The third calculation result value can indicate a result value of bias calculation.

[0132] If data is provided from the PE array 410 directly to the gate buffer block 440, the transfer of the first calculation result value, the second calculation result value, and the third calculation result value from the IO buffer block 420 to the gate buffer block 440 can be omitted.

[0133] The weight buffer block 430 can provide the third input data and the fourth input data to the PE array 410 in a second direction.

[0134] In an embodiment, the PE controller 480 can be configured to control the entire operation of the accelerator 400 according to the calculation method provided from the host device 100.

[0135] In an embodiment, in a case where the data storage device 200 determines the calculation method by itself, the PE controller 480 can be configured to control the entire operation of the accelerator 400 and determine one of the first calculation method and the second calculation method as the calculation method including a method of inputting the first input data and the second input data to the PE array 410 based on at least one or more among a result value of comparing the batch size with the batch reference value, a result value of comparing the sequence size with the sequence reference value, and a combination of the result values.

[0136] When the first calculation method is determined as the calculation method, the PE controller 480 can control the first input data or the second input data corresponding to the batch size to be input to the PE array 410 in the first direction.

[0137] If the second calculation method is determined as the calculation method, the PE controller 480 can control the first input data corresponding to the sequence size to be input to the PE array 410 in the first direction.

[0138] The gate buffer block 440 can perform addition processing on the first calculation result value, the second calculation result value, and the third calculation result value provided from the PE array 410, and can store the related data.

[0139] As will be described below, the function of the gate buffer block 440 can also be implemented within the state buffer block 470. Without being limited thereto, the function of the gate buffer block 440 can also be implemented within the IO buffer block 420.

[0140] The activation function unit 450 can be configured to perform activation function processing on data obtained by performing calculation and provided from the gate buffer block 440.

[0141] The specific function unit 460 can be configured to perform a specific calculation other than the activation function processing on data obtained by performing the activation function processing to obtain a state value of the current unit and an output value of the current unit.

[0142] The state buffer block 470 can be configured to store and provide the state value of the current unit and the output value of the current unit provided from the activation function unit 450.

[0143] The data transfer unit 490 can be coupled to each of the IO buffer block 420 and the state buffer block 470. The data transfer unit 490 can transfer data provided from the host device 100 to the IO buffer block 420. The data transfer unit 490 can transfer data provided from the state buffer block 470 to the host device 100.

[0144] Figure 13 is a flowchart illustrating the operation of an acceleration device based on some embodiments of the disclosed technology.

[0145] The acceleration device 40 can receive a batch size and a sequence size (S101). Here, the batch size and the sequence size can be provided from the host device 100.

[0146] The acceleration device 40 can be configured to determine one of a first calculation method and a second calculation method as a calculation method based on at least one or more among a result value of comparing the batch size with a batch reference value, a result value of comparing the sequence size with a sequence reference value, and a combination of the result values, the calculation method including a method of inputting the first input data and the second input data to the PE array 410.

[0147] According to the first calculation method, the first input data and the second input data are input to the PE array 410 based on a batch size. According to the second calculation method, the first input data is input to the PE array 410 based on a sequence size.

[0148] The acceleration device 40 can determine whether the batch size is smaller than a batch reference value (S103). Here, the batch reference value can be equal to or smaller than a batch size that the PE array 410 can handle, and can be arbitrarily determined by an operator.

[0149] If it is determined in step S103 that the batch size is smaller than the batch reference value, the acceleration device 40 can determine whether the sequence size is greater than a sequence reference value (S105). Here, the sequence reference value can be equal to or smaller than a sequence size that the PE array 410 can handle, and can be arbitrarily determined by an operator.

[0150] If it is determined in step S105 that the sequence size is greater than the sequence reference value, the acceleration device 40 can determine the second calculation method as the calculation method, and can input the first input data corresponding to the sequence size to the PE array 410 in the first direction (S107). Here, the acceleration device 40 can also input the second input data corresponding to the batch size, not the sequence size, to the PE array 410 in the first direction.

[0151] The acceleration device 40 can obtain the state value of the current cell and the output value of the current cell by performing a calculation process using the first input data and the second input data and the weights for the first input data and the second input data, respectively (S109).

[0152] If it is determined in step S103 that the batch size is equal to or greater than the batch reference value, the acceleration device 40 can determine the first calculation method as the calculation method, and can input the first input data or the second input data corresponding to the batch size to the PE array 410 in the first direction (S111).

[0153] Then, the acceleration device 40 can perform step S109.

[0154] Figure 14 is a flowchart showing part of the operation of the acceleration device shown in Figure 13 Figure 14 is a flowchart showing part of the operation of the acceleration device shown in

[0155] The acceleration device 40 can perform a calculation on the first input data and third input data which is a weight value of the first input data to obtain a first calculation result value (S201).

[0156] ​The acceleration device 40 can perform a calculation on the second input data and fourth input data which is a weight value of the second input data to obtain a second calculation result value (S203).

[0157] The acceleration device 40 can perform an addition process on the first calculation result value, the second calculation result value, and a third calculation result value which is a result value of the bias calculation (S205).

[0158] Based on some embodiments of the disclosed technology, a calculation can be separately performed on the first input data, the second input data, and the bias value to obtain the first calculation result value, the second calculation result value, and the third calculation result value, and then a specific calculation such as addition can be performed on the first calculation result value, the second calculation result value, and the third calculation result value. Thus, parallel calculation can be performed within the PE array 410, and an effect that the speed of data calculation within the acceleration device 40 can be improved can be expected.

[0159] The acceleration device 40 can perform an activation function process on a result value obtained by performing the addition (S207).

[0160] The acceleration device 40 can perform a specific calculation other than the deactivation function process on data obtained by performing the activation function process to obtain a state value (e.g., "ct") of the current cell and an output value (e.g., "ht") of the current cell (S209). Figure 3 Figure 3

[0161] Figure 15 is a diagram illustrating a configuration of an acceleration device based on some embodiments of the disclosed technology. Figure 16 is a diagram illustrating in detail a configuration of the state buffer block shown in Figure 15

[0162] Hereinafter, an example in which the state buffer block 470 performs an addition process on the first calculation result value, the second calculation result value, and the third calculation result value and stores data will be described.

[0163] Referring to Figure 15 , the acceleration device 40 can include the accelerator 400 configured to process a calculation by determining a calculation method based on at least one or more between the batch size and the sequence size and by controlling an input path of the first input data and the second input data to the PE array 410 according to the determined calculation method.

[0164] The calculation method can include a first calculation method and a second calculation method. According to the first calculation method, the first input data and the second input data are input to the PE array 410 based on the batch size. According to the second calculation method, the first input data is input to the PE array 410 based on the sequence size.​​​

[0165] The accelerator 400 can include a PE array 410, an IO buffer block 420, a weight buffer block 430, an excitation function unit 450, a specific function unit 460, a state buffer block 470, a PE controller 480, and a data transfer unit 490.

[0166] The PE array 410 can include a plurality of PEs.

[0167] The IO buffer block 420 can provide the first input data and the second input data to the PE array 410 in a first direction.

[0168] The IO buffer block 420 can receive the first calculation result value, the second calculation result value, and the third calculation result value provided from the PE array 410 to transfer the first calculation result value, the second calculation result value, and the third calculation result value to the state buffer block 470. The first calculation result value can be a result of calculating the first input data and the third input data which is a weight value of the first input data. The second calculation result value can be a result of calculating the second input data and the fourth input data which is a weight value of the second input data.

[0169] If data is provided from the PE array 410 directly to the state buffer block 470, the transfer of the first calculation result value, the second calculation result value, and the third calculation result value from the IO buffer block 420 to the state buffer block 470 can be omitted.

[0170] The weight buffer block 430 can provide the third input data and the fourth input data to the PE array 410 in a second direction.

[0171] The PE controller 480 can be configured to control the entire operation of the accelerator 400 and determine one of the first calculation method and the second calculation method as the calculation method including a method of inputting the first input data and the second input data to the PE array 410 based on at least one or more of a result value of comparing the batch size with the batch reference value, a result value of comparing the sequence size with the sequence reference value, and a combination of the result values.

[0172] According to the first calculation method, the first input data and the second input data can be input to the PE array 410 based on the batch size. According to the second calculation method, the first input data can be input to the PE array 410 based on the sequence size.

[0173] If the first calculation method is determined as the calculation method, the PE controller 480 can control the first input data or the second input data corresponding to the batch size to be input to the PE array 410 in the first direction (i.e., the direction "①" in the above-described equation 1). Figure 15 ​

[0174] If the second calculation method is determined as the calculation method, the PE controller 480 can control the first input data corresponding to the sequence size to be input to the PE array 410 in the first direction.

[0175] The state buffer block 470 can perform addition processing on the first calculation result value, the second calculation result value, and the third calculation result value provided from the PE array 410, and can store the related data.

[0176] The state buffer block 470 can receive the first calculation result value, the second calculation result value, and the third calculation result value through the IO buffer block 420 or the special function unit 460. In this case, the IO buffer block 420 or the special function unit 460 can receive the first calculation result value, the second calculation result value, and the third calculation result value provided from the PE array 410 to transfer the first calculation result value, the second calculation result value, and the third calculation result value to the state buffer block 470.

[0177] The state buffer block 470 can store data (e.g., a state value (e.g., "ct") of a current cell and an output value (e.g., "ht") of the current cell) provided from the activation function unit 450, and provide the data (e.g., the state value (e.g., "ct") of the current cell and the output value (e.g., "ht") of the current cell) to the PE array 410. Figure 3

[0178] Figure 3

[0179] Figure 3 Figure 3 Figure 16 Referring to FIG. 4B, the state buffer block 470 can include a multiplexer (MUX) 473, a gate controller 474, an adder 475, a gate buffer 476, and a gate buffer controller 477.

[0180] The multiplexer 473 can be configured to process the input of the data and the first calculation result value, the second calculation result value, and the third calculation result value.

[0181] The multiplexer 473 can include a first multiplexer 471 and a second multiplexer 472. The first multiplexer 471 can selectively input at least one or more among the first calculation result value, the second calculation result value, and the third calculation result value provided from the PE array 410 to the adder 475. The second multiplexer 472 can selectively input one between the data "0" and the data fed back from the gate buffer 476 to the adder 475.

[0182] ​​​​The gate controller 474 can be configured to control the input of data. That is, the gate controller 474 can be configured to control the input of data at the multiplexer 473 and the first calculation result value, the second calculation result value, and the third calculation result value.

[0183] The gate buffer 476 can be configured to store one or more of the first calculation result value, the second calculation result value, and the third calculation result value provided from the PE array 410 and a result of the additive processing of the first calculation result value, the second calculation result value, and the third calculation result value.

[0184] Also, the gate buffer 476 can store a state value (for example, "ct") of the current cell and an output value (for example, "ht") of the current cell. Figure 3 Figure 3

[0185] The adder 475 can perform additive processing of the first calculation result value, the second calculation result value, and the third calculation result value.

[0186] The gate buffer controller 477 can be configured to control the overall operation of the state buffer block 470.

[0187] The gate buffer controller 477 can separately store the first calculation result value and the second calculation result value provided through the multiplexer 473 in the gate buffer 476 according to a corresponding sequence.

[0188] Although not shown, the third calculation result value can be separately input with the first calculation result value and the second calculation result value through the multiplexer 473, and the third calculation result value can be input together with the first calculation result value through the multiplexer 473. The gate buffer controller 477 can separately store the third calculation result value in the gate buffer 476.

[0189] The state buffer block 470 can include at least one or more groups each including the multiplexer 473, the gate controller 474, the adder 475, and the gate buffer 476, the number of groups being as many as the number of PEs disposed in the second direction (that is, the direction "②" in FIG. 4) within the PE array 410. Figure 15

[0190] The state buffer block 470 can be configured to store the state value of the current cell and the output value of the current cell provided from the activation function unit 450 and to provide the state value of the current cell and the output value of the current cell.

[0191] The activation function unit 450 can be configured to perform activation function processing on data obtained by performing calculation and provided from the state buffer block 470.

[0192] ​​​The specific function unit 460 can be configured to perform a specific calculation other than the activation function processing on the data obtained by performing the activation function processing to obtain a state value of the current unit and an output value of the current unit.

[0193] The data transfer unit 490 can be coupled to each of the IO buffer block 420 and the state buffer block 470. The data transfer unit 490 can transfer data provided from the host device 100 (see Figure 2 ) to the IO buffer block 420. The data transfer unit 490 can transfer data provided from the state buffer block 470 to the host device 100.

[0194] Although only specific embodiments are described above as examples. However, the acceleration device, the data storage device, the data processing system, and the operation method of the acceleration device should not be limited based on the described embodiments. Rather, based on the content disclosed in the present patent document, the disclosed embodiments and other embodiments of the acceleration device, the data storage device, the data processing system, and the operation method of the acceleration device can be changed, modified, or enhanced.

Claims

1. An acceleration device comprising: an array of processing elements that outputs a calculation result value for input data; a processing element controller that determines a calculation method based on at least one of a batch size and a sequence size, and controls an input path of the input data to the array of processing elements according to the calculation method, the batch size corresponding to a number of data that the array of processing elements can process at the same time, and the sequence size corresponding to a length of data that is sequentially input to the array of processing elements; and a gate buffer block including: a multiplexer that selectively outputs a value including the calculation result value provided from the array of processing elements, wherein the calculation result value includes a first calculation result value that is a result of a calculation on first input data and third input data corresponding to a weight value of the first input data, a second calculation result value that is a result of a calculation on second input data and fourth input data corresponding to a weight value of the second input data, and a third calculation result value that is a result value of a bias calculation; an adder that performs addition processing on the value output from the multiplexer; and a gate buffer that stores the value output from the adder, the value output from the adder including at least one of the first calculation result value, the second calculation result value, the third calculation result value, and a result of the addition processing on the first calculation result value, the second calculation result value, and the third calculation result value, wherein, when it is determined that the calculation method is a first calculation method, the input data is input into the array of processing elements based on the batch size, and when it is determined that the calculation method is a second calculation method, the input data is input into the array of processing elements based on the sequence size. 2.The acceleration device of claim 1, further comprising: an input / output (IO) buffer block that provides the first input data and the second input data to the array of processing elements in a first direction; and a weight buffer block that provides the third input data and the fourth input data to the array of processing elements in a second direction. 3.The acceleration device of claim 2, when it is determined that the calculation method is the first calculation method, the processing element controller controls the first input data or the second input data corresponding to the batch size to be input to the array of processing elements in the first direction, and wherein, when it is determined that the calculation method is the second calculation method, the processing element controller controls the first input data corresponding to the sequence size to be input to the array of processing elements in the first direction. wherein the processing element controller determines the first calculation method as the calculation method when the batch size is greater than or equal to a batch reference value or the sequence size is less than or equal to a sequence reference value, and determines the second calculation method as the calculation method when the batch size is less than the batch reference value and the sequence size is greater than the sequence reference value. ​ 4. The acceleration device of claim 2, wherein, ​ 5.The accelerator of claim 2, wherein the gate buffer block further comprises: a gate controller that controls the multiplexer. 6.The accelerator of claim 1, wherein the multiplexer comprises: a first multiplexer that selectively outputs at least one among the first computation result value, the second computation result value, and the third computation result value provided from the processing element array to the adder; and a second multiplexer that selectively outputs zero or data fed back from the gate buffer to the adder. 7.The accelerator of claim 5, wherein the processing element array comprises a plurality of processing elements; wherein the gate buffer block comprises at least one group, each group comprising the multiplexer, the gate controller, the adder, and the gate buffer, and wherein the number of the at least one group corresponds to the number of processing elements in the processing element array along the second direction. 8.The accelerator of claim 1, wherein the gate buffer block further comprises a gate buffer controller that separately stores the first computation result value and the second computation result value provided through the multiplexer in the gate buffer. 9.The accelerator of claim 2, further comprising: an activation function unit that performs an activation function process on data provided from the gate buffer block; and a specific function unit that performs a specific computation other than the activation function process on data obtained by performing the activation function process to obtain a state value of a current cell and an output value of the current cell. 10.The accelerator of claim 9, further comprising: a state buffer block that stores the state value of the current cell and the output value of the current cell provided from the activation function unit and provides the state value of the current cell and the output value of the current cell; and a data transfer unit that is coupled to each of the IO buffer block and the state buffer block and transfers data provided from a host device to the IO buffer block or data provided from the state buffer block to the host device. 11.A data processing system comprising: an accelerator comprising a processing element array and a gate buffer block, the processing element array outputting a computation result value for input data, a host device that determines a computation method based on at least one comparison among a comparison between a batch size and a batch reference value and a comparison between a sequence size and a sequence reference value, the batch size corresponding to the number of data that the processing element array can process at the same time, the sequence size corresponding to the length of data that is sequentially input to the processing element array, wherein the accelerator further comprises a gate buffer block, the gate buffer block comprising: ​ a multiplexer that selectively outputs a value including the calculation result value provided from the processing element array, wherein the calculation result value includes a first calculation result value, a second calculation result value, and a third calculation result value, the first calculation result value is a result of calculation on a first input data and a third input data corresponding to a weight value of the first input data, the second calculation result value is a result of calculation on a second input data and a fourth input data corresponding to a weight value of the second input data, and the third calculation result value is a result value of bias calculation; and an adder that performs addition processing on a value output from the multiplexer, wherein the gate buffer stores a value output from the adder, the value output from the adder including at least one of the first calculation result value, the second calculation result value, the third calculation result value, and a result of addition processing on the first calculation result value, the second calculation result value, and the third calculation result value, and wherein, when it is determined that the calculation method is the first calculation method, the input data is input into the processing element array based on the batch size, and when it is determined that the calculation method is the second calculation method, the input data is input into the processing element array based on the sequence size.

12. The data processing system according to claim 11, wherein the accelerator further includes: an input / output (I / O) buffer block that provides the first input data and the second input data to the processing element array in a first direction; a weight buffer block that provides the third input data and the fourth input data to the processing element array in a second direction; and a processing element controller that controls an operation of the accelerator according to the calculation method determined by the host device.

13. The data processing system according to claim 12, wherein when it is determined that the calculation method is the first calculation method, the processing element controller controls the first input data or the second input data corresponding to the batch size to be input to the processing element array in the first direction, and wherein, when it is determined that the calculation method is the second calculation method, the processing element controller controls the first input data corresponding to the sequence size to be input to the processing element array in the first direction.

14. The data processing system according to claim 12, wherein the accelerator further includes: an activation function unit that performs activation function processing on data provided from the gate buffer block; and a specific function unit that performs a specific calculation other than the activation function processing on data obtained by performing the activation function processing to obtain a state value of a current unit and an output value of the current unit.

15. The data processing system according to claim 14, wherein the accelerator further includes: a state buffer block that stores the state value of the current unit and the output value of the current unit provided from the activation function unit, and provides the state value of the current unit and the output value of the current unit; and and a data transfer unit coupled to each of the IO buffer block and the state buffer block and transferring data provided from the host device to the IO buffer block or transferring data provided from the state buffer block to the host device.

16. An operating method of an acceleration device, the operating method comprising: receiving, by a processing element controller, a batch size and a sequence size, the batch size corresponding to a number of data that a processing element array can process at a time, the sequence size corresponding to a length of data that is sequentially input to the processing element array; selecting, by the processing element controller, one of a first calculation method and a second calculation method as a calculation method based on at least one of a comparison between the batch size and a batch reference value and a comparison between the sequence size and a sequence reference value; when it is determined that the calculation method is the first calculation method, inputting, by the processing element controller, input data corresponding to the batch size to the processing element array in a first direction; when it is determined that the calculation method is the second calculation method, inputting, by the processing element controller, input data corresponding to the sequence size to the processing element array in the first direction; and performing, by the processing element array, a calculation process using the input data and weight values, and then outputting a calculation result value, wherein the calculation result value includes a first calculation result value, a second calculation result value, and a third calculation result value, the first calculation result value being a result of calculating first input data and third input data corresponding to a weight value of the first input data, the second calculation result value being a result of calculating second input data and fourth input data corresponding to a weight value of the second input data, and the third calculation result value being a result value of bias calculation, selectively outputting, by a multiplexer, a value including the calculation result value provided from the processing element array; and performing, by an adder, an addition process on a value output from the multiplexer, wherein a value output from the adder is stored in a storage gate buffer, and the value output from the adder includes at least one of the first calculation result value, the second calculation result value, the third calculation result value, and a result of performing the addition process on the first calculation result value, the second calculation result value, and the third calculation result value.

17. The operating method of claim 16, further comprising: performing, by an activation function unit, an activation function process on data obtained by performing the addition process; and performing, by a specific function unit, a specific calculation other than the activation function process on data obtained by performing the activation function process to obtain a state value of a current cell and an output value of the current cell.

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