Access method and memory

Abstract

The present application provides an access method and a memory. The access method is applied to a memory and includes receiving an external data, reading a plurality of first storage units of the memory according to a write address to obtain an original data, comparing the external data with the original data to determine whether a number of the first storage units in which a value is to be changed from a first value to a second value is greater than a preset value, writing the external data to the first storage units when the number of the first storage units in which the value is to be changed from the first value to the second value is not greater than the preset value, and inverting the external data to generate an inverted data and writing the inverted data to the first storage units when the number of the first storage units in which the value is to be changed from the first value to the second value is greater than the preset value.

Description

Technical Field

[0001] This invention relates to an access method, and more particularly to an access method suitable for a memory. Background Technology

[0002] Generally speaking, memory can be divided into volatile memory and non-volatile memory. Common volatile memory includes Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). Non-volatile memory includes Read-Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash memory. Summary of the Invention

[0003] An embodiment of the present invention provides an access method applicable to a memory, comprising: receiving external data; reading a plurality of first storage cells of the memory according to a write address to obtain original data; comparing the external data with the original data to determine whether the number of first storage cells in the first storage cells whose values ​​are to change from a first value to a second value is greater than a preset value; if the number of first storage cells in the first storage cells whose values ​​are to change from the first value to the second value is not greater than the preset value, writing external data to the first storage cells to replace the original data; and if the number of first storage cells in the first storage cells whose values ​​are to change from the first value to the second value is greater than the preset value, inverting the external data to generate inverted data, and writing the inverted data to the first storage cells to replace the original data.

[0004] The access method of the present invention can be implemented by the system of the present invention, which is hardware or firmware capable of performing specific functions, or it can be implemented by incorporating program code into a recording medium and combining it with specific hardware. When the program code is loaded and executed by an electronic device, processor, computer, or machine, the electronic device, processor, computer, or machine becomes a memory for implementing the present invention. Attached Figure Description

[0005] Figure 1 This is a schematic flowchart of the access method of the present invention.

[0006] Figure 2 This is a schematic diagram of the write operation of the present invention.

[0007] Figure 3 This is a schematic diagram of the reading operation of the present invention.

[0008] Figure 4 This is a schematic diagram of the memory structure of the present invention.

[0009] Figure 5A This is a schematic diagram of the storage array of the present invention.

[0010] Figure 5B This is another schematic diagram of the storage array of the present invention.

[0011] Figure 6 This is a schematic diagram of the reading circuit of the present invention.

[0012] Figure 7 This is a schematic diagram of the control circuit of the present invention.

[0013] Figure label:

[0014] S101~S104, S201~S206, S301~S306: Steps;

[0015] 400: Memory

[0016] 402: Decoding circuit

[0017] 404, 500A, 500B: Storage arrays

[0018] 406, 700: Control circuit

[0019] 408, 600: Reading circuit

[0020] ADR: Address

[0021] ADB: Address Control Signal

[0022] WL0~WL N-1 : Word line

[0023] RBL, BL0~BL7, ​​RBL 00 RBL 0,1 BL 00 ~BL 71 Bit line

[0024] RDL, DL0~DL7, RDL 00 RDL 1,1 DL 00 ~DL 71 Data cable

[0025] DIN0~DIN7: External Data

[0026] SD0~SD7: Raw data

[0027] SDU0~SDU7, SDV0~SDV7: Output data

[0028] SC, RDR: Control signals

[0029] IO0~IO7: Channels

[0030] WR: Enable signal

[0031] RD0~RD N-1 RD 00 ~RD N-1,1 Inverted memory unit

[0032] C 0,0 ~C N-1,7 C 0,0,0 ~C N-1,7,1 Storage unit

[0033] 602: Magnification Module

[0034] 604: Inverting module

[0035] 606: Buffer Module

[0036] SA, SA0~SA7: Sensor amplifiers

[0037] MUXB R MUXB0~MUXB7, MUX0~MUX7: Multiplexers

[0038] INV0~INV7, 608, 708: Inverters

[0039] SW0~SW7: Selectors

[0040] BF0~BF7: Buffer

[0041] 702: Comparison Module

[0042] 704: Write to state machine

[0043] 706: Transmission Module

[0044] C0~C7: Comparison Results

[0045] G0~G7: Logic gates

[0046] TWDIN0~TWDIN7: Write data

[0047] SDRD: Amplified Data

[0048] WRD: Write inverted data Detailed Implementation

[0049] To make the objectives, features, and advantages of this invention more apparent and understandable, embodiments are provided below in conjunction with the accompanying drawings for detailed description. This specification provides different embodiments to illustrate the technical features of different implementations of the invention. The configuration of the elements in the embodiments is for illustrative purposes only and is not intended to limit the invention. Furthermore, the repetition of some reference numerals in the embodiments is for simplification and does not imply any correlation between different embodiments.

[0050] Figure 1 This is a flowchart illustrating the access method of the present invention. The access method of the present invention is applicable to a memory. The present invention does not limit the type of memory. The memory may be volatile memory or non-volatile memory. First, an external instruction is received and decoded (step S101). Next, it is determined whether the external instruction is a write instruction (step S102). When the external instruction is a write instruction, a write operation is performed (step S103). However, when the external instruction is not a write instruction, it indicates that the external instruction is a read instruction. Therefore, a read operation is performed (step S104). In this embodiment, the write address and the read address used by the write or read operation are generated by decoding the external instruction in step S101.

[0051] Figure 2 This is a flowchart illustrating the write operation of the present invention. First, external data is received (step S201). The present invention does not limit the format of the external data. In one possible embodiment, the external data is a serial data or a parallel data. Next, according to a write address, a plurality of first storage cells of the memory are read to obtain original data (step S202). In one possible embodiment, the plurality of first storage cells are all coupled to the same word line and coupled to different bit lines. In this embodiment, the number of bits in the original data is the same as the number of bits in the external data.

[0052] The external data is compared with the original data to determine whether the number of first storage units in the first storage unit whose value needs to be changed from a first value to a second value is greater than a preset value (step S203). In this embodiment, the first value is different from the second value. For example, the first value is 0, and the second value is 1. In another possible embodiment, the first value is 1, and the second value is 0. In other embodiments, the preset value is half the total number of bits of the external data. For example, when the external data is four bits, the preset value may be 2.

[0053] When the number of first storage units whose values ​​need to be changed from the first value to the second value is not greater than a preset value, external data is directly written into the first storage unit to replace the original data originally stored in the first storage unit (step S204). For example, suppose the external data is 0001 and the original data is 0000. In this example, since the external data has four bits, the preset value may be 2. At this time, after comparing the external data and the original data, it can be found that only one bit (such as the least significant bit LSB) of the original data needs to be changed from the value 0 (or the first value) to the value 1 (or the second value). Therefore, the external data (such as 0001) is directly written into the first storage unit to replace the original data (0000). At this time, the data stored in the first storage unit is exactly the same as the external data.

[0054] However, if the number of first storage units in the first storage unit whose value needs to be changed from the first value to the second value is greater than a preset value, the external data is inverted to generate inverted data (step S205), and the inverted data is written to the first storage unit to replace the original data (step S206). At this time, the data stored in the first storage unit is inverted compared to the external data. For example, suppose the external data is 1111 and the original data is 0000. In this example, since all four bits of the original data need to be changed from the value 0 to the value 1, the number of storage units whose value needs to be changed is 4, which is greater than the preset value of 2. Therefore, the external data (1111) is inverted to generate inverted data (0000), and the inverted data (0000) is written to the first storage unit. Since the inverted data is the same as the original data (0000) originally stored in the first storage unit, the data in the first storage unit does not need to be changed, thus reducing the number of times the first storage unit is written, thereby extending the life of the first storage unit.

[0055] To indicate whether the data in the first memory cell has been reversed, step S205 further sets the data of the first reversed memory cell to a second value. In this example, the first reversed memory cell is also coupled to the first word line. For example, when the external data is 1111 and the original data is 0000, although the data in the first memory cell is not changed, the data in the first reversed memory cell needs to be set to a second value (such as the value 1) to indicate that the data in the first memory cell is reversed. Therefore, when the user wants to read the data in the first memory cell, a read circuit (not shown) inside the memory first reads the data in the first reversed memory cell to determine whether the data in the first memory cell needs to be reversed. For example, when the data in the first reversed memory cell is the value 1, the read circuit first reverses the data in the first memory cell (0000) and then outputs the reversed data (1111). However, when the data in the first reversed memory cell is the value 0, the read circuit directly outputs the data in the first memory cell.

[0056] In some embodiments, step S204 further sets the data of the first inverted memory cell to a first value (e.g., 0). For example, when the external data is 0001 and the original data is 0000, since only one bit of the original data needs to be changed from the value 0 to the value 1, the external data is directly written to the first memory cell, and the first inverted memory cell is set to the first value to indicate that the data stored in the first memory cell does not need to be inverted. Therefore, when the user wants to read the data of the first memory cell, a read circuit (not shown) directly outputs the data (0001) of the first memory cell according to the data of the first inverted memory cell (e.g., the value 0).

[0057] Figure 3 This is a schematic diagram of the read operation of the present invention. First, according to a read address, multiple second storage cells of the memory are read to obtain a second original data (step S301). In a possible embodiment, the read address is determined by... Figure 1 The decoding in step S101 is generated. In this embodiment, the second memory cell is coupled to the same word line. In other embodiments, the multiple second memory cells read in step S301 may be... Figure 2 The first storage cell written in step S204 or S206.

[0058] According to the read address, a second inverted memory cell is read (step S302). In this embodiment, the second inverted memory cell is coupled to the second memory cell on the same word line. Then, it is determined whether the data in the second inverted memory cell is the second value (step S303). When the data in the second inverted memory cell is not the second value, it means that the second original data has not undergone an inversion process before being stored in the second memory cell. Therefore, the second original data is directly used as a first output data and the first output data is output (step S304).

[0059] However, when the data in the second inverted storage unit is a second value (such as 1), it indicates that the second original data has already undergone an inversion process before being stored in the second storage unit. Therefore, the second original data is inverted (step S305), and the inverted data is used as the first output data and output (step S306).

[0060] Figure 4 This is a schematic diagram of the memory structure of the present invention. As shown, the memory 400 includes a decoding circuit 402, a storage array 404, a control circuit 406, and a read circuit 408. The decoding circuit 402 decodes one address ADR to enable word lines WL0 to WL0. N-1 One of them.

[0061] Memory array 404 has word lines WL0 to WL N-1 And data lines DL0 to DL7. The present invention does not limit the number of data lines. In other embodiments, the storage array 404 has more or fewer data lines. In this embodiment, the storage array 404 further includes multiple storage cells (not shown). Each storage cell is coupled to a single word line and a single data line. In other embodiments, the storage array 404 further includes an inverted data line RDL. In this example, the storage array 404 further includes multiple inverted storage cells (not shown). Each inverted storage cell is coupled to a single word line and an inverted data line RDL.

[0062] The control circuit 406 enters a write mode or a read mode based on the enable signal WR. For example, when the enable signal WR is at a first level (e.g., high level), the control circuit 406 enters a write mode. In write mode, the control circuit 406 receives external data DIN0 to DIN7 and commands the read circuit 408 to read multiple first memory cells of the memory array 404 via a control signal SC. At this time, the read circuit 408 may read data from data lines DL0 to DL7 to provide output data SDV0 to SDV7 to the control circuit 406. The control circuit 406 compares the external data DIN0 to DIN7 with the output data SDV0 to SDV7 to determine whether the number of memory cells in the first memory cells whose values ​​need to change from a first value to a second value is greater than a preset value. If the number of first storage units in the first storage unit whose value needs to be changed from the first value to the second value is not greater than a preset value, the control circuit 406 directly uses the external data DIN0 to DIN7 as write data TWDIN0 to TWDIN7 and writes the write data TWDIN0 to TWDIN7 into the first storage unit through data lines DL0 to DL7. However, if the number of first storage units in the first storage unit whose value needs to be changed from the first value to the second value is greater than the preset value, the control circuit 406 inverts the external data DIN0 to DIN7 to generate inverted data, uses the inverted data as write data TWDIN0 to TWDIN7, and writes the write data TWDIN0 to TWDIN7 into the first storage unit through data lines DL0 to DL7. At this time, the control circuit 406 further sets a first inverted storage unit as the second value through the inverted data line RDL. In this example, the first inverted storage unit is coupled to the plurality of first storage units to the same word line (such as WL0).

[0063] When the enable signal WR is at a second level (e.g., a low level), the control circuit 406 enters a read mode. In read mode, the control circuit 406 reads a second inverted memory cell and determines whether the data in the second inverted memory cell is a second value. When the data in the second inverted memory cell is the second value (e.g., 1), the control circuit 406 uses a control signal RDR to command the read circuit 408 to directly output the data from data lines DL0 to DL7 to channels IO0 to IO7. However, when the data in the second inverted memory cell is not the second value, the control circuit 406, through the control signal RDR, commands the read circuit 408 to directly output the data from data lines DL0 to DL7 to channels IO0 to IO7. In one possible embodiment, when the data in the second inverted memory cell is the second value, the control circuit 406 sets the control signal RDR to a high level. When the data in the second inverted memory cell is the first value, the control circuit 406 sets the control signal RDR to a low level.

[0064] The read circuit 408 determines whether to invert the data on data lines DL0 to DL7 based on the control signal RDR. For example, when the control signal RDR is at a first specific level (e.g., high), the read circuit 408 inverts the data on data lines DL0 to DL7 and outputs the inverted data to channels IO0 to IO7. However, when the control signal RDR is not at the first specific level, the read circuit 408 does not invert the data on data lines DL0 to DL7. In this example, the read circuit 408 directly outputs the data on data lines DL0 to DL7 to channels IO0 to IO7.

[0065] In other embodiments, the read circuit 408 determines whether to provide output data SDV0 to SDV7 to the control circuit 406 based on the control signal SC. For example, when the control signal SC is at a second specific level (e.g., low level), the read circuit 408 does not provide output data SDV0 to SDV7 to the control circuit 406. In this case, the read circuit 408 determines whether to invert the data on data lines DL0 to DL7 based on the control signal RDR. When the control signal SC is not at the second specific level, the read circuit 408 provides output data SDV0 to SDV7 to the control circuit 406. In one possible embodiment, the read circuit 408 has a sample hold circuit to maintain the data on data lines DL0 to DL7.

[0066] Figure 5A This is a schematic diagram of the storage array of the present invention. As shown in the figure, the storage array 500A includes storage cells C. 0,0 ~C N-1,7However, this is not intended to limit the invention. In other embodiments, the memory array 500A has more or fewer memory cells. Each column (horizontal) of memory cells is coupled to the same word line and to different bit lines. For example, memory cell C 0,0 C 0,1 C 0,2 C 0,3 C 0,4 C 0,5 C 0,6 and C 0,7 The word line WL0 is coupled, and each memory cell is coupled to bit lines BL0 through BL7. Furthermore, each row (vertical direction) of memory cell is coupled to the same bit line and to different word lines. For example, memory cell C... 0,0 C 1,0 ..., C N-2,0 and C N-1,0 Coupled to bit line BL0, and respectively coupled to word lines WL0, WL1, ..., WL N-2 and WL N-1 In one possible embodiment, bit lines BL0 to BL7 serve as data lines DL0 to DL7.

[0067] In this embodiment, data from storage cells in the same row is output through the same channel. For example, storage cell C 0,0 C 1,0 ..., C N-2,0 and C N-1,0 The data is output from channel IO0, and the storage unit C 0,1 C 1,1 ..., C N-2,1 and C N-1,1 The data is output from channel IO1, and the storage unit C 0,7 C 1,7 ..., C N-2,7 and C N-1,7 The data is output by channel IO7.

[0068] In other embodiments, the storage array 500A further includes inverted memory cells RD0 to RD0. N-1 Inverted memory cells RD0 to RD0 N-1 Connect word lines WL0 to WL respectively N-1 And coupled to the bit line RBL. The bit line RBL can serve as the inverting data line RDL. In this embodiment, the inverting memory cells RD0 to RD1 are... N-1 The data indicates whether the data in the corresponding memory cell has been inverted. For example, when the data in the inverted memory cell RD0 is the first value (such as 0), it indicates that the memory cell (such as C) coupled to the same word line (i.e., WL0) as the inverted memory cell RD0 is...0,0 C 0,1 C 0,2 C 0,3 C 0,4 C 0,5 C 0,6 and C 0,7 The data in storage unit C has not been inverted. 0,0 C 0,1 C 0,2 C 0,3 C 0,4 C 0,5 C 0,6 and C 0,7 Data can be directly output through channels IO0 to IO7. However, when the data in the inverted memory cell RD0 is the second value (e.g., 1), it indicates that the memory cell (e.g., C) coupled to the same word line (i.e., WL0) as the inverted memory cell RD0 is... 0,0 C 0,1 C 0,2 C 0,3 C 0,4 C 0,5 C 0,6 and C 0,7 The data in storage unit C has been inverted. 0,0 C 0,1 C 0,2 C 0,3 C 0,4 C 0,5 C 0,6 and C 0,7 The data needs to be inverted before it can be output through channels IO0 to IO7.

[0069] Figure 5B This is another schematic diagram of the storage array of the present invention. As shown in the figure, the storage array 500B includes storage cells C. 0,0,0 ~C N-1,7,1 In each column (horizontal direction), each memory cell is coupled to the same word line, but to different bit lines. For example, memory cell C... 0,0,0 C 0,0,1 C 0,1,0 C 0,1,1 ..., C 0,6,0 C 0,6,1 C 0,7,0 and C 0,7,1 Couple word line WL0, and then couple bit line BL. 00 BL 01 BL 10 BL 11 BL 60 BL61 BL 70 BL 71 Furthermore, within each row (vertical direction), each memory cell is coupled to the same bit line, but to different word lines. For example, memory cell C... 0,0,0 C 1,0,0 ..., C N-2,0,0 ~C N-1,0,0 Coupled bit line BL 00 And respectively coupled to word lines WL0 to WL N-1 .

[0070] In this embodiment, the storage array 500B further includes multiplexers MUXB0 to MUXB7. Each of the multiplexers MUXB0 to MUXB7 is coupled to a bit line group, wherein each bit line group has a first bit line and a second bit line. In this example, each of the multiplexers MUXB0 to MUXB7 outputs data from the first or second bit line to the corresponding data line according to an address control signal ADB.

[0071] Taking multiplexers MUXB0 and MUXB7 as examples, the coupling bit line BL of multiplexer MUXB0 00 and BL 01 And according to the address control signal ADB, the bit line BL is output. 00 (or first line) or position line BL 01 The data (or second bit line) is sent to data line DL0. In this example, the data on data line DL0 is output from channel IO0. Additionally, the multiplexer MUXB7 is coupled to bit line BL. 70 and BL 71 And according to the address control signal ADB, the bit line BL is output. 70 (or first line) or position line BL 71 The data (or second bit line) is sent to data line DL7. In this example, the data on data line DL7 is output from channel IO7. In other embodiments, the bit line group coupled to each of multiplexers MUXB0 to MUXB7 may have other numbers of bit lines, such as four, eight, or sixteen bit lines. In this example, each bit line is connected to only one multiplexer.

[0072] In one possible embodiment, the memory array 500B further includes an inverting memory cell RD. 0,0 ~RD N-1,0 RD 0,1 ~RD N-1,1 and multiplexer MUXB R Inverting memory cell RD 0,0 ~RD N-1,0 Coupled bit line RBL 00 And respectively coupled to word lines WL0 to WL N-1Inverting memory cell RD 0,1 ~RD N-1,1 Coupled bit line RBL 01 And respectively coupled to word lines WL0 to WL N-1 Due to the inverted memory cell RD 0,0 ~RD N-1,0 With RD 0,1 ~RD N-1,1 Since they serve the same function, the following only describes the inverting memory cell RD. 0,0 ~RD N-1,0 .

[0073] Coupled bit line RBL 00 Inverted memory cell RD 0,0 ~RD N-1,0 The stored data is used to represent the first bit line (e.g., BL) coupled to multiplexers MUXB0~MUXB7. 00 BL 10 BL 60 and BL 70 Has the data in the storage unit RD undergone an inversion process? 0,0 and RD N-1,0 For example, when the inverted memory cell RD 0,0 When the data is the first value (e.g., 0), it represents the memory location that couples word line WL0 and the first bit line (e.g., C). 0,0,0 C 0,1,0 ..., C 0,6,0 and C 0,7,0 The data in the inverted memory cell RD has not been inverted. Similarly, when the inverted memory cell RD... N-1,0 When the data is the first value, it indicates that the coupling word line WL N-1 and the first line of memory (such as C) N-1,0,0 C N-1,1,0 ..., C N-1,6,0 and C N-1,7,0 The data has not been inverted.

[0074] However, when the inverted memory cell RD 0,0 When the data is the second value (e.g., 1), it represents the memory cell that couples word line WL0 and the first bit line (e.g., C). 0,0,0 C 0,1,0 ..., C 0,6,0 and C 0,7,0 The data is inverted. Similarly, when the inverted memory cell RD... N-1,0 When the data is the second value, it indicates that the coupling word line WL N-1 and the first line of memory (such as C) N-1,0,0 C N-1,1,0 ..., C N-1,6,0 and CN-1,7,0 The data has been inverted.

[0075] In this embodiment, the multiplexer MUXB R Coupled bit line RBL 00 and RBL- 01 MUXB multiplexer R Based on the address control signal ADB, the bit line RBL is output. 00 or RBL 01 The data is sent to the inverting data line RDL. For example, when the address control signal ADB is at a first level (e.g., low), the multiplexer MUXB... R Output bit line RBL 00 The data is sent to the inverting data line RDL. At this time, the multiplexers MUXB0 to MUXB7 output the first bit line (e.g., BL). 00 BL 10 BL 60 and BL 70 Data is sent to data lines DL0-DL7. When the address control signal ADB is at a second level (e.g., high level), the multiplexer MUXB... R Output bit line RBL 01 The data is sent to the inverting data line RDL. At this time, multiplexers MUXB0 to MUXB7 output the second bit line (such as BL) respectively. 01 BL 11 BL 61 Data from BL7 to data lines DL0 to DL7.

[0076] Figure 6This is a schematic diagram of the readout circuit of the present invention. As shown, the readout circuit 600 includes an amplification module 602, an inverting module 604, and a buffer module 606. The amplification module 602 is used to amplify the data on data lines DL0 to DL7. In one possible embodiment, the amplification module 602 includes sense amplifiers SA0 to SA7 and multiplexers MUX0 to MUX7. The sense amplifiers SA0 to SA7 are respectively coupled to data lines DL0 to DL7 and amplify the data on data lines DL0 to DL7 to generate raw data SD0 to SD7. The multiplexers MUX0 to MUX7 determine whether to output the raw data SD0 to SD7 to the control circuit 406 or the inverting module 604 according to the control signal SC. For example, when the control signal SC is at a second specific level (e.g., low level), multiplexers MUX0 to MUX7 use the original data SD0 to SD7 as output data SDU0 to SDU7 and provide the output data SDU0 to SDU7 to the inverting module 604. At this time, the inverting module 604 determines whether to invert the output data SDU0 to SDU7 according to the control signal RDR. When the control signal SC is not at the second specific level, multiplexers MUX0 to MUX7 use the original data SD0 to SD7 as output data SDV0 to SDV7 and provide the output data SDV0 to SDV7 to the control circuit 406. In one possible embodiment, when the control signal SC is not at the second specific level, multiplexers MUX0 to MUX7 provide the output data SDV0 to SDV7 to a sample-and-hold circuit (not shown) to maintain the output data SDV0 to SDV7. Therefore, even if the data on data lines DL0 to DL7 changes, the output data SDV0 to SDV7 remains unchanged.

[0077] The inverter module 604 determines whether to invert the output data SDU0 to SDU7 based on the control signal RDR. For example, when the control signal RDR is equal to a first specific level, the inverter module 604 inverts the output data SDU0 to SDU7 to generate inverted data, which is then output to the buffer module 606. However, when the control signal RDR is not equal to the first specific level, the inverter module 604 does not invert the output data SDU0 to SDU7. In this example, the inverter module 604 directly outputs the data SDU0 to SDU7 to the buffer module 606.

[0078] In this embodiment, the inverter module 604 includes inverters INV0 to INV7 and selectors SW0 to SW7. Inverters INV0 to INV7 are used to invert the output data SDU0 to SDU7. Selectors SW0 to SW7 receive the inverted data generated by inverters INV0 to INV7 and the output data SDU0 to SDU7 provided by multiplexers MUX0 to MUX7, and determine whether to output the inverted data generated by inverters INV0 to INV7 or the output data SDU0 to SDU7 provided by multiplexers MUX0 to MUX7 according to the control signal RDR. For example, when the control signal RDR is equal to a first specific level (such as a high level), selectors SW0 to SW7 output the inverted data generated by inverters INV0 to INV7. When the control signal RDR is not equal to the first specific level, selectors SW0 to SW7 output the output data SDU0 to SDU7 provided by multiplexers MUX0 to MUX7. The present invention does not limit the architecture of selectors SW0 to SW7. In one possible embodiment, each of selectors SW0 to SW7 is a multiplexer.

[0079] In another possible embodiment, each of the selectors SW0 to SW7 has a first transmission gate and a second transmission gate. In this example, the inverting module 604 further includes an inverter 608. Inverter 608 inverts the control signal RDR to generate an inverted signal / RDR. When the control signal RDR is equal to a first specific level (e.g., a high level), since the inverted signal / RDR is not equal to the first specific level, the first transmission gate of selectors SW0 to SW7 is turned on to output the inverted data generated by inverters INV0 to INV7. However, when the control signal RDR is not equal to the first specific level (e.g., the control signal RDR is a low level), since the inverted signal / RDR is equal to the first specific level (e.g., a high level), the second transmission gate of selectors SW0 to SW7 is turned on to output the output data SDU0 to SDU7 of multiplexers MUX0 to MUX7.

[0080] The buffer module 606 is used to amplify the driving capability of the output data of the inverting module 604. In this embodiment, the buffer module 606 includes buffers BF0 to BF7. Buffers BF0 to BF7 amplify the outputs of selectors SW0 to SW7 respectively, and provide the amplified results OD0 to OD7 to channels IO0 to IO7.

[0081] Figure 7This is a schematic diagram of the control circuit of the present invention. As shown, the control circuit 700 includes a comparison module 702, a write state machine 704, and a transmission module 706. The comparison module 702 is used to compare output data SDV0-SDV7 with external data DIN0-DIN7 and generate comparison results C0-C7. In this embodiment, the comparison module 702 includes logic gates G0-G7. Each of the logic gates G0-G7 compares one of the output data SDV0-SDV7 with one of the external data DIN0-DIN7. For example, logic gate G0 compares output data SDV0 with external data DIN0 and generates a comparison result C0. Logic gate G1 compares output data SDV1 with external data DIN1 and generates a comparison result C1. In a possible embodiment, logic gates G0-G7 are mutually exclusive OR gates (XOR).

[0082] The write state machine 704 determines, based on comparison results C0 to C7, whether the number of bits required for the output data SDV0 to SDV7 to change from the first value to the second value is greater than a preset value. When the number of bits required for the output data SDV0 to SDV7 to change from the first value to the second value is not greater than the preset value, the write state machine 704 directly uses the external data DIN0 to DIN7 as the write data TWDIN0 to TWDIN7 and outputs the write data TWDIN0 to TWDIN7 to the transmission module 706. However, when the number of bits required for the output data SDV0 to SDV7 to change from the first value to the second value is greater than the preset value, the write state machine 704 inverts the external data DIN0 to DIN7 and outputs the inverted result as the write data TWDIN0 to TWDIN7 to the transmission module 706.

[0083] In this embodiment, the write state machine 704 further reads data from a specific inverted memory cell on the inverted data line RDL via a sensor amplifier SA. The sensor amplifier SA amplifies the data in the specific inverted memory cell and generates an amplified data SDRD. In this example, when the write state machine 704 directly uses external data DIN0 to DIN7 as write data TWDIN0 to TWDIN7, the write state machine 704 determines whether the amplified data SDRD is a first value (e.g., 0). If so, the write state machine 704 may not modify the data in the specific inverted memory cell. However, if the amplified data SDRD is not the first value, the write state machine 704 sets the write inverted data WRD to the first value and writes the write inverted data WRD to the specific inverted memory cell.

[0084] In other embodiments, when the write state machine 704 inverts external data DIN0 to DIN7 and uses the inversion result as write data TWDIN0 to TWDIN7, the write state machine 704 determines whether the amplified data SDRD is a second value (e.g., 1). If so, the write state machine 704 may not modify the data in the specific inverted memory cell. However, if the amplified data SDRD is not the second value, the write state machine 704 sets the write inverted data WRD to the second value and writes the write inverted data WRD to the specific inverted memory cell.

[0085] The transmission module 706 determines whether to transmit write data TWDIN0 to TWDIN7 to data lines DL0 to DL7 based on the control signal SC. For example, when the control signal SC is at a second specific level (e.g., low level), the transmission module 706 does not transmit write data TWDIN0 to TWDIN7 to data lines DL0 to DL7, nor does it transmit write inverted data WRD to the inverted data line RDL. When the control signal SC is not at the second specific level (e.g., the control signal SC is high level), the transmission module 706 transmits write data TWDIN0 to TWDIN7 to data lines DL0 to DL7 and transmits write inverted data WRD to the inverted data line RDL.

[0086] This invention does not limit the architecture of the transmission module 706. In one possible embodiment, the transmission module 706 has multiple transmission gates. Each transmission gate is coupled between the write state machine 704 and a single data line. When the control signal SC is not at a second specific level, all transmission gates are turned on to transmit write data TWDIN0 to TWDIN7 to data lines DL0 to DL7. When the control signal SC is at a second specific level (e.g., low level), all transmission gates are turned off to stop transmitting write data TWDIN0 to TWDIN7 to data lines DL0 to DL7. In this example, the control circuit 700 further includes an inverter 708. The inverter 708 inverts the control signal SC and provides the inverted result to the transmission module 706 to control the transmission gates inside the transmission module 706.

[0087] The access method, or a specific form or part thereof, of the present invention may exist in the form of program code. The program code may be stored on physical media, such as floppy disks, optical discs, hard disks, or any other machine-readable (e.g., computer-readable) storage media, or may be a computer program product, not limited to an external form. When the program code is loaded and executed by a machine, such as a computer, that machine becomes a memory used in the present invention. The program code may also be transmitted via some transmission medium, such as wires or cables, optical fibers, or any transmission method. When the program code is received, loaded, and executed by a machine, such as a computer, that machine becomes a memory used in the present invention.

[0088] Unless otherwise defined, all terms herein (including technical and scientific terms) are as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, unless expressly stated otherwise, definitions of terms in general dictionaries should be interpreted as consistent with their meaning in the context of their respective technical fields, and not as idealized or overly formal expressions.

[0089] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods described in the embodiments of the present invention can be implemented in physical embodiments using hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention should be determined by the claims.

Claims

1. An access method, characterized by, A memory access method is suitable for a memory including a first data line, a second data line, a third data line, a fourth data line, a first multiplexer and a second multiplexer, the first multiplexer is coupled to the first data line and the second data line, the second multiplexer is coupled to the third data line and the fourth data line, the memory access method includes: receiving an external data; reading a plurality of first storage units of the memory according to a write address to obtain a first original data; comparing the external data and the first original data to determine whether a number of first storage units in the plurality of first storage units whose values are to be changed from a first value to a second value is greater than a preset value; when the number of first storage units in the plurality of first storage units whose values are to be changed from the first value to the second value is not greater than the preset value, writing the external data to the plurality of first storage units to replace the first original data; when the number of first storage units in the plurality of first storage units whose values are to be changed from the first value to the second value is greater than the preset value, inverting the external data to generate an inverted data, and writing the inverted data to the plurality of first storage units to replace the first original data; and when the number of first storage units in the plurality of first storage units whose values are to be changed from the first value to the second value is greater than the preset value and the values of the plurality of first storage units are completely different from the values of the external data, not changing the data of the plurality of first storage units, wherein when the first multiplexer outputs data of the first data line, the second multiplexer outputs data of the third data line, when the second multiplexer outputs data of the second data line, the second multiplexer outputs data of the fourth data line.

2. The access method of claim 1, wherein, The first value is 0 and the second value is 1.

3. The access method of claim 1, wherein, Further comprising: when the number of first storage units in the plurality of first storage units whose values are to be changed from the first value to the second value is greater than the preset value, setting data of a first inverted storage unit as the second value according to the write address.

4. The access method of claim 3, wherein, The first inverted storage unit and the plurality of first storage units are coupled to a first word line.

5. The access method of claim 3, wherein, Further comprising: when the number of first storage units in the plurality of first storage units whose values are to be changed from the first value to the second value is not greater than the preset value, setting data of the first inverted storage unit as the first value according to the write address.

6. The access method of claim 5, wherein, Further comprising: reading a plurality of second storage units of the memory according to a first read address to obtain a second original data; reading a second inverted storage unit according to the first read address; determining whether data of the second inverted storage unit is the second value; when the data of the second inverted storage unit is the second value, inverting the second original data to generate a first output data; and when the data of the second inverted storage unit is not the second value, taking the second original data as the first output data.

7. The access method of claim 6, wherein, The second inverted storage unit and the plurality of second storage units are coupled to a second word line.

8. The access method of claim 7, wherein, Further comprising: According to a second read address, a plurality of third storage units of the memory are read to obtain a third original data; According to the second read address, a third inverted storage unit is read; It is judged whether the data of the third inverted storage unit is the second value; When the data of the third inverted storage unit is the second value, the third original data is inverted to generate a second output data; and When the data of the third inverted storage unit is not the second value, the third original data is taken as the second output data.

9. The access method of claim 8, wherein, The third inverted storage unit is coupled to the second word line with the plurality of third storage units.

10. The access method of claim 9, wherein, The second inverted storage unit and the third inverted storage unit are coupled to different bit lines.

11. A memory, comprising: It comprises: A memory array comprising: A first data line; A second data line; A third data line; A fourth data line; A first multiplexer coupled to the first data line and the second data line; and A second multiplexer coupled to the third data line and the fourth data line; A read circuit reading a plurality of first storage units of the memory array according to a write address to generate a first original data; and A control circuit comparing an external data with the first original data to judge whether the number of first storage units in the plurality of first storage units whose values are to be changed from a first value to a second value is greater than a preset value; When the number of first storage units in the plurality of first storage units whose values are to be changed from the first value to the second value is not greater than the preset value, the control circuit writes the external data to the plurality of first storage units; When the number of first storage units in the plurality of first storage units whose values are to be changed from the first value to the second value is greater than the preset value, the control circuit inverts the external data to generate an inverted data and writes the inverted data to the plurality of first storage units, When the number of first storage units in the plurality of first storage units whose values are to be changed from the first value to the second value is greater than the preset value and the values of the plurality of first storage units are completely different from the values of the external data, the data of the plurality of first storage units is not changed, When the first multiplexer outputs the data of the first data line, the second multiplexer outputs the data of the third data line, and when the second multiplexer outputs the data of the second data line, the second multiplexer outputs the data of the fourth data line.

12. The memory of claim 11, wherein, The first value is 0 and the second value is 1.

13. The memory of claim 11, wherein, When the number of first storage units in the plurality of first storage units whose values are to be changed from the first value to the second value is greater than the preset value, the control circuit sets the data of a first inverted storage unit in the memory array to the second value according to the write address.

14. The memory of claim 13, wherein, The first inverted storage unit is coupled to a first word line with the plurality of first storage units.

15. The memory of claim 13, wherein, When the number of first storage units in the plurality of first storage units whose values are to be changed from the first value to the second value is not greater than the preset value, the control circuit sets the data of the first inverted storage unit to the first value according to the write address.

16. The memory of claim 15, wherein, The read circuit reads a plurality of second storage units of the storage array according to a first read address to obtain a second original data, the control circuit reads a second inverted storage unit of the storage array according to the first read address, the control circuit judges whether the data of the second inverted storage unit is the second value, when the data of the second inverted storage unit is the second value, the read circuit inverts the second original data to generate a first output data, when the data of the second inverted storage unit is not the second value, the read circuit takes the second original data as the first output data.

17. The memory of claim 16, wherein, The second inverted storage unit and the plurality of second storage units are coupled to a second word line.

18. The memory of claim 17, wherein, The read circuit reads a plurality of third storage units of the storage array according to a second read address to obtain a third original data, the control circuit reads a third inverted storage unit according to the second read address, and judges whether the data of the third inverted storage unit is the second value, when the data of the third inverted storage unit is the second value, the read circuit inverts the third original data to generate a second output data, when the data of the third inverted storage unit is not the second value, the read circuit takes the third original data as the second output data.

19. The memory of claim 18, wherein, The third inverted storage unit and the plurality of third storage units are coupled to the second word line.

20. The memory of claim 19, wherein, The second inverted storage unit and the third inverted storage unit are coupled to different bit lines.

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