Multilevel signal receiver, memory system, and electronic device

Abstract

Multi-level signal receivers, memory systems, and electronic devices are disclosed. The multi-level signal receiver includes a data sampler circuit and a reference voltage generator circuit. The data sampler circuit includes M-1 sense amplifiers that compare a multi-level signal to M-1 reference voltages, the multi-level signal having one of M voltage levels that are different from each other. The data sampler circuit generates a data signal that includes N bits, M is an integer greater than 2, and N is an integer greater than 1. The reference voltage generator circuit generates the M-1 reference voltages. At least two of the M-1 sense amplifiers have different sensing characteristics.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2020-0110031, filed on August 31, 2020, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0002] The example embodiments generally relate to semiconductor integrated circuits, and more specifically to multilevel signal receivers, memory systems, and electronic devices. Background Technology

[0003] Semiconductor memory devices are generally classified into two categories based on whether they retain stored data when disconnected from power. These include volatile memory devices, which lose stored data when power is disconnected, and non-volatile memory devices, which retain stored data when power is disconnected. Volatile memory devices can perform read and write operations at high speed, but the contents stored within them are lost when power is off. Non-volatile memory devices retain their stored contents even when power is off; therefore, non-volatile memory devices can be used to store data that must be retained, regardless of whether the memory device is powered on.

[0004] Recently, with the improvement of semiconductor memory device performance, high communication speeds (or interface speeds) are required between the memory controller and the semiconductor memory device. Therefore, multi-level signaling that transmits multiple bits during a unit interval (UI) has been investigated. Summary of the Invention

[0005] According to one aspect of the disclosure, a multi-level signal receiver is provided, the multi-level signal receiver comprising: a data sampler circuit including M-1 sensing amplifiers configured to compare a multi-level signal with M-1 reference voltages, the data sampler circuit being configured to generate a data signal comprising N bits, the multi-level signal having one of M voltage levels that are different from each other, M being an integer greater than two and N being an integer greater than one; and a reference voltage generator circuit configured to generate the M-1 reference voltages, wherein at least two of the M-1 sensing amplifiers have different sensing characteristics.

[0006] According to another aspect of the disclosure, a memory system is provided, the memory system comprising: a memory controller configured to: generate a multi-level signal based on input data, the multi-level signal having one of M voltage levels that are different from each other, M being an integer greater than two; and a memory device configured to: receive the multi-level signal from the memory controller and compare the multi-level signal with M-1 reference voltages to generate a data signal comprising N bits, N being an integer greater than one, wherein the memory device comprises: a data sampler circuit including M-1 sense amplifiers configured to compare the multi-level signal with the M-1 reference voltages to generate the data signal; and a reference voltage generator circuit configured to generate the M-1 reference voltages, and wherein at least two of the M-1 sense amplifiers have different sensing characteristics.

[0007] According to another aspect of the disclosure, a multi-level signal receiver is provided, the multi-level signal receiver comprising: a data sampler circuit including a first sensing amplifier configured to compare a multi-level signal with a first reference voltage, a second sensing amplifier configured to compare the multi-level signal with a second reference voltage, and a third sensing amplifier configured to compare the multi-level signal with a third reference voltage; the data sampler circuit being configured to generate a data signal comprising two bits, and the multi-level signal having one of a first voltage level, a second voltage level, a third voltage level, and a fourth voltage level, the first voltage level to the fourth voltage level being different from each other; and a reference voltage generator circuit configured to... The system is configured to generate a first reference voltage to a third reference voltage, wherein a first sensing amplifier is configured to compare a multi-level signal with the first reference voltage based on a clock signal to output a first comparison signal, a second sensing amplifier is configured to compare a multi-level signal with the second reference voltage based on a clock signal to output a second comparison signal, and a third sensing amplifier is configured to compare a multi-level signal with the third reference voltage based on a clock signal to output a second comparison signal. At least two of the first to third sensing amplifiers have different sensing characteristics, and the level of the second reference voltage is greater than the level of the first reference voltage, and the level of the third reference voltage is greater than the level of the second reference voltage.

[0008] According to another aspect of the disclosure, an apparatus is provided, the apparatus comprising: M-1 sensing amplifiers configured to: compare a multi-level signal with M-1 reference voltages and output one or more sensing signals; and an output decoder configured to generate an output data signal based on the one or more sensing signals, the output data signal comprising N bits, wherein the multi-level signal has one of M voltage levels that are different from each other, M being an integer greater than two and N being an integer greater than one, and wherein the M-1 sensing amplifiers comprise: a first sensing amplifier having a first voltage threshold; and a second sensing amplifier having a second voltage threshold different from the first voltage threshold. Attached Figure Description

[0009] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a memory system according to one or more example embodiments.

[0011] Figure 2 and Figure 3 It is shown Figure 1 A block diagram of an example memory system.

[0012] Figure 4 This is a block diagram illustrating an example of a memory controller included in a memory system according to one or more example embodiments.

[0013] Figure 5A This illustrates the inclusion of examples according to one or more example embodiments. Figure 1 A block diagram illustrating an example of a semiconductor memory device in a memory system.

[0014] Figure 5B This illustrates the inclusion of examples according to one or more example embodiments. Figure 1 A block diagram of another example of a semiconductor memory device in a memory system.

[0015] Figure 6 and Figure 7 It is a diagram used to describe a data signal generated by a method for generating multi-level signals according to one or more example embodiments.

[0016] Figure 8 This is a block diagram illustrating an example of a transmitter according to one or more example embodiments.

[0017] Figure 9 It is a diagram used to describe a data signal generated by a method for generating multi-level signals according to one or more example embodiments.

[0018] Figure 10This is a block diagram illustrating another example of a transmitter according to an example embodiment.

[0019] Figure 11 This is a block diagram illustrating a multilevel signal receiver according to an example embodiment.

[0020] Figure 12A This illustrates an example embodiment. Figure 11 A block diagram of an example data sampler in a multi-level signal receiver.

[0021] Figure 12B This illustrates one or more example embodiments. Figure 11 A block diagram of another example of a data sampler in a multi-level signal receiver.

[0022] Figure 13 The multi-level signal and reference voltage are shown.

[0023] Figure 14 This is a circuit diagram illustrating an example of a first sense amplifier according to one or more exemplary embodiments.

[0024] Figure 15 This is a circuit diagram illustrating an example of a third sense amplifier according to one or more example embodiments.

[0025] Figure 16 This is a circuit diagram illustrating another example of a third sense amplifier according to one or more example embodiments.

[0026] Figure 17 This is a circuit diagram illustrating another example of a third sense amplifier according to one or more example embodiments.

[0027] Figure 18 This is a circuit diagram illustrating another example of a third sense amplifier according to one or more example embodiments.

[0028] Figure 19 This is a circuit diagram illustrating another example of a third sense amplifier according to one or more example embodiments.

[0029] Figure 20 This illustrates one or more example embodiments. Figure 1 A block diagram of an example memory system.

[0030] Figure 21A , Figure 21B and Figure 21C It is shown that it includes Figure 20 A diagram illustrating an example of the driver circuitry in a transmitter.

[0031] Figure 22This is a flowchart illustrating a method for receiving multilevel signals in a semiconductor memory device according to one or more example embodiments.

[0032] Figure 23 This is a block diagram illustrating a semiconductor memory device according to one or more example embodiments.

[0033] Figure 24 This is a block diagram illustrating a communication system according to one or more example embodiments. Detailed Implementation

[0034] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, which illustrate embodiments. However, the disclosure may be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Throughout this application, the same reference numerals denote the same elements.

[0035] Figure 1 This is a block diagram illustrating a memory system according to one or more example embodiments.

[0036] Reference Figure 1 The memory system 10 includes a memory controller 100 and a semiconductor memory device 200. The memory system 10 may further include multiple signal lines 30 that electrically connect the memory controller 100 and the semiconductor memory device 200.

[0037] Semiconductor memory device 200 is controlled by memory controller 100. For example, based on a request from a host, memory controller 100 may store data (e.g., write or program) into semiconductor memory device 200, or may retrieve (e.g., read or sense) data from semiconductor memory device 200. For example, memory controller 100 may write or program data or information into semiconductor memory device 200, or may read or sense data or information from semiconductor memory device 200.

[0038] The multiple signal lines 30 may include control lines, command lines, address lines, data input / output (I / O) lines, and power lines. The memory controller 100 can send the command CMD, address ADDR, and control signal CTRL to the memory device 200 via the command lines, address lines, and control lines; can exchange data signals MLDAT with the semiconductor memory device 200 via the data I / O lines; and can send the power supply voltage PWR to the semiconductor memory device 200 via the power lines.

[0039] For example, the data signal MLDAT may be a multi-level signal generated and transmitted according to one or more example embodiments. According to example embodiments, the multiple signal lines 30 may also include a DQS line for transmitting a data strobe signal (DQS).

[0040] In some example embodiments, at least a portion or all of the signal lines 30 may be referred to as a channel. As used herein, the term "channel" may refer to a signal line that includes a data I / O line for transmitting the data signal MLDAT. However, the example embodiments are not limited thereto, and a channel may also include a command line for transmitting the command CMD and / or an address line for transmitting the address ADDR.

[0041] Figure 2 and Figure 3 It is shown Figure 1 A block diagram of an example memory system.

[0042] Reference Figure 2 and Figure 3 The memory system 11 includes a memory controller 101, a semiconductor memory device 201, and multiple channels 31a, 31b, and 31c.

[0043] Memory controller 101 may include multiple transmitters 25a, 25b, and 25c, multiple receivers 27a, 27b, and 27c, and multiple data I / O pads 29a, 29b, and 29c. Semiconductor memory device 201 may include multiple transmitters 45a, 45b, and 45c, multiple receivers 47a, 47b, and 47c, and multiple data I / O pads 49a, 49b, and 49c. Although Figures 2 to 3 Three sets of channels, receivers, transmitters, and data I / O pads are shown, but the disclosure is not limited thereto, and various numbers of channels, receivers, transmitters, and data I / O pads may be provided according to other example embodiments.

[0044] Each of the plurality of transmitters 25a, 25b, 25c, 45a, 45b, and 45c can generate a multilevel signal. For example, each of the plurality of transmitters 25a, 25b, 25c, 45a, 45b, and 45c can perform a method for generating a multilevel signal. Each of the plurality of receivers 27a, 27b, 27c, 47a, 47b, and 47c can receive the multilevel signal. The plurality of transmitters 25a, 25b, 25c, 45a, 45b, and 45c and the plurality of receivers 27a, 27b, 27c, 47a, 47b, and 47c can transmit and receive the multilevel signal through multiple channels 31a, 31b, and 31c.

[0045] Each of the multiple data I / O pads 29a, 29b, 29c, 49a, 49b and 49c can be connected to a corresponding one of the multiple transmitters 25a, 25b, 25c, 45a, 45b and 45c and a corresponding one of the multiple receivers 27a, 27b, 27c, 47a, 47b and 47c.

[0046] Multiple channels 31a, 31b and 31c can connect the memory controller 101 to the semiconductor memory device 201.

[0047] Each of the multiple channels 31a, 31b, and 31c can be connected to a corresponding one of the multiple transmitters 25a, 25b, and 25c and a corresponding one of the multiple receivers 27a, 27b, and 27c via a corresponding one of the multiple data I / O pads 29a, 29b, and 29c. Additionally, each of the multiple channels 31a, 31b, and 31c can be connected to a corresponding one of the multiple transmitters 45a, 45b, and 45c and a corresponding one of the multiple receivers 47a, 47b, and 47c via a corresponding one of the multiple data I / O pads 49a, 49b, and 49c. Multilevel signals can be transmitted through each of the multiple channels 31a, 31b, and 31c.

[0048] Figure 2 This illustrates the operation of transferring data from memory controller 101 to semiconductor memory device 201. For example, transmitter 25a can generate an output data signal DS11 as a multi-level signal based on input data DAT11. The output data signal DS11 can be sent from memory controller 101 to memory device 201 via channel 31a, and receiver 47a can receive the output data signal DS11 to obtain data ODAT11 corresponding to input data DAT11.

[0049] Similarly, transmitter 25b can generate an output data signal DS21 as a multi-level signal based on input data DAT21. The output data signal DS21 can be sent to memory device 201 via channel 31b, and receiver 47b can receive the output data signal DS21 to obtain data ODAT21 corresponding to input data DAT21. Transmitter 25c can generate an output data signal DSN1 as a multi-level signal based on input data DATN1. The output data signal DSN1 can be sent to semiconductor memory device 201 via channel 31c, and receiver 47c can receive the output data signal DSN1 to obtain data ODATN1 corresponding to input data DATN1. For example, input data DAT11, input data DAT21, and input data DATN1 can be write data to be written to semiconductor memory device 201.

[0050] Figure 3This illustrates the operation of transferring data from a semiconductor memory device 201 to a memory controller 101. For example, a transmitter 45a can generate an output data signal DS12 as a multi-level signal based on input data DAT12. The output data signal DS12 can be sent from the memory device 201 to the memory controller 101 via channel 31a, and a receiver 27a can receive the output data signal DS12 to obtain data ODAT12 corresponding to the input data DAT12.

[0051] Similarly, transmitter 45b can generate an output data signal DS22 as a multi-level signal based on input data DAT22. The output data signal DS22 can be sent to memory controller 101 via channel 31b, and receiver 27b can receive the output data signal DS22 to obtain data ODAT22 corresponding to input data DAT22. Transmitter 45c can generate an output data signal DSN2 as a multi-level signal based on input data DATN2. The output data signal DSN2 can be sent to memory controller 101 via channel 31c, and receiver 27c can receive the output data signal DSN2 to obtain data ODATN2 corresponding to input data DATN2. For example, input data DAT12, input data DAT22, and input data DATN2 can be read data retrieved from semiconductor memory device 201.

[0052] Figure 4 This is a block diagram illustrating an example of a memory controller included in a memory system according to one or more example embodiments.

[0053] Reference Figure 4 The memory controller 100 may include at least one processor 110, a buffer memory 120, a host interface (I / F) 130, an error correction code (ECC) engine 140, and a memory interface (I / F) 150.

[0054] Processor 110 can control the operation of memory controller 100 in response to commands and / or requests received from an external host via host interface 130. For example, processor 110 can control the operation of memory controller 100 by employing methods for operating memory devices (e.g., Figure 1 The firmware of the semiconductor memory device 200 is used to control the corresponding components.

[0055] Buffer memory 120 may store instructions and data executed and processed by processor 110. For example, buffer memory 120 may be implemented using volatile memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), cache memory, etc.

[0056] The host interface 130 provides a physical connection between the host and the memory controller 100. The host interface 130 provides an interface for communication between the host and the memory controller 100, corresponding to the host's bus format.

[0057] The ECC engine 140 used for error correction can perform coding and modulation using Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc., or can use the codes described above or other error-correcting codes to perform ECC encoding and ECC decoding.

[0058] Memory interface 150 can exchange data with semiconductor memory device 200. Memory interface 150 can send commands and addresses to semiconductor memory device 200, and can send data to semiconductor memory device 200, or receive data read from semiconductor memory device 200. According to an example embodiment, a transmitter that generates multi-level signals according to one or more example embodiments and a receiver that receives multi-level signals may be included in memory interface 150. According to an example embodiment, the transmitter may be... Figure 2 The transmitter 25a shown in the figure can be a receiver. Figure 2 The receiver 27a is shown in the figure.

[0059] Figure 5A This illustrates the inclusion of examples according to one or more example embodiments. Figure 1 A block diagram illustrating an example of a semiconductor memory device in a memory system.

[0060] Reference Figure 5A The semiconductor memory device 200a includes control logic circuitry 210, address register 220, memory bank control logic 230, refresh counter 245, row address (RA) multiplexer (MUX) 240, column address (CA) latch 250, row decoder 260, column decoder 270, memory cell array 300, sense amplifier unit 285, I / O gating circuitry 290, error correction code (ECC) engine 390, on-die termination (ODT) circuitry 297, data I / O buffer 295, and data I / O pad 299.

[0061] According to one or more example embodiments, semiconductor memory device 200a may be a volatile memory device and may include a dynamic random access memory (DRAM) device.

[0062] The memory cell array 300 includes a first memory array 310 to an eighth memory array 380. The row decoder 260 includes first memory cell row decoders 260a to 260h respectively connected to the first memory array 310 to the eighth memory array 380. The column decoder 270 includes first memory cell column decoders 270a to 270h respectively connected to the first memory array 310 to the eighth memory array 380. The sense amplifier unit 285 includes first memory cell sense amplifiers 285a to 285h respectively connected to the first memory array 310 to the eighth memory array 380.

[0063] First memory arrays 310 to 380, first memory row decoders 260a to 260h, first memory column decoders 270a to 270h, and first memory sense amplifiers 285a to 285h can form first to eighth memory arrays. Each of the first memory arrays 310 to 380 includes multiple memory cells MC formed at the intersection of multiple word lines WL and multiple bit lines BTL.

[0064] Address register 220 receives address ADDR from memory controller 100, which includes bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR. Address register 220 provides the received bank address BANK_ADDR to bank control logic 230, the received row address ROW_ADDR to row address multiplexer 240, and the received column address COL_ADDR to column address latch 250.

[0065] The memory bank control logic 230 generates a memory bank control signal in response to the memory bank address BANK_ADDR. One of the first memory bank row decoders 260a to the eighth memory bank row decoder 260h corresponding to the memory bank address BANK_ADDR is activated in response to the memory bank control signal, and one of the first memory bank column decoders 270a to the eighth memory bank column decoder 270h corresponding to the memory bank address BANK_ADDR is activated in response to the memory bank control signal.

[0066] Row address multiplexer 240 receives row address ROW_ADDR from address register 220 and refresh row address REF_ADDR from refresh counter 245. Row address multiplexer 240 selectively outputs row address ROW_ADDR or refresh row address REF_ADDR as row address RA. Row address RA output from row address multiplexer 240 is applied to first memory bank row decoders 260a to eighth memory bank row decoders 260h.

[0067] The refresh counter 245 can sequentially output the refresh row address REF_ADDR under the control of the control logic circuit 210.

[0068] One of the first to eighth bank row decoders 260a, activated by the bank control logic 230, decodes the row address RA output from the row address multiplexer 240 and activates the word line corresponding to the row address RA. For example, the activated bank row decoder applies a word line drive voltage to the word line corresponding to the row address.

[0069] Column address latch 250 receives column address COL_ADDR from address register 220 and temporarily stores the received column address COL_ADDR. In some embodiments, in burst mode, column address latch 250 generates a column address that is incremented from the received column address COL_ADDR. Column address latch 250 applies the temporarily stored or generated column address to first bank column decoders 270a to eighth bank column decoders 270h.

[0070] One of the activated sensor amplifiers in the first to eighth bank column decoders 270a to 270h is activated via I / O gate circuit 290, corresponding to the bank address BANK_ADDR and the column address COL_ADDR.

[0071] I / O gate circuit 290 includes a circuit system for gated input / output data, and also includes input data masking logic, a read data latch for storing data output from the first memory array 310 to the eighth memory array 380, and a write driver for writing data to the first memory array 310 to the eighth memory array 380.

[0072] The codeword CW read from one of the memory arrays 310 to 380 is sensed by a sense amplifier connected to the memory array whose data is being read and stored in a read data latch. After the codeword CW is ECC decoded by the ECC engine 390, the codeword CW stored in the read data latch can be provided to the memory controller 100 via the data I / O buffer 295.

[0073] Data DQ to be written to one of the memory arrays 310 to 380 can be provided from the memory controller 100 to the data I / O buffer 295, and from the data I / O buffer 295 to the ECC engine 390. The ECC engine 390 can perform ECC encoding on the data DQ to generate parity bits. The ECC engine 390 can provide the data DQ and parity bits to the I / O gating circuit 290, which can write the data DQ and parity bits into a subpage in a memory array via a write driver.

[0074] The data I / O buffer 295 can provide a target data signal DQ to the ECC engine 390 during a write operation of the semiconductor memory device 200a, and can provide the data signal DQ from the ECC engine 390 to the memory controller 100 during a read operation of the semiconductor memory device 200a. The data I / O buffer 295 may include a multi-level signal receiver according to an example embodiment, which can decode multi-level data MLDAT into a target data signal and provide the target data signal to the ECC engine 390 during a write operation.

[0075] The ECC engine 390 can perform ECC encoding and ECC decoding on the target data signal DQ under the control of the control logic circuit 210.

[0076] Control logic circuitry 210 can control the operation of semiconductor memory device 200a. For example, control logic circuitry 210 can generate control signals for semiconductor memory device 200a to perform write or read operations. Control logic circuitry 210 includes command decoder 211 for decoding commands CMD received from memory controller 100 and mode register 212 for setting the operating mode of semiconductor memory device 200a.

[0077] For example, the command decoder 211 can generate control signals corresponding to the command CMD by decoding the write enable signal, row address strobe signal, column address strobe signal, chip select signal, etc.

[0078] The ODT circuit 297 can be connected to the data I / O pad 299 and the data I / O buffer 295. When the ODT circuit 297 is enabled, it can perform ODT operation. When ODT operation is performed, the signal integrity of the transmitted / received signals can be enhanced by preventing signal reflections caused by impedance mismatch.

[0079] Although the DRAM-based description includes memory devices in memory systems according to exemplary embodiments, the memory devices according to exemplary embodiments can be any volatile memory device and / or any non-volatile memory device, such as flash memory, phase random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PORRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), transistor random access memory (TRAM), etc.

[0080] Figure 5B This illustrates the inclusion of examples according to one or more example embodiments. Figure 1 A block diagram of another example of a semiconductor memory device in a memory system.

[0081] Reference Figure 5B The semiconductor memory device 200b can be implemented using a non-volatile memory device and may include a memory cell array 630, an address decoder 660, a page buffer circuit 610, a data input / output (I / O) circuit 620, a control circuit 650, a voltage generator 670, and a data I / O pad 690.

[0082] The memory cell array 630 is connected to the address decoder 660 via a serial select line SSL, multiple word lines WL, and a ground select line GSL. Additionally, the memory cell array 630 is connected to the page buffer circuit 610 via multiple bit lines BL. The memory cell array 630 includes multiple non-volatile memory cells connected to the multiple word lines WL and the multiple bit lines BL.

[0083] The control circuit 650 can receive command signals CMD and address signals ADDR from the memory controller 100, and control the erase cycle, programming cycle, and read operation of the non-volatile memory device 200b based on the command signals CMD and ADDR. The erase cycle may include erase operations and erase verification operations, and the programming cycle may include programming operations and programming verification operations.

[0084] For example, control circuit 650 can generate control signal CTL for controlling voltage generator 670 based on command signal CMD, and generate row address R_ADDR and column address C_ADDR based on address signal ADDR. Control circuit 650 can provide row address R_ADDR to address decoder 660, and provide column address C_ADDR to data input / output circuit 620.

[0085] For example, address decoder 660 is connected to memory cell array 630 via serial select line SSL, multiple word lines WL, and ground select line GSL. Address decoder 660 can, during programming and read operations, determine one of the word lines WL as the first word line (selected word line) and the other word lines in WL as unselected word lines based on the row address R_ADDR from control circuitry 650.

[0086] For example, voltage generator 670 uses power PWR to generate word line voltage VWL for the operation of non-volatile memory device 200b based on control signal CTL. Word line voltage VWL is applied to multiple word lines WL by address decoder 660.

[0087] For example, during a programming operation, voltage generator 670 can apply a programming voltage to the selected word line and a programming pass voltage to the unselected word line. Similarly, during a programming verification operation, voltage generator 670 can apply a programming verification voltage to the selected word line and a verification pass voltage to the unselected word line. Furthermore, during a reading operation, voltage generator 670 can apply a reading voltage to the selected word line and a reading pass voltage to the unselected word line.

[0088] For example, page buffer circuit 610 is connected to memory cell array 630 via multiple bit lines BL. Page buffer circuit 610 may include multiple page buffers. In an exemplary embodiment, a page buffer may be connected to one bit line. In other exemplary embodiments, a page buffer may be connected to two or more bit lines.

[0089] Page buffer circuit 610 can temporarily store data to be programmed in a selected page or data read from a selected page. Page buffer circuit 610 is controlled in response to control signal PCTL received from control circuit 650.

[0090] For example, data input / output circuitry 620 is connected to page buffer circuitry 610 via data line DL and to data I / O pad 690. During programming operations, data input / output circuitry 620 may receive multilevel data MLDAT. Data input / output circuitry 620 may include a multilevel signal receiver according to an example embodiment, capable of decoding multilevel data MLDAT into a target data signal, and capable of providing the target data signal to page buffer circuitry 610 based on column address C_ADDR from control circuitry 650.

[0091] In the following sections, various examples of multilevel signaling schemes and various examples of transmitters based on multilevel signaling schemes will be described in detail, including exemplary embodiments. For example, a multilevel signaling scheme according to one or more exemplary embodiments may be a pulse amplitude modulation (PAM) scheme.

[0092] Figure 6 and Figure 7 It is a diagram used to describe a data signal generated by a method for generating multi-level signals according to one or more example embodiments.

[0093] Figure 6 An ideal eye diagram of the data signal generated based on a 4-level scheme is shown. For example, Figure 6 An ideal eye diagram of a four-level pulse amplitude modulation (PAM-4) signal generated based on a four-level pulse amplitude modulation (PAM-4) signaling scheme is shown. Figure 7 It is shown Figure 6 A simplified diagram of the eye diagram.

[0094] Reference Figure 6 Eye diagrams can be used to indicate the quality of signals in high-speed transmissions. For example, an eye diagram can represent four symbols of a signal (e.g., "00", "01", "10", and "11"), each of which can be represented by a corresponding one of different voltage levels (e.g., voltage amplitudes) VL11, VL21, VL31, and VL41. Eye diagrams can provide a healthy visual indication of signal integrity and can also indicate the noise margin of a data signal.

[0095] To generate an eye diagram, an oscilloscope or other computing device samples a digital signal according to a sampling period SP (e.g., a unit interval or bit interval). The sampling period SP can be defined by a clock associated with the transmission of the signal being measured. The oscilloscope or other computing device measures the voltage level of the signal during the sampling period SP to form multiple traces TRC. Various characteristics associated with the measured signal can be determined by superimposing multiple traces TRC.

[0096] Eye diagrams can be used to identify multiple characteristics of communication signals, such as jitter, crosstalk, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof.

[0097] For example, the width W of the eye in an eye diagram can be used to indicate the timing synchronization of the measured signal or the jitter effect of the measured signal. For instance, an eye diagram can indicate the eye opening OP, which represents the peak-to-peak voltage difference between various voltage levels VL11, VL21, VL31, and VL41. The eye opening OP can be related to the voltage tolerances used to distinguish the different voltage levels VL11, VL21, VL31, and VL41 of the measured signal. The eye opening OP can correspond to a reference... Figure 1The voltage range described. For example, an eye diagram can be used to confirm the rise time RT and / or fall time FT of the transition from a first amplitude to a second amplitude. The rise time RT or fall time FT indicates the time required for a transition from one voltage level to another and can be related to or associated with the rising edge and falling edge, respectively. Jitter JT can represent timing errors caused by misalignment of the rise and fall times. Jitter JT may occur when the rising or falling edge occurs at a time different from the ideal time defined by the data clock.

[0098] According to the example embodiment, Figure 7 The diagram shows different first voltage levels VL11, second voltage level VL21, third voltage level VL31 and fourth voltage level VL41 of the data signal as a PAM-4 signal, different first voltage ranges VOH11, second voltage ranges VOH21 and third voltage ranges VOH31 of the data signal, and the voltage swing width VSW1 of the data signal.

[0099] The first voltage level VL11, which is the lowest voltage level, can be lower than the second voltage level VL21. The second voltage level VL21 can be lower than the third voltage level VL31. The third voltage level VL31 can be lower than the fourth voltage level VL41, which is the highest voltage level. Furthermore, the first voltage range VOH11 can represent the difference between the first voltage level VL11 and the second voltage level VL21, the second voltage range VOH21 can represent the difference between the second voltage level VL21 and the third voltage level VL31, the third voltage range VOH31 can represent the difference between the third voltage level VL31 and the fourth voltage level VL41, and the voltage swing width VSW1 can represent the difference between the first voltage level VL11 and the fourth voltage level VL41.

[0100] Figure 8 This is a block diagram illustrating an example of a transmitter according to one or more example embodiments.

[0101] Reference Figure 8 The transmitter 400 includes a multiplexer 410, a first driver 420, and a second driver 440. The transmitter 400 may also include a termination resistor RZQ connected between the data I / O pad 450 and the ground voltage VSS.

[0102] Multiplexer 410 can divide input data DAT1 into a first bit D0 and a second bit D1 based on a four-phase clock signal CK_4P. The first bit D0 can be the least significant bit (LSB) of input data DAT1, and the second bit D1 can be the most significant bit (MSB) of input data DAT1. Multiplexer 410 can provide the second bit D1 to the first driver 420 and can provide the first bit D0 to the second driver 440. According to an example embodiment, multiplexer 410 can be a 4:1 MUX. Although Figure 8 A four-phase clock signal CK_4P and a 4:1 multiplexer are shown, but the disclosure is not limited thereto, and other types of clock signals and multiplexers may be provided according to other example embodiments.

[0103] The first driver 420 includes a plurality of p-channel metal-metal-oxide-semiconductor (PMOS) transistors 421 to 42t connected in parallel between the power supply voltage VDDQ and node N1, and a plurality of n-channel metal-metal-oxide-semiconductor (NMOS) transistors 431 to 43t connected in parallel between node N1 and ground voltage VSS. Here, t is an integer greater than one. A second bit D1 may be applied to each gate of the PMOS transistors 421 to 42t and each gate of the NMOS transistors 431 to 43t.

[0104] The second driver 440 is connected between node N1 and data I / O pad 450. The second driver 440 includes a PMOS transistor 441 and an NMOS transistor 443. PMOS transistor 441 is connected between the power supply voltage VDDQ and node N1, and NMOS transistor 443 is connected between node N1 and ground voltage VSS. The gates of PMOS transistor 441 and NMOS transistor 443 are connected to each other and can receive the first bit D0.

[0105] According to an example embodiment, the first driver 420 includes a plurality of inverters and drives the second bit D1 to the data I / O pad 450, and the second driver 440 drives the first bit D0 to the data I / O pad 450 to generate an output data signal DS1 as a multi-level signal. The data I / O pad 450 can output the output data signal DS1, which can have one of a first voltage level to a fourth voltage level. The output data signal DS1 can correspond to Figure 6 and Figure 7 The data signal in the middle, and may have one of the first voltage level to the fourth voltage level VL11, VL21, VL31 and VL41.

[0106] Figure 9 This is a diagram illustrating a data signal generated according to another example embodiment by a method for generating multi-level signals. (The symbols omitted are likely part of a larger text and cannot be translated.) Figure 7 Repeated description.

[0107] According to the example embodiment, Figure 9 The diagram illustrates different first voltage levels VL12, second voltage level VL22, third voltage level VL32, fourth voltage level VL42, fifth voltage level VL52, sixth voltage level VL62, seventh voltage level VL72, and eighth voltage level VL82 of a data signal generated based on an 8-level scheme; different first voltage ranges VOH12, second voltage range VOH22, third voltage range VOH32, fourth voltage range VOH42, fifth voltage range VOH52, sixth voltage range VOH62, and seventh voltage range VOH72 of the data signal; and the voltage swing width VSW2 of the data signal. For example, the data signal is an 8-level pulse amplitude modulation (PAM-8) signal generated based on an 8-level pulse amplitude modulation (PAM-8) signaling scheme. As described above, selective level changes for adjusting the voltage range and / or voltage swing width can be performed.

[0108] Figure 10 This is a block diagram illustrating another example of a transmitter according to one or more example embodiments.

[0109] Reference Figure 10 Transmitter 460 includes multiplexer 465, first driver 470, second driver 475, and third driver 480. Transmitter 400 may also include a termination resistor RZQ connected between data I / O pad 490 and ground voltage VSS. Multiplexer 465 may be an 8:1 MUX.

[0110] Multiplexer 465 can divide input data DAT2 into three bits: D0, D1, and D2, based on an eight-phase clock signal CK_8P. The first bit, D0, can be the least significant bit (LSB) of input data DAT2, the second bit, D1, can be the center significant bit (CSB) of input data DAT2, and the third bit, D2, can be the most significant bit (MSB) of input data DAT2. Multiplexer 465 can provide the third bit, D2, to the first driver 470, the second bit, D1, to the second driver 475, and the first bit, D0, to the third driver 480.

[0111] The first driver 470 drives the third bit D2 to the data I / O pad 490, the second driver 475 drives the second bit D1 to the data I / O pad 490, and the third driver 480 drives the first bit D0 to the data I / O pad 490. The data I / O pad 490 can output the output data signal DS2, which corresponds to... Figure 9 The data signal in the middle, and can have Figure 9 One of the first voltage level VL12 to the eighth voltage level VL82 shown in the figure.

[0112] Figure 11 This is a block diagram illustrating a multilevel signal receiver according to one or more example embodiments.

[0113] Reference Figure 11 The multilevel signal receiver 500 may include a data sampler 505 and a reference voltage generator 580.

[0114] Data sampler 505 receives a multi-level (data) signal MLDAT having one of M voltage levels that are different from each other, compares the multi-level signal MLDAT with M-1 reference voltages VREF1 to VREF(M-1), and generates a target data signal DQ comprising N bits. For example, the N bits may include the first and second bits. Here, M is an integer greater than two, and N is an integer greater than one. Data sampler 505 may include M-1 sense amplifiers, at least two of which may include different types of sense amplifiers with different sensing characteristics.

[0115] The reference voltage generator 580 can generate M-1 reference voltages VREF1 to VREF(M-1) and can provide the M-1 reference voltages VREF1 to VREF(M-1) to the data sampler 505.

[0116] Figure 12A This illustrates an example embodiment. Figure 11 A block diagram of an example data sampler 505 in a multi-level signal receiver 500, wherein it is assumed that M is four and N is two. However, the disclosure is not limited thereto, and therefore, according to another example embodiment, M can be any integer greater than two, and N can be an integer greater than one.

[0117] Reference Figure 12A The data sampler 505a may include sense amplifiers (SA) 510, 520 and 530, clock generator 540 and output decoder 550.

[0118] Clock generator 540 generates a clock signal CK and provides the clock signal CK to the first sense amplifiers through the third sense amplifiers 510, 520, and 530. According to an example embodiment, clock generator 540 may generate a double data rate (DDR) clock signal, a quad-phase clock signal, or an eight-phase clock signal.

[0119] The first sensing amplifier 510 compares the multi-level signal MLDAT with the first reference voltage VREF1 based on the clock signal CK, and outputs the first comparison signal CS1 to the output decoder 550. The second sensing amplifier 520 compares the multi-level signal MLDAT with the second reference voltage VREF2 based on the clock signal CK, and outputs the second comparison signal CS2 to the output decoder 550. The third sensing amplifier 530 compares the multi-level signal MLDAT with the third reference voltage VREF3 based on the clock signal CK, and outputs the third comparison signal CS3 to the output decoder 550.

[0120] For reference Figure 7 As stated above, when M corresponds to four, the multi-level signal MLDAT can have one of the first to fourth voltage levels VL11, VL21, VL31, and VL41. The first reference voltage VREF1 can be set to a level between the first voltage level VL11 and the second voltage level VL21, the second reference voltage VREF2 can be set to a level between the second voltage level VL21 and the third voltage level VL31, and the third reference voltage VREF3 can be set to a level between the third voltage level VL31 and the fourth voltage level VL41. Therefore, the second reference voltage VREF2 can have a voltage level greater than that of the first reference voltage VREF1, and the third reference voltage VREF3 can have a voltage level greater than that of the second reference voltage VREF2.

[0121] The output decoder 550 can decode the first comparison signal CS1, the second comparison signal CS2 and the third comparison signal CS3, determine the data bit corresponding to the multi-level signal MLDAT based on the levels of the first comparison signal CS1, the second comparison signal CS2 and the third comparison signal CS3, and output the target data signal DQ indicating the determined data bit.

[0122] For example, when the first comparison signal CS1, the second comparison signal CS2, and the third comparison signal CS3 indicate that the voltage level of the multi-level signal MLDAT is greater than the third reference voltage VREF3, the output decoder 550 can output the target data signal DQ corresponding to "11". For example, when the first comparison signal CS1, the second comparison signal CS2, and the third comparison signal CS3 indicate that the voltage level of the multi-level signal MLDAT is less than the third reference voltage VREF3 and greater than the second reference voltage VREF2, the output decoder 550 can output the target data signal DQ corresponding to "10".

[0123] For example, when the first comparison signal CS1, the second comparison signal CS2, and the third comparison signal CS3 indicate that the voltage level of the multi-level signal MLDAT is less than the second reference voltage VREF2 and greater than the first reference voltage VREF1, the output decoder 550 can output the target data signal DQ corresponding to "01". For example, when the first comparison signal CS1, the second comparison signal CS2, and the third comparison signal CS3 indicate that the voltage level of the multi-level signal MLDAT is less than the first reference voltage VREF1, the output decoder 550 can output the target data signal DQ corresponding to "00".

[0124] Figure 12B This illustrates an embodiment according to another example. Figure 11 A block diagram of another example of a data sampler 505 in a multi-level signal receiver 500, where it is assumed that M is four and N is two.

[0125] Reference Figure 12B The data sampler 505b may include sense amplifiers 570, 575 and 580, clock generator 540a, latch circuitry 590 and output decoder 595.

[0126] Clock generator 540a can generate a four-phase clock signal CK_4P and provide the clock signal CK_4P to the first sense amplifier to the third sense amplifier 570, 575 and 580 and the latch circuit 590.

[0127] The first sensing amplifier 570 may include a first sub-sensing amplifier SSA11 to a fourth sub-sensing amplifier SSA14, the second sensing amplifier 575 may include a first sub-sensing amplifier SSA21 to a fourth sub-sensing amplifier SSA24, and the third sensing amplifier 580 may include a first sub-sensing amplifier SSA31 to a fourth sub-sensing amplifier SSA34.

[0128] The latch circuit 590 may include latches LAT11 to LAT14 corresponding to the first sub-sensing amplifier SSA11 to the fourth sub-sensing amplifier SSA14, latches LAT21 to LAT24 corresponding to the first sub-sensing amplifier SSA21 to the fourth sub-sensing amplifier SSA24, and latches LAT31 to LAT34 corresponding to the first sub-sensing amplifier SSA31 to the fourth sub-sensing amplifier SSA34.

[0129] Each of the first sub-sensing amplifiers SSA11 to SSA14 can compare a multi-level signal MLDAT with a first reference voltage VREF1 at each phase of the four-phase clock signal CK_4P, and can provide a corresponding one of the first comparison signals CS11 to CS14 and a corresponding one of the first inverted comparison signals CS11B to CS14B to a corresponding one of the latches LAT11 to LAT14 based on the comparison result. Each of the latches LAT11 to LAT14 can latch a corresponding one of the first comparison signals CS11 to CS14 and a corresponding one of the first inverted comparison signals CS11B to CS14B to output a corresponding latch signal LS11 to LS14. The internal signals of the latches LAT11 to LAT14 can correspond to a differential type and can be fed back to the first sub-sensing amplifiers SSA11 to SSA14. For example, the internal signal of latch LAT11 can be provided to sub-sensing amplifier SSA12, the internal signal of latch LAT12 can be provided to sub-sensing amplifier SSA13, the internal signal of latch LAT13 can be provided to sub-sensing amplifier SSA14, and the internal signal of latch LAT14 can be provided to sub-sensing amplifier SSA11.

[0130] Each of the first sub-sensing amplifiers SSA21 to the fourth sub-sensing amplifiers SSA24 can compare the multi-level signal MLDAT with the second reference voltage VREF2 at each phase of the four-phase clock signal CK_4P, and can provide a corresponding one of the second comparison signals CS21 to CS24 and a corresponding one of the second inverted comparison signals CS21B to CS24B to the corresponding one of the latches LAT21 to LAT24 based on the comparison result. Each of the latches LAT21 to LAT24 can latch a corresponding one of the second comparison signals CS21 to CS24 and a corresponding one of the second inverted comparison signals CS21B to CS24B to output a corresponding latch signal LS21 to LS24. The internal signals of the latches LAT21 to LAT24 can correspond to a differential type and can be fed back to the first sub-sensing amplifiers SSA21 to the fourth sub-sensing amplifiers SSA24. For example, the internal signal of latch LAT21 can be provided to sub-sensor amplifier SSA22, the internal signal of latch LAT22 can be provided to sub-sensor amplifier SSA23, the internal signal of latch LAT23 can be provided to sub-sensor amplifier SSA24, and the internal signal of latch LAT24 can be provided to sub-sensor amplifier SSA21.

[0131] Each of the first sub-sensing amplifiers SSA31 to the fourth sub-sensing amplifiers SSA34 can compare the multi-level signal MLDAT with the third reference voltage VREF3 at each phase of the four-phase clock signal CK_4P, and based on the comparison result, can provide a corresponding one of the third comparison signals CS31 to CS34 and a corresponding one of the third inverted comparison signals CS31B to CS34B to a corresponding one of the latches LAT31 to LAT34. Each of the latches LAT31 to LAT34 can latch a corresponding one of the third comparison signals CS31 to CS34 and a corresponding one of the third inverted comparison signals CS31B to CS34B to output a corresponding latch signal LS31 to LS34. The internal signals of the latches LAT31 to LAT34 can correspond to a differential type and can be fed back to the first sub-sensing amplifiers SSA31 to the fourth sub-sensing amplifiers SSA34. For example, the internal signal of latch LAT31 can be provided to sub-sensor amplifier SSA32, the internal signal of latch LAT32 can be provided to sub-sensor amplifier SSA33, the internal signal of latch LAT33 can be provided to sub-sensor amplifier SSA34, and the internal signal of latch LAT34 can be provided to sub-sensor amplifier SSA31.

[0132] The output decoder 595 can decode latch signals LS11 to LS14, latch signals LS21 to LS24 and latch signals LS31 to LS34 to output a target data signal DQ indicating the determined data bits.

[0133] Figure 13 The multilevel (PAM-4) signal and reference voltage are shown according to an example embodiment.

[0134] Reference Figure 13 The multi-level signal MLDAT may have one of a first voltage level to a fourth voltage level, VL11, VL21, VL31, and VL41. Furthermore, the first reference voltage VREF1 may be set to a level between the first voltage level VL11 and the second voltage level VL21, the second reference voltage VREF2 may be set to a level between the second voltage level VL21 and the third voltage level VL31, and the third reference voltage VREF3 may be set to a level between the third voltage level VL31 and the fourth voltage level VL41.

[0135] Figure 14 This is a circuit diagram illustrating an example of a first sense amplifier according to one or more exemplary embodiments.

[0136] Reference Figure 14The first sensing amplifier 510 may include a first default PMOS transistor to a third default PMOS transistor 511, 512 and 513, a default transmission gate 516, a first default NMOS transistor 514 and a second default NMOS transistor 515.

[0137] The first default PMOS transistor 511 is connected between the power supply voltage VDDQ and the first internal node N11, and has a gate for receiving the clock signal CK. The second default PMOS transistor 512 is connected between the first internal node N11 and the second internal node N12, and has a gate for receiving the multi-level signal MLDAT. The third default PMOS transistor 513 is connected between the first internal node N11 and the third internal node N13, and has a gate for receiving the first reference voltage VREF1.

[0138] Default transmission gate 516 is connected between the second internal node N12 and the third internal node N13, and is connected to ground voltage VSS and power supply voltage VDDQ. First default NMOS transistor 514 is connected between the second internal node N12 and ground voltage VSS, and has a gate for receiving clock signal CK. Second default NMOS transistor 515 is connected between the third internal node N13 and ground voltage VDDQ, and also has a gate for receiving clock signal CK.

[0139] The default transmission gate 516 may include a PMOS transistor connected to the power supply voltage VDDQ and an NMOS transistor connected to the ground voltage VSS. The default transmission gate 516 may be replaced with one of the PMOS transistor connected to the power supply voltage VDDQ and the NMOS transistor connected to the ground voltage VSS.

[0140] When the first default PMOS transistor 511 turns on in response to the clock signal CK, the first default NMOS transistor 514 and the second NMOS transistor 515 turn off. Therefore, the current corresponding to the voltage difference between the multi-level signal MLDAT and the first reference voltage VREF1 is provided to the second internal node N12 and the third internal node N13, respectively. Furthermore, the default transmission gate 516 turns on based on the current corresponding to the voltage difference between the multi-level signal MLDAT and the first reference voltage VREF1, and the first sense amplifier 510 can provide a first comparison signal CS1 at the third internal node N13 based on the potential difference between the second internal node N12 and the third internal node N13. When the first default NMOS transistor 514 and the second NMOS transistor 515 turn on in response to the clock signal CK, the second internal node N12 and the third internal node N13 discharge to ground voltage VSS. The above description of the operation of the first sense amplifier 510 can be similarly applied to... Figures 15 to 19The third sensing amplifiers 530a, 530b, 530c, 530d, and 530e are included.

[0141] Therefore, the first sensing amplifier 510 can compare the multi-level signal MLDAT with the first reference voltage VREF1, output the first comparison signal CS1 at the third internal node N13, and output the first inverted comparison signal CS1B at the second internal node N12.

[0142] Figure 12A The second sensing amplifier 520 in the middle may have the same Figure 14 The first sensing amplifier 510 has the same construction. That is, the first type of sensing amplifier may have Figure 14 The structure of the second sensing amplifier 520 is as follows. For example, the main difference between the second sensing amplifier 520 and the first sensing amplifier 510 is that the gate of the third default PMOS transistor in the second sensing amplifier 520 receives the second reference voltage VREF2.

[0143] Figure 15 This is a circuit diagram illustrating an example of a third sense amplifier according to one or more example embodiments.

[0144] Reference Figure 15 The third sensing amplifier 530a may include a first PMOS transistor to a third PMOS transistor 531, 532 and 534, a transmission gate 539, a first NMOS transistor 537 and a second NMOS transistor 538.

[0145] The first PMOS transistor 531 is connected between the power supply voltage VDDQ and the first node N21, and has a gate for receiving the clock signal CK. The second PMOS transistor 532 is connected between the first node N21 and the second node N22, and has a gate for receiving the multi-level signal MLDAT. The third PMOS transistor 534 is connected between the first node N21 and the third node N23, and has a gate for receiving the third reference voltage VREF3.

[0146] Transmission gate 539 is connected between the second node N22 and the third node N23, and is connected to ground voltage VSS and power supply voltage VDDQ. A first NMOS transistor 537 is connected between the second node N22 and ground voltage VSS, and has a gate for receiving clock signal CK. A second NMOS transistor 538 is connected between the third node N23 and ground voltage VDDQ, and also has a gate for receiving clock signal CK. Transmission gate 539 may include a PMOS transistor connected to power supply voltage VDDQ and an NMOS transistor connected to ground voltage VSS. Transmission gate 539 may be replaced with one of the PMOS transistor connected to power supply voltage VDDQ and the NMOS transistor connected to ground voltage VSS.

[0147] Therefore, the third sensing amplifier 530a can compare the multi-level signal MLDAT with the third reference voltage VREF3, output the third comparison signal CS3 at the third node N23, and output the third inverted comparison signal CS3B at the second node N22.

[0148] According to the example embodiment, each threshold voltage of the second PMOS transistor 532 and the third PMOS transistor 534 is less than each threshold voltage of the second default PMOS transistor 512 and the third default PMOS transistor 513. Therefore, based on the difference in threshold voltages, the first sensing amplifier 510 and the third sensing amplifier 530a have a first sensing characteristic and a second sensing characteristic, respectively, relative to the first reference voltage VREF1 and the third reference voltage VREF3.

[0149] A third reference voltage VREF3 is applied to the gate of the third PMOS transistor 534, and a first reference voltage VREF1, whose level is lower than that of the third reference voltage VREF3, is applied to the gate of the third default PMOS transistor 513. If the threshold voltages of the third PMOS transistor 534 and the third default PMOS transistor 513 are the same, the second sensing characteristic of the third sensing amplifier 530a may be worse than the first sensing characteristic of the first sensing amplifier 510.

[0150] Because the threshold voltage of the third PMOS transistor 534 is lower than the threshold voltage of the third default PMOS transistor 513, the third PMOS transistor 534 turns on in response to a voltage level greater than the voltage level at which the third default PMOS transistor 513 turns on, thus enhancing the second sensing characteristic of the third sensing amplifier 530a. The above description of the sensing characteristics can be similarly applied to... Figures 16 to 19 The third sensing amplifiers in the series are 530b, 530c, 530d, and 530e.

[0151] Figure 16 This is a circuit diagram illustrating an example of a third sensing amplifier according to another example embodiment.

[0152] Reference Figure 16 The third sense amplifier 530b may include a first PMOS transistor to a fifth PMOS transistor 531, 532b, 533b and 534b, 535b, a transmission gate 539, a first NMOS transistor 537 and a second NMOS transistor 538.

[0153] The first PMOS transistor 531 is connected between the power supply voltage VDDQ and the first node N21, and has a gate for receiving the clock signal CK. The second PMOS transistor 532b and the third PMOS transistor 533b are connected in parallel between the first node N21 and the second node N22, and have gates for receiving the multi-level signal MLDAT. The fourth PMOS transistor 534b and the fifth PMOS transistor 535b are connected in parallel between the first node N21 and the third node N23, and have gates for receiving the third reference voltage VREF3.

[0154] Transmission gate 539 is connected between the second node N22 and the third node N23, and is connected to ground voltage VSS and power supply voltage VDDQ. A first NMOS transistor 537 is connected between the second node N22 and ground voltage VSS, and has a gate for receiving clock signal CK. A second NMOS transistor 538 is connected between the third node N23 and ground voltage VDDQ, and also has a gate for receiving clock signal CK. Transmission gate 539 may include a PMOS transistor connected to power supply voltage VDDQ and an NMOS transistor connected to ground voltage VSS. Transmission gate 539 may be replaced with one of the PMOS transistor connected to power supply voltage VDDQ and the NMOS transistor connected to ground voltage VSS.

[0155] Therefore, the third sensing amplifier 530b can compare the multi-level signal MLDAT with the third reference voltage VREF3, output the third comparison signal CS3 at the third node N23, and output the third inverted comparison signal CS3B at the second node N22.

[0156] In this embodiment, each threshold voltage of the second to fifth PMOS transistors 532b, 533b and 534b, 535b is less than each threshold voltage of the second default PMOS transistor 512 and the third default PMOS transistor 513. Therefore, based on the difference in threshold voltages, the first sensing amplifier 510 and the third sensing amplifier 530b have a first sensing characteristic and a second sensing characteristic relative to the first reference voltage VREF1 and the third reference voltage VREF3, respectively.

[0157] exist Figure 16 In this configuration, the second PMOS transistor 532b and the third PMOS transistor 533b, which receive the multi-level signal MLDAT, are connected in parallel between the first node N21 and the second node N22. Similarly, the fourth PMOS transistor 534b and the fifth PMOS transistor 535b, which receive the third reference voltage VREF3, are connected in parallel between the first node N21 and the third node N23. Therefore, the channel width along the channel length of the PMOS transistor receiving the third reference voltage VREF3 is increased.

[0158] Figure 17 This is a circuit diagram illustrating an example of a third sense amplifier according to an exemplary embodiment.

[0159] Reference Figure 17 The third sense amplifier 530c may include a first PMOS transistor to a third PMOS transistor 531, 532c and 534c, a transmission gate 539, a first NMOS transistor 537 and a second NMOS transistor 538.

[0160] The first PMOS transistor 531 is connected between the power supply voltage VDDQ and the first node N21, and has a gate for receiving the clock signal CK. The second PMOS transistor 532c is connected between the first node N21 and the second node N22, and has a source connected to the first node N21, a drain connected to the second node N22, a gate for receiving the multi-level signal MLDAT, and a body connected to the first node N21. The third PMOS transistor 534c is connected between the first node N21 and the third node N23, and has a source connected to the first node N21, a drain connected to the third node N23, a gate for receiving the third reference voltage VREF3, and a body connected to the first node N21.

[0161] Transmission gate 539 is connected between the second node N22 and the third node N23, and is connected to ground voltage VSS and power supply voltage VDDQ. A first NMOS transistor 537 is connected between the second node N22 and ground voltage VSS, and has a gate for receiving clock signal CK. A second NMOS transistor 538 is connected between the third node N23 and ground voltage VDDQ, and also has a gate for receiving clock signal CK. Transmission gate 539 may include a PMOS transistor connected to power supply voltage VDDQ and an NMOS transistor connected to ground voltage VSS. Transmission gate 539 may be replaced with one of the PMOS transistor connected to power supply voltage VDDQ and the NMOS transistor connected to ground voltage VSS.

[0162] Therefore, the third sensing amplifier 530c can compare the multi-level signal MLDAT with the third reference voltage VREF3, output the third comparison signal CS3 at the third node N23, and output the third inverted comparison signal CS3B at the second node N22.

[0163] According to the example embodiment, each threshold voltage of the second PMOS transistor 532c and the third PMOS transistor 534c is less than each threshold voltage of the second default PMOS transistor 512 and the third default PMOS transistor 513. Therefore, based on the difference in threshold voltages, the first sensing amplifier 510 and the third sensing amplifier 530c have a first sensing characteristic and a second sensing characteristic, respectively, relative to the first reference voltage VREF1 and the third reference voltage VREF3.

[0164] exist Figure 17 In this configuration, the bodies of the second PMOS transistor 532c and the third PMOS transistor 534c are respectively connected to their sources, and the threshold voltages of the second PMOS transistor 532c and the third PMOS transistor 534c can be reduced. Therefore, the third PMOS transistor 534c turns on in response to a voltage level greater than the voltage level at which the third default PMOS transistor 513 is turned on, and the second sensing characteristic of the third sensing amplifier 530c is enhanced.

[0165] Figure 18 This is a circuit diagram illustrating an example of a third sense amplifier according to an exemplary embodiment.

[0166] Reference Figure 18 The third sense amplifier 530d may include a first PMOS transistor to a third PMOS transistor 531, 532d and 534d, a transmission gate 539, a first NMOS transistor 537 and a second NMOS transistor 538.

[0167] The first PMOS transistor 531 is connected between the power supply voltage VDDQ and the first node N21, and has a gate for receiving the clock signal CK. The second PMOS transistor 532d is connected between the first node N21 and the second node N22, and has a source connected to the first node N21, a drain connected to the second node N22, a gate for receiving the multi-level signal MLDAT, and a body connected to the bias voltage VB. The third PMOS transistor 534d is connected between the first node N21 and the third node N23, and has a source connected to the first node N21, a drain connected to the third node N23, a gate for receiving the third reference voltage VREF3, and a body connected to the bias voltage VB.

[0168] Transmission gate 539 is connected between the second node N22 and the third node N23, and is connected to ground voltage VSS and power supply voltage VDDQ. A first NMOS transistor 537 is connected between the second node N22 and ground voltage VSS, and has a gate for receiving clock signal CK. A second NMOS transistor 538 is connected between the third node N23 and ground voltage VDDQ, and also has a gate for receiving clock signal CK. Transmission gate 539 may include a PMOS transistor connected to power supply voltage VDDQ and an NMOS transistor connected to ground voltage VSS. Transmission gate 539 may be replaced with one of the PMOS transistor connected to power supply voltage VDDQ and the NMOS transistor connected to ground voltage VSS.

[0169] Therefore, the third sensing amplifier 530d can compare the multi-level signal MLDAT with the third reference voltage VREF3, output the third comparison signal CS3 at the third node N23, and output the third inverted comparison signal CS3B at the second node N22.

[0170] According to the example embodiment, since each of the second PMOS transistor 532d and the third PMOS transistor 534d is connected to the bias voltage VB, each threshold voltage of the second PMOS transistor 532d and the third PMOS transistor 534d is less than each threshold voltage of the second default PMOS transistor 512 and the third default PMOS transistor 513. Therefore, based on the difference in threshold voltages, the first sensing amplifier 510 and the third sensing amplifier 530c have a first sensing characteristic and a second sensing characteristic, respectively, relative to the first reference voltage VREF1 and the third reference voltage VREF3.

[0171] exist Figure 18 In this configuration, each of the second PMOS transistor 532d and the third PMOS transistor 534d is connected to a bias voltage VB, and each threshold voltage of the second PMOS transistor 532d and the third PMOS transistor 534d can be reduced. Therefore, the third PMOS transistor 534d turns on in response to a voltage level greater than the voltage level at which the third default PMOS transistor 513 is turned on, and the second sensing characteristic of the third sensing amplifier 530d is enhanced.

[0172] Figure 19 This is a circuit diagram illustrating an example of a third sense amplifier according to an exemplary embodiment.

[0173] Reference Figure 19 The third sensing amplifier 530c may include a first PMOS transistor 561 and a second PMOS transistor 562, a transmission gate 563, and first NMOS transistors to third NMOS transistors 564, 565 and 566.

[0174] A first PMOS transistor 561 is connected between a first node N31 and a second node N32 connected to the power supply voltage VDDQ, and has a gate for receiving a clock signal CK. A second PMOS transistor 562 is connected between the first node N31 and a third node N33, and also has a gate for receiving the clock signal CK. A transmission gate 563 is connected between the second node N32 and the third node N33, and is connected to ground voltage VSS and the power supply voltage VDDQ. The transmission gate 563 may include a PMOS transistor connected to the power supply voltage VDDQ and an NMOS transistor connected to ground voltage VSS. The transmission gate 563 may be replaced by one of the PMOS transistor connected to the power supply voltage VDDQ and the NMOS transistor connected to ground voltage VSS.

[0175] The first NMOS transistor 564 is connected between the second node N22 and the fourth node N34, and has a gate for receiving the multi-level signal MLDAT. The second NMOS transistor 565 is connected between the third node N33 and the fourth node N34, and has a gate for receiving the third reference voltage VREF3. The third NMOS transistor 566 is connected between the fourth node N34 and the ground voltage VSS, and has a gate for receiving the clock signal CK.

[0176] Therefore, the third sensing amplifier 530e can compare the multi-level signal MLDAT with the third reference voltage VREF3, output the third comparison signal CS3 at the third node N33, and output the third inverted comparison signal CS3B at the second node N32.

[0177] According to the example embodiment, each threshold voltage of the first NMOS transistor 564 and the second NMOS transistor 565 is different from each threshold voltage of the second default PMOS transistor 512 and the third default PMOS transistor 513. Therefore, based on the difference in threshold voltages, the first sensing amplifier 510 and the third sensing amplifier 530c have first sensing characteristics and second sensing characteristics, respectively, relative to the first reference voltage VREF1 and the third reference voltage VREF3.

[0178] exist Figure 19 In the third sense amplifier 530e, since the first NMOS transistor 564 and the second NMOS transistor 565 are included instead of the PMOS transistor, the first NMOS transistor 564 and the second NMOS transistor 565 are easily turned on as the voltage applied to the gate increases. Therefore, the second NMOS transistor 565 turns on in response to a voltage level greater than the voltage level at which the third default PMOS transistor 513 is turned on, and the second sensing characteristic of the third sense amplifier 530e can be enhanced.

[0179] The second type of sensing amplifier may have Figures 15 to 19 One of the constructions. In one example, the second sensing amplifier 520 may include a second type of sensing amplifier.

[0180] Figure 20 This illustrates one or more example embodiments. Figure 1 A block diagram of an example memory system. (The following will be omitted:) Figure 2 and Figure 3 Repeated description.

[0181] Reference Figure 20 The memory system 12 includes a memory controller 102, a semiconductor memory device 202, and a channel 31a.

[0182] The memory controller 102 may include a transmitter 400a. The transmitter 400a includes pull-up / pull-down control circuitry 420 and driver circuitry 440. The transmitter 400a may also include a multiplexer 410 and a data I / O pad 29a.

[0183] Multiplexer 410 can receive input data DAT1 including two bits D0 and D1 or more bits, and a clock signal (e.g., a quad-phase clock signal CK_4P), and can divide the input data DAT1 into two bits D0 and D1 or more bits. Pull-up / pull-down control circuit 420 generates two pull-up control signals PUS1 and PUS2 or more pull-up control signals and two pull-down control signals PDS1 and PDS2 or more pull-down control signals based on the input data DAT1 (e.g., two bits D0 and D1 or more bits). Driver circuit 440 generates an output data signal DS1 as a multi-level signal based on the two pull-up control signals PUS1 and PUS2 or more pull-up control signals and the two pull-down control signals PDS1 and PDS2 or more pull-down control signals. Data I / O pad 29a can output the output data signal DS1.

[0184] The semiconductor memory device 202 may include at least one of a first on-chip termination (ODT) circuit 297a connected between a power supply voltage VDDQ and a data I / O pad 49a, and a second ODT circuit 297b connected between the data I / O pad 49a and a ground voltage VSS. The first ODT circuit 297a may include a first termination resistor RTa, and the second ODT circuit 297b may include a second termination resistor RTb.

[0185] Based on the configuration of the driver circuit 440 and the first ODT circuit 297a and the second ODT circuit 297b, the receiver 47a in the semiconductor memory device 202 can receive multi-level signals according to one of a first type of interface, a second type of interface, and a third type of interface. The first type of interface may correspond to a Low Voltage Swing Terminated Logic (LVSTL) interface, the second type of interface may correspond to a pseudo-open drain interface, and the third type of interface may correspond to a center tap interface.

[0186] When receiver 47a receives a multi-level signal according to the first type of interface, Figure 12A Each of the first sensing amplifier 510 and the second sensing amplifier 520 may employ a sensing amplifier corresponding to the first type. Figure 14 The sensing amplifier 510, Figure 12A The third sensing amplifier 530 in the middle can be a type corresponding to the second type of sensing amplifier. Figures 15 to 19 One of the sensing amplifiers 530a, 530b, 530c, 530d and 530e.

[0187] When receiver 47a receives a multi-level signal according to the second type of interface or the third type of interface, Figure 12A The first sensing amplifier 510 in the middle can be a type corresponding to the first type of sensing amplifier. Figure 14 The sensing amplifier 510, Figure 12A Each of the second sensing amplifier 520 and the third sensing amplifier 530 may be a type of sensing amplifier corresponding to the second type. Figures 15 to 19 One of the sensing amplifiers 530a, 530b, 530c, 530d and 530e.

[0188] Figure 21A , Figure 21B and Figure 21C It is shown that it includes Figure 20 A diagram illustrating an example of the driver circuit 440 in the transmitter.

[0189] Reference Figure 21A The driver circuit 440 may include a first pull-up circuit 441, a second pull-up circuit 443, a first pull-down circuit 444, and a second pull-down circuit 447.

[0190] The first pull-up circuit 441 can pull up the data I / O pad 49a based on the first pull-up control signal PUS1. The second pull-up circuit 443 can pull up the data I / O pad 49a based on the second pull-up control signal PUS2.

[0191] The first pull-down circuit 444 can pull down the data I / O pad 49a based on the first pull-down control signal PDS1. The second pull-down circuit 447 can pull down the data I / O pad 49a based on the second pull-down control signal PDS2.

[0192] In some example embodiments, as described above, the first pull-up control signal PUS1 and the first voltage setting control signal VSU1 can be control signals for the LSB, and the second pull-up control signal PUS2 and the second voltage setting control signal VSU2 can be control signals for the MSB. Therefore, the driving capability of the second pull-up circuit 443 pulling up the data I / O pad 49a can be greater than the driving capability of the first pull-up circuit 441 pulling up the data I / O pad 49a. According to the example embodiment, the driving capability of the second pull-up circuit 443 pulling up the data I / O pad 49a can be approximately twice the driving capability of the first pull-up circuit 441 pulling up the data I / O pad 49a. Similarly, the driving capability of the second pull-down circuit 447 pulling down the data I / O pad 49a can be greater than the driving capability of the first pull-down circuit 444 pulling down the data I / O pad 49a.

[0193] Reference Figure 21B The driver circuit 440a may include a first pull-up circuit 441a, a second pull-up circuit 443a, a first pull-down circuit 444a, and a second pull-down circuit 447a.

[0194] The first pull-up circuit 441a may include a plurality of first pull-up transistors T11, ..., T1X connected in parallel between the power supply voltage and the data I / O pad 49a. The plurality of first pull-up transistors T11, ..., T1X may be selectively turned on based on the first pull-up control signal PUS1.

[0195] The second pull-up circuit 443a may include a plurality of second pull-up transistors T21, T22, ..., T2Y connected in parallel between the power supply voltage and the data I / O pad 49a. The plurality of second pull-up transistors T21, T22, ..., T2Y may be selectively turned on based on the second pull-up control signal PUS2.

[0196] When it is necessary to pull the output data signal DS1 up to the second voltage level VL21, the first pull-up circuit 441a can be enabled or activated by turning on at least some of the plurality of first pull-up transistors T11, ..., T1X based on the first pull-up control signal PUS1. In this case, the second voltage level VL21 can be adjusted by controlling the number (or amount) of the plurality of first pull-up transistors T11, ..., T1X that are turned on. For example, the second voltage level VL21 can increase as the number of the plurality of first pull-up transistors T11, ..., T1X that are turned on increases. Similarly, when it is necessary to pull the output data signal DS1 up to the third voltage level VL31, the second pull-up circuit 443a can be enabled based on the second pull-up control signal PUS2, and the third voltage level VL31 can be adjusted by controlling the number of the plurality of second pull-up transistors T21, T22, ..., T2Y that are turned on. When it is necessary to pull the output data signal DS1 up to the fourth voltage level VL41, both the first pull-up circuit 441a and the second pull-up circuit 443a can be simultaneously activated based on the first pull-up control signal PUS1 and the second pull-up control signal PUS2. The fourth voltage level VL41 can be adjusted by controlling the number of multiple first pull-up transistors T11, ..., T1X and multiple second pull-up transistors T21, T22, ..., T2Y that are turned on. When at least one of the second voltage level VL21, the third voltage level VL31, and the fourth voltage level VL41 is adjusted as described above, the voltage range and voltage swing width can be adjusted.

[0197] The first pull-down circuit 444a may include a plurality of first pull-down transistors T31, ..., T3X connected in parallel between the data I / O pad 49a and the ground voltage. The plurality of first pull-down transistors T31, ..., T3X may be selectively turned on based on the first pull-down control signal PDS1.

[0198] The second pull-down circuit 447a may include a plurality of second pull-down transistors T41, T42, ..., T4Y connected in parallel between the data I / O pad 49a and the ground voltage. The plurality of second pull-down transistors T41, T42, ..., T4Y may be selectively turned on based on the second pull-down control signal PDS2.

[0199] The operation of the first pull-down circuit 444a and the second pull-down circuit 447a can be similar to the operation of the first pull-up circuit 441a and the second pull-up circuit 443a.

[0200] In some example embodiments, transistors T11, ..., T1X, T21, T22, ..., T2Y can be PMOS transistors, and transistors T31, ..., T3X, T41, T42, ..., T4Y can be NMOS transistors. In some example embodiments, the number and / or size of the transistors can be varied so that the driving capabilities of pull-up circuits 441a and 443a are different from the driving capabilities of pull-down circuits 444a and 447a.

[0201] Reference Figure 21C The driver circuit 440b may include first pull-up circuits 441a and 441b, second pull-up circuits 443a and 443b, first pull-down circuits 444a and 444b, and second pull-down circuits 447a and 447b. (The last part, "and," is omitted.) Figure 21B Repeated description.

[0202] and Figure 21B Compared to driver circuit 440a, driver circuit 440b may further include pull-up circuits 441b and 443b and pull-down circuits 444b and 447b. Pull-up circuits 441b and 443b and pull-down circuits 444b and 447b may be similar to pull-up circuits 441a and 443a and pull-down circuits 444a and 447a, respectively. Pull-up circuits 441b and 443b may include pull-up transistors T11b, ..., T1Xb, T21b, T22b, ..., T2Yb that are selectively turned on based on pull-up control signals PUS1b and PUS2b. Pull-down circuits 444a and 447a may include pull-down transistors T31b, ..., T3Xb, T41b, T42b, ..., T4Yb that are selectively turned on based on pull-down control signals PDS1b and PDS2b.

[0203] exist Figure 21A In the middle, when pull-up circuits 441 and 443 and pull-down circuits 444 and 447 include NMOS transistors and Figure 20 When the semiconductor memory device 202 includes the second ODT circuit 297b, the semiconductor memory device 202 can receive multi-level signals according to the LVSTL interface. That is, when the second ODT circuit 297b is enabled, the semiconductor memory device 202 can receive multi-level signals according to the LVSTL interface.

[0204] exist Figure 21A In the middle, when pull-up circuits 441 and 443 and pull-down circuits 444 and 447 include PMOS transistors and Figure 20When the semiconductor memory device 202 includes the first ODT circuit 297a, the semiconductor memory device 202 can receive multi-level signals according to the pseudo-open-drain interface. That is, when the first ODT circuit 297a is enabled, the semiconductor memory device 202 can receive multi-level signals according to the pseudo-open-drain interface.

[0205] exist Figure 21A In the above, when pull-up circuits 441 and 443 include PMOS transistors, and pull-down circuits 444 and 447 include NMOS transistors, and Figure 20 When the semiconductor memory device 202 includes a first ODT circuit 297a and a second ODT circuit 297b, the semiconductor memory device 202 can receive multi-level signals according to the center tap interface. That is, when the first ODT circuit 297a and the second ODT circuit 297b are enabled, the semiconductor memory device 202 can receive multi-level signals according to the center tap interface.

[0206] Figure 22 This is a flowchart illustrating a method for receiving multilevel signals in a semiconductor memory device according to an example embodiment.

[0207] Reference Figures 1 to 22 In a method for receiving a multi-level signal in a semiconductor memory device, a multi-level signal receiver 400 in the semiconductor memory device 200 receives a multi-level signal MLDAT having one of M voltage levels that are different from each other through a channel (operation S100). Here, M is an integer greater than two. Each of the M-1 sense amplifiers in the multi-level signal receiver 400 compares the multi-level signal MLDAT with one of the M-1 reference voltages to generate a corresponding one of the M-1 comparison signals (operation S200). The output decoder 550 in the multi-level signal receiver 400 decodes the M-1 comparison signals, determines the voltage level of the multi-level signal MLDAT based on the decoding, and outputs a target data signal DQ (operation S300).

[0208] Figure 23 This is a block diagram illustrating a semiconductor memory device according to one or more example embodiments.

[0209] Reference Figure 23 The semiconductor memory device 700 may include at least one buffer die 710 and a plurality of memory dies 720-1 to 720-p (p is a natural number equal to or greater than three) that provide soft error analysis and correction functions in a stacked chip structure.

[0210] Multiple memory dies 720-1 to 720-p are stacked on buffer die 710 and data is transmitted through multiple through-silicon via (TSV) lines.

[0211] At least one of the memory dies 720-1 to 720-p may include a memory core for storing data and a cell core ECC engine 723, the cell core ECC engine 723 generating transmission parity bits (i.e., transmission parity data) based on the transmission data to be sent to at least one buffer die 710. The cell core 721 may include a plurality of memory cells having a DRAM cell structure.

[0212] The buffer die 710 may include an ECC engine 712 that, when a transmission error is detected from transmitted data received via the TSV line, the ECC engine 712 uses transmission parity bits to correct the transmission error and generates error-corrected data.

[0213] The buffer die 710 may also include a receiver 713 and a transmitter 714. The receiver 713 may employ... Figure 11 The receiver 500 is a multi-level signal receiver. Therefore, the receiver 713 receives a multi-level signal having one of M voltage levels that are different from each other, and the voltage level of the multi-level signal can be determined by using M-1 sensing amplifiers. At least two of the M-1 sensing amplifiers include a first type of sensing amplifier and a second type of sensing amplifier with different sensing characteristics.

[0214] The semiconductor memory device 700 can be a stacked chip-type memory device or a stacked memory device that transmits data and control signals via TSV lines. TSV lines can also be referred to as "through electrodes".

[0215] The unit core ECC engine 723 can perform error correction on the data output from the memory die 720-p before the data is sent.

[0216] Transmission errors occurring at the data transmission point may be due to noise at the TSV line. Because data failures caused by noise at the TSV line can be distinguished from data failures caused by erroneous operation of the memory die, data failures caused by noise at the TSV line can be considered soft data failures (or soft errors). Soft data failures can be generated by transmission failures on the transmission path and can be detected and remedied through ECC operations.

[0217] Using the above description, a data TSV line group 732 formed at a memory die 720-p may include TSV lines L1 to Lp, and a parity TSV line group 734 may include TSV lines L10 to Lq.

[0218] The TSV lines L1 to Lp of the data TSV line group 732 and the parity TSV lines L10 to Lq of the parity TSV line group 734 can be connected to the microbumps MCB formed respectively between the memory dies 720-1 to 720-p.

[0219] At least one of the memory dies 720-1 to 720-p may include a DRAM cell, each DRAM cell including at least one access transistor and a storage capacitor.

[0220] The semiconductor memory device 700 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with the host via the data bus B10. The buffer die 710 may be connected to the memory controller via the data bus B10.

[0221] The unit core ECC engine 723 can output parity bits and data transmission bits through the parity check TSV line group 734 and the data TSV line group 732, respectively. The output transmission data can be data corrected by the unit core ECC engine 723.

[0222] The ECC engine 712 can determine whether a transmission error has occurred at the point of transmission received via the data TSV line group 732 based on the transmission parity bits received via the parity TSV line group 734. When a transmission error is detected, the ECC engine 712 can use the transmission parity bits to correct the transmission error in the transmitted data. When the transmission error is uncorrectable, the ECC engine 712 can output information indicating the occurrence of an uncorrectable data error.

[0223] Figure 24 This is a block diagram illustrating a communication system according to one or more example embodiments.

[0224] Reference Figure 24 The communication system 800 includes a first communication device 810, a second communication device 830, and a channel 850.

[0225] The first communication device 810 includes a first transmitter 811 and a first receiver 812. The second communication device 830 includes a second transmitter 831 and a second receiver 832. The first transmitter 811 and the first receiver 812 are connected to the second transmitter 831 and the second receiver 832 via a channel 850. In some example embodiments, each of the first communication device 810 and the second communication device 830 may include multiple transmitters and multiple receivers, and the communication system 800 may include multiple channels for connecting the multiple transmitters and multiple receivers.

[0226] Receiver 812 and receiver 832 may be multilevel signal receivers according to one or more example embodiments, capable of receiving multilevel signals having one of M voltage levels that are different from each other, and the voltage level of the multilevel signal may be determined by using M-1 sensing amplifiers.

[0227] The inventive concept can be applied to a wide variety of devices and systems, including memory devices and memory systems. For example, the inventive concept can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0228] The foregoing is a description of exemplary embodiments and should not be construed as limiting the exemplary embodiments. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the exemplary embodiments without substantially departing from the novel teachings and advantages of the exemplary embodiments. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments as defined in the claims. It should be understood that the foregoing is a description of various exemplary embodiments and should not be construed as limiting oneself to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. A multi-level signal receiver, comprising: The data sampler circuit includes M-1 sense amplifiers configured to compare a multi-level signal with M-1 reference voltages. The data sampler circuit is configured to generate a data signal comprising N bits, wherein the multi-level signal has one of M voltage levels that are different from each other, where M is an integer greater than two and N is an integer greater than one. and The reference voltage generator circuit is configured to generate the M-1 reference voltages. Among them, at least two of the M-1 sensing amplifiers have different sensing characteristics. The at least two sensing amplifiers having different sensing characteristics include a first type of sensing amplifier having a first voltage threshold and a second type of sensing amplifier having a second voltage threshold different from the first voltage threshold. Wherein, the first voltage threshold and the second voltage threshold correspond to the voltage thresholds used to turn on the corresponding transistors in the first type of sense amplifier and the second type of sense amplifier.

2. The multi-level signal receiver according to claim 1, wherein, The M voltage levels include a first voltage level, a second voltage level greater than the first voltage level, a third voltage level greater than the second voltage level, and a fourth voltage level greater than the third voltage level; The M-1 reference voltages include a first reference voltage, a second reference voltage, and a third reference voltage; The N bits include the first and second bits; and The level of the second reference voltage is greater than the level of the first reference voltage, and the level of the third reference voltage is greater than the level of the second reference voltage.

3. The multi-level signal receiver according to claim 2, in, The M-1 sensing amplifiers include: A first sensing amplifier is configured to compare a multi-level signal with a first reference voltage based on a clock signal to output a first comparison signal; The second sensing amplifier is configured to: compare a multi-level signal with a second reference voltage based on a clock signal to output a second comparison signal; and The third sensing amplifier is configured to compare a multi-level signal with a third reference voltage based on a clock signal to output a third comparison signal, and The data sampler circuit includes: A clock generator is configured to generate a clock signal; and The output decoder is configured to decode the first comparison signal, the second comparison signal, and the third comparison signal to output a data signal.

4. The multi-level signal receiver according to claim 3, wherein, The multilevel signal receiver receives multilevel signals through a first type of interface: Each of the first sensing amplifier and the second sensing amplifier includes a first type of sensing amplifier having a first sensing characteristic; and The third sensing amplifier includes a second type of sensing amplifier with second sensing characteristics that are different from the first sensing characteristics.

5. The multi-level signal receiver according to claim 4, wherein, The first type of sensing amplifier includes: A first default p-channel metal-oxide-semiconductor PMOS transistor is connected between a power supply voltage and a first internal node, wherein the gate of the first default PMOS transistor receives a clock signal. A second default PMOS transistor is connected between the first internal node and the second internal node, wherein the gate of the second PMOS transistor receives a multi-level signal; A third default PMOS transistor is connected between the first internal node and the third internal node, wherein the gate of the third default PMOS transistor receives one of a first reference voltage and a second reference voltage. The first default transmission gate is connected between the second and third internal nodes and is connected to the ground voltage and the power supply voltage. A first default n-channel metal-oxide-semiconductor (NMOS) transistor is connected between a second internal node and ground voltage, wherein the gate of the first default NMOS transistor receives a clock signal; and The second default NMOS transistor is connected between the third internal node and ground voltage, wherein the gate of the second default NMOS transistor receives the clock signal. The first type of sensing amplifier outputs one of the first comparison signal and the second comparison signal at the third internal node.

6. The multi-level signal receiver according to claim 5, wherein, The second type of sensing amplifier includes: A first p-channel metal-oxide-semiconductor (PMOS) transistor is connected between a power supply voltage and a first node, wherein the gate of the first PMOS transistor receives a clock signal. A second PMOS transistor is connected between the first node and the second node, wherein the gate of the second PMOS transistor receives a multi-level signal; A third PMOS transistor is connected between the first node and the third node, wherein the gate of the third PMOS transistor receives a third reference voltage; The transmission gate is connected between the second and third nodes and is connected to both ground voltage and power supply voltage. A first n-channel metal-oxide-semiconductor (NMOS) transistor is connected between the second node and ground voltage, wherein the gate of the first NMOS transistor receives a clock signal; and The second NMOS transistor is connected between the third node and ground voltage, and its gate receives the clock signal. The second type of sensing amplifier outputs a third comparison signal at the third node.

7. The multi-level signal receiver according to claim 6, wherein, The first threshold voltage of each of the second and third PMOS transistors is less than the second threshold voltage of each of the second and third default PMOS transistors; and The first type of sensing amplifier and the second type of sensing amplifier have a first sensing characteristic and a second sensing characteristic, respectively, relative to one of the first reference voltage and the second reference voltage and the third reference voltage.

8. The multi-level signal receiver according to claim 5, wherein, The second type of sensing amplifier includes: A first p-channel metal-oxide-semiconductor (PMOS) transistor is connected between a power supply voltage and a first node, wherein the gate of the first PMOS transistor receives a clock signal. The second PMOS transistor and the third PMOS transistor are connected in parallel between the first node and the second node, wherein the gate of the second PMOS transistor and the gate of the third PMOS transistor receive multi-level signals. The fourth PMOS transistor and the fifth PMOS transistor are connected in parallel between the first node and the third node, wherein the gate of the fourth PMOS transistor and the gate of the fifth PMOS transistor receive a third reference voltage. The second default transmission gate is connected between the second node and the third node, and is connected to the ground voltage and the power supply voltage; A first n-channel metal-oxide-semiconductor (NMOS) transistor is connected between the second node and ground voltage, wherein the gate of the first NMOS transistor receives a clock signal; and The second NMOS transistor is connected between the third node and ground voltage, and its gate receives the clock signal. The second type of sensing amplifier outputs a third comparison signal at the third node.

9. The multi-level signal receiver according to claim 8, wherein, The first threshold voltage of each of the second to fifth PMOS transistors is less than the second threshold voltage of each of the second default PMOS transistor and the third default PMOS transistor; and The first type of sensing amplifier and the second type of sensing amplifier have a first sensing characteristic and a second sensing characteristic, respectively, relative to one of the first reference voltage and the second reference voltage and the third reference voltage.

10. The multi-level signal receiver according to claim 5, wherein, The second type of sensing amplifier includes: A first p-channel metal-oxide-semiconductor (PMOS) transistor is connected between a power supply voltage and a first node, wherein the gate of the first PMOS transistor receives a clock signal. The second PMOS transistor has a source connected to a first node, a drain connected to a second node, a body connected to the source, and a gate for receiving multi-level signals. The third PMOS transistor has a source connected to the first node, a drain connected to the third node, a body connected to the source, and a gate that receives a third reference voltage. The transmission gate is connected between the second and third nodes and is connected to both ground voltage and power supply voltage. A first n-channel metal-oxide-semiconductor (NMOS) transistor is connected between the second node and ground voltage, wherein the gate of the first NMOS transistor receives a clock signal; and The second NMOS transistor is connected between the third node and ground voltage, and its gate receives the clock signal. The second type of sensing amplifier outputs a third comparison signal at the third node, and The first threshold voltage of each of the second and third PMOS transistors is less than the second threshold voltage of each of the second and third default PMOS transistors.

11. The multi-level signal receiver according to claim 5, wherein, The second type of sensing amplifier includes: A first p-channel metal-oxide-semiconductor (PMOS) transistor is connected between a power supply voltage and a first node, wherein the gate of the first PMOS transistor receives a clock signal. The second PMOS transistor has a source connected to a first node, a drain connected to a second node, a body connected to a bias voltage, and a gate for receiving multi-level signals. The third PMOS transistor has a source connected to the first node, a drain connected to the third node, a body connected to the bias voltage, and a gate that receives a third reference voltage. The transmission gate is connected between the second and third nodes and is connected to both the ground voltage and the power supply voltage. A first n-channel metal-oxide-semiconductor (NMOS) transistor is connected between the second node and ground voltage, wherein the gate of the first NMOS transistor receives a clock signal; and The second NMOS transistor is connected between the third node and ground voltage, and has a gate for receiving clock signals. The second type of sensing amplifier outputs a third comparison signal at the third node, and The first threshold voltage of each of the second and third PMOS transistors is less than the second threshold voltage of each of the second and third default PMOS transistors.

12. The multi-level signal receiver according to claim 5, wherein, The second type of sensing amplifier includes: A first p-channel metal-oxide-semiconductor (PMOS) transistor is connected between a power supply voltage and a first node, wherein the gate of the first PMOS transistor receives a clock signal. A second PMOS transistor is connected between the first node and the second node, wherein the gate of the second PMOS transistor receives a clock signal; The transmission gate is connected between the second and third nodes and is connected to both ground voltage and power supply voltage. A first n-channel metal-oxide-semiconductor (NMOS) transistor is connected between the second node and the fourth node, wherein the gate of the first NMOS transistor receives a multi-level signal; A second NMOS transistor is connected between the third and fourth nodes, wherein the gate of the second NMOS transistor receives a third reference voltage; and The third NMOS transistor is connected between the fourth node and ground voltage, and its gate receives the clock signal. In this configuration, the second type of sensing amplifier outputs a third comparison signal at the second node, and in, The first threshold voltage of each of the second NMOS transistor and the third NMOS transistor is different from the second threshold voltage of each of the second default NMOS transistor and the third default NMOS transistor, and The first type of sensing amplifier and the second type of sensing amplifier have a first sensing characteristic and a second sensing characteristic, respectively, relative to one of the first reference voltage and the second reference voltage and the third reference voltage.

13. The multi-level signal receiver according to claim 3, wherein, The multi-level signal receiver receives multi-level signals through a second type of interface, which is different from the first type of interface: The first sensing amplifier includes a first type of sensing amplifier having a first sensing characteristic, and Each of the second and third sensing amplifiers includes a second type of sensing amplifier having second sensing characteristics that differ from the first sensing characteristics.

14. The multi-level signal receiver according to claim 13, wherein, The first type of sensing amplifier includes: A first default p-channel metal-oxide-semiconductor PMOS transistor is connected between a power supply voltage and a first internal node, wherein the gate of the first default PMOS transistor receives a clock signal. A second default PMOS transistor is connected between the first internal node and the second internal node, wherein the gate of the second PMOS transistor receives a multi-level signal; A third default PMOS transistor is connected between the first internal node and the third internal node, wherein the gate of the third default PMOS transistor receives a first reference voltage. The default transmission gate connects the second and third internal nodes and is connected to both ground voltage and power supply voltage. A first default n-channel metal-oxide-semiconductor (NMOS) transistor is connected between a second internal node and ground voltage, wherein the gate of the first default NMOS transistor receives a clock signal; and The second default NMOS transistor is connected between the third internal node and ground voltage, wherein the gate of the second default NMOS transistor receives the clock signal. The first type of sensing amplifier outputs a first comparison signal at the third internal node.

15. The multi-level signal receiver according to claim 14, wherein, The second type of sensing amplifier includes: A first p-channel metal-oxide-semiconductor (PMOS) transistor is connected between a power supply voltage and a first node, wherein the gate of the first PMOS transistor receives a clock signal. A second PMOS transistor is connected between the first node and the second node, wherein the gate of the second PMOS transistor receives a multi-level signal; A third PMOS transistor is connected between the first node and the third node, wherein the gate of the third PMOS transistor receives one of the second reference voltage and the third reference voltage; The transmission gate is connected between the second and third nodes and is connected to both ground voltage and power supply voltage. A first n-channel metal-oxide-semiconductor (NMOS) transistor is connected between the second node and ground voltage, wherein the gate of the first NMOS transistor receives a clock signal; and The second NMOS transistor is connected between the third node and ground voltage, wherein the gate of the second NMOS transistor receives a clock signal, and In this configuration, the second type of sensing amplifier outputs one of the second and third comparison signals at the third node, and in, The first threshold voltage of each of the second and third PMOS transistors is less than the second threshold voltage of each of the second and third default PMOS transistors, and The first type of sensing amplifier and the second type of sensing amplifier have a first sensing characteristic and a second sensing characteristic, respectively, relative to a first reference voltage and one of a second reference voltage and a third reference voltage.

16. The multi-level signal receiver according to any one of claims 3 to 15, wherein, Based on the first comparison signal, the second comparison signal, and the third comparison signal, the output decoder is configured as follows: When the multi-level signal is greater than the third reference voltage, the data signal corresponding to "11" is output. When the multi-level signal is less than the third reference voltage and greater than the second reference voltage, the data signal corresponding to "10" is output. When the multi-level signal is less than the second reference voltage and greater than the first reference voltage, the data signal corresponding to "01" is output; and When the multi-level signal is less than the first reference voltage, the data signal corresponding to "00" is output.

17. A memory system comprising: The memory controller is configured to generate a multi-level signal based on the input data, wherein the multi-level signal has one of M voltage levels that are different from each other, where M is an integer greater than two; and The memory device is configured to: receive a multi-level signal from a memory controller and compare the multi-level signal with M-1 reference voltages to generate a data signal comprising N bits, where N is an integer greater than one. The memory device includes: The data sampler circuit includes M-1 sense amplifiers configured to compare a multi-level signal with the M-1 reference voltages to generate a data signal; and The reference voltage generator circuit is configured to generate the M-1 reference voltages, and Among them, at least two of the M-1 sensing amplifiers have different sensing characteristics. The at least two sensing amplifiers having different sensing characteristics include a first type of sensing amplifier having a first voltage threshold and a second type of sensing amplifier having a second voltage threshold different from the first voltage threshold. Wherein, the first voltage threshold and the second voltage threshold correspond to the voltage thresholds used to turn on the corresponding transistors in the first type of sense amplifier and the second type of sense amplifier.

18. The memory system according to claim 17, wherein, The memory device also includes a memory cell array comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, the memory cell array being configured to store data signals, and Each of the plurality of memory cells has a dynamic random access memory cell configuration.

19. The memory system according to claim 17, wherein, The memory device also includes a memory cell array comprising a plurality of non-volatile memory cells connected to a plurality of word lines and a plurality of bit lines, the memory cell array being configured to store data signals.

20. An electronic device, comprising: M-1 sensing amplifiers are configured to compare multi-level signals with M-1 reference voltages and output one or more sensing signals; and An output decoder is configured to decode the one or more sensing signals and generate an output data signal based on the decoded one or more sensing signals, the output data signal comprising N bits. In this context, the multi-level signal has one of M distinct voltage levels, where M is an integer greater than two and N is an integer greater than one. The M-1 sensing amplifiers include: A first sensing amplifier having a first voltage threshold; and The second sensing amplifier has a second voltage threshold different from the first voltage threshold, and Wherein, the first voltage threshold and the second voltage threshold correspond to the voltage thresholds used to turn on the corresponding transistors in the first sensing amplifier and the second sensing amplifier.

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