Multi-phase power converter in light-load working mode and control method thereof

Abstract

A control apparatus includes a first signal generator configured to generate a first reset signal for determining an on-time of a high-voltage side switch of a first phase of a multi-phase power converter; a first comparator configured to generate a first set signal for determining a conduction moment of the high-voltage side switch of the first phase based on comparing the first current sensing signal and the voltage control signal; a first zero-crossing detection circuit configured to detect a zero-crossing point of the inductive current of the first phase; and a first phase bias voltage generator configured to generate a first bias voltage for configuring the first phase to exit the first continuous conduction mode when a zero crossing point of the inductive current of the first phase is detected.

Description

Technical Field

[0001] This invention relates to multiphase power converters, and particularly to multiphase power converters for light-load operating modes. Background Technology

[0002] With the development of mobile computing, artificial intelligence (AI), and cloud computing, an increasing number of systems require the ability to provide low-voltage and high-current power supplies. Multiphase power supplies are widely used in these applications due to their fast transient response, low output ripple, and simplified thermal and mechanical design. Valley current control combined with control methods such as internal clocking or constant on-time (COT) is widely used in multiphase power supplies. These control methods provide a simple and cost-effective circuit structure.

[0003] Figure 1 A multiphase power converter 100 employing COT and valley current control methods is demonstrated. This multiphase power converter 100 includes N phases. Each phase is implemented as a buck converter. These N phases are connected in parallel between the input power supply VIN and the output voltage VOUT.

[0004] like Figure 1 As shown, each buck converter phase includes a control circuit, two switches, and an inductor. The first buck converter phase can also be referred to as the first phase or main phase of the multiphase power converter 100. Figure 1 As shown, the first phase of the multiphase power converter 100 includes a first high-voltage side switch QH1, a first low-voltage side switch QL1, a first control circuit, and a first inductor L1. The high-voltage side switch QH1 and the low-voltage side switch QL1 are connected in series between the input power supply VIN and ground. The common node of QH1 and QL1 is labeled SW1. The first inductor L1 is connected between SW1 and VOUT.

[0005] The first control circuit includes a first phase-locked loop (PLL) oscillator (OSC) plus ramp signal generator module 102, a first phase turn-on timer 104, a first latch 105, a first control logic block 106, drivers 108 and 110 for driving switches QH1 and QL1, a first current sensing amplifier 112, and a first comparator 114. Throughout this description, the first PLL oscillator (OSC) plus ramp signal generator module 102 may also be referred to as the first PLL+OSC ramp generator 102 or the first ramp generator 102. The first phase turn-on timer 104 may also be referred to as the main phase turn-on timer 104 or the first turn-on timer 104.

[0006] The second phase of the multiphase power converter 100 includes a second high-voltage side switch QH2, a second low-voltage side switch QL2, a second control circuit, and a second inductor L2. Switches QH2 and QL2 are connected in series between VIN and ground. The common node of QH2 and QL2 is labeled SW2. The second inductor L2 is connected between SW2 and VOUT.

[0007] The second control circuit includes a second phase-locked loop (PLL) oscillator (OSC) plus ramp signal generator module 122, a second phase-on timer 124, a second latch 125, a second control logic block 126, drivers 128 and 130 for driving switches QH2 and QL2, a second current sensing amplifier 132, and a second comparator 134. Throughout this description, the second PLL oscillator (OSC) plus ramp signal generator module 122 may also be referred to as the second PLL+OSC ramp generator 122 or the second ramp generator 122. The second phase-on timer 124 may also be referred to as the second on-time timer 124.

[0008] Similarly, each subsequent phase of the multiphase power converter 100 (e.g., the third phase, the fourth phase, etc.) includes corresponding switches (e.g., QH3, QL3 for the third phase, QH4, QL4 for the fourth phase, and so on), control circuitry, and inductors (L3, L4, etc.). These components are configured identically to the first and second phases, with each pair of switches connected in series between VIN and ground, and the inductor for each phase connected between its respective common node (SW3, SW4, etc.) and VOUT.

[0009] Output capacitor C1 is connected between VOUT and ground to stabilize the output voltage. The load is coupled between VOUT and ground. Figure 1 (Not shown in the image). The inductors of each phase of the multiphase power converter 100 are connected in parallel and further connected to the load.

[0010] The multiphase power converter 100 also includes an error amplifier 116 as part of the feedback circuit. For example... Figure 1As shown, the inverting input of error amplifier 116 is used to detect the voltage at the common node of the voltage divider formed by resistors R1 and R2, which is proportional to the output voltage VOUT. The signal input to the inverting input of error amplifier 116 is labeled FB. Capacitor C2 is connected between the common node of resistors R1 and R2 and the output VOUT of multiphase power converter 100, providing additional filtering or stabilization compensation for the feedback circuit. The non-inverting input of error amplifier 116 is connected to a preset reference voltage VREF. In addition, error amplifier 116 also includes a soft-start signal input to gradually increase the output voltage during startup, preventing inrush current and overshoot. Error amplifier 116 compares the FB signal with VREF to generate a control voltage VC, which is used to regulate the operation of multiphase power converter 100.

[0011] A compensation network is connected between the output of error amplifier 116 and ground. The compensation network includes resistor R3, capacitor C3, and capacitor C4. Resistor R3 and capacitor C4 are connected in series, and further connected in parallel with capacitor C3.

[0012] The frequency signal (Freq), typically determined by an external resistor or resistor-capacitor network, sets the oscillation frequency of the ramp generator in each phase. Each buck converter phase uses a tuning resistor associated with the Freq parameter to adjust its operating frequency and align it with its clock input. The first ramp generator 102 receives the clock input (CLK) and generates a master clock signal (CLKO) to coordinate the timing and phase offset of all slave phases in the multiphase power converter 100. The CLK signal is a high-frequency clock signal that provides a timing reference to ensure that the multiphase power converter 100 operates at the set frequency. Each slave phase ramp generator receives the CLKO signal as its clock to ensure synchronized operation. PHN signals (PH1, PH2, etc.) are input to the ramp generator of each phase and are used to select the appropriate phase offset for each phase in the multiphase power converter 100.

[0013] like Figure 1 As shown, a ramp generator for each phase generates a ramp signal, which is then input into the on-time timer to achieve precise timing control within each phase. The on-time timer uses the ramp signal in conjunction with other inputs to determine the precise switching interval between the high-voltage and low-voltage side switches, thereby achieving efficient power conversion. The other phases operate in the same manner as the first phase, each with its own dedicated ramp generator, on-time timer, latch, and control logic block to maintain synchronized and optimized operation throughout the multiphase power converter 100.

[0014] Taking the first phase as an example, the current through the first inductor L1 is detected by the first current sensing device, generating a first detected current signal Isns1. Then, the first detected current signal Isns1 is converted into a voltage and amplified by the first current sensing amplifier 112, with the amplified output voltage labeled Vcs1. The current-sensing voltage Vcs1 is then input to the inverting input of the first comparator 114. The non-inverting input of the first comparator 114 is connected to the output of the error amplifier 116, providing a control voltage VC. When Vcs1 at the inverting input drops below VC at the non-inverting input, the first comparator 114 generates a pulse signal PUMP1.

[0015] The PUMP1 signal generated by the first comparator 114 is input to a first on-time generator, which includes a first on-time timer 104 and a first latch 105. The first on-time generator generates a PWM signal TON1, which determines the duration for which the first high-side switch QH1 remains on. TON1 is then input to a first control logic block 106, which converts the signal into gate drive signals Hson1 and Lson1. The first control logic block 106 sends the Hson1 signal to a drive circuit 108, which amplifies it to a level suitable for driving the first high-side switch QH1. When Hson1 is high, QH1 is on, and the voltage at the first switching node SW1 equals the input voltage VIN. By controlling the on-time of QH1, the first on-time generator ensures that the current in the first inductor L1 rises appropriately, delivering appropriate energy to the load. Once the on-time duration determined by the on-time generator ends, the first control logic block 106 lowers Hson1, thereby turning off QH1. Simultaneously, the first control logic block 106 activates the Lson1 signal and sends it to the drive circuit 110. The drive circuit 110 then turns on the first low-voltage side switch QL1, allowing the current in the first inductor L1 to decrease and prepare for the next cycle. This process is repeated cyclically to ensure that the multiphase power converter 100 achieves efficient and stable voltage regulation during operation.

[0016] Figure 2 Showing with Figure 1 The timing diagram of various signals related to the multiphase power converter 100 is shown. Figure 2 The horizontal axis represents the time interval. The timing diagram has three rows. The first row represents the current-induced voltage Vcs1 of the first phase. Vcs1 consists of a series of periodic triangular waveforms. The first row also contains the control voltage VC, which is depicted as a stable horizontal line. The control voltage VC serves as a reference for comparison with Vcs1. The second row represents the voltage of the output TON1 of the first on-time generator. TON1 consists of a series of rectangular pulses that transition between logic high and logic low states. The third row represents the output PUMP1 of the first comparator 114.

[0017] like Figure 2 As shown, at time t1, the current-sensing voltage Vcs1 drops below the control voltage VC. This condition triggers the first comparator 114 to generate a pulse signal PUMP1. In response to this pulse, TON1 changes from a logic low state to a logic high state. TON1 is then input to the first control logic block 116, where the logic high state of TON1 is converted into a gate drive signal to turn on the first high-side switch QH1. Once QH1 is turned on, the voltage on the switching node SW1 is equal to the input voltage VIN.

[0018] From time t1 to t2, QH1 remains on, causing the current flowing through the first inductor L1 to increase linearly. Therefore, Vcs1 also increases accordingly, as shown below. Figure 2 As shown. When the current-sensing voltage Vcs1 exceeds the control voltage VC, the pulse signal PUMP1 changes from high to low. At time t2, the conduction time determined by the first conduction time generator ends. Therefore, TON1 changes from a logic high state to a logic low state. In response to this logic low state, QH1 is turned off, and the low-voltage side switch QL1 is turned on. Once QL1 is turned on, the voltage on the common node SW1 is equal to ground potential. From time t2 to t3, QL1 remains on, causing the current flowing through the first inductor L1 to decrease linearly. Therefore, Vcs1 also decreases accordingly, as... Figure 2 As shown. At time t3, the current-induced voltage Vcs1 drops below the control voltage VC, causing the pulse signal PUMP1 to change from low to high again. This process then repeats cyclically.

[0019] Traditional multiphase power converters typically operate in fixed-frequency pulse-width modulation (FPWM) mode. In this mode, all power paths continue to operate simultaneously as the load decreases, and the switching frequency remains constant. This can cause inductor current to cross zero, resulting in significant efficiency losses, especially under light-load conditions. With increasing global emphasis on green energy initiatives and growing user demand for longer battery life in mobile devices, improving light-load efficiency has become a key objective in modern power system design, necessitating more advanced solutions to adapt to varying load conditions without compromising performance.

[0020] This invention proposes a novel device and method for light-load control of multiphase power converters. This method smoothly reduces the number of operating phases as the load decreases, thereby reducing the number of switching operations and improving light-load efficiency while maintaining stable output voltage and low ripple. Summary of the Invention

[0021] The embodiments of this application achieve technical advantages by describing a multiphase power converter operating in a light-load mode.

[0022] According to one embodiment, a control device includes: a first signal generator configured to generate a first reset signal for determining the on-time of a high-voltage side switch of a first phase of a multiphase power converter; a first comparator configured to generate a first set signal for determining the moment of on-time of the high-voltage side switch of the first phase based on a comparison of a first current sensing signal and a voltage control signal; a first zero-crossing detection circuit configured to detect the zero-crossing point of the inductor current of the first phase; and a first phase bias voltage generator configured to generate a first bias voltage for configuring the first phase to exit a first continuous conduction mode when the zero-crossing point of the inductor current of the first phase is detected.

[0023] According to another embodiment, a control method includes: generating a first reset signal for determining the moment of turn-off of a high-voltage side switch of a first phase of a multiphase power converter; generating a first set signal for determining the moment of turn-on of a high-voltage side switch of the first phase by a first comparator based on a comparison between a first current sensing signal and a voltage control signal; detecting the zero-crossing point of the inductor current of a first output inductor of the first phase by a first zero-crossing detection circuit; and generating a first bias voltage by a first phase bias voltage generator for configuring the first phase to exit a first continuous conduction mode when the inductor current in the first phase reaches the zero-crossing point.

[0024] According to another embodiment, a power converter includes: a first buck converter including a first high-voltage side switch, a first low-voltage side switch, and a first inductor; a second buck converter including a second high-voltage side switch, a second low-voltage side switch, and a second inductor; and a control device including: a first on-time timer configured to generate a first reset signal for determining an on-time of the first high-voltage side switch; a first comparator configured to generate a first set signal for determining an on-time of the first high-voltage side switch based on a comparison between a first current sensing signal and a voltage control signal; a first zero-crossing detection circuit configured to detect a zero-crossing point of the current flowing through the first inductor; and a first phase bias voltage generator configured to generate a first bias voltage for configuring the first high-voltage side switch to turn on when the zero-crossing point of the current in the first inductor is detected. A first buck converter exits a first continuous conduction mode; a second conduction timer is configured to generate a second reset signal for determining the conduction time of the second high-voltage side switch; a second comparator is configured to generate a second set signal for determining the moment the second high-voltage side switch is turned on based on a comparison between a second current sensing signal and a voltage control signal; a second zero-crossing detection circuit is configured to detect the zero-crossing point of the current in the second inductor; and a second phase bias voltage generator is configured to generate a second bias voltage for configuring the second buck converter to exit the continuous conduction mode when the zero-crossing point of the current in the second inductor is detected, wherein the first bias voltage is greater than the second bias voltage, and the second phase exits the second continuous conduction mode before the first phase exits the first continuous conduction mode.

[0025] To better understand the following detailed description of the invention, the features and technical advantages of this application have been given a fairly broad overview above. Additional features and advantages of the invention that form the subject matter of the claims will be described below. Those skilled in the art will recognize that the disclosed concepts and specific embodiments can be readily used as the basis for modifying or designing other structures or processes for achieving the same purpose as the invention. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. Attached Figure Description

[0026] To gain a more complete understanding of this application and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0027] Figure 1 A multiphase power converter employing a constant on-time and valley current control method is shown;

[0028] Figure 2 It shows the relationship with Figure 1 The timing diagrams for various signals related to the multiphase power converter are shown below.

[0029] Figure 3 A schematic diagram of a multiphase power converter according to various embodiments of this application is shown;

[0030] Figure 4 Various embodiments according to this application are shown. Figure 3 The timing diagrams for various signals related to the multiphase power converter are shown below.

[0031] Figure 5 Various embodiments according to this application are shown. Figure 3 The timing diagrams for various signals related to the multiphase power converter are shown below.

[0032] Figure 6 Various embodiments according to this application are shown. Figure 3 The timing diagrams for various signals related to the multiphase power converter are shown below.

[0033] Figure 7 Various embodiments according to this application are shown. Figure 3 The diagram shown is of the Nth ramp generator;

[0034] Figure 8 Various embodiments according to this application are shown. Figure 3 The diagram shown is of the Nth on-time generator;

[0035] Figure 9 Various embodiments according to this application are shown. Figure 3 The diagram shows the zero-crossing detector and Vcs bias generator in the Nth phase.

[0036] Figure 10 A schematic diagram of another multiphase power converter according to various embodiments of this application is shown;

[0037] Figure 11 A schematic diagram of another multiphase power converter according to various embodiments of this application is shown;

[0038] Figure 12 A schematic diagram of another multiphase power converter according to various embodiments of this application is shown;

[0039] Figure 13 A flowchart of a method for controlling a multiphase power converter according to various embodiments of this application is shown.

[0040] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The accompanying drawings are provided to clearly illustrate relevant aspects of various embodiments and are not necessarily drawn to scale. Detailed Implementation

[0041] The following describes the preparation and use of the presently preferred embodiments. However, it should be recognized that the present invention provides many applicable inventive concepts that can be practiced in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of particular methods of preparation and use of this application and are not intended to limit the scope of this application. Furthermore, it should be understood that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this application, as defined in the appended claims.

[0042] Furthermore, one or more features of one or more embodiments described below may be combined to create alternative embodiments not explicitly described, and features suitable for such combinations should be considered within the scope of this application. Therefore, the appended claims are intended to cover any such modifications or embodiments.

[0043] This application describes a preferred embodiment in a specific environment, namely a multiphase power converter operating under light load conditions. However, this invention can also be applied to various power converters. Various embodiments will be explained in detail below with reference to the accompanying drawings.

[0044] Figure 3 A schematic diagram of a multiphase power converter according to various embodiments of this application is shown. Figure 3 The multiphase power converter 300 includes N phases. Each phase is implemented as a buck converter. These N phases are connected in parallel between the input power supply VIN and the output VOUT. It should be noted that... Figure 3 The number of buck converters shown is only for clearly illustrating the innovative aspects of each embodiment. This application is not limited to any particular number of buck converters and may include two or more.

[0045] like Figure 3 As shown, each buck converter phase includes a control circuit, a switch, and an inductor. For example, the first buck converter includes a first high-side switch QH1, a first low-side switch QL1, and a first inductor L1. Switches QH1 and QL1 are connected in series between the input power supply VIN and ground. The first inductor L1 is connected between the common node of QH1 and QL1 (referred to as SW1) and the output voltage VOUT. The first phase can serve as the main phase of the multiphase power converter 300. Throughout this description, the first buck converter may also be referred to as the first phase or main phase of the multiphase power converter 300.

[0046] The second buck converter of the multiphase power converter 300 includes a second high-voltage side switch QH2, a second low-voltage side switch QL2, and a second inductor L2. Switches QH2 and QL2 are connected in series between VIN and ground. The second inductor L2 is connected between the common node of QH2 and QL2 (referred to as SW2) and VOUT. The second phase can serve as a slave phase of the multiphase power converter 300. Throughout this description, the second buck converter may also be referred to as the second phase of the multiphase power converter 300.

[0047] It should be noted that this description also applies to phases other than the second phase, as indicated by the variable N, where N can be greater than 2. Each additional phase, such as the Nth phase, includes corresponding switches QHN and QLN, and an inductor LN, all connected in the same manner as the first and second phases. Each inductor LN is connected between the common node (referred to as SWN) of QHN and QLN and the output VOUT. All other phases besides the first phase can be considered slave phases, also referred to as slave phases of the multiphase power converter 300.

[0048] Figure 3 The switches shown (e.g., QH1) can be implemented as n-type metal-oxide-semiconductor (NMOS) transistors. These switches can also be implemented by other suitable controllable devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), superjunction transistors (SJTs), insulated-gate bipolar transistors (IGBTs), gallium nitride (GaN) power devices, etc.

[0049] like Figure 3 As shown, output capacitor C5 is connected between VOUT and ground to stabilize the output voltage. Load ( Figure 3 (Not shown in the image) Coupled between VOUT and ground. N phase inductors are connected in parallel and further connected to the load.

[0050] like Figure 3As shown, each phase also includes a control circuit. The control circuit for the first phase of the multiphase power converter 300 includes a first phase-locked loop (PLL) oscillator (OSC) plus ramp signal generator module 302, a first phase PLL turn-on timer 304, a first latch 305, a first control logic block 306, drive circuits 308 and 310 for driving switches QH1 and QL1, a first current sensing amplifier 312, a first comparator 314, a first zero-crossing detector (ZCD) 316, and a first bias voltage generator 318. Throughout this description, the first phase-locked loop (PLL) oscillator (OSC) plus ramp signal generator module 302 may also be referred to as the first PLL+OSC ramp generator 302 or the first ramp generator 302. The first phase PLL turn-on timer 304 may also be referred to as the main phase turn-on timer 304, the first phase turn-on timer 304, or the first turn-on timer 304. The first bias voltage generator 318 can also be referred to as the first Vcs bias generator 318.

[0051] The control circuit for the second phase includes a second phase-locked loop (PLL) oscillator (OSC) with ramp signal generator module 322, a second-phase PLL on-time timer 324, a second latch 325, a second control logic block 326, drivers 328 and 330 for driving switches QH2 and QL2, a second current sensing amplifier 332, a second comparator 334, a second zero-crossing detector (ZCD) 336, and a second bias voltage generator 338. Throughout this description, the second PLL oscillator (OSC) with ramp signal generator module 322 may also be referred to as the second PLL+OSC ramp generator 322 or the second ramp generator 322. The second-phase PLL on-time timer 324 may also be referred to as the second-phase on-time timer 324 or the second on-time timer 324. The second bias voltage generator 338 may also be referred to as the second Vcs bias generator 338.

[0052] Similarly, the multiphase power converter 300 includes an Nth phase-locked loop (PLL) oscillator (OSC) with ramp signal generator module 342, an Nth phase PLL on-time timer 344, an Nth latch 345, an Nth control logic block 346, drivers 348 and 350 for driving switches QHN and QLN, an Nth current amplifier 352, an Nth comparator 354, an Nth zero-crossing detector (ZCDN) 356, and an Nth bias voltage generator 358. The Nth phase on-time generator includes the Nth phase on-time timer 344 and the Nth latch 345. Throughout this description, the Nth phase-locked loop (PLL) oscillator (OSC) with ramp signal generator module 342 may also be referred to as the Nth PLL+OSC ramp generator 342 or the Nth ramp generator 342. The Nth phase PLL turn-on timer 344 can also be referred to as the Nth phase turn-on timer 344 or the Nth turn-on timer 344. The Nth bias voltage generator 358 can also be referred to as the NVcs bias generator 358.

[0053] The multiphase power converter 300 also includes an error amplifier 360 as part of the feedback circuit. For example... Figure 3 As shown, error amplifier 360 is used to detect the voltage at the common node of the voltage divider formed by resistors R4 and R5, which is proportional to the output voltage VOUT. The signal input to the inverting input of error amplifier 360 is labeled FB. The non-inverting input of error amplifier 360 is connected to a preset reference voltage VREF. Capacitor C6 is connected between the common node of resistors R4 and R5 and VOUT. Furthermore, a soft-start signal is applied to error amplifier 360 to gradually increase the output voltage during startup, preventing inrush current and overshoot. Error amplifier 360 compares the FB signal with VREF to generate a control voltage VC to regulate the output voltage of multiphase power converter 300.

[0054] A compensation network is connected between the output of error amplifier 360 and ground. The compensation network includes resistor R6, capacitor C7, and capacitor C8. Resistor R6 and capacitor C8 are connected in series, and further connected in parallel with capacitor C7.

[0055] Each buck converter phase is connected to a corresponding frequency modulation resistor via Freq, thereby making the operating frequency of that phase close to the frequency of the external clock input signal. The first ramp generator 302 receives the clock input CLK and generates a master clock signal CLKO to coordinate the timing and phase offset of all slave phases in the multiphase power converter 300. The CLK signal is a high-frequency clock signal that provides a timing reference to ensure that the multiphase power converter 300 operates at the set frequency. Each slave phase ramp generator receives the CLKO signal as its clock, ensuring synchronized operation. PHN signals (PH1, PH2, etc.) are input to each phase ramp generator to select the appropriate phase offset for each phase in the multiphase power converter 300.

[0056] like Figure 3 As shown, the current through the first inductor L1 is detected by the first current sensing device, generating a first detected current signal, denoted as Isns1. Then, this detected current signal Isns1 is converted into a voltage and amplified by the first current sensing amplifier 312 with appropriate gain; the amplified output is denoted as Vcs1.

[0057] The first zero-crossing detector 316 is used to receive the first detected current signal Isns1. As the load decreases, the current demand from the load decreases, and the power converter needs less energy to maintain the required output voltage. Therefore, the inductor current in each phase, including the first phase, decreases proportionally until it approaches zero. When the first detected current signal Isns1 is detected to cross zero, the first zero-crossing detector 316 generates a first zero-crossing detection signal ZCD1. When the current crosses zero, the first zero-crossing detection signal ZCD1 changes from a logic low state to a logic high state.

[0058] The first zero-crossing detection signal ZCD1 is then input to the first Vcs bias voltage generator 318. The first Vcs bias voltage generator 318 receives the phase signal PH1 and the first zero-crossing detection signal ZCD1. The phase signal PH1 ensures that the first Vcs bias voltage generator 318 is synchronized with the timing of the first phase. When the first zero-crossing detection signal ZCD1 changes from a logic low state to a logic high state, the first Vcs bias voltage generator 318 outputs a first bias voltage VOS1. VOS1 is injected into the output Vcs1 of the first current sensing amplifier 312 to generate an adjusted current sensing voltage Vcs1'. In some embodiments, VOS1 may be subtracted from the first current sensing voltage Vcs1 to generate the adjusted current sensing voltage Vcs1'.

[0059] like Figure 3As shown, the non-inverting input of the first comparator 314 is connected to the output of the error amplifier 360, which provides the control voltage VC. The inverting input of the first comparator 314 is connected to Vcs1'. The first comparator 314 compares Vcs1' with the control voltage VC. When Vcs1' at the inverting input drops below VC at the non-inverting input, the first comparator 314 generates a pulse signal PUMP1. At this time, PUMP1 changes from a logic low state to a logic high state. When PUMP1 goes high, the first bias voltage VOS1 injected into the output Vcs1 of the first current sensing amplifier 312 is simultaneously removed.

[0060] The output of the first phase-on timer 304 is connected to the reset input of the first latch 305. When the PUMP1 signal is high, the first latch 305 is set and outputs a PWM signal TON1, which determines the duration for which QH1 remains on. TON1 is then input to the first control logic block 306, which converts the signal into gate drive signals Hson1 and Lson1. The first control logic block 306 sends the Hson1 signal to the drive circuit 308, amplifying it to a level suitable for driving QH1. When Hson1 is high, QH1 is turned on, and the voltage on SW1 equals VIN. Simultaneously, the Lson1 signal is driven low, ensuring that the low-side switch QL1 remains off during this period. By controlling the on-time of QH1, the first on-time generator ensures that the current in the first inductor L1 rises appropriately, delivering the correct energy to the load.

[0061] Once the conduction duration determined by the first phase conduction timer 304 ends, a reset signal is generated to reset the first latch 305. This causes the first control logic block 306 to drive Hson1 low, turning off QH1. Simultaneously, the first control logic block 306 activates the Lson1 signal and sends it to the drive circuit 310. The drive circuit 310 turns on QL1, allowing the current in the first inductor L1 to decrease, preparing for the next cycle.

[0062] like Figure 3As shown, the operation of each phase in the multiphase power converter 300 is similar to that of the first phase described above. Each phase generates a corresponding detection current signal (Isns1, Isns2, etc.). The current flowing through the inductors (L1, L2, etc.) in each phase is also detected and amplified by a current sensing amplifier, and converted into a current-sensing voltage signal (Vcs1, Vcs2, etc.) proportional to the current. When the inductor current crosses zero, the zero-crossing detector of each phase detects the zero-crossing of the current. When the zero-crossing of the current is detected, the zero-crossing detector block of each phase outputs a zero-crossing detection signal (ZCD1, ZCD2, etc.). This zero-crossing detection signal is then input to the Vcs bias generator of that phase. The Vcs bias generator uses this signal to generate a bias voltage (VOS1, VOS2, etc.), which is injected into the corresponding current-sensing voltage signal (Vcs1, Vcs2, etc.) to generate an adjusted current-sensing voltage (Vcs1', Vcs2', etc.). The adjusted current-sensing voltages (Vcs1', Vcs2', etc.) are applied to the inverting inputs of the comparators in the corresponding phases. Each comparator compares its corresponding adjusted current-sensing voltage with the control voltage VC. When the adjusted current-sensing voltage drops below VC, the PUMP signal for that phase goes high, opening the high-voltage side switch (QH1, QH2, etc.). In each phase, a conduction timer and latch work together to form a conduction time generator configured to generate a PWM signal (TON1 for the first phase, TON2 for the second phase, and so on). The PWM signal is then sent to the control logic block of the corresponding phase to manage the switching of that phase. After the fixed TON time determined by the conduction time generator in each phase, the high-voltage side switch closes and the low-voltage side switch opens.

[0063] Figure 4 Various embodiments according to the present invention are shown. Figure 3 Timing diagrams of various signals related to the 300 multiphase power converter. Figure 4 The horizontal axis represents the time interval, with key time points marked as t1, t2, and t3. There are four rows in total. The first row represents the adjusted current-induced voltage Vcs' and control voltage VC in a phase. The second row represents the voltage TON output by the on-time generator in that phase. The third row represents the zero-crossing detection signal (ZCD) in that phase. The fourth row represents the comparator output (PUMP) in that phase.

[0064] As the load decreases, the inductor current flowing through this phase also decreases until it crosses zero. At time t1, when the zero-crossing detector of this phase detects the zero-crossing of the inductor current (Isns), the ZCD signal goes high. In response to this high ZCD signal, the Vcs bias generator injects a bias voltage (VOS) into the current-induced voltage Vcs of this phase, thereby generating an adjusted current-induced voltage Vcs' signal. The comparator in this phase then compares Vcs' with VC. Figure 4 As shown, at time t1, if Vcs' is lower than VC, the PUMP signal in this phase immediately goes high, maintaining this phase in continuous conduction mode (CCM). The on-time generator for this phase receives the PUMP signal, changing TON from a logic low state to a logic high state. In response to the logic high state of TON, the high-side gate drive signal Hson changes from a logic low state to a logic high state, and the low-side gate drive signal Lson changes from a logic high state to a logic low state. Therefore, QH is turned on, and QL is turned off. Once QH is turned on, the voltage on the switching node SW is equal to VIN. As the inductor current in this phase increases and moves away from the zero-crossing point, the ZCD signal returns to a logic low state, removing the Vcs bias voltage and restoring Vcs' to its original level. Since the restored Vcs is higher than VC, the PUMP signal in this phase returns to a logic low state after t1.

[0065] From t1 to t2, switch QH remains open, causing the current flowing through the inductor in that phase to increase linearly, as shown by the increasing slope of the Vcs' waveform.

[0066] At time t2, the conduction time determined by the conduction time generator ends. TON transitions from a logic high state to a logic low state. In response to this logic low state, the high-side gate drive signal Hson transitions from a logic high state to a logic low state, and the low-side gate drive signal Lson transitions from a logic low state to a logic high state. Therefore, QH is off, and QL is on. Once QL is on, the voltage on the switching node SW equals the ground potential.

[0067] From t2 to t3, QL remains on, causing the current flowing through the phase inductor to decrease linearly, as shown by the decreasing slope of the Vcs' waveform.

[0068] At time t3, when the inductor current crosses zero again, the ZCD signal transitions to a logic high state. This causes the PUMP signal to go high again, turning QH on and QL off, thus repeating this cycle.

[0069] Figure 5 Various embodiments according to the present invention are shown. Figure 3 Timing diagrams of various signals related to the 300 multiphase power converter. Figure 5The horizontal axis represents the time interval. There are four rows. The first row represents the adjusted current-induced voltage (Vcs') and control voltage (VC) in a phase. The second row represents the voltage output by the on-time generator (TON) in that phase. The third row represents the zero-crossing detection signal (ZCD) in that phase. The fourth row represents the PUMP signal in that phase.

[0070] like Figure 5 As shown, at time t1, when the zero-crossing detector module detects the zero-crossing of the inductor current (Isns), the ZCD signal goes high. In response to the high ZCD signal, the Vcs bias generator injects a bias voltage VOS into the current-induced voltage VCS in that phase, generating an adjusted current-induced voltage signal Vcs'. The comparator in that phase compares Vcs' with VC. Figure 5 As shown, at time t1, if Vcs' is still higher than VC, the PUMP signal in this phase remains low to prevent the high-voltage side switch QH from opening. Since the low-voltage side switch QL also remains closed after the inductor current reaches zero to prevent reverse conduction, the system is in discontinuous conduction mode (DCM).

[0071] From t1 to t2, VOUT continues to decrease due to the load. As VOUT decreases, the difference between the feedback signal FB and VREF increases. In response to this increased error signal, the error amplifier raises VC to correct the decrease in VOUT. From t1 to t2, the ZCD signal remains logic high, indicating that the inductor current in this phase remains zero. Since the inductor current does not increase, Vcs' remains constant during t1 to t2.

[0072] like Figure 5 As shown, at time t2, when VC rises above Vcs', the comparator is triggered, sending a PUMP signal with a logic high state. The on-time generator in this phase receives the PUMP signal, changing TON from a logic low state to a logic high state. In response to the logic high state of TON, the high-side gate drive signal Hson changes from a logic low state to a logic high state. Therefore, QH turns on and QL turns off. Once QH turns on, the voltage on the switching node SW equals VIN. As the inductor current begins to increase, the zero-crossing detector detects this change and changes ZCD from high to low, indicating that the current is no longer at a zero-crossing point. When the ZCD signal goes low, the VOS bias voltage is removed, restoring Vcs' to its original value. Since the restored Vcs' is higher than VC, the PUMP signal in this phase quickly returns to a low state after going high.

[0073] From t2 to t3, QH remains on, and the inductor current rises linearly, as shown by the increasing slope of the Vcs' waveform.

[0074] At time t3, the conduction time determined by the conduction time generator ends. TON transitions from a logic high state to a logic low state. In response to this logic low state, the high-side gate drive signal Hson transitions from a logic high state to a logic low state, and the low-side gate drive signal Lson transitions from a logic low state to a logic high state. Therefore, QH is off, and QL is on. Once QL is on, the voltage on the switching node SW equals the ground potential.

[0075] From t3 to t4, QL remains on, causing the current flowing through the phase inductor to decrease linearly, as shown by the decreasing slope of the Vcs' waveform.

[0076] At time t4, the zero-crossing detector detects the zero-crossing point of the inductor current Isns again, thus repeating this cycle.

[0077] If the rise of VC does not exceed Vcs', the comparator will not trigger a high PUMP signal. Therefore, the PUMP signal remains low, preventing the on-time generator from initiating a new switching cycle, and QH remains off. Thus, this phase completely exits active operation until load demand increases or VOUT decreases, causing VC to rise above Vcs', allowing the phase to re-enter active operation.

[0078] In a multiphase power converter, although the error amplifier output VC is shared across all phases, each phase may have a different VC threshold due to the different VOS bias voltage applied to the current-sensing voltage (Vcs) in each phase. Different VC thresholds correspond to different load currents, allowing each phase to enter or exit active operation at different load levels. As the load decreases, each phase may enter DCM at different times depending on its specific VOS bias voltage. If Vcs' in a phase is higher, making it easier for VC to drop below it, the phase with the smallest negative VOS bias voltage will reach the DCM threshold first and exit active operation earlier. Conversely, the phase with the largest negative VOS bias voltage added to Vcs, typically the dominant phase, will be the last to enter DCM and continue operating in light-load mode, as it requires a significant decrease in VC to reach the same conditions.

[0079] Figure 6 Various embodiments according to the present invention are shown. Figure 3 Timing diagrams of various signals related to a multiphase power converter are shown. Taking a four-phase power converter as an example... Figure 6This diagram illustrates how each phase transitions from Continuous Conductive Mode (CCM) to Discontinuous Conductive Mode (DCM). The phase offsets of the four phases relative to the master clock CLKO are 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively. There are nine lines in total. The first line shows the adjusted current-sensing voltages Vcs' (Vcs1', Vcs2', Vcs3', and Vcs4') and control voltage VC for the four phases. The second line shows the zero-crossing detection signal (ZCD1) for the first phase. The third line shows the zero-crossing detection signal (ZCD3) for the third phase. The fourth line shows the zero-crossing detection signal (ZCD2) for the second phase. The fifth line shows the zero-crossing detection signal (ZCD4) for the fourth phase. The sixth line shows the PUMP signal (PUMP1) for the first phase. The seventh line shows the PUMP signal (PUMP3) for the third phase. The eighth line shows the PUMP signal (PUMP2) for the second phase. The ninth line shows the PUMP signal (PUMP4) for the fourth phase.

[0080] like Figure 6 As shown, 0 degrees, 90 degrees, 180 degrees, and 270 degrees correspond to...

[0081] Vcs1 / ZCD1 / PUMP1, Vcs2 / ZCD2 / PUMP2, Vcs3 / ZCD3 / PUMP3, and Vcs4 / ZCD4 / PUMP4. The Vcs bias generator in each phase generates VOS bias signals labeled -VOS4, -VOS1, -VOS3, and -VOS2 when the ZCD signal goes high, respectively, for the 0°, 90°, 180°, and 270° phases. The amplitudes of the bias voltages satisfy the relationship VOS4 > VOS3 >

[0082] VOS2 > VOS1, where VOS1, VOS2, VOS3, and VOS4 are positive values. Figure 6 The display shows that at a certain moment, the 90-degree phase has exited, the 270-degree phase is in DCM state, and the 180-degree and 0-degree phases are still operating in CCM state.

[0083] like Figure 6As shown, as the load decreases, the 90-degree offset phase associated with the -VOS1 signal enters the DCM first. This is because -VOS1 represents the minimum negative bias. This means that the adjusted current-induced voltage (Vcs2') in the 90-degree phase will be slightly higher than the other phases with larger negative bias voltages. Thus, as the load continues to decrease, Vcs2' is more likely to remain above VC. Therefore, as the load continues to decrease, the switching frequency of the 90-degree offset phase gradually decreases until it stops switching. This occurs when VC drops below the threshold set by Vcs0-VOS1, where Vcs0 represents the current-induced voltage corresponding to zero inductor current when there is no additional bias voltage. During this process, the system continuously adjusts VC within the range between Vcs0-VOS1 and Vcs0-VOS2. While VC remains above Vcs0-VOS2, the other three phases (0 degrees, 180 degrees, and 270 degrees) continue to operate in the CCM, with their inductor currents still crossing zero.

[0084] As the load continues to decrease, the system adjusts the VC voltage below Vcs0-VOS2, causing a 270-degree phase shift (related to the -VOS2 signal) phase to enter the DCM, and similarly reduces its switching frequency until switching stops. During this process, the system adjusts VC within the range between Vcs0-VOS2 and Vcs0-VOS3. When VC drops below Vcs0-VOS3, a 180-degree phase shift (related to the -VOS3 signal) phase enters the DCM, and similarly reduces its switching frequency until switching stops. During this process, the system adjusts VC between Vcs0-VOS3 and Vcs0-VOS4, while the 0-degree phase (related to the -VOS4 signal) remains in the CCM. Finally, as the load continues to decrease, VC drops below Vcs0-VOS4, causing a 0-degree phase shift phase to enter the DCM. This phase also reduces its switching frequency until switching stops completely. During this process, the system continuously adjusts VC between Vcs0-VOS4 and the lower limit of VC to ensure that each phase transitions to DCM in an orderly manner as the load decreases.

[0085] Figure 7 Various embodiments according to this application are shown. Figure 3A schematic diagram of the Nth ramp generator. The Nth ramp generator uses an input clock signal to generate a synchronized, phase-shifted clock for the Nth phase. The Nth ramp generator 342 includes a phase-locked loop and oscillator circuit, as well as a ramp generation circuit. The phase-locked loop and oscillator circuit includes a first SR flip-flop 702, a second SR flip-flop 704, an AND gate 706, a current mirror containing a first transistor Q10 and a second transistor Q12, a first current source Ich1, a second current source Ich2, an operational amplifier 708, a comparator 710, capacitors C10, C12 and C14, resistors R8 and R10, a third transistor Q14 and a fourth transistor Q16, a first switch SC1, a second switch SC2, multiple D flip-flops (720, 721, ..., 790), and a first combinational logic circuit 712.

[0086] like Figure 7 As shown, the input clock signal is fed into the set input of the first SR flip-flop 702. In the master phase, the input clock signal is the master system clock signal CLK. However, in the slave phase, the input clock signal is the CLKO signal generated by the master phase. The CLKO signal is distributed to all slave phases as their clock input to coordinate synchronization and phase shift. The reset inputs of the first SR flip-flop 702 and the second SR flip-flop 704 are connected to a common node and further connected to the output of AND gate 706. AND gate 706 receives the output signal (QCLK) of the first SR flip-flop 702 at its first input and the output (QHSON) of the second SR flip-flop 704 at its second input. The set input of the second SR flip-flop 704 receives the output signal (RS) from the first combinational logic circuit 712.

[0087] The first switch SC1 is controlled by the QCLK signal, and the second switch SC2 is controlled by the QHSON signal. Current source Ich1, switches SC1 and SC2, and current source Ich2 are connected in series between the power supply VCC and ground. The common node of switches SC1 and SC2 is labeled VCTRL. The non-inverting input of operational amplifier 708 is connected to VCTRL, and the inverting input is connected to the reference voltage VREF1. Resistor R8 and capacitor C10 are connected in series between VCTRL and ground. Capacitor C12 is connected between VCTRL and ground, and in parallel with resistor R8 and capacitor C10. The output of operational amplifier 708 is connected to the gate of the third transistor Q14.

[0088] The third transistor Q14 and resistor R10 are connected in series between the first transistor Q10 and ground. The gate of the first transistor Q10 is connected to the gate of the second transistor Q12, and further connected to the drain of the third transistor Q14. The sources of Q10 and Q12 are connected to VCC. The non-inverting input of comparator 710 is connected to the common node of the second transistor Q12 and capacitor C14. The inverting input of comparator 710 is connected to the reference voltage VREF2. Capacitor C14 is connected between the non-inverting input of comparator 710 and ground. The output of comparator 710 (labeled OUT) is connected to the gate of the fourth transistor Q16 and the clock input of the first D flip-flop 720. The source of the fourth transistor Q16 is connected to ground, and its drain is connected to the non-inverting input of comparator 710.

[0089] D flip-flops 720-790 are cascaded, with the output of one flip-flop serving as the clock input for the next. The QB (Q-inverted) output of each D flip-flop is connected to its D input. The output signals (S0 to SM) from the D flip-flops 720-790 are connected to the inputs of a first combinational logic circuit 712, which generates an output signal RS connected to the reset input of the D flip-flops 720-790, ensuring proper reset of the flip-flops. Furthermore, the RS signal is connected to the set input of a second SR flip-flop 704.

[0090] The first combinational logic circuit 712 works in conjunction with D flip-flops 720-790 to generate a phase-shifted signal relative to the input clock signal. Each flip-flop introduces a certain delay, enabling the circuit to precisely control the phase shift. The first combinational logic circuit 712 receives the outputs (S0, S1, etc.) of the D flip-flops 720-790 and generates an RS signal. The RS signal determines the reset point of the D flip-flops 720-790, ensuring consistent phase shifts and resetting the phases in the multiphase power converter at the correct intervals.

[0091] During operation, if the rising edge of the input clock signal occurs before the rising edge of the RS signal, the QCLK signal goes high and remains high until the rising edge of RS arrives. During this period, while QCLK is high, switch SC1 is off, increasing the charging current to capacitor C12, causing the voltage on VCTRL to rise. Operational amplifier 708 compares VCTRL with a reference voltage VREF1 and adjusts the conduction state of the third transistor Q14 according to the voltage comparison. When VCTRL increases and exceeds VREF1, operational amplifier 708 increases the conduction of Q14, pulling the gate voltages of transistors Q10 and Q12 low. The current mirror formed by Q10 and Q12 charges capacitor C14. Therefore, the voltage on C14 increases. If the voltage on C14 reaches the reference voltage VREF2, comparator 710 outputs a logic high signal. The increased charging rate of capacitor C12 shortens the output clock cycle, causing the rising edge of the next output clock signal to occur earlier.

[0092] If the rising edge of the RS signal occurs before the rising edge of the input clock signal, the QHSON signal goes high and remains high until the rising edge of the input clock signal arrives. During this period, while QHSON is high, switch SC2 is off, causing C12 to discharge. The discharge of C12 causes the voltage on VCTRL to drop. Operational amplifier 708 then compares VCTRL with VREF1. When VCTRL drops below VREF1, operational amplifier 708 reduces the conduction of Q14, thereby reducing the current in the current mirror formed by Q10 and Q12. This reduced current causes C14 to charge more slowly. Due to the slower charging rate of C14, it takes longer for C14 to reach VREF2. Therefore, the output clock period is lengthened, delaying the rising edge of the next output clock signal. This process lengthens the output clock period and delays the rising edge of the next output clock signal.

[0093] By adjusting the charging and discharging cycles of C12, the circuit shortens or lengthens the output clock cycle. This feedback mechanism maintains the phase relationship between the output clock signal and the input clock signal. When a timing deviation is detected, the circuit corrects it to synchronize the output clock signal with the input clock signal, achieving phase alignment and frequency locking of the multiphase power converter.

[0094] like Figure 7 As shown, the ramp generation circuit includes a current source Ich3, a fifth transistor Q18, a capacitor C16, and a second combinational logic circuit 714. The second combinational logic circuit 714 receives output signals S0, S1 to SM, and a phase selection signal PHS. The drain of transistor Q18 is connected to the current source Ich3, and its source is connected to ground. The gate of transistor Q18 is controlled by a clock signal CLKN, which determines the frequency of the ramp signal RAMPN.

[0095] The PHS signal is used to select the desired phase shift for each phase in the multiphase power converter. In operation, when the second combinational logic circuit 714 receives the PHS signal, it outputs the corresponding phase clock CLKN to control the timing of the ramp signal generation for the Nth phase in the power converter. The CLKN signal generated by the second combinational logic circuit 714 controls transistor Q18, thereby controlling the charging and discharging of capacitor C16 to generate the ramp signal RAMPN. When the clock signal CLKN is low, transistor Q18 is off. In this state, capacitor C16 is charged by current source Ich3. As C16 is charged, the voltage across C16 increases linearly, causing the ramp signal RAMPN to rise. This ramp-up phase continues as long as CLKN remains low. When the clock signal CLKN goes high, transistor Q18 turns on, causing the capacitor to discharge rapidly. As capacitor C16 discharges, the voltage across C16 drops sharply, causing the ramp signal RAMPN to drop sharply. Therefore, due to the alternating charging and discharging of capacitor C16, a sawtooth-shaped ramp signal RAMPN is formed.

[0096] Figure 8 Various embodiments according to this application are shown. Figure 3 A schematic diagram of the Nth on-time generator. The Nth on-time generator includes the Nth phase on-time timer 344 and the Nth latch 345. CLKN serves as the input clock signal for the Nth on-time generator, and HsonN is the high-voltage side gate drive signal for the Nth phase.

[0097] like Figure 8 As shown, the Nth phase turn-on timer 344 includes a first latch 802 and a second latch 804, an AND gate 806, a current mirror composed of a first transistor Q20 and a second transistor Q22, a first current source Ich4, a second current source Ich5, a third current source Ich6, an operational amplifier 808, a comparator 810, capacitors C20, C22 and C224, a resistor R18, a third transistor Q26, switches SC3 and SC4, and an inverter 812.

[0098] like Figure 8As shown, the CLKN signal is connected to the set input of the first latch 802. The reset inputs of the first latch 802 and the second latch 804 are connected to a common node and further connected to the output of AND gate 806. AND gate 806 receives the output of the first latch 802 (labeled QCLK) at its first input and the output of the second latch 804 (labeled QHSON) at its second input. The set input of the second latch 804 receives the HsonN signal, which is the output of the Nth latch 345. Switch SC3 is controlled by the QCLK signal. Switch SC4 is controlled by the QHSON signal. The first current source Ich4, switch SC3, switch SC4, and current source Ich5 are connected in series between VCC and ground. The common node of switches SC3 and SC4 is labeled VTCMP.

[0099] like Figure 8 As shown, the inverting input of operational amplifier 808 is connected to VTCMP. The non-inverting input of operational amplifier 808 is connected to the reference voltage VTREF. Resistor R18 and capacitor C20 are connected in series between VTCMP and ground. Capacitor C22 is connected between VTCMP and ground, and further connected in parallel with resistor R18 and capacitor C20. The output of operational amplifier 808 is connected to the gates of transistors Q20 and Q22. The sources of Q20 and Q22 are connected to VCC. The non-inverting input of comparator 810 is connected to the common node of transistor Q22 and capacitor C24. The inverting input of comparator 810 is connected to the reference voltage VCREF. In some embodiments, the reference voltage may also be the power supply voltage VCC. Capacitor C24 is connected between the non-inverting input of comparator 810 and ground. The output of comparator 810 (labeled OUT) is connected to the reset input of the Nth latch 345.

[0100] The Nth latch 345 generates a TONN signal, which determines the on-time of switch QHN in the Nth phase. The reset input of the Nth latch 345 is configured to receive the output signal of the Nth phase on-time timer 344. The set input of the Nth latch 345 is configured to receive a PUMPN signal from the Nth comparator 354. The TONN signal also controls the gate of the third ramp transistor Q26 via an inverter 812. The source of Q26 is connected to ground, and its drain is connected to the common node of the drains of Q22 and C24.

[0101] The Nth phase turn-on timer 344 synchronizes the HsonN signal of the power converter with the CLKN signal by adjusting the charging current, ensuring that the circuit's operating frequency matches the frequency of the CLKN signal. When the system detects that the HsonN signal and the CLKN signal are out of sync, it adjusts the VTCMP voltage and increases or decreases the TONN period to bring the two signals closer together.

[0102] like Figure 8 As shown, when the rising edge of the CLKN signal occurs before the rising edge of the HsonN signal, the QCLK signal goes high and remains high until the rising edge of HsonN arrives. During this period, when QCLK is high, switch SC3 is off, increasing the charging current to capacitor C22, causing the voltage on VTCMP to rise. Operational amplifier 808 monitors this rise and adjusts the current to C24 accordingly. As the current to C24 increases, the voltage on C24 rises faster. This rapid voltage rise triggers comparator 810 earlier, thereby resetting the Nth latch 345. Resetting the Nth latch 345 causes the high-side switch QHN to turn off earlier, thus shortening the TONN period of the Nth phase. This causes the next rising edge of the HsonN signal to occur earlier, bringing the HsonN signal closer to the CLKN signal for alignment.

[0103] Conversely, if the rising edge of Hson occurs before the rising edge of CLKN, the QHSON signal goes high and remains high until the rising edge of CLKN arrives. During this period, while QHSON is high, switch SC4 is off, reducing the voltage on VTCMP and slowing down the charging rate of capacitor C22. The slower charging rate causes comparator 810 to output a high signal for a longer time, keeping the high-voltage side switch QHN on for a longer period, thus extending the TONN period and delaying the next rising edge of HsonN. This delay adjustment time brings the rising edge of HsonN closer to the rising edge of CLKN, effectively synchronizing the two signals. The continuous adjustment of the TONN period ensures that the switching frequency remains synchronized with the CLKN frequency.

[0104] Figure 9 Various embodiments according to this application are shown. Figure 3 A schematic diagram of the zero-crossing detector and Vcs bias generator for the Nth phase is shown. The Nth zero-crossing detector includes a comparator 902 and a latch 904. The non-inverting input of comparator 902 is connected to the SWN node, and the inverting input is connected to the reference voltage, typically grounded (GNDN). Comparator 902 compares the SWN signal with the reference voltage. When the low-side switch is turned on and the SWN signal crosses zero, the output state of comparator 902 changes, indicating that a zero-crossing point has been detected. The output signal of comparator 902 is then input to the set input of latch 904, which captures and holds the zero-crossing event until it is processed by subsequent circuitry. The reset input of latch 904 is connected to the HsonN signal. The output of latch 904, labeled ZCDN, indicates the occurrence of a zero-crossing event. The ZCDN signal is then used to generate a bias voltage in the Nth bias voltage generator 358.

[0105] The Nth bias voltage generator 358 includes transistors Q30 and Q32, amplifier 908, current source IN, and current source I. The sources of transistors Q30 and Q32 are connected to VCC. The gates of transistors Q30 and Q32 are connected to a common node, which is further connected to the output of amplifier 908. The output of amplifier 908 drives the gates of transistors Q30 and Q32. The non-inverting input of amplifier 908 receives the SWN signal through resistor R24. The drain of transistor Q30 is connected to the non-inverting input of amplifier 908. The inverting input of amplifier 908 is connected to ground GNDN through resistor R26, thereby establishing a reference voltage at the inverting input of amplifier 908. Current source IN and switch SC5 are connected in series between the supply voltage VCC and the inverting input of amplifier 908. Switch SC5 is controlled by the ZCDN signal, which is generated by the Nth zero-crossing detector 356. Current source I is connected between VCC and the inverting input of amplifier 908. The drain of transistor Q32 is connected to ground via resistor R20. The common node of the drain of transistor Q32 and resistor R20 is labeled VcsN, and serves as the output of the Nth bias voltage generator 358.

[0106] During operation, when the inductor current of the Nth phase crosses zero, the Nth zero-crossing detector 356 generates a ZCDN signal. This signal triggers switch SC5 to close, allowing current from current source IN to flow into the inverting input of amplifier 908. The current from IN boosts the voltage at the inverting input of amplifier 908. Amplifier 908 compares its non-inverting input (received via the SWN signal from R24) with the voltage at the inverting input and adjusts its output to control the gates of transistors Q30 and Q32, thereby regulating the output voltage VcsN. If the voltage at the inverting input (due to the current from IN) is higher than the voltage at the non-inverting input, amplifier 908 reduces the gate drive voltage applied to transistors Q30 and Q32, causing them to conduct more. When transistors Q30 and Q32 conduct more, the drain current flowing to VcsN increases, thereby boosting the voltage across VcsN.

[0107] Figure 10 A schematic diagram of another multiphase power converter according to various embodiments of this application is shown. Multiphase power converter 1000 and... Figure 3 Similar to the multiphase power converter 300 shown, the difference is that the Vcs bias generator in each phase is replaced by a VC bias generator. The VC bias voltage generated by the VC bias generator is added to the control voltage (VC) generated by the error amplifier to produce an adjusted control voltage VCN' for the corresponding phase. The non-inverting input of the comparator for that phase receives the adjusted control voltage VCN', and its inverting input receives the current-induced voltage VcsN, where VcsN is proportional to the current in the output inductor for that phase.

[0108] Figure 11 A schematic diagram of another multiphase power converter according to various embodiments of this application is shown. Figure 3 The method of using constant on-time differs for each phase. Figure 11 The multiphase power converter 1100 employs a clock-based approach. In this configuration, the high-voltage side switch QH of each phase is turned off on the rising edge of the clock signal generated by the corresponding phase ramp generator. For example... Figure 11 As shown, the clock signal generated by the ramp generator is connected to the reset input of the phase latch. The ramp signal generated by the ramp generator is also injected into the adjusted current sensing voltage VcsN' to enhance the stability of the power converter 1100 and optimize its response.

[0109] Figure 12 A schematic diagram of another multiphase power converter according to various embodiments of this application is shown. Figure 10 The method of using constant on-time differs for each phase. Figure 12 The multiphase power converter 1200 employs a clock-based approach. In this configuration, the high-voltage side switch QH of each phase is turned off on the rising edge of the clock signal generated by the corresponding phase ramp generator. For example... Figure 12 As shown, the clock signal generated by the ramp generator is connected to the reset input of the phase latch. The ramp signal generated by the ramp generator is also injected into the adjusted current sensing voltage VcsN' to enhance the stability of the power converter 1200 and optimize its response.

[0110] Figure 13 A flowchart illustrating a method for controlling a multiphase power converter according to various embodiments of this application is shown. Figure 13 The flowchart shown is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, Figure 13 The various steps shown can be added, removed, replaced, rearranged, and repeated.

[0111] Multiphase power converters (e.g., multiphase power converters 300, 1000, 1100, 1200) include multiple step-down converters connected in parallel between the input power source and the load.

[0112] Step 1302: Generate a first reset signal to determine the moment of turn-off of the high-voltage side switch of the first phase of the multiphase power converter.

[0113] Step 1304: The first comparator generates a first set signal to determine the moment when the high-voltage side switch of the first phase is turned on based on the comparison between the first current sensing signal and the voltage control signal.

[0114] Step 1306: The zero-crossing point of the inductor current of the first output inductor of the first phase is detected by the first zero-crossing detection circuit.

[0115] Step 1308: A first bias voltage is generated by the first phase bias voltage generator, which is used to configure the first phase to exit the first continuous conduction mode when the inductor current in the first phase reaches the zero crossing point.

[0116] The method further includes generating a second reset signal for determining the moment of turn-off of the high-voltage side switch of the second phase of the multiphase power converter; generating a second set signal by a second comparator based on a comparison between a second current sensing signal and a voltage control signal to determine the moment of turn-on of the high-voltage side switch of the second phase; detecting the zero-crossing point of the inductor current in the second output inductor of the second phase by a second zero-crossing detection circuit; and generating a second bias voltage by a second phase bias voltage generator for configuring the second phase to exit the second continuous conduction mode when the zero point of the current in the second phase is detected, wherein: the first bias voltage is greater than the second bias voltage; and the second phase exits the second continuous conduction mode before the first phase exits the first continuous conduction mode.

[0117] The method further includes generating a first on-time signal by a first on-time generator including a first timer and a first latch; generating a second on-time signal by a second on-time generator including a second timer and a second latch; generating a first high-voltage side gate drive signal and a first low-voltage side gate drive signal by a first control logic block based on the first on-time signal, respectively for driving the high-voltage side switch and the low-voltage side switch of the first phase of the multiphase power converter; and generating a second high-voltage side gate drive signal and a second low-voltage side gate drive signal by a second control logic block based on the second on-time signal, respectively for driving the high-voltage side switch and the low-voltage side switch of the second phase of the multiphase power converter.

[0118] The method further includes generating the voltage control signal by an error amplifier, wherein the inverting input of the error amplifier is configured to receive a feedback signal proportional to the output voltage of the multiphase power converter, and the non-inverting input is configured to receive a preset reference voltage; generating a first current sensing signal by injecting a first bias voltage generated by a first phase bias voltage generator into the first current sensing voltage, wherein the first current sensing voltage is proportional to the inductor current flowing through the first output inductor; comparing the first current sensing signal with the voltage control signal by a first comparator to generate a first set signal; generating a second current sensing signal by injecting a second bias voltage generated by a second phase bias voltage generator into a second current sensing voltage, wherein the second current sensing voltage is proportional to the inductor current flowing through the second output inductor; and comparing the second current sensing signal with the voltage control signal by a second comparator to generate a second set signal.

[0119] The method further includes generating the voltage control signal by an error amplifier, wherein the inverting input of the error amplifier is configured to receive a feedback signal proportional to the output voltage of the multiphase power converter, and the non-inverting input is configured to receive a preset reference voltage; generating a first voltage control signal by injecting a first bias voltage generated by a first phase bias voltage generator into the control voltage signal; comparing a first current sensing signal with the first voltage control signal by a first comparator to generate a first set signal, wherein the first current sensing voltage is proportional to the inductor current flowing through the first output inductor; generating a second voltage control signal by injecting a second bias voltage generated by a second phase bias voltage generator into the control voltage signal; and comparing a second current sensing signal with the second voltage control signal by a second comparator to generate a second set signal, wherein the second current sensing signal is proportional to the inductor current flowing through the second output inductor.

[0120] The method further includes generating a first zero-crossing detection signal by the first zero-crossing detection circuit when the zero-crossing point of the inductor current in the first phase is detected; and generating a second zero-crossing detection signal by the second zero-crossing detection circuit when the zero-crossing point of the inductor current in the second phase is detected, wherein the first zero-crossing detection circuit and the second zero-crossing detection circuit each include: a zero-crossing comparator, the non-inverting input of which is configured to receive a current-induced voltage generated at a common node of the high-side switch and the low-side switch of the respective phase of the multiphase power converter, and the inverting input of which is configured to receive a reference voltage; and a latch, the set input of which is configured to receive an output signal from the zero-crossing comparator, and the reset input of which is configured to receive a high-side switch control signal of the respective phase, wherein the zero-crossing detection signal of the respective phase is generated at the output of the latch; the first bias voltage is generated by the first phase bias voltage generator; and the second bias voltage is generated by the second phase bias voltage generator, wherein the first phase bias voltage generator and Each of the second phase bias voltage generators includes: an amplifier whose non-inverting input is configured to receive the current-induced voltage through a first resistor, and whose inverting input is configured to be connected to ground through a second resistor; a first current source and a switch connected in series between a voltage source and the inverting input of the amplifier, wherein the gate of the switch is controlled by the zero-crossing detection signal generated by the respective phase; a second current source connected in parallel with the first current source and the switch between the voltage source and the inverting input of the amplifier; and a first transistor and a second transistor, wherein: the gates of the first transistor and the second transistor are connected to a common node, the common node being further connected to the output of the amplifier; the sources of the first transistor and the second transistor are connected to the voltage source; the drain of the first transistor is connected to the non-inverting input of the amplifier; and the drain of the second transistor is connected to ground through a third resistor, the common node of the drain of the second transistor and the third resistor serving as the output of the bias voltage generator for the respective phase.

[0121] While embodiments of the invention and their advantages have been described in detail, it should be understood that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Furthermore, it is not intended that the scope of this application be limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, methods, and steps described herein. Those skilled in the art will readily understand from the disclosure of this invention that, according to the invention, processes, machines, manufactures, compositions of matter, methods, or steps currently existing or to be developed later for performing substantially the same function or achieving substantially the same result as the corresponding embodiments described herein can be utilized. Therefore, it is intended that the appended claims encompass such processes, machines, manufactures, compositions of matter, methods, or steps within their scope.

Claims

1. A control device, characterized by, include: A first signal generator is configured to generate a first reset signal for determining the on-time of the high-voltage side switch of the first phase of the multiphase power converter; The first comparator is configured to generate a first set signal for determining the moment the high-voltage side switch of the first phase is turned on, based on a comparison of a first current sensing signal and a voltage control signal. The first zero-crossing detection circuit is configured to detect the zero-crossing point of the inductor current of the first phase; as well as A first-phase bias voltage generator is configured to generate a first bias voltage for configuring the first phase to exit a first continuous conduction mode when the zero-crossing point of the inductor current of the first phase is detected.

2. The control device of claim 1, wherein Further includes: A second signal generator is configured to generate a second reset signal for determining the on-time of the high-voltage side switch of the second phase of the multiphase power converter; The second comparator is configured to generate a second set signal for determining the moment the high-voltage side switch of the second phase is turned on based on a comparison of the second current sensing signal and the voltage control signal; The second zero-crossing detection circuit is configured to detect the zero-crossing point of the inductor current in the second phase; as well as A second-phase bias voltage generator is configured to generate a second bias voltage for configuring the second phase to exit the second continuous conduction mode when the zero-crossing point of the inductor current of the second phase is detected, wherein: The first bias voltage is greater than the second bias voltage; as well as The second phase exits the second continuous conduction mode before the first phase exits the first continuous conduction mode.

3. The control device of claim 2, wherein It further includes a first latch and a second latch, wherein: The first on-time generator includes a first signal generator and a first latch. The first on-time generator is configured to generate a first on-time signal for input to a first control logic block, wherein the first control logic block is configured based on the first on-time signal to generate a first high-voltage-side gate drive signal and a first low-voltage-side gate drive signal, which are respectively used to drive the high-voltage-side switch and the low-voltage-side switch of the first phase of the multiphase power converter. The second on-time generator includes a second signal generator and a second latch. The second on-time generator is configured to generate a second on-time signal input to a second control logic block. The second control logic block is configured based on the second on-time signal to generate a second high-voltage side gate drive signal and a second low-voltage side gate drive signal, which are used to drive the high-voltage side switch and the low-voltage side switch of the second phase of the multiphase power converter, respectively.

4. The control device of claim 3, wherein Further includes: An error amplifier, wherein its inverting input is configured to receive a feedback signal proportional to the output voltage of the multiphase power converter, and its non-inverting input is configured to receive a preset reference voltage.

5. The control device of claim 4, wherein The first zero-crossing detection circuit includes: A zero-crossing comparator, its non-inverting input configured to receive a current-induced voltage at the common node of the high-voltage side switch and the low-voltage side switch of the first phase, and its inverting input configured to receive a reference voltage; and A latch, wherein its set input is configured to receive the output signal of the zero-crossing comparator, its reset input is configured to receive the high-voltage side switch control signal of the first phase, and wherein the zero-crossing detection signal of the first phase is generated at the output of the latch.

6. The control device of claim 5, wherein The first phase bias voltage generator includes: An amplifier, wherein its non-inverting input is configured to receive the current-induced voltage through a first resistor, and its inverting input is configured to be connected to ground through a second resistor; A first current source and a switch are connected in series between a voltage source and the inverting input of the amplifier, wherein the gate of the switch is controlled by the zero-crossing detection signal generated in the first phase; A second current source, which is connected in parallel with the first current source and the switch between the voltage source and the inverting input terminal of the amplifier; and The first transistor and the second transistor, wherein: The gates of the first transistor and the second transistor are connected to a common node, which is further connected to the output of the amplifier; The sources of the first transistor and the second transistor are connected to the voltage source; The drain of the first transistor is connected to the non-inverting input of the amplifier; and The drain of the second transistor is connected to ground through a third resistor, and the common node of the drain of the second transistor and the third resistor serves as the output of the first phase bias voltage generator.

7. The control device as described in claim 4, characterized in that, in: The non-inverting input of the first comparator is configured to receive the voltage control signal generated by the error amplifier, and its inverting input is configured to receive the first current sensing signal, wherein the first current sensing signal is generated by injecting the first bias voltage into the first current sensing voltage, and the first current sensing voltage is proportional to the inductor current in the first phase. as well as The non-inverting input of the second comparator is configured to receive the voltage control signal generated by the error amplifier, and its inverting input is configured to receive the second current sensing signal, wherein the second current sensing signal is generated by injecting the second bias voltage into the second current sensing voltage, and the second current sensing voltage is proportional to the inductor current in the second phase.

8. The control device as described in claim 4, characterized in that, in: The non-inverting input of the first comparator is configured to receive a first voltage control signal, and its inverting input is configured to receive a first current sensing signal, wherein the first voltage control signal is generated by injecting the first bias voltage into the voltage control signal generated by the error amplifier, and the first current sensing signal is proportional to the inductor current in the first phase; as well as The non-inverting input of the second comparator is configured to receive a second voltage control signal, and its inverting input is configured to receive a second current sensing signal, wherein the second voltage control signal is generated by injecting the second bias voltage into the voltage control signal generated by the error amplifier, and the second current sensing signal is proportional to the inductor current in the second phase.

9. The control device as described in claim 1, characterized in that, The first signal generator includes: The first phase-locked loop circuit is configured to generate multiple phase-shifted clock signals and select one clock signal for a corresponding phase; and The second phase-locked loop circuit is cascaded with the first phase-locked loop circuit, and wherein: The second phase-locked loop circuit is configured to receive the clock signal and generate a preset on-time based on the clock signal.

10. The control device as claimed in claim 1, characterized in that, in: The first signal generator includes a phase-locked loop circuit configured to generate a clock signal, wherein the clock signal is used as the first reset signal.

11. A control method, characterized in that, include: Generate a first reset signal to determine the moment of turn-off of the high-voltage side switch of the first phase of the multiphase power converter; A first set signal is generated by a first comparator based on a comparison between a first current sensing signal and a voltage control signal to determine the instant the high-voltage side switch of the first phase is turned on. The zero-crossing point of the inductor current of the first output inductor of the first phase is detected by the first zero-crossing detection circuit; as well as A first bias voltage is generated by a first phase bias voltage generator, which is used to configure the first phase to exit the first continuous conduction mode when the inductor current in the first phase reaches the zero crossing point.

12. The method as described in claim 11, characterized in that, Further includes: A second reset signal is generated to determine the moment of turn-off of the high-voltage side switch of the second phase of the multiphase power converter; A second set signal is generated by a second comparator based on a comparison between a second current sensing signal and the voltage control signal to determine the instant the high-voltage side switch of the second phase is turned on; The zero-crossing point of the inductor current in the second output inductor of the second phase is detected by the second zero-crossing detection circuit; as well as A second bias voltage is generated by a second-phase bias voltage generator, which is used to configure the second phase to exit the second continuous conduction mode when the zero-crossing point of the inductor current in the second phase is detected, wherein: The first bias voltage is greater than the second bias voltage; as well as The second phase exits the second continuous conduction mode before the first phase exits the first continuous conduction mode.

13. The method as described in claim 12, characterized in that, Further includes: A first conduction time signal is generated by a first conduction time generator, which includes a first timer and a first latch; The second on-time signal is generated by a second on-time generator, which includes a second timer and a second latch; The first control logic block generates a first high-voltage side gate drive signal and a first low-voltage side gate drive signal based on the first conduction time signal, which are used to drive the high-voltage side switch and the low-voltage side switch of the first phase of the multiphase power converter, respectively. as well as The second control logic block generates a second high-voltage side gate drive signal and a second low-voltage side gate drive signal based on the second conduction time signal, which are used to drive the high-voltage side switch and the low-voltage side switch of the second phase of the multiphase power converter, respectively.

14. The method as described in claim 12, characterized in that, Further includes: The voltage control signal is generated by an error amplifier, wherein the inverting input of the error amplifier is configured to receive a feedback signal proportional to the output voltage of the multiphase power converter, and the non-inverting input is configured to receive a preset reference voltage. The first current sensing signal is generated by injecting the first bias voltage generated by the first phase bias voltage generator into the first current sensing voltage, wherein the first current sensing voltage is proportional to the inductor current flowing through the first output inductor. The first comparator compares the first current sensing signal with the voltage control signal to generate the first set signal; The second current sensing signal is generated by injecting the second bias voltage generated by the second phase bias voltage generator into the second current sensing voltage, wherein the second current sensing voltage is proportional to the inductor current flowing through the second output inductor. as well as The second comparator compares the second current sensing signal with the voltage control signal to generate the second set signal.

15. The method as described in claim 12, characterized in that, Further includes: The voltage control signal is generated by an error amplifier, wherein the inverting input of the error amplifier is configured to receive a feedback signal proportional to the output voltage of the multiphase power converter, and the non-inverting input is configured to receive a preset reference voltage. A first voltage control signal is generated by injecting the first bias voltage generated by the first phase bias voltage generator into the control voltage signal; The first comparator compares the first current sensing signal with the first voltage control signal to generate the first set signal, wherein the first current sensing voltage is proportional to the inductor current flowing through the first output inductor; A second voltage control signal is generated by injecting the second bias voltage generated by the second phase bias voltage generator into the control voltage signal; as well as The second comparator compares the second current sensing signal with the second voltage control signal to generate the second set signal, wherein the second current sensing signal is proportional to the inductor current flowing through the second output inductor.

16. The method as described in claim 12, characterized in that, Further includes: When the zero-crossing point of the inductor current in the first phase is detected, the first zero-crossing detection circuit generates a first zero-crossing detection signal. as well as When the zero-crossing point of the inductor current in the second phase is detected, a second zero-crossing detection signal is generated by the second zero-crossing detection circuit, wherein the first zero-crossing detection circuit and the second zero-crossing detection circuit each include: A zero-crossing comparator, its non-inverting input configured to receive a current-induced voltage generated at the common node of the high-side and low-side switches of each phase of the multiphase power converter, and its inverting input configured to receive a reference voltage; and A latch, its set input configured to receive an output signal from the zero-crossing comparator, and its reset input configured to receive a high-voltage side switch control signal for each phase, wherein a zero-crossing detection signal for each phase is generated at the output of the latch; a first bias voltage is generated by a first-phase bias voltage generator; and The second bias voltage is generated by the second phase bias voltage generator, wherein the first phase bias voltage generator and the second phase bias voltage generator each include: An amplifier, wherein its non-inverting input is configured to receive the current-induced voltage through a first resistor, and its inverting input is configured to be connected to ground through a second resistor; A first current source and a switch are connected in series between a voltage source and the inverting input of the amplifier, wherein the gate of the switch is controlled by the zero-crossing detection signal generated by its respective phase; A second current source, which is connected in parallel with the first current source and the switch between the voltage source and the inverting input terminal of the amplifier; and The first transistor and the second transistor, wherein: The gates of the first transistor and the second transistor are connected to a common node, which is further connected to the output of the amplifier; The sources of the first transistor and the second transistor are connected to the voltage source; The drain of the first transistor is connected to the non-inverting input of the amplifier; and The drain of the second transistor is connected to ground through a third resistor, and the common node of the drain of the second transistor and the third resistor serves as the output of the bias voltage generator for their respective phases.

17. A power converter, characterized in that, include: The first buck converter includes a first high-voltage side switch, a first low-voltage side switch, and a first inductor; The second buck converter includes a second high-voltage side switch, a second low-voltage side switch, and a second inductor; as well as A control device, comprising: A first on-time timer is configured to generate a first reset signal for determining the on-time of the first high-voltage side switch; The first comparator is configured to generate a first set signal for determining the moment the first high-voltage side switch is turned on, based on a comparison between a first current sensing signal and a voltage control signal. The first zero-crossing detection circuit is configured to detect the zero-crossing point of the current flowing through the first inductor; A first phase bias voltage generator is configured to generate a first bias voltage for configuring the first buck converter to exit the first continuous conduction mode when the zero-crossing point of the current in the first inductor is detected. The second on-time timer is configured to generate a second reset signal for determining the on-time of the second high-voltage side switch; The second comparator is configured to generate a second set signal for determining the moment the second high-voltage side switch is turned on, based on a comparison between the second current sensing signal and the voltage control signal. The second zero-crossing detection circuit is configured to detect the zero-crossing point of the current in the second inductor; and A second-phase bias voltage generator is configured to generate a second bias voltage for configuring the second buck converter to exit continuous conduction mode when the zero-crossing point of the current in the second inductor is detected, wherein the first bias voltage is greater than the second bias voltage, and the second phase exits the second continuous conduction mode before the first phase exits the first continuous conduction mode.

18. The power converter as claimed in claim 17, characterized in that, in: The first high-voltage side switch and the first low-voltage side switch are connected in series between the input voltage bus and ground; The first inductor is connected between the common node of the first high-voltage side switch and the first low-voltage side switch and the output terminal of the power converter; The second high-voltage side switch and the second low-voltage side switch are connected in series between the input voltage bus and ground; and The second inductor is connected between the common node of the second high-voltage side switch and the second low-voltage side switch and the output terminal of the power converter.

19. The power converter as claimed in claim 17, characterized in that, in: The first zero-crossing detection circuit includes: A zero-crossing comparator, wherein its non-inverting input is configured to receive a current-induced voltage generated at the common node of the first high-voltage side switch and the first low-voltage side switch, and its inverting input is configured to receive a reference voltage; and A latch, wherein its set input is configured to receive an output signal from the zero-crossing comparator, and its reset input is configured to receive a high-voltage side switch control signal from the first high-voltage side switch, wherein a zero-crossing detection signal of the first buck converter is generated at the output of the latch. The first phase bias voltage generator includes: An amplifier, wherein its non-inverting input is configured to receive the current-induced voltage through a first resistor, and its inverting input is configured to be connected to ground through a second resistor; A first current source and a switch are connected in series between a voltage source and the inverting input of the amplifier, wherein the gate of the switch is controlled by the zero-crossing detection signal; A second current source, which is connected in parallel with the first current source and the switch between the voltage source and the inverting input terminal of the amplifier; and The first transistor and the second transistor, wherein: The gates of the first transistor and the second transistor are connected to a common node, which is further connected to the output of the amplifier; The sources of the first transistor and the second transistor are connected to the voltage source; The drain of the first transistor is connected to the non-inverting input of the amplifier; and The drain of the second transistor is connected to ground through a third resistor, and the common node of the drain of the second transistor and the third resistor serves as the output of the first phase bias voltage generator.

20. The power converter as claimed in claim 17, characterized in that, Further includes: An error amplifier, wherein its inverting input is configured to receive a feedback signal proportional to the output voltage of the power converter, and its non-inverting input is configured to receive a preset reference voltage, wherein: The non-inverting input of the first comparator is configured to receive the voltage control signal generated by the error amplifier, and its inverting input is configured to receive the first current sensing signal, wherein the first current sensing signal is generated by injecting the first bias voltage into the first current sensing voltage, and the first current sensing voltage is proportional to the current flowing through the first inductor. as well as The non-inverting input of the second comparator is configured to receive the voltage control signal generated by the error amplifier, and its inverting input is configured to receive the second current sensing signal, wherein the second current sensing signal is generated by injecting the second bias voltage into the second current sensing voltage, and the second current sensing voltage is proportional to the current flowing through the second inductor.

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