Effective turn-around strategy for bus

Abstract

This application relates to effective turn-around strategies for a bus. An apparatus can include a memory and a bus for communicating with the memory. The apparatus can operate the bus in a first direction relative to the memory associated with a first type of access command. The apparatus can determine, for the memory, a quantity of a second type of queued access command is for a group for which a timing constraint for activating different rows in the same group has been satisfied. Based on determining the quantity of the second type of queued access command is for one or more groups for which the timing constraint has been satisfied, the apparatus can operate the bus in a second direction relative to the memory associated with the second type of access command.

Description

[0001] Cross-reference

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 070,576, filed August 26, 2020, entitled “Efficient Turnover Policy for a Bus”, which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to efficient turnaround strategies for buses. Background Technology

[0004] The following text generally refers to one or more memory systems, and more specifically, to efficient turnaround strategies for buses.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to different states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0006] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time even without external power. Volatile DRAM devices, on the other hand, may lose their stored state when disconnected from external power. Summary of the Invention

[0007] Describe a device. The device may include: a memory; and a controller coupled to the memory and configured to cause the device to: operate a data bus for the memory in a first direction relative to the memory and associated with a first type of access command; determine for the memory a number of queued access commands of a second type for a group that have satisfied timing constraints for activating different rows in the same group; and operate the data bus in a second direction associated with the second type of access commands, at least in part based on the determination that a number of queued access commands of the second type are for a group that have satisfied timing constraints.

[0008] Describe a device. The device may include: a memory; and a controller coupled to the memory and configured to cause the device to: configure a data bus for the memory to operate in a first direction for conveying data read from the memory; determine that a certain number of write commands queued for the memory are for a group whose timing constraints for activating different rows in the same group have been satisfied; and configure the data bus to operate in a second direction for conveying data to the memory, based at least in part on the determination that a certain number of write commands queued for the memory are for a group whose timing constraints have been satisfied.

[0009] Describe an apparatus. The apparatus may include: a memory; and a controller coupled to the memory and configured to cause the apparatus to: configure a data bus for the memory to operate in a first direction for conveying data to the memory; determine that a certain number of read commands queued for the memory are for a group whose timing constraints for activating different rows in the same group have been satisfied; and configure the data bus to operate in a second direction for conveying data read from the memory, based at least in part on the determination that a certain number of read commands queued for the memory are for a group whose timing constraints have been satisfied. Attached Figure Description

[0010] Figure 1 This describes an example of a system that supports an efficient bus turnaround strategy, based on examples disclosed herein.

[0011] Figure 2 This describes an example of a memory subsystem that supports an efficient bus turnover strategy, based on examples disclosed herein.

[0012] Figure 3 This document illustrates an example of a timing diagram for an efficient turnaround strategy for a bus, based on examples disclosed herein.

[0013] Figure 4 This document describes an example of a process flow that supports an efficient turnaround strategy for the bus, based on examples disclosed herein.

[0014] Figure 5 This document describes an example of a process flow that supports an efficient turnaround strategy for the bus, based on examples disclosed herein.

[0015] Figure 6 A block diagram illustrating an apparatus for an efficient bus turnaround strategy according to aspects of this disclosure.

[0016] Figures 7 to 9 The flowchart illustrates one or more methods supporting efficient turnaround strategies for the bus, based on examples disclosed herein. Detailed Implementation

[0017] For example, an electronic device may include a main memory (e.g., a main memory for storing information and other operations) and an auxiliary memory operable as a cache. This configuration allows the device to benefit from the advantages of non-volatile memory (e.g., non-volatility, high storage capacity, low power consumption) while maintaining compatibility with the host device. However, non-volatile memory may have turnaround strategies for its data bus that, in some cases, prevent the device from efficiently scheduling access commands to the non-volatile memory. For instance, if the non-volatile memory has timing constraints for activating different rows in the same group, then these timing constraints, as part of the turnaround strategy, can prevent the device from efficiently scheduling non-volatile memory access commands when there are multiple access commands queued for different rows in the same group of the non-volatile memory. This can lead to unnecessary delays in scheduling and executing access commands, as well as other disadvantages.

[0018] According to the techniques described herein, a device can efficiently schedule access commands for nonvolatile memory by using a turnaround strategy that takes into account timing constraints for activating different regions (e.g., different rows within the same group). For example, the device can change the direction of the data bus for the nonvolatile memory based on the number of queued access commands for one or more groups ready to be activated (e.g., groups whose timing constraints have been met). Therefore, the device can issue access commands to other groups ready to be activated while one or more groups are in the process of meeting their timing constraints, thereby improving the scheduling efficiency and overall performance of the device, as well as other advantages.

[0019] First, as referenced Figure 1 and 2 The features of this disclosure are described in the context of the system and memory subsystem described herein. The features of this disclosure are further described in reference to, for example, [reference 2]. Figure 3 The described timing diagram and as referenced Figure 4 and 5 The process flow is described within the context of the described process flow. (See reference...) Figures 6 to 9The equipment diagrams and flowcharts describing effective turnover strategies are used to further illustrate and describe these and other features of this disclosure, and reference is made to the equipment diagrams and flowcharts.

[0020] Figure 1 This document describes an example of a memory system 100 that supports an efficient bus turnaround strategy, as disclosed herein. The memory system 100 may be included in an electronic device such as a computer or telephone. The memory system 100 may include a host device 105 and a memory subsystem 110. The host device 105 may be a processor or system-on-a-chip (SoC) that interfaces with an interface controller 115 and other components of the electronic device containing the memory system 100. The memory subsystem 110 may store and provide access to electronic information (e.g., digital information, data) for the host device 105. The memory subsystem 110 may include an interface controller 115, volatile memory 120, and non-volatile memory 125. In some instances, the interface controller 115, volatile memory 120, and non-volatile memory 125 may be included in the same physical package, such as package 130. However, the interface controller 115, volatile memory 120, and non-volatile memory 125 may be disposed on different corresponding dies (e.g., silicon dies).

[0021] Devices in memory system 100 can be coupled by various wires (e.g., traces, printed circuit board (PCB) routes, redistribution layer (RDL) routes) that enable the transmission of information (e.g., commands, addresses, data) between devices. These wires can form channels, data buses, command buses, address buses, etc.

[0022] Memory subsystem 110 may be configured to provide the benefits of non-volatile memory 125 while maintaining compatibility with host device 105 that supports protocols for different types of memory, such as volatile memory 120, and other instances. For example, non-volatile memory 125 may provide benefits (e.g., relative to volatile memory 120), such as non-volatility, higher capacity, or lower power consumption. However, host device 105 may be configured in a way that is incompatible with or inefficient with various aspects of non-volatile memory 125. For example, host device 105 may support voltages, access latency, protocols, page sizes, etc., that are incompatible with non-volatile memory 125. To compensate for the incompatibility between host device 105 and non-volatile memory 125, memory subsystem 110 may be configured with volatile memory 120 that is compatible with host device 105 and acts as a cache for non-volatile memory 125. Therefore, host device 105 can use the protocols supported by volatile memory 120 while also benefiting from the advantages of non-volatile memory 125.

[0023] In some instances, the memory system 100 may be included in, or coupled to, a computing device, electronic device, mobile computing device, or wireless device. The device may be a portable electronic device. For example, the device may be a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, Internet-connected device, etc. In some instances, the device may be configured for bidirectional wireless communication via a base station or access point. In some instances, the device associated with the memory system 100 may be capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication. In some instances, the device associated with the memory system 100 may be referred to as user equipment (UE), station (STA), mobile terminal, etc.

[0024] Host device 105 may be configured to interface with memory subsystem 110 using a first protocol (e.g., Low Power Double Data Rate (LPDDR)) supported by interface controller 115. Therefore, in some instances, host device 105 may interface directly with interface controller 115 and indirectly with non-volatile memory 125 and volatile memory 120. In alternative instances, host device 105 may interface directly with non-volatile memory 125 and volatile memory 120. Host device 105 may also interface with other components of the electronic device that includes memory system 100. Host device 105 may be or include a SoC, a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or another programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations of these types of components. In some instances, host device 105 may be referred to as a host.

[0025] Interface controller 115 can be configured to interface with volatile memory 120 and non-volatile memory 125 on behalf of host device 105 (e.g., based on one or more commands or requests issued by host device 105). For example, interface controller 115 can facilitate the retrieval and storage of data in volatile memory 120 and non-volatile memory 125 on behalf of host device 105. Therefore, interface controller 115 can facilitate data transfer between various sub-components, such as data transfer between at least some of host device 105, volatile memory 120, or non-volatile memory 125. Interface controller 115 can interface with host device 105 and volatile memory 120 using a first protocol and with non-volatile memory 125 using a second protocol supported by non-volatile memory 125.

[0026] Non-volatile memory 125 may be configured to store digital information (e.g., data) of an electronic device including memory system 100. Therefore, non-volatile memory 125 may include one or more memory cell arrays and a local memory controller configured to operate the memory cell arrays. In some instances, the memory cells may be or include FeRAM cells (e.g., non-volatile memory 125 may be FeRAM). Non-volatile memory 125 may be configured to interface with interface controller 115 using a second protocol different from the first protocol used between interface controller 115 and host device 105. In some instances, non-volatile memory 125 may have a longer latency for access operations compared to volatile memory 120. For example, retrieving data from non-volatile memory 125 may take longer than retrieving data from volatile memory 120. Similarly, writing data to non-volatile memory 125 may take longer than writing data to volatile memory 120. In some instances, non-volatile memory 125 may have a smaller page size than volatile memory 120, as described herein.

[0027] Volatile memory 120 may be configured to operate as a cache for one or more components (e.g., non-volatile memory 125). For example, volatile memory 120 may store information (e.g., data) for an electronic device containing memory system 100. Therefore, volatile memory 120 may include one or more memory cell arrays and a local memory controller configured to operate the memory cell arrays. In some instances, the memory cells may be or include DRAM cells (e.g., the volatile memory may be DRAM). Non-volatile memory 125 may be configured to interface with interface controller 115 using a first protocol used between interface controller 115 and host device 105.

[0028] In some instances, volatile memory 120 may have shorter latency for access operations compared to non-volatile memory 125. For example, retrieving data from volatile memory 120 may take less time than retrieving data from non-volatile memory 125. Similarly, writing data to volatile memory 120 may take less time than writing data to non-volatile memory 125. In some instances, volatile memory 120 may have a larger page size than non-volatile memory 125. For example, the page size of volatile memory 120 may be 2 kilobytes (2kB) and the page size of non-volatile memory 125 may be 64 bytes (64B) or 128 bytes (128B).

[0029] While non-volatile memory 125 may be a higher-density memory compared to volatile memory 120, accessing non-volatile memory 125 may take longer than accessing volatile memory 120 (e.g., due to different architectures and protocols, and other reasons). Therefore, operating volatile memory 120 as a cache can reduce latency in memory system 100. As an example, by retrieving data from volatile memory 120 instead of from non-volatile memory 125, access requests for data from host device 105 can be satisfied relatively quickly. To facilitate the operation of volatile memory 120 as a cache, interface controller 115 may include multiple buffers 135. Buffers 135 may be disposed on the same die as interface controller 115 and may be configured to temporarily store data for transfer between volatile memory 120, non-volatile memory 125, or host device 105 (or any combination thereof) during one or more access operations (e.g., store and retrieve operations).

[0030] Access operations may also be referred to as access procedures or access routines and may involve one or more sub-operations performed by one or more components of the memory subsystem 110. Examples of access operations may include: a storage operation in which data provided by the host device 105 is stored (e.g., written to) volatile memory 120 or non-volatile memory 125 (or both); and a retrieval operation in which data requested by the host device 105 is obtained (e.g., read) from volatile memory 120 or non-volatile memory 125 and returned to the host device 105.

[0031] To store data in memory subsystem 110, host device 105 can initiate a storage operation (or “stored procedure”) by sending a storage command (also referred to as a storage request, write command, or write request) to interface controller 115. The storage command can target a set of non-volatile memory cells in non-volatile memory 125. In some instances, the set of memory cells may also be referred to as a portion of memory. Host device 105 can also provide data to be written to the set of non-volatile memory cells to interface controller 115. Interface controller 115 can temporarily store the data in buffer 135-a. After storing the data in buffer 135-a, interface controller 115 can transfer the data from buffer 135-a to volatile memory 120 or non-volatile memory 125, or both. In write-through mode, interface controller 115 can transfer data to both volatile memory 120 and non-volatile memory 125. In write-back mode, interface controller 115 can transfer data only to volatile memory 120.

[0032] In either mode, interface controller 115 may identify an appropriate set of one or more volatile memory cells in volatile memory 120 for storing data associated with a storage command. To this end, interface controller 115 may implement set association mapping, wherein each set (e.g., a block) of one or more non-volatile memory cells in non-volatile memory 125 may be mapped to multiple sets of volatile memory cells in volatile memory 120. For example, interface controller 115 may implement an n-way association mapping, which allows data from a set of non-volatile memory cells to be stored in one of n sets of volatile memory cells in volatile memory 120. Therefore, interface controller 115 can manage volatile memory 120 as a cache for non-volatile memory 125 by referencing n sets of volatile memory cells associated with a target set of non-volatile memory cells. As used herein, unless otherwise described or mentioned, a “set” of objects may refer to one or more objects. Although described with reference to set association mapping, interface controller 115 can manage volatile memory 120 as a cache by implementing one or more other types of mapping (such as direct mapping or association mapping, and other instances).

[0033] After determining which n volatile memory cell sets are associated with the target non-volatile memory cell set, the interface controller 115 can store the data in one or more of the n volatile memory cell sets. Therefore, by retrieving data from the lower latency volatile memory 120 instead of the higher latency non-volatile memory 125, subsequent retrieval commands for data from the host device 105 can be efficiently satisfied. The interface controller 115 can determine which of the n volatile memory sets 120 to store data based on one or more parameters (such as data validity, timeliness, or modification status) associated with the data stored in the n volatile memory sets 120. Therefore, storage commands from the host device 105 can be satisfied fully (e.g., in write-back mode) or partially (e.g., in write-through mode) by storing the data in the volatile memory 120. In order to track data stored in volatile memory 120, interface controller 115 can store tag addresses for one or more sets of volatile memory cells (e.g., for each set of volatile memory cells), the tag addresses indicating non-volatile memory cells with data stored in a given set of volatile memory cells.

[0034] To retrieve data from memory subsystem 110, host device 105 can initiate a retrieval operation (also referred to as a retrieval process) by sending a retrieval command (also referred to as a retrieval request, read command, or read request) to interface controller 115. The retrieval command can target one or more sets of non-volatile memory cells in non-volatile memory 125. Upon receiving the retrieval command, interface controller 115 can examine the requested data in volatile memory 120. For example, interface controller 115 can examine the requested data in n sets of volatile memory cells associated with the target set of non-volatile memory cells. If one of the n sets of volatile memory cells stores the requested data (e.g., data is stored for the target set of non-volatile memory cells), then interface controller 115 can transfer the data from volatile memory 120 to buffer 135-a (e.g., in response to determining that one of the n sets of volatile memory cells stores the requested data), so that the data can be sent to host device 105. The term "hit" can be used to refer to a scenario where volatile memory 120 stores data requested by host device 105. If one or more sets of n volatile memory cells do not store the requested data (e.g., the n volatile memory cell sets store data for a set of non-volatile memory cells other than the target non-volatile memory cell set), then interface controller 115 can transfer the requested data from non-volatile memory 125 to buffer 135-a (e.g., in response to determining that the n volatile memory cell sets do not store the requested data), so that the data can be transmitted to host device 105. The term "miss" can be used to refer to a scenario where volatile memory 120 does not store data requested by host device 105.

[0035] In a miss scenario, after transferring the requested data to buffer 135-a, interface controller 115 may transfer the requested data from buffer 135-a to volatile memory 120, so that subsequent read requests for the data can be satisfied through volatile memory 120 instead of non-volatile memory 125. For example, interface controller 115 may store data in one of n sets of volatile memory cells associated with a target set of non-volatile memory cells. However, the n sets of volatile memory cells may already be storing data for other sets of non-volatile memory cells. Therefore, to preserve this other data, interface controller 115 may transfer the other data to buffer 135-b so that it can be transferred to non-volatile memory 125 for storage. This process may be called "eviction," and the data transferred from volatile memory 120 to buffer 135-b may be called "victimized" data. In some cases, interface controller 115 may transfer a subset of the victimized data from buffer 135-b to non-volatile memory 125. For example, interface controller 115 can transmit one or more subsets of victim data that have changed since the data was initially stored in non-volatile memory 125. Data that is inconsistent between volatile memory 120 and non-volatile memory 125 (e.g., due to an update in one memory but not in another) can in some cases be referred to as "modified" or "dirty" data. In some instances (e.g., when the interface controller is operating in a mode such as write-back mode), dirty data can be data that exists in volatile memory 120 but not in non-volatile memory 125.

[0036] In some instances, such as memory subsystem 110 (but not limited thereto), the device may be coupled to or include a data bus that allows the device to communicate data between memory and another component of the device (e.g., a scheduler or other processing component). The data bus may be configured such that data flows in only one direction at a time; for example, from memory to scheduler, or from memory to scheduler. However, the device may be able to dynamically switch the direction of the data bus, allowing data to be communicated in both directions, although in some instances, data may be communicated at different times. According to the techniques described herein, the device may switch the direction of the data bus when one or more parameters are met, thereby increasing the number of access commands that can be published and served relative to other different technologies, thus improving device performance and other advantages.

[0037] Although described in some cases with reference to a device having a particular configuration (e.g., the configuration of memory subsystem 110, the configuration of interface controller 115), the techniques described herein can be implemented by any device containing a bus that transports information between two components, such as a component of memory and a device (e.g., a scheduler). Furthermore, the techniques described herein are applicable to any type of bus, including data buses, command buses, and address buses, as well as others. Additionally, the techniques described herein can be implemented for any type of memory. However, it should be understood that the techniques described herein can be advantageous for memories with relatively small page sizes (e.g., 32B, 64B).

[0038] Figure 2 This describes an example of a memory subsystem 200 for an efficient bus turnaround strategy, as illustrated in the examples disclosed herein. The memory subsystem 200 may be a reference. Figure 1 An example of the described memory subsystem 110. Therefore, the memory subsystem 200 can be compared with, as in the reference... Figure 1 The host device interaction is described. The memory subsystem 200 may include an interface controller 202, volatile memory 204, and non-volatile memory 206, which may be as described in reference... Figure 1 The described interface controller 115, volatile memory 120, and non-volatile memory 125 are examples. Therefore, the interface controller 202 can represent, as referenced... Figure 1 The described host device interfaces with volatile memory 204 and non-volatile memory 206. For example, interface controller 202 can operate volatile memory 204 as a cache for non-volatile memory 206. Operating volatile memory 204 as a cache allows the subsystem to provide the benefits of non-volatile memory 206 (e.g., non-volatile, high-density storage) while maintaining compatibility with host devices that support protocols different from those of non-volatile memory 206.

[0039] exist Figure 2 In this diagram, dashed lines between components represent data flows or data transmission paths, while solid lines between components represent command flows or command transmission paths. In some cases, the memory subsystem 200 is one of several similar or identical subsystems that may be included in an electronic device. In some instances, each subsystem may be referred to as a slice and may be associated with a corresponding channel of the host device.

[0040] Non-volatile memory 206 can be configured to operate as main memory for a host device (e.g., memory for long-term data storage). In some cases, non-volatile memory 206 may comprise one or more arrays of FeRAM cells. Each FeRAM cell may include a select element and a ferroelectric capacitor and can be accessed by applying appropriate voltages to one or more access lines such as word lines, board lines, and digital lines. In some instances, a subset of FeRAM cells coupled to an active word line may be sensed, for example, in parallel or simultaneously, without having to sense all FeRAM cells coupled to an active word line. Therefore, the page size for the FeRAM array may be different from (e.g., smaller than) the DRAM page size. In the context of a memory device, a page may refer to a row of memory cells (e.g., a group of memory cells with a common row address), and the page size may refer to the number of row of memory cells or column addresses, or the number of column addresses accessed during an access operation. Alternatively, the page size may refer to the size of data processed by various interfaces. In some cases, different memory device types may have different page sizes. For example, a DRAM page size (e.g., 2kB) can be a superset of a non-volatile memory (e.g., FeRAM) page size (e.g., 64B).

[0041] The smaller page size of FeRAM arrays offers various efficiency benefits because individual FeRAM cells may require more power to read or write compared to individual DRAM cells. For example, a smaller page size for FeRAM arrays promotes efficient energy use because a smaller number of FeRAM cells can be activated at minute intervals of correlated changes in information. In some instances, depending on the nature of the data and commands used for FeRAM operations, the page size for the FeRAM cell array can, for example, change dynamically (e.g., during operation of the FeRAM cell array).

[0042] While individual FeRAM cells may require more power to read or write compared to individual DRAM cells, FeRAM cells can maintain their stored logic states for extended periods in the absence of an external power supply because the ferroelectric material in the FeRAM cell can maintain a non-zero polarization in the absence of an electric field. Therefore, including an FeRAM array in non-volatile memory 206 can provide efficiency benefits relative to volatile memory cells (e.g., DRAM cells in volatile memory 204) because it reduces or eliminates the requirement for refresh operations.

[0043] Volatile memory 204 can be configured to operate as a cache for non-volatile memory 206. In some cases, volatile memory 204 may comprise one or more arrays of DRAM cells. Each DRAM cell may include a capacitor containing dielectric material for storing charges representing programmable states. The memory cells of volatile memory 204 may be logically grouped or arranged into one or more memory groups (as referred to herein as “groups”). For example, volatile memory 204 may comprise sixteen groups. The memory cells of a group may be arranged in a grid or an array of intersecting columns and rows, and each memory cell can be accessed or refreshed by applying appropriate voltages to the digital lines (e.g., column lines) and word lines (e.g., row lines) for the memory cell. A row of a group may be referred to as a page, and the page size may refer to the number of columns or memory cells in a row. As mentioned, the page size of volatile memory 204 may be different from (e.g., larger than) the page size of non-volatile memory 206.

[0044] Interface controller 202 may include various circuitry for interfacing (e.g., communicating) with other devices, such as host devices, volatile memory 204, and non-volatile memory 206. For example, interface controller 202 may include a data (DA) bus interface 208, a command and address (C / A) bus interface 210, a data bus interface 212, a C / A bus interface 214, a data bus interface 216, and a C / A bus interface 264. The data bus interfaces may support the use of one or more communication protocols to convey information. For example, data bus interface 208, C / A bus interface 210, data bus interface 216, and C / A bus interface 264 may support information conveyed using a first protocol (e.g., LPDDR signaling), while data bus interface 212 and C / A bus interface 214 may support information conveyed using a second protocol. Therefore, the various bus interfaces coupled to interface controller 202 may support different data volumes or data rates.

[0045] Data bus interface 208 can be coupled to data bus 260, transaction bus 222, and buffer circuitry system 224. Data bus interface 208 can be configured to transmit and receive data via data bus 260 and to transmit and receive control information (e.g., acknowledgment / negative acknowledgment) or metadata via transaction bus 222. Data bus interface 208 can also be configured to transfer data between data bus 260 and buffer circuitry system 224. Data bus 260 and transaction bus 222 can be coupled to interface controller 202 and host device, thereby establishing a conductive path between interface controller 202 and host device. In some instances, the pin of transaction bus 222 may be referred to as a Data Mask Inversion (DMI) pin. Although shown as having one data bus 260 and one transaction bus 222, any number of data buses 260 and any number of transaction buses 222 may be coupled to one or more data bus interfaces 208.

[0046] C / A bus interface 210 can be coupled to C / A bus 226 and decoder 228. C / A bus interface 210 can be configured to transmit and receive commands and addresses via C / A bus 226. Commands and addresses received via C / A bus 226 can be associated with data received or transmitted via data bus 260. C / A bus interface 210 can also be configured to transmit commands and addresses to decoder 228, such that decoder 228 can decode the commands and forward the decoded commands and associated addresses to command circuitry 230.

[0047] Data bus interface 212 can be coupled to data bus 232 and memory interface circuitry 234. Data bus interface 212 can be configured to transmit and receive data on data bus 232, which can be coupled to non-volatile memory 206. Data bus interface 212 can also be configured to transfer data between data bus 232 and memory interface circuitry 234. C / A bus interface 214 can be coupled to C / A bus 236 and memory interface circuitry 234. C / A bus interface 214 can be configured to receive commands and addresses from memory interface circuitry 234 and forward commands and addresses on C / A bus 236 to non-volatile memory 206 (e.g., to a local controller of non-volatile memory 206). Commands and addresses transmitted via C / A bus 236 can be associated with data received or transmitted via data bus 232. The data bus 232 and the C / A bus 236 can be coupled to the interface controller 202 and the non-volatile memory 206, thereby establishing a conductive path between the interface controller 202 and the non-volatile memory 206.

[0048] Data bus interface 216 can be coupled to data bus 238 and memory interface circuitry 240. Data bus interface 216 can be configured to transmit and receive data via data bus 238, which can be coupled to volatile memory 204. Data bus interface 216 can also be configured to transfer data between data bus 238 and memory interface circuitry 240. C / A bus interface 264 can be coupled to C / A bus 242 and memory interface circuitry 240. C / A bus interface 264 can be configured to receive commands and addresses from memory interface circuitry 240 and forward commands and addresses to volatile memory 204 via C / A bus 242 (e.g., to a local controller of volatile memory 204). Commands and addresses transmitted via C / A bus 242 can be associated with data received or transmitted via data bus 238. The data bus 238 and the C / A bus 242 can be coupled to the interface controller 202 and the volatile memory 204, thereby establishing a conductive path between the interface controller 202 and the volatile memory 204.

[0049] In addition to the bus and bus interface for communicating with the coupled devices, the interface controller 202 may also include circuitry for operating the non-volatile memory 206 as main memory and the volatile memory 204 as a cache. For example, the interface controller 202 may include a command circuitry 230, a buffer circuitry 224, a cache management circuitry 244, one or more engines 246, and one or more schedulers 248.

[0050] Command circuitry system 230 may be coupled to buffer circuitry system 224, decoder 228, cache management circuitry system 244, scheduler 248, and other components. Command circuitry system 230 may be configured to receive command and address information from decoder 228 and store the command and address information in queue 250. Command circuitry system 230 may include logic 262 that processes command information (e.g., from a host device) and stores information from other components (e.g., cache management circuitry system 244, buffer circuitry system 224) and uses the information to generate one or more commands for scheduler 248. Command circuitry system 230 may also be configured to transmit address information (e.g., address bits) to cache management circuitry system 244. In some instances, logic 262 may be circuitry configured to operate as a finite state machine (FSM).

[0051] Buffer circuitry system 224 may be coupled to data bus interface 208, command circuitry system 230, memory interface circuitry system 234, and memory interface circuitry system 234. Buffer circuitry system 224 may include a collection of one or more buffer circuits for at least some groups (if not every group) of volatile memory 204. Buffer circuitry system 224 may also include components for accessing the buffer circuits (e.g., a memory controller). In one example, volatile memory 204 may include sixteen groups and buffer circuitry system 224 may include sixteen sets of buffer circuits. Each set of buffer circuits may be configured to store data from a corresponding group of volatile memory 204 or for a corresponding group of volatile memory 204 (or both). As an example, the buffer circuitry for group 0 (BK0) may be configured to store data from or for the first group of volatile memory 204 (or both), and the buffer circuitry for group 15 (BK15) may be configured to store data from or for the sixteenth group of volatile memory 204 (or both).

[0052] Each set of buffer circuits in buffer circuit system 224 may include a pair of buffers. The pair of buffers may include: one buffer (e.g., an open page data (OPD) buffer) configured to store data targeted by an access command (e.g., a store command or retrieval command) from the host device; and another buffer (e.g., a victim page data (VPD) buffer) configured to store data for a retrieval process triggered by the access command. For example, the set of buffer circuits for BK0 may include buffers 218 and 220, which may be instances of buffers 135-a and 135-b, respectively. Buffer 218 may be configured to store BK0 data targeted by an access command from the host device. And buffer 220 may be configured to store data transferred from BK0 as part of a retrieval process triggered by the access command. Each buffer in the set of buffer circuits may be configured with a size (e.g., storage capacity) corresponding to the page size of volatile memory 204. For example, if the page size of volatile memory 204 is 2kB, then the size of each buffer can be 2kB. Therefore, in some instances, the size of the buffer can be equal to the page size of volatile memory 204.

[0053] Cache management circuitry system 244 may be coupled to command circuitry system 230, engine 246, scheduler 248, and other components. Cache management circuitry system 244 may include sets of cache management circuitry for one or more groups (e.g., each group) of volatile memory. As an example, cache management circuitry system 244 may include sixteen sets of cache management circuitry for BK0 through BK15. Each set of cache management circuitry may include two memory arrays configured to store storage information for volatile memory 204. As an example, the set of cache management circuitry for BK0 may include memory array 252 (e.g., a CDRAM tag array (CDT-TA)) and memory array 254 (e.g., a CDRAM active (CDT-V) array), configured to store storage information for BK0. In some instances, the memory array may also be referred to as an array or buffer. In some cases, the memory array may be or contain volatile memory cells, such as SRAM cells.

[0054] The storage information may include content information, validity information, or dirty information (or any combination thereof) associated with volatile memory 204. Content information (which may also be referred to as tag information or address information) indicates which data is stored in the set of volatile memory cells. For example, content information (e.g., tag addresses) for a set of one or more volatile memory cells may indicate which set of one or more non-volatile memory cells currently has data stored in that set of one or more volatile memory cells. Validity information may indicate whether the data stored in the set of volatile memory cells is actual data (e.g., data with a desired order or form) or placeholder data (e.g., random or dummy data without a desired or important order). Dirty information may indicate whether the data stored in the set of one or more volatile memory cells of volatile memory 204 is different from the corresponding data stored in the set of one or more non-volatile memory cells of non-volatile memory 206. For example, dirty information may indicate whether the data stored in the set of volatile memory cells has been updated relative to the data stored in non-volatile memory 206.

[0055] Memory array 252 may include memory cells that store storage information (e.g., content and validity information) for an associated group (e.g., BK0) of volatile memory 204. The storage information may be stored on a per-page basis (e.g., there may be corresponding storage information for each page of an associated non-volatile memory group). Interface controller 202 can examine requested data in volatile memory 204 by referring to the storage information in memory array 252. For example, interface controller 202 may receive a retrieval command from a host device for data in a set of non-volatile memory cells in non-volatile memory 206. Interface controller 202 may use a set of one or more address bits (e.g., a set of row address bits) targeted by the access request to refer to the storage information in memory array 252. For example, using set association mapping, interface controller 202 may refer to content information in memory array 252 to determine which set of volatile memory cells (if it exists) stores the requested data.

[0056] In addition to storing content information for the volatile memory cells, memory array 252 may also store validity information, indicating whether data in the set of volatile memory cells is actual data (also called valid data) or random data (also called invalid data). For example, a volatile memory cell in volatile memory 204 may initially store random data and continue to do so until data is written to the volatile memory cell from a host device or non-volatile memory 206. To track which data is valid, memory array 252 may be configured to set a bit for each set of volatile memory cells as actual data is stored in the set. This bit may be called a validity bit or validity flag. Like content information, validity information stored in memory array 252 may be stored on a per-page basis. Thus, in some instances, each validity bit may indicate the validity of data stored in the associated page.

[0057] Memory array 254 may be similar to memory array 252 and may also include memory cells that store validity information for a group (e.g., BK0) of volatile memory 204 associated with memory array 252. However, instead of a per-page basis for memory array 252, the validity information stored in memory array 254 may be stored on a sub-block basis. For example, the validity information stored in a memory cell of memory array 254 may indicate the validity of data for a subset of volatile memory cells in a set of volatile memory cells (e.g., pages). As an example, the validity information in memory array 254 may indicate the validity of each subset (e.g., 64B) of data in a data page stored in BK0 of volatile memory 204. Storing content information and validity information on a per-page basis in memory array 252 allows interface controller 202 to quickly and efficiently determine whether there is a hit or miss for data in volatile memory 204. The sub-block-based storage validity information allows the interface controller 202 to determine which subsets of data are retained in the non-volatile memory 206 during the repossession process.

[0058] Each cache management circuitry may also include a corresponding pair of registers coupled to command circuitry system 230, engine 246, memory interface circuitry system 234, memory interface circuitry system 240, and the memory array for the cache management circuitry, as well as other components. For example, the cache management circuitry may include a first register (e.g., register 256, which may be an Open Page Mark (OPT) register) configured to receive storage information (e.g., one or more bits of tag information, validity information, or dirty information) from memory array 252 or scheduler 248-b, or both. The cache management circuitry may also include a second register (e.g., register 258, which may be a Victim Page Mark (VPT) register) configured to receive storage information from memory array 254 and scheduler 248-a, or both. The information in registers 256 and 258 can be passed to command circuitry system 230 and engine 246 to enable decisions to be made by these components. For example, the command circuit system 230 can issue commands to read non-volatile memory 206 or volatile memory 204 based on content information from register 256.

[0059] Engine 246-a can be coupled to registers 256 and 258 and scheduler 248. Engine 246-a can be configured to receive stored information from various components and issue commands to scheduler 248 based on the stored information. For example, when interface controller 202 is in a first mode, such as write-through mode, engine 246-a can issue commands to scheduler 248-b, and in response, scheduler 248-b can initiate or facilitate data transfers from buffer 218 to both volatile memory 204 and non-volatile memory 206. Alternatively, when interface controller 202 is in a second mode, such as write-back mode, engine 246-a can issue commands to scheduler 248-b, and in response, scheduler 248-b can initiate or facilitate data transfers from buffer 218 to volatile memory 204. In the case of a write-back operation, data stored in volatile memory 204 during a subsequent eviction process can eventually be transferred to non-volatile memory 206.

[0060] Engine 246-b may be coupled to register 258 and scheduler 248-a. Engine 246-b may be configured to receive stored information from register 258 and issue commands to scheduler 248-a based on the stored information. For example, engine 246-b may issue commands to scheduler 248-a to initiate or facilitate the transfer of dirty data from buffer 220 to non-volatile memory 206 (e.g., as part of a retrieval process). If buffer 220 holds a set of data transferred from volatile memory 204 (e.g., damaged data), then engine 246-b may indicate which one or more subsets (e.g., which 64Bs) of the set of data in buffer 220 should be transferred to non-volatile memory 206.

[0061] Scheduler 248-a can be coupled to various components of interface controller 202 and can facilitate access to non-volatile memory 206 by issuing commands to memory interface circuitry 234. Commands issued by scheduler 248-a can be based on commands from command circuitry 230, engine 246-a, engine 246-b, or a combination of these components. Similarly, scheduler 248-b can be coupled to various components of interface controller 202 and can facilitate access to volatile memory 204 by issuing commands to memory interface circuitry 240. Commands issued by scheduler 248-b can be based on commands from command circuitry 230 or engine 246-a, or both.

[0062] The memory interface circuitry 234 can communicate with the non-volatile memory 206 via one or more of the data bus interface 212 and the C / A bus interface 214. For example, the memory interface circuitry 234 can prompt the C / A bus interface 214 to forward commands issued by the memory interface circuitry 234 to a local controller in the non-volatile memory 206 via the C / A bus 236. Furthermore, the memory interface circuitry 234 can transmit data to or receive data from the non-volatile memory 206 via the data bus 232. In some instances, commands issued by the memory interface circuitry 234 may be supported by the non-volatile memory 206 rather than the non-volatile memory 204 (e.g., commands issued by the memory interface circuitry 234 may differ from commands issued by the memory interface circuitry 240).

[0063] Memory interface circuitry 240 can communicate with volatile memory 204 via one or more of data bus interface 216 and C / A bus interface 264. For example, memory interface circuitry 240 can prompt C / A bus interface 264 to forward commands issued by memory interface circuitry 240 to the local controller of volatile memory 204 via C / A bus 242. Additionally, memory interface circuitry 240 can transmit data to or receive data from volatile memory 204 via one or more data buses 238. In some instances, commands issued by memory interface circuitry 240 may be supported by volatile memory 204 instead of non-volatile memory 206 (e.g., commands issued by memory interface circuitry 240 may differ from commands issued by memory interface circuitry 234).

[0064] In summary, the components of interface controller 202 can operate non-volatile memory 206 as main memory and volatile memory 204 as cache. This operation can be prompted by one or more access commands (e.g., read / retrieve command / request and write / store command / request) received from the host device.

[0065] In some instances, interface controller 202 may receive a store command from a host device. The store command may be received via C / A bus 226 and transmitted to command circuitry 230 via one or more of C / A bus interface 210 and decoder 228. The store command may include or be accompanied by address bits targeting a memory address of non-volatile memory 206. Data to be stored may be received via data bus 260 and transmitted to buffer 218 via data bus interface 208. In write-through mode, interface controller 202 may transmit data to both non-volatile memory 206 and volatile memory 204. In write-back mode, interface controller 202 may transmit data only to volatile memory 204. In either mode, interface controller 202 may first check whether volatile memory 204 has memory cells available for storing data. For this purpose, the command circuitry 230 can refer to the memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n volatile memory cell sets (e.g., pages) associated with a memory address are empty (e.g., storing random or invalid data). In some cases, the volatile memory cell set in the volatile memory 204 may be referred to as a line or cache line.

[0066] If one of the n associated sets of volatile memory cells is available for storing information, then the interface controller 202 can transfer data from buffer 218 to volatile memory 204 for storage in the set of volatile memory cells. However, if the associated set of volatile memory cells is not empty, then the interface controller 202 can initiate a reclamation process to free up space for data in volatile memory 204. The reclamation process may involve transferring old data (e.g., existing data) from one of the n associated sets of volatile memory cells to buffer 220. Dirty information for the old data may also be transferred to memory array 254 or register 258 to identify a dirty subset of the old data. After storing the old data in buffer 220, new data can be transferred from buffer 218 to volatile memory 204, and old data can be transferred from buffer 220 to non-volatile memory 206. In some cases, a dirty subset of the old data is transferred to non-volatile memory 206, and a clean subset (e.g., an unmodified subset) is discarded. A dirty subset can be identified by engine 246-b based on dirty information transferred to memory array 254 or register 258 during the recovery process (e.g., from volatile memory 204).

[0067] In another example, interface controller 202 may receive a retrieval command from a host device. The retrieval command may be received via C / A bus 226 and transmitted to command circuitry 230 via one or more of C / A bus interface 210 and decoder 228. The retrieval command may include address bits targeting a memory address of non-volatile memory 206. Before attempting to access the target memory address of non-volatile memory 206, interface controller 202 may check to determine whether volatile memory 204 stores data. To do this, command circuitry 230 may refer to memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of a set of n volatile memory cells associated with the memory address store the requested data. If the requested data is stored in volatile memory 204, then interface controller 202 may transmit the requested data to buffer 218 for transmission to the host device via data bus 260.

[0068] If the requested data is not stored in volatile memory 204, then interface controller 202 can retrieve the data from non-volatile memory 206 and transfer the data to buffer 218 for transmission to the host device via data bus 260. Alternatively, interface controller 202 can transfer the requested data from buffer 218 to volatile memory 204, allowing access to the data with lower latency during subsequent retrieval operations. However, before transferring the requested data, interface controller 202 can first determine whether one or more of the n associated sets of volatile memory cells are available to store the requested data. Interface controller 202 can determine the availability of the n associated sets of volatile memory cells by communicating with the associated cache management circuitry. If the associated sets of volatile memory cells are available, then interface controller 202 can transfer the data in buffer 218 to volatile memory 204 without performing a retrieval process. Otherwise, interface controller 202 can transfer the data from buffer 218 to volatile memory 204 after performing a retrieval process.

[0069] The memory subsystem 200 can be implemented in one or more configurations, including single-chip and multi-chip versions. The multi-chip version may include one or more components of the memory subsystem 200, including interface controller 202, volatile memory 204, and non-volatile memory 206 (and other components or combinations thereof), on a separate chip from the chip containing one or more other components of the memory subsystem 200. For example, in a multi-chip version, the respective separate chip may contain each of interface controller 202, volatile memory 204, and non-volatile memory 206. In contrast, the single-chip version may include interface controller 202, volatile memory 204, and non-volatile memory 206 on a single chip.

[0070] It should be understood that volatile memory 204 and non-volatile memory 206 can support various strategies for accessing memory cells. For example, non-volatile memory 206 can adhere to an activation strategy that requires non-volatile memory 206 to activate a row before reading data from or writing data to it. Additionally, non-volatile memory 206 can adhere to a page closing strategy that requires closing (or “deactivating”) a row in the same group of non-volatile memory 206 before activating another row in the same group. Due to the activation and page closing strategies, as well as various timing and operational parameters, non-volatile memory 206 can wait for a threshold duration between the activation of different rows in the same memory group. The threshold duration between the activation of different rows in the same memory group may be referred to herein as a timing constraint tRC, timing parameter tRC, or timing limit tRC, and other suitable terms. Therefore, non-volatile memory 206 can satisfy the timing constraint tRC between the activation of different rows in the same memory group. Groups that have satisfied the timing constraint tRC may be referred to herein as groups ready to service or execute commands.

[0071] As mentioned, data can be transmitted between non-volatile memory 206 and interface controller 202 via data bus 232. To facilitate the transmission of data in and out of non-volatile memory 206, interface controller 202 (or another component in an alternative embodiment) can be configured (e.g., via scheduler 248-a) to change the direction of data bus 232. The direction of data bus 232 can also be referred to as the mode of data bus 232, and can refer to the incoming or outgoing data flow from the perspective of interface controller 202 (or conversely, from the perspective of non-volatile memory 206). To operate data bus 232 in a direction or mode, interface controller 202 can configure data bus 232 and any suitable interface component (e.g., data bus interface 212) to support incoming data flow (relative to interface controller 202) or outgoing data flow (relative to interface controller 202). However, reconfiguring data bus 232 to switch directions can be a time-consuming process.

[0072] To reduce the time spent reconfiguring the data bus 232, the interface controller 202 can change the direction of the data bus 232 based on a turnaround strategy that defines various conditions for changing the direction of the data bus 232. For example, the interface controller 202 can monitor queued read and write commands for non-volatile memory and switch the direction of the data bus 232 based on the number and / or relative number of read and write commands. For example, the interface controller 202 can maintain the data bus 232 in read mode until the number of queued read commands is below a threshold number, the number of queued write commands is above a threshold number, and / or the number of write commands exceeds (e.g., by a threshold number) the number of read commands (e.g., by a threshold number).

[0073] However, in some situations, this turnaround strategy (e.g., a strategy that focuses solely on the number of access commands) can introduce inefficiencies. For example, consider a scenario where there are more read commands than write commands. Furthermore, read commands are for different rows within the same group of non-volatile memory 206, while write commands are for different groups within non-volatile memory 206. In these scenarios, interface controller 202 can continue operating the data bus 232 in the read direction—even if doing so increases the latency (tRC) from satisfying the timing constraints of the groups targeted by read commands—because the number of read commands is greater than the number of write commands. Therefore, the latency of non-volatile memory 206 can increase, which can negatively impact the performance of interface controller 202.

[0074] According to the techniques described herein, the latency of nonvolatile memory 206 can be reduced by using an efficient turnaround strategy that allows interface controller 202 to strategically (e.g., dynamically) change the direction of data bus 232, such that the satisfaction of timing constraint tRC for one group does not delay the issuance of access commands for other groups.

[0075] Although described with reference to memory subsystem 200, the effective turnover strategies described herein can be implemented in any device containing memory that conforms to, for example, the activation strategies, page closing strategies, and / or timing constraints described herein.

[0076] Figure 3 Timing diagram 300 illustrates an efficient turnaround strategy for a bus based on examples disclosed herein. Timing diagram 300 illustrates an example of the efficient turnaround strategy described herein when the device has a larger queue of read commands than queued write commands for the memory. Therefore, Figure 3 The access commands shown herein can be access commands issued by the device using the efficient turnaround strategies described herein. The device may be or include, as referenced... Figure 1The memory subsystem 110 described or as referenced Figure 2 The described aspects of the memory subsystem 200. Alternatively, the device can be any type of device comprising various components, such as memory and a bus, such as a data bus. For example, the device may include a data bus between memory and a scheduler (or “scheduling component”). Compared to other turnaround strategies, the efficient turnaround strategy described herein allows the device to strategically issue access commands, making timing constraints (e.g., timing penalties) for activating different rows in the same group more effectively hidden.

[0077] Each access command in sequence diagram 300 may include a command opcode (indicating the command type) and address information. The address information may include the row and group targeted by the access command. Figure 3 In this document, the command type (denoted as "CMD") is represented by "Ar", "Ra", "Aw", and "Wa", where "Ar" indicates an activation command for a read operation, "Ra" indicates a read command with automatic precharge, "Aw" indicates an activation command for a write operation, and "Wa" indicates a write command with automatic precharge. For simplicity, the activation command for a read operation may be referred to herein as a read activation command, and the command for activating a write operation may be referred to herein as a write activation command. A read command or write command with automatic precharge can be a read command or write command that causes the memory to automatically perform a precharge operation independently of an explicit precharge command. Although described with reference to read commands and write commands with automatic precharge, the turnaround strategies described herein can be implemented with read commands and write commands that do not have automatic precharge or may otherwise have other differences or characteristics.

[0078] According to the efficient turnaround strategy described herein, the device can change the direction of the data bus based on the readiness of one or more groups of service (e.g., execution) activation commands and other factors. Compared to other turnaround strategies, the efficient turnaround strategy allows the device to issue more access commands during time period 305, and thus transmit more data via the data bus, thereby improving device performance. For example, in addition to issuing read activation commands 310, 320, and 330 during time period 305, the efficient turnaround strategy may also allow the device to issue write activation commands 315 and 325, which, under other different turnaround strategies, would not be issued until much later (e.g., after time t5).

[0079] As mentioned, timing diagram 300 illustrates access commands issued under the efficient turnaround strategy described herein. It should be understood that the issuance of different types of access commands can be associated with or linked to the direction or mode of the data bus. For example, a write command can be associated with a first direction of the data bus (or "write mode"), and a read command can be associated with a second direction of the data bus (or "read mode"). Therefore, issuing different types of commands can be associated with changes in the direction or mode of the data bus, enabling the communication of data associated with the commands between the scheduler and memory. Furthermore, it should be understood that increasing the rate of access command issuance can increase the rate of data exchange between the scheduler and memory, thereby improving device performance.

[0080] In the provided examples, there may be more queued read commands than queued write commands for the memory. For example, there may be six queued read commands (although only three are explicitly shown) and three queued write commands. Furthermore, read commands may be available for a first set of groups in the memory, and write commands may be available for a second set of groups in the memory. For example, read commands may be available for groups 0, 1, and 2 in the memory, and write commands may be available for groups 3, 4, and 5 in the memory. According to the efficient turnaround strategy described herein, the device may issue activation commands for read commands at time t0. For example, the device may issue read activation command 310, such that read activation commands are issued for group 0, for group 1, and for group 2. Each of the read activation commands 310 may ultimately be communicated to the memory.

[0081] After issuing a read activation command 310, the device may wait for a duration 335 before issuing a read command 320. Additionally, the device may wait for a duration 340 before issuing read activation commands 330 for groups 0, 1, and 2. The duration 335 may represent the minimum amount of time required before issuing a read or write command after the associated activation command. Therefore, a duration 335 may exist between each activation command and its associated read or write command. In some instances, the duration 335 may be referred to as timing constraint tRCD, timing parameter tRCD, timing limit tRCD, or other suitable terms. It should be understood that, in addition to complying with timing constraint tRCD, the device may also comply with timing constraint tRC, which may be represented by the duration 340 and, as indicated, may be the minimum amount of time required between activations of different rows in the memory group. Therefore, the device can effectively prevent the issuance of activation commands for the first set of memory groups (e.g., groups 0, 1, and 2) until the duration 340 has expired for each read activation command 310. As an example, the device may prevent the issuance of a read activation command 330 for group 0 until time t4. The duration 340 between activation commands for a group may be related to the issuance of the activation command.

[0082] However, the device can issue a write activation command 315 during duration 335 according to the efficient turnaround strategy described herein, instead of waiting until all six read commands have been issued to memory before the write activation command 315 for memory is issued. For example, the device can issue the write activation command 315 at time t1. The device can do this because the write activation command 315 is for a different group than the read activation command 310. As a condition for issuing the write activation command 315 at time t1, the device can determine that each group targeted by the write command 325 is ready to serve activation commands. That is, the device can determine that the group targeted by the write command 325 has satisfied or complied with timing constraints tRC. Therefore, the device can use the satisfaction of timing constraints tRC, along with other factors, as a basis for switching the type of issued command and thus the direction of the data bus.

[0083] After a duration of 335, the device may issue a read command 320 at time t2. In response to the read command 320, the device may receive the data requested by the read command via the data bus, which can be configured in read mode. At time t3, the device may issue a write command 325 that can target groups 3, 4, and 5. A duration of 335 may exist between each write command and its associated write activation command to satisfy the timing constraint tRCD. To provide the data to be written to memory, the device may configure the data bus to operate in write mode. Therefore, the device may reconfigure the data bus according to the efficient turnaround strategy described herein, which may allow data to be written to memory earlier than other turnaround strategies (without delaying the issuance of the read activation command 330). For example, even if write activation command 315 and write command 325 are issued, the device may still issue read activation command 330 at time t4, which may be the earliest time that the device is allowed to issue read activation command 330 due to the timing constraint tRC. Therefore, a device using the efficient turnaround strategy described herein can issue a larger number of access commands between time t0 and time t5, and in doing so, it will improve the efficiency of the device, as well as other advantages.

[0084] Figure 4 This describes an example of process flow 400 supporting an efficient turnaround strategy for the bus, based on examples disclosed herein. Process flow 400 can be derived from, as referenced... Figure 1 The interface controller 115 described or as referenced Figure 2 The described interface controller 202 is implemented. However, other types of devices may implement process flow 400. Process flow 400 can illustrate the operation of a device that uses the efficient turnaround technique described herein to change the operating mode of the data bus from a read direction to a write direction.

[0085] For ease of reference, process flow 400 is described using a reference apparatus. For example, aspects of process flow 400 may be implemented by an apparatus comprising a data bus (or coupled thereto) between components of the apparatus (e.g., a scheduler) and a memory. Alternatively, aspects of process flow 400 may be implemented as instructions stored in memory (e.g., firmware stored in volatile memory 120 and / or non-volatile memory 125). For example, instructions, when executed by a controller, may cause the controller to perform the operations of process flow 400.

[0086] At 405, the data bus can be configured to operate in read mode (e.g., the data bus can be configured to operate in a first direction), which can be a mode that supports the transmission of data from memory to the scheduler. In some instances, the data bus can be configured to operate in read commands after power-on or hold-reset. At 410, it can be determined whether 1) the read queue for memory is empty and 2) whether at least one group (or a threshold number of groups) targeted by queued write commands is available for write activation commands. The term read queue can refer to a physical or conceptual queue of read commands pending in memory, and thus the number of read commands in the read queue can represent the number of read commands queued for memory. If a group has satisfied the timing constraint tRC for activating different rows in the group, then the group is "available" or "ready for" write activation commands.

[0087] If at 410 it is determined that 1) the read queue for memory is empty and 2) at least one group (or a threshold number of groups) targeted by the queued write command is available for the write activation command, then the process can proceed to 440. At 440, the data bus can be configured to operate in write mode (e.g., the data bus can be configured to operate in a second direction), which can be a mode that supports the transfer of data from the scheduler to memory.

[0088] If at 410 it is determined that 1) the read queue for memory is not empty, or 2) no group (or fewer than a threshold number of groups) targeted by a queued write command is available for a write activation command, then the process proceeds to 415. At 415, it is determined whether 1) at least one group (or a threshold number of groups) targeted by a read command is available for a read activation command, and 2) whether a high priority is assigned to any queued write command. If a group has satisfied the timing constraint tRC for activating different rows in the group, then the group is "available" or "ready for" a read activation command. In some instances, the priority of a write command can be determined by checking the high priority flag of the write command.

[0089] If present, the two conditions at 415 may conflict, where the availability of the group for read activation commands proves the maintenance of the data bus in read mode, and the high-priority ordering of queued write commands proves the reconfiguration of the data bus to write mode. To resolve the conflict arising when these two conditions exist, the device may be configured to proceed to 425. For example, if at 415 it is determined that 1) at least one group (or a threshold number of groups) targeted by read commands is available for read activation commands, and 2) a high priority is assigned to any of the queued write commands, then the process may proceed to 425. At 425, it may be determined whether the number of queued write commands for memory is greater than or equal to (e.g., matches or exceeds) a threshold number (e.g., threshold 2).

[0090] If at 415 it is determined that 1) no group (or fewer than the threshold number of groups) is targeted by the read command and is available for the read activation command, and 2) none of the queued write commands (or fewer than the threshold number) are assigned high priority, then the process can proceed to 420. At 420 it can be determined that 1) no group (or fewer than the threshold number of groups) is available for the read activation command, or 2) the threshold number of read activation commands (or read commands) have been issued (e.g., threshold 1) because the data bus is configured in read mode.

[0091] If at 420 it is determined that 1) at least one group (or more than a threshold number of groups) targeted by the read command is available for the read activation command, and 2) since the data bus is configured in read mode, fewer than a threshold number (e.g., threshold 1) of read activation commands (or read commands) have been issued, then the data bus can be maintained in read mode, and the process can proceed to 410.

[0092] If at 420 it is determined that 1) no group (or fewer than the threshold number of groups) is available for a read activation command, or 2) a threshold number of read activation commands (or read commands) have been issued (e.g., threshold 1) because the data bus is configured in read mode, then the process can proceed to 425. At 425, it can be determined whether the number of queued write commands for memory is greater than or equal to the threshold number (e.g., threshold 2). Alternatively, at 425, it can be determined whether the queued write commands for memory are for a sixteen-byte write command (e.g., a WR16 command) or a masked write command (e.g., MWR).

[0093] If at 425 it is determined that the number of queued write commands for memory is less than a threshold number (e.g., threshold 2), then the data bus can be maintained in read mode, and the process can proceed to 410. Alternatively, if at 425 it is determined that the queued write commands for memory are not WR16 or MWR commands, then the process can proceed to 410. If at 425 it is determined that the number of queued write commands for memory is greater than or equal to the threshold number (e.g., number 2), then the process can proceed to 430. Alternatively, if at 425 it is determined that the queued write commands for memory are WR16 or MWR commands, then the process can proceed to 430.

[0094] At 430, it can be determined whether the group targeted by the queued write command is available for the write activation command. If at 430 it is determined that the group targeted by the write command is not available for the write activation command, then the process can proceed to 435. At 435, one or more high-priority flags for queued write commands can be set to indicate that one or more write commands are assigned high priority (e.g., relative to other queued access commands). If at 430 it is determined that the group targeted by the write command is available for the write activation command, then at 440, the data bus can be configured to operate in write mode.

[0095] Therefore, the device can be configured to use the satisfaction of the group pair timing constraint tRC, either alone or in combination with one or more other bases, as a basis for changing the operating mode of the data bus from a read direction to a write direction. It should be understood that the various thresholds used in process flow 400 are configurable and can therefore be dynamically updated by the device based on one or more operating parameters or operating conditions of the device or system. It should also be understood that alternative instances of process flow 400 can be implemented, in which some operations are performed in a different order than those described or not at all. Additionally, operations may include additional features not mentioned, or additional operations may be added.

[0096] Figure 5 This describes an example of process flow 500 supporting an efficient turnaround strategy for the bus, based on examples disclosed herein. Process flow 500 can be derived from, as referenced... Figure 1 The interface controller 115 described or as referenced Figure 2 The described interface controller 202 is implemented. However, other types of devices may implement process flow 500. Process flow 500 can illustrate the operation of a device that uses the efficient turnaround technique described herein to change the operating mode of the data bus from a write direction to a read direction.

[0097] For ease of reference, process flow 500 is described using a reference apparatus. For example, aspects of process flow 500 may be implemented by an apparatus comprising a data bus (or coupled thereto) between components of the apparatus (e.g., a scheduler) and a memory. Alternatively, aspects of process flow 500 may be implemented as instructions stored in memory (e.g., firmware stored in volatile memory 120 and / or non-volatile memory 125). For example, instructions, when executed by a controller, may cause the controller to perform the operations of process flow 500.

[0098] At 505, the data bus can be configured to operate in write mode (e.g., the data bus can be configured to operate in a first direction). At 510, it can be determined that 1) no group (or fewer than a threshold number of groups) is available for a write activation command, or 2) since the data bus is configured in write mode, a threshold number of write activation commands (or write commands) has been issued (e.g., threshold 3). If at 420 it is determined that 1) at least one group (or more than a threshold number of groups) targeted by the write command is available for a write activation command, and 2) since the data bus is configured in write mode, fewer than a threshold number of write commands (e.g., threshold 3) has been issued, then the data bus can be maintained in write mode, and the process can proceed to 510.

[0099] If at 510 it is determined that 1) no group (or fewer than the threshold number of groups) is available for a write activation command, or 2) since the data bus is configured in write mode, a threshold number of write activation commands (or write commands) have been issued (e.g., threshold 3), then the process can proceed to 515. At 515, it is determined whether to assign high priority to any queued read commands and target the groups available for read activation commands. If at 515 it is determined that queued read commands are assigned high priority and the groups available for read activation commands are targeted, then at 525, the data bus can be configured to operate in read mode.

[0100] If at 515 it is determined that none of the queued read commands (less than a certain threshold number) are assigned high priority and the group available for read activation commands is targeted, then the process can proceed to 520. At 520, it can be determined whether the number of groups available for read activation commands is greater than or equal to the threshold number (e.g., threshold 4). If at 520 it is determined that the number of groups available for read activation commands is less than the threshold number (e.g., threshold 4), then the data bus can be maintained in write mode, and the process can proceed to 510. If at 520 the number of groups available for read activation commands is greater than or equal to the threshold number (e.g., threshold 4), then at 525, the data bus can be configured to operate in read mode.

[0101] Therefore, the device can use the satisfaction of the group pair timing constraint tRC as the basis for changing the operating mode of the data bus from write to read. It should be understood that the various thresholds used in process flow 500 are configurable and therefore can be dynamically updated by the device based on one or more operating parameters of the device or system. It should also be understood that alternative instances of process flow 500 can be implemented, some of which may be performed in a different order than described or not at all. Additionally, operations may include additional features not mentioned, or additional operations may be added.

[0102] Figure 6A block diagram 600 illustrates a device 605 supporting an efficient bus turnaround strategy according to examples disclosed herein. Device 605 may be an example of a memory subsystem 110, interface controller 115, memory subsystem 200, or interface controller 202, or other means. Device 605 may include a bus management component 610, a queue management component 615, a timing component 620, an access command component 625, a receive component 630, and a transmit component 635. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses or other conductive connections).

[0103] Bus management component 610 may be or include logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein. Queue management component 615 may be or include logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein. Timing component 620 may be or include logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein. Access command component 625 may be or include logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein. Receiving component 630 may be or include logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein. Transmitting component 635 may be or include logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein.

[0104] The bus management component 610 can operate the data bus for the memory in a first direction relative to the memory and associated with a first type of access command.

[0105] In some instances, the bus management component 610 can operate the data bus in a second direction associated with a second type of access command based on determining that a certain number of second-type queued access commands are for a group that has met timing constraints.

[0106] In some instances, the bus management component 610 can configure the data bus for memory to operate in a first direction to communicate data read from memory.

[0107] In some instances, the bus management component 610 may configure the data bus to operate in the second direction to deliver data to the memory based on determining that a certain number of write commands queued for the memory are for a group that has met timing constraints.

[0108] In some instances, the bus management component 610 can configure the data bus for memory to operate in a first direction for delivering data to memory.

[0109] In some instances, the bus management component 610 may configure the data bus to operate in a second direction to convey data from the memory based on determining that a certain number of read commands queued for the memory are for a group that has met timing constraints.

[0110] In some cases, the first direction supports the transmission of data from memory, and the first type of access command includes a read command, while the second direction supports the transmission of data to memory, and the second type of access command includes a write command.

[0111] The queue management component 615 can determine a certain number of second-type queued access commands for the memory that are used for groups that have satisfied timing constraints for activating different rows in the same group.

[0112] In some instances, the queue management component 615 can determine that a certain number of write commands queued for memory are for groups that have satisfied timing constraints for activating different rows in the same group.

[0113] In some instances, the queue management component 615 can determine that a certain number of read commands queued for memory are for groups that have satisfied timing constraints for activating different rows in the same group.

[0114] In some instances, the queue management component 615 can determine that the number of queued access commands of the second type meets a threshold number, wherein the data bus is configured to operate in the second direction based on the determination that the threshold number is met.

[0115] In some instances, the queue management component 615 can determine that fewer than a threshold number of first-type queuing commands are for groups whose timing constraints have been met, wherein the data bus is configured to operate in a second direction based on the determination that fewer than a threshold number of first-type queuing commands are for groups whose timing constraints have been met.

[0116] In some instances, the queue management component 615 can determine that the number of queued write commands meets a threshold number, wherein the data bus is configured to operate in a second direction based on the determination that the threshold number is met.

[0117] In some instances, the queue management component 615 may compare the number of queued write commands with a threshold number, wherein the determination of whether the number of queued write commands meets the threshold number is based on the comparison.

[0118] In some instances, the queue management component 615 may determine that at least one write command among a number of queued write commands is assigned a higher priority relative to other queued write commands, wherein the comparison is based on determining that the at least one write command is assigned a higher priority.

[0119] In some instances, queue management component 615 may determine that the number of read commands issued after the data bus is configured to operate in a first direction meets a threshold number, wherein the data bus is configured to operate in a second direction based on the determination that the threshold number is met.

[0120] In some instances, the queue management component 615 can determine that fewer than a threshold number of queued read commands are for groups that have satisfied timing constraints for activating different rows, wherein the data bus is configured to operate in a second direction based on the determination that fewer than a threshold number of queued read commands are for groups that have satisfied timing constraints for activating different rows.

[0121] In some instances, the queue management component 615 can determine that the number of queued read commands meets a threshold number, wherein the data bus is configured to operate in a second direction based on the determination that the threshold number is met.

[0122] In some instances, the queue management component 615 may compare the number of queued read commands with a threshold number, wherein the determination of whether the number of queued read commands meets the threshold number is based on the comparison.

[0123] In some instances, the queue management component 615 can determine a certain number of queue read commands that are assigned low priority, wherein the comparison is based on determining that a certain number of queue read commands are assigned low priority.

[0124] In some instances, queue management component 615 may determine that the number of write commands issued after the data bus is configured to operate in a first direction meets a threshold number, wherein the data bus is configured to operate in a second direction based on the determination that the threshold number is met.

[0125] In some instances, the queue management component 615 can determine that fewer than a threshold number of queued write commands are for groups that have satisfied timing constraints for activating different rows, wherein the data bus is configured to operate in a second direction based on the determination that fewer than a threshold number of queued write commands are for groups that have satisfied timing constraints for activating different rows.

[0126] The timing component 620 can determine for each group in the group that a threshold duration has elapsed since the last activation command was issued for the group, wherein the timing constraint is determined to be satisfied based on the determination that the threshold duration has elapsed for each group.

[0127] In some instances, the timing component 620 can determine for each group in a group that a threshold duration has elapsed since the last activation command was issued for the group, wherein the timing constraint is determined to be satisfied based on the determination that the threshold duration has elapsed for each group.

[0128] In some instances, the timing component 620 can determine for each group in a group that a threshold duration has elapsed since the last activation command was issued for the group, wherein the timing constraint is determined to be satisfied based on the determination that the threshold duration has elapsed for each group.

[0129] Access command component 625 can issue activation commands associated with a number of queued access commands of a second type to the group between issuing activation commands associated with a first type of command for different groups.

[0130] In some instances, the access command component 625 can issue an activation command associated with a number of queued write commands to the group between issuing activation commands associated with read commands for different groups.

[0131] In some instances, the access command component 625 may issue a write command to the memory, the write command being associated with second data.

[0132] In some instances, the access command component 625 can issue activation commands associated with a number of queued read commands to the group between issuing activation commands associated with write commands for different groups.

[0133] The receiving component 630 can receive the first data requested by the read command via the data bus while the data bus is configured in the first direction.

[0134] In some instances, the receiving component 630 may receive second data via the data bus after the data bus has been configured to operate in the second direction.

[0135] The transmitting component 635 can transmit second data via the data bus after being configured to operate in the second direction.

[0136] In some instances, the transmitting component 635 can transmit first data associated with a queued write command via the data bus while the data bus is configured to operate in a first direction.

[0137] Figure 7 The flowchart illustrates one or more methods 700 supporting an efficient bus turnaround strategy according to aspects of this disclosure. Operation of method 700 may be implemented by means or components thereof as described herein. For example, operation of method 700 may be performed by means as described in reference... Figure 1 and 2 The described apparatus performs the function. In some instances, the apparatus may execute a set of instructions to control the functional elements of the apparatus to perform the described function. Alternatively, the apparatus may use dedicated hardware to perform aspects of the described function.

[0138] In some instances, the operation of method 700 may be implemented by a device comprising a memory and a controller coupled to the memory. The controller is configured such that the device performs the operation of method 700.

[0139] At 705, the device can operate the data bus for the memory in a first direction relative to the memory and associated with an access command of the first type. The operation of 705 can be performed according to the methods described herein. In some instances, aspects of the operation of 705 can be determined by reference to... Figure 6 The described bus management component is executed.

[0140] At 710, the device can determine for the memory a certain number of second-type queued access commands for a group that has satisfied timing constraints for activating different rows in the same group. The operation of 710 can be performed according to the method described herein. In some instances, aspects of the operation of 710 can be as described in the reference... Figure 6 The described queue management component is executed.

[0141] At 715, the device can operate the data bus in a second direction associated with the second type of access commands based on determining that a certain number of second-type queued access commands are for groups that have met timing constraints. The operation of 715 can be performed according to the method described herein. In some instances, aspects of the operation of 715 may be as referenced... Figure 6 The described bus management component is executed.

[0142] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include a memory and a controller coupled to the memory. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: operating a data bus for the memory in a first direction relative to the memory and associated with a first type of access command; determining, for the memory, a certain number of queued access commands of a second type for a group whose timing constraints for activating different rows in the same group have been satisfied; and operating the data bus in a second direction associated with the second type of access commands based on determining that a certain number of queued access commands of the second type are for a group whose timing constraints have been satisfied.

[0143] Method 700 and some instances of the devices described herein may further include operations, features, means, or instructions for determining, for each group in the group, that a threshold duration may have elapsed since the last activation command was issued for the group, wherein the determination that a group may have met timing constraints may be based on the determination that a threshold duration may have elapsed for each group.

[0144] Method 700 and some instances of the devices described herein may further include operations, features, means, or instructions for determining that the number of queued access commands of the second type meets a threshold number, wherein the data bus may be configured to operate in a second direction based on determining that the threshold number can be met.

[0145] Method 700 and some instances of the devices described herein may further include operations, features, means, or instructions for determining a first type of queuing command of less than a threshold number that may be available for a group that may have met timing constraints, wherein the data bus may be configured to operate in a second direction based on determining that a first type of queuing command of less than a threshold number may be available for a group that may have met timing constraints.

[0146] Method 700 and some examples of the devices described herein may further include operations, features, means, or instructions for issuing activation commands associated with a number of queued access commands of a second type to said group between issuing activation commands associated with a first type of command for a different group.

[0147] In some instances of method 700 and the device described herein, the first direction supports the transmission of data from memory, and the access command of the first type includes a read command, and wherein the second direction supports the transmission of data to memory, and the access command of the second type includes a write command.

[0148] Figure 8 The flowchart illustrates one or more methods 800 supporting an efficient bus turnaround strategy according to aspects of this disclosure. Operation of method 800 may be implemented by means or components thereof as described herein. For example, operation of method 800 may be performed by means as described in reference... Figure 1 and 2 The described apparatus performs the function. In some instances, the apparatus may execute a set of instructions to control the functional elements of the apparatus to perform the described function. Alternatively, the apparatus may use dedicated hardware to perform aspects of the described function.

[0149] In some instances, the operation of method 800 may be implemented by a device comprising a memory and a controller coupled to the memory. The controller is configured such that the device performs the operation of method 800.

[0150] At 805, the device can configure the data bus for memory to operate in a first direction for conveying data read from memory. Operation of 805 can be performed according to the methods described herein. In some instances, aspects of operation of 805 may be as described in references... Figure 6 The described bus management component is executed.

[0151] At 810, the device can determine that a certain number of write commands queued for the memory are for a group that has satisfied timing constraints for activating different rows in the same group. The operation of 810 can be performed according to the method described herein. In some instances, aspects of the operation of 810 can be derived from, as referenced... Figure 6 The described queue management component is executed.

[0152] At 815, the device can configure the data bus to operate in the second direction for delivering data to memory based on determining that a certain number of write commands queued for memory are for a group whose timing constraints have been met. The operation of 815 can be performed according to the methods described herein. In some instances, aspects of the operation of 815 may be as referenced... Figure 6 The described bus management component is executed.

[0153] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include a memory and a controller coupled to the memory. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: configuring a data bus for the memory to operate in a first direction for conveying data read from the memory; determining that a queue of write commands for the memory is for a group whose timing constraints for activating different rows in the same group have been satisfied; and configuring the data bus to operate in a second direction for conveying data to the memory based on the determination that a queue of write commands for the memory is for a group whose timing constraints have been satisfied.

[0154] Method 800 and some instances of the devices described herein may further include operations, features, means, or instructions for determining, for each group in the group, that a threshold duration may have elapsed since the last activation command was issued for the group, wherein the determination that a group may have met timing constraints may be based on the determination that a threshold duration may have elapsed for each group.

[0155] Method 800 and some instances of the devices described herein may further include operations, features, means, or instructions for determining that the number of queued write commands meets a threshold number, wherein the data bus may be configured to operate in a second direction based on determining that the threshold number can be met.

[0156] Method 800 and some instances of the devices described herein may further include operations, features, means, or instructions for: comparing the number of queued write commands with a threshold number, wherein the determination of the threshold number may be based on the comparison; and determining that at least one write command among a certain number of queued write commands may be assigned a higher priority relative to other queued write commands, wherein the comparison may be based on the determination that the at least one write command may be assigned a higher priority.

[0157] Method 800 and some instances of the devices described herein may further include operations, features, means, or instructions for determining that the number of read commands issued after configuring the data bus to operate in a first direction meets a threshold number, wherein the data bus may be configured to operate in a second direction based on determining that the threshold number can be met.

[0158] Method 800 and some instances of the devices described herein may further include operations, features, means, or instructions for determining a group of queued read commands less than a threshold number that may be available for use in meeting timing constraints for activating different rows, wherein the data bus may be configured to operate in a second direction based on determining that a group of queued read commands less than a threshold number may be available for use in meeting timing constraints for activating different rows.

[0159] Method 800 and some instances of the devices described herein may further include operations, features, means, or instructions for issuing activation commands associated with a number of queued write commands to said group between issuing activation commands associated with read commands for different groups.

[0160] Method 800 and some examples of the devices described herein may further include operations, features, components, or instructions for performing: receiving first data requested by a read command via the data bus while the data bus can be configured in a first direction; issuing a write command to a memory, the write command being associated with second data; and issuing the second data via the data bus after the data bus is configured to operate in a second direction.

[0161] Figure 9 The flowchart illustrates one or more methods 900 supporting an efficient bus turnaround strategy according to aspects of this disclosure. Operation of method 900 may be implemented by means or components thereof as described herein. For example, operation of method 900 may be performed by means as described in reference... Figure 1 and 2 The described apparatus performs the function. In some instances, the apparatus may execute a set of instructions to control the functional elements of the apparatus to perform the described function. Alternatively, the apparatus may use dedicated hardware to perform aspects of the described function.

[0162] In some instances, the operation of method 900 may be implemented by a device comprising a memory and a controller coupled to the memory. The controller is configured such that the device performs the operation of method 900.

[0163] At 905, the device can configure the data bus for memory to operate in a first direction for transmitting data to memory. The operation of 905 can be performed according to the methods described herein. In some instances, aspects of the operation of 905 can be as described in reference... Figure 6 The described bus management component is executed.

[0164] At 910, the device can determine that a certain number of read commands queued for the memory are for a group that has satisfied timing constraints for activating different rows in the same group. The operation at 910 can be performed according to the method described herein. In some instances, aspects of the operation at 910 can be derived from, as referenced... Figure 6 The described queue management component is executed.

[0165] At 915, the device can configure the data bus to operate in a second direction to convey data read from memory based on determining that a certain number of read commands queued for the memory are for a group whose timing constraints have been met. The operation of 915 can be performed according to the method described herein. In some instances, aspects of the operation of 915 can be as described in the reference... Figure 6 The described bus management component is executed.

[0166] In some instances, the device as described herein may perform one or more methods, such as method 900. The device may include a memory and a controller coupled to the memory. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following: configuring a data bus for the memory to operate in a first direction for conveying data to the memory; determining that a queue of read commands for the memory is for a group whose timing constraints for activating different rows in the same group have been satisfied; and configuring the data bus to operate in a second direction for conveying data read from the memory based on the determination that a queue of read commands for the memory is for a group whose timing constraints have been satisfied.

[0167] Method 900 and some instances of the devices described herein may further include operations, features, means, or instructions for determining, for each group in the group, that a threshold duration may have elapsed since the last activation command was issued for the group, wherein the determination that a group may have met timing constraints may be based on the determination that a threshold duration may have elapsed for each group.

[0168] Method 900 and some instances of the devices described herein may further include operations, features, means, or instructions for determining that the number of queued read commands meets a threshold number, wherein the data bus may be configured to operate in a second direction based on determining that the threshold number can be met.

[0169] Method 900 and some instances of the device described herein may further include operations, features, means, or instructions for performing: comparing the number of queued read commands with a threshold number, wherein the determination of the threshold number may be based on the comparison; and determining a certain number of queued read commands that may be assigned a low priority, wherein the comparison may be based on the determination of a certain number of queued read commands that may be assigned a low priority.

[0170] Method 900 and some instances of the devices described herein may further include operations, features, means, or instructions for determining that the number of write commands issued after configuring the data bus to operate in a first direction meets a threshold number, wherein the data bus may be configured to operate in a second direction based on determining that the threshold number can be met.

[0171] Method 900 and some instances of the devices described herein may further include operations, features, means, or instructions for determining a group of queued write commands of less than a threshold number that may be available for use in meeting timing constraints for activating different rows, wherein the data bus may be configured to operate in a second direction based on determining that a group of queued write commands of less than a threshold number may be available for use in meeting timing constraints for activating different rows.

[0172] Method 900 and some instances of the devices described herein may further include operations, features, means, or instructions for issuing activation commands associated with a number of queued read commands to said group between issuing activation commands associated with write commands for different groups.

[0173] Method 900 and some examples of the devices described herein may further include operations, features, means, or instructions for performing: transmitting first data associated with a queued write command via the data bus while the data bus is configured to operate in a first direction; and receiving second data via the data bus after configuring the data bus to operate in a second direction.

[0174] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described can be combined.

[0175] The information and signals described herein can be represented using any of a variety of techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may show signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0176] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that enables the flow of signals between them. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path between connected components that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, may be used to interrupt the signal flow between connected components for a period of time.

[0177] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently not allowed to travel between the components via a conductive path, and in which a signal can travel between the components via the conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0178] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. If there is an open circuit between components, then those components are isolated from each other. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0179] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0180] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. These terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped with an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0181] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0182] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash followed by the reference numeral and a second label to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0183] The information and signals described herein can be represented using any of a variety of techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0184] A protocol can define one or more communication procedures and one or more communication parameters supported for use by a device or component. For example, a protocol can define various operations, timing and frequency for those operations, the meaning of various commands or signals or both, one or more addressing schemes for one or more memories, the type of communication where pins are reserved, the size of data processed at various components such as interfaces, the data rates supported by various components such as interfaces, or the bandwidth supported by various components such as interfaces, and other parameters and metrics, or any combination thereof. The use of shared protocols enables interaction between devices because each device can operate in a way that is expected, recognized, and understood by another device. For example, two devices supporting the same protocol can interact according to the policies, procedures, and parameters defined by the protocol, while two devices supporting different protocols can be incompatible.

[0185] To illustrate, two devices supporting different protocols can be incompatible because the protocols define different addressing schemes (e.g., different numbers of address bits). As another illustration, two devices supporting different protocols can be incompatible because the protocols define different transmission procedures for responding to a single command (e.g., the burst length or number of bytes allowed in response to a command can be different). Simply translating a command into an action should not be interpreted as the use of two different protocols. In fact, if the corresponding procedures or parameters defined by the two protocols change, then the protocols can be considered different. For example, if a device supports different addressing schemes or different transmission procedures for responding to commands, then the device can be said to support two different protocols.

[0186] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0187] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functionality can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented in different physical locations. Furthermore, as used herein, the word "or" in the list of items included in the claims (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). And, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as “based on condition A” may be based on both condition A and condition B. In other words, as used herein, the phrase “based on” should also be interpreted as the phrase “at least partially based on”.

[0188] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0189] This description is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications to this disclosure and can apply the general principles defined herein to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: Memory; and A controller, coupled to and configured to cause the memory device to perform the following operations: A data bus for the memory is operated in a first direction relative to the memory and associated with a first type of access command; For the memory, a certain number of second-type queued access commands are determined to be for groups that have satisfied timing constraints for activating different rows in the same group; and The data bus is operated in a second direction associated with the second type of access command, based at least in part on the determination that the certain number of queued access commands of the second type are for a group that has satisfied the timing constraints.

2. The memory device of claim 1, wherein the controller is further configured to cause the memory device to perform the following operations: For each group, it is determined that a threshold duration has elapsed since the last activation command was issued for the group, wherein the determination that the timing constraint has been satisfied is based at least in part on the determination that the threshold duration has elapsed for each group.

3. The memory device of claim 1, wherein the controller is further configured to cause the memory device to perform the following operations: The number of queued access commands of the second type is determined to meet a threshold number, wherein the data bus is configured to operate in the second direction at least in part based on the determination that the threshold number is met.

4. The memory device of claim 1, wherein the controller is further configured to cause the memory device to perform the following operations: The first type of queuing commands, which are determined to be fewer than a threshold number, are for groups that have met the timing constraints, wherein the data bus is configured to operate in the second direction at least in part based on the determination that the first type of queuing commands, which are determined to be fewer than the threshold number, are for groups that have met the timing constraints.

5. The memory device of claim 1, wherein the controller is further configured to cause the memory device to perform the following operations: Between issuing activation commands associated with the first type of commands for different groups, activation commands associated with the certain number of queued access commands of the second type are issued to the group.

6. The memory device of claim 1, wherein the first direction supports the transmission of data from the memory, and the first type of access command includes a read command, and wherein the second direction supports the transmission of data to the memory, and the second type of access command includes a write command.

7. A memory device comprising: Memory; and A controller, coupled to and configured to cause the memory device to perform the following operations: The data bus for the memory is configured to operate in a first direction to convey data read from the memory; Determine a certain number of write commands queued for the memory as a group that has satisfied timing constraints for activating different rows in the same group; and The data bus is configured to operate in a second direction to deliver data to the memory, at least in part based on determining that a certain number of write commands queued for the memory are for a group that has met the timing constraints.

8. The memory device of claim 7, wherein the controller is further configured to cause the memory device to perform the following operations: For each group, it is determined that a threshold duration has elapsed since the last activation command was issued for the group, wherein the determination that the timing constraint has been satisfied is based at least in part on the determination that the threshold duration has elapsed for each group.

9. The memory device of claim 7, wherein the controller is further configured to cause the memory device to perform the following operations: The number of queued write commands is determined to meet a threshold number, wherein the data bus is configured to operate in the second direction at least in part based on the determination that the threshold number is met.

10. The memory device of claim 9, wherein the controller is further configured to cause the memory device to perform the following operations: The number of queued write commands is compared with the threshold number, wherein the determination of the number of queued write commands satisfying the threshold number is based at least in part on the comparison; and Determine that at least one write command among the certain number of queued write commands is assigned a higher priority relative to other queued write commands, wherein the comparison is based at least in part on determining that the at least one write command is assigned the higher priority.

11. The memory device of claim 7, wherein the controller is further configured to cause the memory device to perform the following operations: The number of read commands issued after the data bus is configured to operate in the first direction is determined to meet a threshold number, wherein the data bus is configured to operate in the second direction at least in part based on the determination that the threshold number is met.

12. The memory device of claim 7, wherein the controller is further configured to cause the memory device to perform the following operations: The data bus is configured to operate in the second direction based at least in part on the determination that fewer than the threshold number of queued read commands are for a group that has satisfied the timing constraints for activating different rows.

13. The memory device of claim 7, wherein the controller is further configured to cause the memory device to perform the following operations: Between issuing activation commands associated with read commands for different groups, activation commands associated with the number of queued write commands are issued to the group.

14. The memory device of claim 13, wherein the controller is further configured to cause the memory device to perform the following operations: While the data bus is configured in the first direction, the first data requested by the read command is received via the data bus. The write command is sent to the memory, and the write command is associated with the second data; and The second data is transmitted via the data bus after the data bus is configured to operate in the second direction.

15. A memory device comprising: Memory; and A controller, coupled to and configured to cause the memory device to perform the following operations: The data bus for the memory is configured to operate in a first direction for transmitting data to the memory; Determine a certain number of read commands queued for the memory as a group that has satisfied timing constraints for activating different rows in the same group; and The data bus is configured to operate in a second direction to convey data read from the memory, based at least in part on determining that a certain number of read commands queued for the memory are for a group that has met the timing constraints.

16. The memory device of claim 15, wherein the controller is further configured to cause the memory device to perform the following operations: For each group, it is determined that a threshold duration has elapsed since the last activation command was issued for the group, wherein the determination that the timing constraint has been satisfied is based at least in part on the determination that the threshold duration has elapsed for each group.

17. The memory device of claim 15, wherein the controller is further configured to cause the memory device to perform the following operations: The number of queued read commands is determined to meet a threshold number, wherein the data bus is configured to operate in the second direction at least in part based on the determination that the threshold number is met.

18. The memory device of claim 17, wherein the controller is further configured to cause the memory device to perform the following operations: The number of queued read commands is compared with the threshold number, wherein the determination of the number of queued read commands satisfying the threshold number is based at least in part on the comparison; and A certain number of queued read commands are assigned low priority, wherein the comparison is based at least in part on determining that the certain number of queued read commands are assigned low priority.

19. The memory device of claim 15, wherein the controller is further configured to cause the memory device to perform the following operations: The number of write commands issued after the data bus is configured to operate in the first direction is determined to meet a threshold number, wherein the data bus is configured to operate in the second direction at least in part based on the determination that the threshold number is met.

20. The memory device of claim 15, wherein the controller is further configured to cause the memory device to perform the following operations: The data bus is configured to operate in the second direction based at least in part on the determination that fewer than the threshold number of queued write commands are for a group that has satisfied the timing constraints for activating different rows.

21. The memory device of claim 15, wherein the controller is further configured to cause the memory device to perform the following operations: Between issuing activation commands associated with write commands for different groups, activation commands associated with the number of queued read commands are issued to the group.

22. The memory device of claim 21, wherein the controller is further configured to cause the memory device to perform the following operations: While the data bus is configured to operate in the first direction, first data associated with the write command is transmitted via the data bus; and After the data bus is configured to operate in the second direction, second data is received via the data bus.

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