Apparatus and method for providing refresh addresses

Abstract

Apparatuses and methods for generating refresh addresses for a row hammer refresh operation are disclosed. In some examples, determination of a row address associated with a highest count value can be initiated at a precharge command preceding a row hammer refresh operation. The row address determined to be associated with the highest count value can be provided for use in generating refresh addresses.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor memory devices. BACKGROUND

[0002] In particular, the present disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Information can be stored as physical signals (e.g., charge on a capacitive element) on individual memory cells of a memory device. A memory device can include volatile memory, and the physical signals can decay over time, which can degrade or destroy the information stored in the memory cells. It can be necessary to periodically refresh the information in the memory cells, e.g., by rewriting the information, to restore the physical signals to an initial value. Such periodic refreshing of the memory cells can be referred to as an auto-refresh operation.

[0003] As memory component sizes decrease, the density of memory cells greatly increases. Repeated access to a particular memory cell or group of memory cells, often referred to as a ‘row hammer,’ can cause an increased rate of data degradation in nearby memory cells (e.g., those located at word lines adjacent to the accessed word line). Memory cells affected by row hammer effects can be identified and refreshed as part of targeted refresh operations performed by the memory device, also referred to as row hammer refresh (RHR) operations. These targeted refresh operations can supplant (e.g., steal) time slots that would otherwise be used for auto-refresh operations.

[0004] To perform RHR operations, addresses of word lines can be stored in an address storage circuit, and one of the addresses is provided from the address storage circuit to generate one or more refresh addresses at a row hammer refresh operation. However, if the addresses are not timely provided from the address storage circuit, the RHR operations can not be properly performed and / or the RHR operations can be delayed (e.g., to a next steal time slot). SUMMARY

[0005] According to embodiments of the present disclosure, an apparatus is provided and includes a plurality of address registers, each address register configured to store a row address; a plurality of counter circuits, each counter circuit configured to store a count value corresponding to an associated one of the plurality of address registers; a comparison circuit configured to determine a counter circuit of the plurality of counter circuits that stores a highest count value; and a precharge command configured to control the comparison circuit to determine the counter circuit of the plurality of counter circuits that stores the highest count value in response to a precharge command received by the apparatus.

[0006] According to embodiments of the present disclosure, a method is provided and includes the steps of receiving a pre-charge command at a memory; and determining, with a count comparison circuit, a counter circuit of a plurality of counter circuits that stores a highest count value, at least partially in response to the pre-charge command.

[0007] According to embodiments of the present disclosure, a method is provided and includes the steps of receiving a signal; receiving an active refresh state signal, wherein the active refresh state signal is associated with a row hammer refresh operation; determining, at least partially in response to the signal, a counter circuit of a plurality of counter circuits that stores a highest count value; and providing a row address from an address register associated with the counter circuit on an address bus. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram of a semiconductor device according to embodiments of the present disclosure.

[0009] Figure 2 is a block diagram of a refresh control circuit according to embodiments of the present disclosure.

[0010] Figure 3 is an illustration of an arrangement of word lines of an array of memory cells.

[0011] Figure 4 is a block diagram of a row hammer address storage circuit according to embodiments of the present disclosure.

[0012] Figure 5 is a timing diagram of various signals during a memory operation of a semiconductor device according to embodiments of the present disclosure.

[0013] Figure 6 is a flowchart of a method according to embodiments of the present disclosure.

[0014] Figure 7 is a flowchart of a method according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] Various embodiments of the present disclosure will be explained in detail below with reference to the drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments of this disclosure. The detailed description includes sufficient details to enable those skilled in the art to practice the embodiments of the present disclosure. Other embodiments can be utilized, and structural, logical, and electrical changes can be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

[0016] Information in volatile memory devices can be stored in memory cells (e.g., as an electrical charge on a capacitive element), but can decay over time. To prevent information from being lost or corrupted due to such decay, the memory can perform refresh processes, such as refresh operations as part of a refresh mode. Memory cells can be organized into rows (word lines) and columns (bit lines), and memory cells can be refreshed row by row. During a refresh operation, information can be overwritten to a word line to restore its initial state. Automatic refresh operations can be performed on the word lines of the memory in sequence, such that over time, each word line of the memory is refreshed at a faster rate than the expected rate of data degradation.

[0017] Repeated access to a particular word line of the memory (e.g., an aggressor row) can cause the rate of decay of word lines proximate to the aggressor row (e.g., victim rows) to increase. These repeated accesses can be part of a deliberate attack on the memory, and / or can be due to a “natural” access pattern of the memory. The increase in the rate of decay in the victim rows can need to be refreshed as part of a targeted refresh operation (also referred to as a row hammer refresh (RHR) operation). As part of a refresh mode, the memory device can periodically perform targeted refresh operations. For example, when the memory device is in a refresh mode, it can perform a set of refresh operations, which includes a plurality of automatic refresh operations and a plurality of RHR operations, and then repeat this cycle. In some embodiments, the RHR operations can ‘steal’ time slots that would otherwise be used for automatic refresh operations. The memory device can generally cycle between performing access operations, entering a refresh mode for a period of time, performing access operations, etc. over a period of time.

[0018] In some applications, some or all of the addresses of the word lines that are accessed can be monitored. For example, the addresses of the word lines that are accessed can be stored in an address storage circuit. The number of times a word line is accessed can also be monitored. For example, each address stored in the address storage circuit can be associated with a counter that tracks the number of times the word line associated with the address is accessed. When performing an RHR operation, one or more addresses of the word lines in the access set (e.g., the aggressor row, the most accessed word lines) can be provided from the address storage circuit to generate one or more refresh addresses (e.g., addresses associated with victim word lines to be refreshed during the RHR operation).

[0019] To provide an address to access a concentrated word line, a determination is made of an address associated with a counter having a highest count value. Typically, a start trigger of the RHR operation is determined (e.g., activation of the RHR signal). However, it can take a period of time to determine the counter having the highest count value. If the start is determined too late and / or takes too long to complete, the address can not be provided in time from the address storage circuit to generate a refresh address by the RHR operation to refresh the associated word line. If the address is not provided in time from the address storage circuit, the RHR operation can not be performed correctly and / or the RHR operation on the word line can be delayed (e.g., to the next snoop slot).

[0020] According to embodiments of the present disclosure, the determination of the counter circuit of the address storage circuit having the highest count value can be initiated by a signal (or transition of a signal) prior to the RHR operation. For example, the determination can be initiated using a command prior to the RHR operation. This can allow an additional period of time prior to the RHR operation to determine the counter having the highest count value, to provide an address associated with the counter, and to generate one or more refresh addresses from the address. The additional time can reduce or eliminate the risk of a refresh address not being available for the RHR operation. In some embodiments of the present disclosure, a precharge command prior to the RHR operation can initiate the determination of the counter circuit of the address storage circuit having the highest count value.

[0021] As used herein, activation of a signal can refer to any portion of a signal waveform to which a circuit responds. For example, if a circuit responds to a rising edge, a signal toggling from a low level to a high level can be an activation. One example type of activation is a pulse, in which a signal toggles from a low level to a high level for a period of time and then back to a low level. This can trigger a circuit that responds to rising edges, falling edges, and / or high logic level signals.

[0022] Figure 1 is a block diagram of a semiconductor device 10 according to embodiments of the present disclosure. For example, the semiconductor device 10 can be a DDR4 SDRAM incorporated in a single semiconductor chip. However, in other embodiments, the semiconductor device 10 can be any other suitable memory type, such as DDR5, LPDDR4, and / or LPDDR5. The semiconductor device 10 can be mounted on an external substrate, such as a memory module substrate or a motherboard. As Figure 1As shown in FIG. 1, the semiconductor device 10 includes a memory cell array 11. The memory cell array 11 includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the word lines WL and the bit lines BL. Selection of the word lines WL is performed by a row address control circuit 12, and selection of the bit lines BL is performed by a column decoder 13. A sense amplifier 14 is connected to a corresponding bit line BL and a pair of local I / O lines LIOT / B. The pair of local I / O lines LIOT / B is connected to a pair of main I / O lines MIOT / B via a pass gate 15 serving as a switch. The memory cell array 11 is divided into (m+1) memory banks, which include memory banks BANKO to BANKm.

[0023] A plurality of external terminals included in the semiconductor device 10 include a command address terminal 21, a clock terminal 22, data terminals 23, and power supply terminals 24 and 25. The data terminals 23 are connected to an I / O circuit 16.

[0024] A command address signal CA is supplied to the command address terminal 21. One of the command address signals CA supplied to the command address terminal 21 that is related to an address is transferred to an address decoder 32 via a command address input circuit 31. Another command related command is transferred to a command control circuit 33 via the command address input circuit 31. The address decoder 32 decodes the address signal and generates a row address XADD and a column address YADD. The row address XADD is supplied to the row address control circuit 12, and the column address YADD is supplied to the column decoder 13. Further, the command address signal CA serving as a clock enable signal CKE is supplied to an internal clock generator 35.

[0025] Complementary external clock signals CK_t and CK_c are supplied to the clock terminal 22. The complementary external clock signals CK_t and CK_c are input to a clock input circuit 34. The clock input circuit 34 generates an internal clock signal ICLK based on the complementary external clock signals CK_t and CK_c. The internal clock signal ICLK is supplied at least to the command control circuit 33 and the internal clock generator 35. For example, the internal clock generator 35 is activated by the clock enable signal CKE and generates an internal clock signal LCLK based on the internal clock signal ICLK. The internal clock signal LCLK is supplied to the I / O circuit 16. The internal clock signal LCLK is used as a timing signal that defines a timing of outputting read data DQ from the data terminals 23 at a read operation. At a write operation, write data is input from the outside to the data terminals 23. At the write operation, a data mask signal DM can be input from the outside to the data terminals 23.

[0026] Power supply potentials VDD and VSS are supplied to the power supply terminals 24. These power supply potentials VDD and VSS are supplied to a voltage generator 36. The voltage generator 36 generates various internal potentials VPP, VOD, VARY, and VPERI, for example, based on the power supply potentials VDD and VSS. The internal potential VPP is mainly used for the row address control circuit 12. The internal potentials VOD and VARY are mainly used for the sense amplifiers 14 included in the memory cell array 11. The internal potential VPERI is used for many other circuit blocks.

[0027] The power supply potentials VDDQ and VSSQ are supplied to the I / O circuit 16 from the power supply terminals 25. Although the power supply potentials VDDQ and VSSQ can be the same as the power supply potentials VDD and VSS supplied to the power supply terminals 24, respectively, the dedicated power supply potentials VDDQ and VSSQ are allocated to the I / O circuit 16 in order to prevent the power supply noise generated in the I / O circuit 16 from propagating to another circuit block.

[0028] The command control circuit 33 can provide one or more internal signals at least partially in response to external commands received via the command address input circuit 31. For example, the command control circuit 33 can provide an activate / precharge signal ACT / PRE, a refresh signal AREF, and / or a column selection signal CYE. When a read command is issued from the outside, the command control circuit 33 activates the column selection signal CYE after an activate command. The column selection signal CYE is supplied to the column decoder 13. In response to this signal, read data is read out from the memory cell array 11. The read data read from the memory cell array 11 is transferred to the I / O circuit 16 via the read / write amplifier 17 and the FIFO circuit 18, and is output to the outside via the data terminals 23.

[0029] The command control circuit 33 activates the activate signal ACT when an activate command is issued, and activates the refresh signal AREF when a refresh command is issued. Both the activate signal ACT and the refresh signal AREF are supplied to the row address control circuit 12. The row address control circuit 12 includes a refresh control circuit 40. The refresh control circuit 40 controls a refresh operation of the memory cell array 11 based on the row address XADD, the activate signal ACT, and the refresh signal AREF.

[0030] In some embodiments, the refresh signal AREF can be a pulse signal activated when the command control circuit 33 receives a signal indicating entry into a self-refresh mode. The refresh signal AREF can be activated once immediately after a command input, and thereafter can be cyclically activated at a desired internal timing. The refresh signal AREF can be used to control the timing of refresh operations during the refresh mode. A self-refresh exit command can cause the automatic activation of the refresh signal AREF to stop, and can cause the device 10 to return to an idle state and / or resume other operations.

[0031] A refresh signal AREF is provided to refresh control circuit 40. Refresh control circuit 40 provides a refresh row address, and row address control circuit 12 can refresh one or more word lines WL indicated by the refresh row address. In some embodiments, the refresh address can represent a single word line. In some embodiments, the refresh address can represent multiple word lines, which can be refreshed sequentially or concurrently by row address control circuit 12. In some embodiments, the number of word lines represented by the refresh address can vary from one refresh address to another. Refresh control circuit 40 can control the timing of refresh operations, and can generate and provide refresh addresses. Refresh control circuit 40 can be controlled to vary the details of refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address, the number of word lines represented by the address), or can operate based on internal logic.

[0032] Refresh control circuit 40 can selectively output a target refresh (e.g., RHR) address, which can specify one or more victim addresses based on the aggressor row address or an automatic refresh address (e.g., from an automatic refresh address sequence) as the refresh address. Based on the type of refresh address, row address control circuit 12 can perform a target refresh or an automatic refresh operation. The automatic refresh address can be from a sequence of addresses provided based on activation of refresh signal AREF. Refresh control circuit 40 can cycle through the automatic refresh address sequence at a rate determined by AREF. In some embodiments, the automatic refresh operation can generally occur at a certain timing such that the automatic refresh address sequence is cycled through such that for a given word line, no information is expected to be degraded for the time between automatic refresh operations. In other words, the automatic refresh operation can be performed such that each word line is refreshed at a faster rate than the expected information decay rate.

[0033] Refresh control circuit 40 can also determine a target refresh address based on the access pattern of nearby addresses (e.g., aggressor addresses corresponding to aggressor rows) in memory cell array 11, the target refresh address being an address (e.g., a victim address corresponding to a victim row) that needs to be refreshed. Refresh control circuit 40 can use one or more signals of device 10 to calculate the target refresh address. For example, the refresh address can be calculated based on row address XADD provided by address decoder 32.

[0034] In some embodiments, refresh control circuit 40 can sample a current value of row address XADD provided by address decoder 32 and determine a target refresh address based on one or more of the sampled addresses. The sampled addresses can be stored in an address storage circuit of refresh control circuit 40. When row address XADD is sampled, it can be compared to the addresses stored in the address storage circuit. In some embodiments, an aggressor address can be determined based on the sampled and / or stored addresses. For example, a comparison between the sampled addresses and the stored addresses can be used to update a count value (e.g., an access count) in a counter circuit associated with the stored addresses. An aggressor address can be calculated based on the count values stored in the counter circuit. A refresh address can then be generated based on the aggressor address.

[0035] While, in general, the present disclosure relates to determining aggressor and victim word lines and addresses, it should be understood that, as used herein, an aggressor word line does not necessarily need to cause data degradation in an adjacent word line, and a victim word line does not necessarily need to suffer from such degradation. Refresh control circuit 40 can use some criteria to judge whether an address is an aggressor address, which can capture potential aggressor addresses, rather than finally determining which addresses cause data degradation in nearby victims. For example, refresh control circuit 40 can determine potential aggressor addresses based on a pattern of accesses to the addresses, and this criterion can include some addresses that are not aggressors, and miss some aggressor addresses. Similarly, victim addresses can be determined based on which word lines are expected to be affected by aggressors, rather than finally determining which word lines are experiencing an increase in data decay rate.

[0036] The refresh addresses can be provided with timing based on the timing of refresh signal AREF. During the periodic refresh operations of the refresh mode, refresh control circuit 40 can have time slots corresponding to the timing of AREF, and can provide one or more refresh addresses during each time slot. In some embodiments, target refresh / RHR addresses can be issued in time slots that would otherwise be allocated to automatic refresh addresses (e.g., “stolen”). In some embodiments, certain time slots can be reserved for target refresh addresses, and refresh control circuit 40 can determine whether to provide a target refresh address or no address during the time slots, or to provide an automatic refresh address during the time slots.

[0037] In some embodiments, some or all of the calculations and / or other operations for determining the aggressor address used to generate the refresh address can be performed each time the refresh control circuit 40 samples the row address. In some embodiments, some or all of the calculations and / or other operations for determining the aggressor address can be performed each time a target / RHR address is issued for an RHR operation. In some embodiments, determining the aggressor address can be performed at least partially in response to one or more signals, such as the ACT / PRE and / or AREF signals provided by the command control circuit 33. In some embodiments, determining the counter circuit having the highest count value can be initiated at least partially by the precharge signal PRE prior to an RHR operation.

[0038] Figure 2 is a block diagram of the refresh control circuit 40 according to embodiments of the present disclosure.

[0039] As shown in Figure 2 The refresh control circuit 40 includes a refresh counter 41, an ARM sample generator 42, a sample circuit 43, a row hammer (RH) address storage circuit 44, an address translator 45, and a refresh address selector 46. The refresh counter 41 generates a counter refresh address NRADD. The counter refresh address NRADD is incremented or decremented in response to an internal refresh signal IREF. The internal refresh signal IREF can be a signal activated a plurality of times based on the refresh signal AREF.

[0040] The sample circuit 43 samples the row address XADD when a sample signal SMP generated by the ARM sample generator 42 is activated and provides the sampled row address XADD to the row hammer address storage circuit 44. The ARM sample generator 42 can activate the sample signal SMP when an activation signal ACT is activated a predetermined number of times. In some embodiments, the ARM sample generator 42 can further generate an operation timing control signal ArmSample, which can also be referred to as a sample signal. The ArmSample signal can control when one or more operations are performed by the row hammer address storage circuit 44. In some embodiments, the ArmSample signal can be a pulsed signal. In some embodiments, the ArmSample signal can be activated a plurality of times during an activation period (e.g., a period in which the activation signal ACT is activated or a period between an activate command and a precharge command). For example, a plurality of pulses of the ArmSample signal can be provided to the row hammer address storage circuit 44 during the activation period. In some embodiments, the ArmSample signal can be provided when the activation signal is activated and the sample signal SMP is also activated.

[0041] Row hammer address storage circuit 44 stores a plurality of row addresses. One or more row addresses stored in row hammer address storage circuit 44 are provided as a row address VADD to address translator 45 via an address bus. The address VADD provided from row hammer address storage circuit 44 can correspond to a word line WL in an access set, e.g., a row address associated with a highest count value of the plurality of row addresses stored in row hammer address storage circuit 44. As will be described in more detail below, in some embodiments, row hammer address storage circuit 44 can include a count comparison circuit that compares count values to determine which row address is associated with the highest count value. In some embodiments, the count comparison circuit can also compare count values to determine which row address is associated with the lowest count value. Whether the count comparison circuit determines the highest or lowest count value can be based at least in part on a state of a min / max selection signal Min / Max Sel. For example, in some embodiments, when Min / Max Sel is high (e.g., a high logic state ‘1’), row hammer address storage circuit 44 can determine the row address associated with the highest count value, while when Min / Max Sel is low (e.g., a low logic state ‘0’), row hammer address storage circuit 44 can determine the row address associated with the lowest count value. Figure 4 and 5 As will be described in more detail below, in some embodiments, row hammer address storage circuit 44 can include a count comparison circuit that compares count values to determine which row address is associated with the highest count value. In some embodiments, the count comparison circuit can also compare count values to determine which row address is associated with the lowest count value. Whether the count comparison circuit determines the highest or lowest count value can be based at least in part on a state of a min / max selection signal Min / Max Sel. For example, in some embodiments, when Min / Max Sel is high (e.g., a high logic state ‘1’), row hammer address storage circuit 44 can determine the row address associated with the highest count value, while when Min / Max Sel is low (e.g., a low logic state ‘0’), row hammer address storage circuit 44 can determine the row address associated with the lowest count value.

[0042] Min / Max Sel signal can be provided by min / max control logic circuit 38. Min / max control logic circuit 38 can receive an activate / precharge ACT / PRE signal and a refresh signal AREF. As will be described in more detail below, in some embodiments, min / max control logic circuit 38 can determine a state of Min / Max Sel signal based at least in part on a state of ACT / PRE signal and / or AREF signal. Figure 5 As will be described in more detail below, in some embodiments, row hammer address storage circuit 44 can include a count comparison circuit that compares count values to determine which row address is associated with the highest count value. In some embodiments, the count comparison circuit can also compare count values to determine which row address is associated with the lowest count value. Whether the count comparison circuit determines the highest or lowest count value can be based at least in part on a state of a min / max selection signal Min / Max Sel. For example, in some embodiments, when Min / Max Sel is high (e.g., a high logic state ‘1’), row hammer address storage circuit 44 can determine the row address associated with the highest count value, while when Min / Max Sel is low (e.g., a low logic state ‘0’), row hammer address storage circuit 44 can determine the row address associated with the lowest count value.

[0043] Address translator 45 translates row address VADD to generate row hammer refresh addresses (collectively referred to as RHR ADD). RHR ADD can include, for example, +1 ADD, -1 ADD, +2 ADD, and -2 ADD. Row hammer refresh addresses +1 ADD and -1 ADD are addresses of word lines WL that are adjacent (e.g., on both sides) to a word line WL having a row address VADD assigned to it. Row hammer refresh addresses +2 ADD and -2 ADD are addresses of word lines WL that are two lines away from a word line WL having a row address VADD assigned to it. For example, when word lines WL1 through WL5 have row addresses VADD assigned to them, row hammer refresh addresses +1 ADD and -1 ADD can be addresses of word lines WLO and WL6, respectively, and row hammer refresh addresses +2 ADD and -2 ADD can be addresses of word lines WL2 and WL5, respectively. Figure 3When the access is concentrated on the word line WL3 (e.g., WL3 is the aggressor row) in the order shown in FIG. 6, the row address VADD corresponds to the word line WL3, the row hammer refresh addresses -1ADD and +1ADD correspond to the word lines WL2 and WL4, respectively, and the row hammer refresh addresses -2ADD and +2ADD correspond to the word lines WL1 and WL5, respectively. In the word lines WL4, WL2, WL5, and WL1 which are respectively assigned with the row hammer refresh addresses +1ADD, -1ADD, +2ADD, and -2ADD, the information storage performance of the memory cells MC associated with the word lines two word lines apart from or away from the word line WL3 can be degraded due to the access concentrated on the word line WL3. The counter refresh address NRADD and the row hammer refresh addresses +1ADD, -1ADD, +2ADD, and -2ADD are supplied to the refresh address selector 46 via one or more address buses.

[0044] The refresh control circuit 40 further includes a counter circuit 47, a comparison circuit 48, and a refresh state circuit 49. The counter circuit 47 increments or decrements the count value CV in response to the internal refresh signal IREF. The comparison circuit 48 receives the count value CV and activates the refresh state signal RHR State whenever the count value CV reaches a predetermined value. The predetermined value can be changed with the mode signal MODE. Thus, when the frequency of the target refresh / RHR operation is to be increased, it is sufficient to set the predetermined value to a small value with the mode signal MODE, and when the frequency of the row hammer refresh operation is to be decreased, it is sufficient to set the predetermined value to a large value with the mode signal MODE. When the refresh state signal RHR State is activated, the refresh counter 41 can temporarily stop the update operation of the counter refresh address NRADD.

[0045] The refresh state signal RHR State is supplied to the refresh state circuit 49. The refresh state circuit 49 generates the refresh selection signals NR, RHR1, and RHR2 based on the internal refresh signal IREF and the refresh state signal RHR State.

[0046] When the refresh state signal RHR State is in the inactive state, the refresh state circuit 49 activates the refresh selection signal NR. The refresh selection signal NR is a signal activated when a refresh operation is to be performed on the counter refresh address NRADD. In the case where the refresh selection signal NR is activated, the refresh address selector 46 selects the counter refresh address NRADD output from the refresh counter 41, and outputs the counter refresh address NRADD as the refresh address REFADD. When the refresh state signal RHR State is in the active state, the refresh state circuit 49 activates the refresh selection signal RHR1 or RHR2. The refresh selection signal RHR1 is a signal activated when a row hammer refresh operation is to be performed on the word line adjacent to the word line accessed in the cluster (for example, for the cluster access of the word line WL3, performed on the word lines WL2 and WL4). In the case where the refresh selection signal RHR1 is activated, the refresh address selector 46 selects the row hammer refresh addresses +1ADD and -1ADD output from the address converter 45, and outputs the row hammer refresh addresses +1ADD and -1ADD as the refresh address REFADD. The refresh selection signal RHR1 is also supplied to the row hammer address storage circuit 44. The refresh selection signal RHR2 is a signal activated when a row hammer refresh operation is to be performed on the word line two word lines away from the word line accessed in the cluster (for example, for the cluster access of the word line WL3, performed on the word lines WL1 and WL5). In the case where the refresh selection signal RHR2 is activated, the refresh address selector 46 selects the row hammer refresh addresses +2ADD and -2ADD output from the address converter 45, and outputs the row hammer refresh addresses +2ADD and -2ADD as the refresh address REFADD.

[0047] Although shown as part of the refresh control circuit 40, in some embodiments the minimum / maximum control logic circuit 38, the counter circuit 47, and / or the comparison circuit 48 can be included in another component of the device 10, such as the command control circuit 33.

[0048] Figure 4 is a block diagram of the row hammer address storage circuit 44 according to an embodiment of the present disclosure.

[0049] As Figure 4 As shown in Figure 4 Although eight address registers 50 to 57 are shown in the example shown in

[0050] The address comparison circuit 70 compares the input row address XADD to each of the row addresses XADD stored in the address registers 50-57. When the input row address XADD matches any of the row addresses XADD stored in the address registers 50-57, the address comparison circuit 70 activates a corresponding one of the hit signals HIT0-HIT7. When any of the hit signals HIT0-HIT7 is activated, the storage control circuit 80 increments the count value of a corresponding one of the counter circuits 60-67. Thus, the count values in the counter circuits 60-67 respectively indicate the number of times the sampling circuit 43 has sampled the row addresses XADD stored in the address registers 50-57.

[0051] The count comparison circuit 90 compares the count values stored in the counter circuits 60-67 and determines which of the counter circuits 60-67 includes the highest count value and / or determines which of the counter circuits 60-67 includes the lowest count value. In some embodiments, the comparison circuit 90 can include one or more comparator circuits (not shown) that can perform one or more operations to compare the count values stored in two or more of the counter circuits 60-67 to determine which of the counter circuits 60-67 includes the highest and / or lowest count value. The one of the counter circuits 60-67 that includes the highest and / or lowest count value can be provided to the storage control circuit 80. The storage control circuit 80 includes a minimum pointer 81 that indicates the one of the counter circuits 60-67 having the lowest count value determined by the count comparison circuit 90 and a maximum pointer 82 that indicates the one of the counter circuits 60-67 having the highest count value determined by the count comparison circuit 90.

[0052] The count comparison circuit 90 can receive a min / max count selection signal Min / Max Sel and an operation timing control / sampling signal ArmSample. In some embodiments, the Min / Max Sel signal can be provided by the min / max control logic circuit 38, and the ArmSample signal can be provided by the ArmSample generator 42. The Min / Max Sel signal can determine which of the counter circuits 60-67 the count comparison circuit 90 determines includes the highest count value or which of the counter circuits 60-67 the count comparison circuit 90 determines includes the lowest count value. The ArmSample signal can at least partially determine when the count comparison circuit 90 makes the lowest count value determination (e.g., determine when the count comparison circuit 90 initiates one or more operations to make the determination). In some embodiments, the count comparison circuit 90 can determine which of the counter circuits 60-67 includes the lowest count value in response to the ArmSample signal being active. In some embodiments, the count comparison circuit 90 can determine which of the counter circuits 60-67 includes the lowest count value at least partially in response to the Min / Max Sel signal transitioning from a state (e.g., a high state) indicating that the highest count value should be determined to a state (e.g., a low state) indicating that the lowest count value should be determined. In some embodiments, the count comparison circuit 90 can determine which of the counter circuits 60-67 includes the highest count value at least partially in response to the Min / Max Sel signal transitioning from a state (e.g., a low state) indicating that the lowest count value should be determined to a state (e.g., a high state) indicating that the highest count value should be determined. In other words, one or both of the ArmSample signal and the Min / Max Sel signal can cause the count comparison circuit 90 to initiate one or more operations to determine the counter circuit associated with the highest and / or lowest count value.

[0053] Returning to the address comparison circuit 70, when none of the hit signals HIT0-HIT7 are active, i.e., when the input row address XADD does not match any of the row addresses XADD stored in the address registers 50-57, respectively, the storage control circuit 80 resets the one of the counter circuits 60-67 indicated by the min pointer 81 to the initial value and provides the point MIN to the address registers 50-57. Thus, the input row address XADD is overwritten in the one of the address registers 50-57 indicated by the point value MIN. In this way, the value of the one of the address registers 50-57 storing the least frequently accessed row address XADD is overwritten when the input row address XADD does not match any of the row addresses XADD stored in the address registers 50-57, respectively.

[0054] In response to the refresh selection signal RHR1, one of the row addresses XADD stored in the address registers 50 to 57 is output as the row address VADD. When the refresh selection signal RHR1 is activated, the point value MAX indicated by the maximum pointer 82 is selected. One of the address registers 50 to 57 is selected by the point value MAX, and the row address XADD stored in the selected one of the address registers 50 to 57 is output as the row address VADD. The value of one of the counter circuits 60 to 67 corresponding to the point value MAX is reset to the initial value.

[0055] In some embodiments, in addition to controlling the timing of operations performed by the count comparison circuit 90, the ArmSample signal can also control the timing of operations performed by the address comparison circuit 70 and / or the storage control circuit 80. In some embodiments, the address comparison circuit 70 can compare the input row address XADD and provide a hit signal (if a match) at least partially in response to activation of the ArmSample signal. In some embodiments, the storage control circuit 80 can increment and / or reset the counter circuits 60 to 67 at least partially in response to activation of the ArmSample signal. In some embodiments, the timing of operations of the address comparison circuit 70 and / or the storage control circuit 80 can be further controlled by additional signals not shown.

[0056] Figure 5 is a timing diagram of various signals of a semiconductor device according to embodiments of the present disclosure during a memory operation. The states of the signals within the device 10 during various operations can be reflected in the timing diagram 500, and the signals of the timing diagram 500 will be described with reference to Figure 1 , 2 and 4. However, the timing diagram 500 can reflect the operation of other memory devices in addition to the specific device 10 shown in Figures 1-4 .

[0057] The first row of the timing diagram 500 shows the state of the refresh signal AREF. In some embodiments, the AREF signal can be provided by a command control circuit such as the command control circuit 33. The second row of the timing diagram 500 indicates the state of the activate / precharge signal ACT / PRE. In some embodiments, the ACT / PRE signal can be provided by a command control circuit. The third row of the timing diagram 500 shows the state of the refresh state signal RHR State. In some embodiments, the RHR State signal can be provided by a comparison circuit such as the comparison circuit 48. The fourth row of the timing diagram 500 shows the state of the operation timing control / sample signal ArmSample. In some embodiments, the ArmSample signal can be provided by an arm sample generator such as the arm sample generator 42.

[0058] The fifth row of timing diagram 500 illustrates the state of a min / max calculation select signal Min / Max Sel. In some embodiments, the Min / Max Sel signal can be provided by a min / max control logic circuit, such as min / max control logic circuit 38. In some embodiments, the Min / Max Sel signal can have a default and / or rest state. The default state refers to the state of the Min / Max Sel signal unless the ACT / PRE is active and the AREF signal is inactive. The default state can refer to a state indicating that the counter circuit (e.g., counter circuits 60-67) having the highest count value should be determined by a count comparison circuit (e.g., count comparison circuit 90). In the example shown in FIG. 6, the default state is a high logic state. Figure 5 In the example shown in FIG. 6, the default state is a high logic state.

[0059] The sixth row of timing diagram 500 indicates the timing of the operation of a count comparison circuit, such as count comparison circuit 90. The operation can include, but is not limited to, comparing count values from two or more counter circuits. The operation can be initiated at or around the left edge of the first "X" and the result of the operation can be available at or around the right edge of the last "X." The seventh row of timing diagram 500 indicates the state of an address bus providing a row address VADD. In some embodiments, the address bus can provide the row address VADD from a row hammer address storage circuit, such as address storage circuit 44, to an address translator, such as address translator 45. The last row of timing diagram 500 indicates the state of an address bus providing one or more row hammer refresh addresses RHR ADD. In some embodiments, the RHR addresses RHR ADD can be provided from the address translator to a refresh address selector, such as refresh address selector 46.

[0060] The refresh command 505 can be received by a device, such as device 10. At least partially in response to the refresh command 505, the AREF signal can transition to an active state (a high state in the example shown in FIG. 6) to indicate a refresh operation, and the ACT / PRE signal can also transition to an active state (a high state in the example shown in FIG. 6) at or around time TO. The refresh operation performed in response to the refresh command 505 can be an auto-refresh operation. Accordingly, the RHRState signal can remain inactive (a low state in the example shown in FIG. 6) during the refresh operation. After the refresh operation ends, the AREF and ACT / PRE signals can transition to an inactive state (a low state in the example shown in FIG. 6) at or around time Tl. Figure 5 Figure 5 Figure 5 Figure 5

[0061] ​​​​The next refresh operation can be determined as the target refresh / RHR operation. Thus, the RHR State signal can transition to the active state at or about time T2. The device can receive an activate command 510. In response to the activate command 510, the ACT / PRE signal can transition to the active state at or about time T3. In response to the active ACT / PRE signal and the inactive AREF signal, the Min / Max Sel signal can transition from a default state (e.g., a high state) that should determine the counter circuit having the highest count value to another state (e.g., a low state) that should determine the counter circuit having the lowest count value at or about time T4.

[0062] In response to the transition of the Min / Max Sel signal, the count comparison circuit can perform one or more operations to determine the counter circuit including the lowest count value starting at or about time T4 indicated by the "X" in the Comparing line. The results of the operations of the count comparison circuit can be used to update a pointer in the control circuit, such as the MIN pointer 81 in the storage control circuit 80.

[0063] At or about time T5, the sample signal ArmSample can provide an active pulse (a high pulse in the example shown in Figure 5 Although not shown in Figure 5 the ArmSample pulse can be associated with and / or trigger an address comparison circuit, such as the address comparison circuit 70, to perform operations to determine whether the sampled row address matches an address stored in an address register (e.g., the address registers 50-57). If the sampled row address matches the row address stored in the address register, the count value in the corresponding counter circuit is incremented. If the sampled row address does not match the row address stored in the address register, the sampled row address is written to the address register associated with the lowest count value determined by the count comparison circuit at or about time T4. The count value associated with the corresponding counter circuit is also reset.

[0064] In response to the active pulse of ArmSample at or around T5 and the persistent low state of the Min / Max Sel signal, the count comparison circuit can again perform operations to determine the counter circuit that includes the lowest count value, indicated by the "X" in the Comparing line. The results of the operations of the count comparison circuit can be used to update a pointer in the control circuit, such as the MIN pointer 81 in the storage control circuit 80. If the sampled row address matches the address stored in the address register and the corresponding counter circuit is incremented, a different address register can be associated with the lowest count value. If the sampled row address is written to the address register, the same address register can be associated with the lowest count value because the corresponding counter circuit is reset.

[0065] At or around the T6 time, the ArmSample signal can provide a second active pulse. Again, the ArmSample pulse can be associated with and / or trigger an address comparison circuit, such as the address comparison circuit 70, to perform operations to determine whether the sampled row address matches the address stored in the address register. Because the second ArmSample signal occurs during the execution of the same active command 510 as the first pulse, the sampled row address will be the same as the previously compared sampled row address. Thus, the sampled row address will match the row address in the address register and the corresponding count value will be incremented.

[0066] In response to the active pulse of ArmSample at or around T6 and the persistent low state of the Min / Max Sel signal, the count comparison circuit can again perform operations to determine the counter circuit that includes the lowest count value, indicated by the "X" in the Comparing line. The results of the operations of the count comparison circuit can be used to update a pointer in the control circuit, such as the MIN pointer 81 in the storage control circuit 80. The counter circuit that includes the lowest count value can or can not change between the two determinations of the lowest count value performed by the count comparison circuit.

[0067] The device can receive a precharge command 515. In response to the precharge command, the ACT / PRE signal can transition to an inactive state at or around the T7 time. At least partially in response to the ACT / PRE signal transitioning to the inactive state, the Min / Max Sel signal can transition from the low state to the default state at or around the T8 time. As previously described, when the Min / Max Sel signal is in the default state, the count comparison circuit determines the counter circuit with the highest count value.

[0068] In response to a transition in the Min / Max Sel signal, the count comparison circuit can perform one or more operations to determine the counter circuit that includes the highest count value beginning at or around the T8 time instant indicated by the "X" in the Comparing line. The results of the operations of the count comparison circuit can be used to update a pointer in the control circuit, such as the MAX pointer 82 in the storage control circuit 80. The updated pointer can be used to provide a row address VADD on the address bus at or around the T9 time instant. The address VADD can be the row address associated with the highest count value. The address translator can use the address VADD to generate the RHR address RHRADD. The RHR address can be provided on the address bus at or around the T10 time instant.

[0069] The device can receive a refresh command 520. In response to the refresh command 520, the refresh signal AREF and the ACT / PRE signal can transition to the active state, and the RHR address RHRADD remains available on the address bus. Because the RHR State is active, the RHR operation can be performed. Thus, the RHR address RHRADD can be used as the refresh address during the refresh operation performed in response to the refresh command 520.

[0070] By triggering the RHR address calculation operation earlier, the RHR address RHRADD can be available earlier than the calculation of the RHR address performed in response to receiving the refresh command 520. This can reduce the risk of the RHR address RHRADD not being available as the refresh address during the RHR operation. This can reduce the need to delay the RHR operation and / or store the RHR address RHRADD for a subsequent RHR operation. In some embodiments of the disclosure, the RHR address calculation operation is triggered by causing the count comparison circuit to determine the counter circuit that includes the highest count value based on the precharge command 515. For example, the Min / Max Sel signal can transition from the low state to the high state upon receiving the precharge command 515, and the count comparison circuit can determine the counter circuit that includes the highest count value in response to the transition of the Min / Max Sel signal.

[0071] Figure 6 is a flow diagram of a method according to embodiments of the disclosure. In some embodiments, the method 600 can be performed by the device 10.

[0072] At block (602), a "receive a precharge command" can be performed. In some embodiments, the inactive activation signal can be provided at least partially in response to the precharge command. In some embodiments, the signal can be provided to a minimum / maximum control logic circuit, such as the minimum / maximum control logic circuit 38.

[0073] At block (604), responsive at least in part to the precharge command, a determination of a counter circuit of the plurality of counter circuits storing a highest count value can be performed with a count comparison circuit. In some embodiments, the determination can be performed by the count comparison circuit 90. In some embodiments, the counter circuits can include the counter circuits 60-67.

[0074] In some embodiments, the method 600 can further include providing a row address from an address register associated with the counter circuit of the plurality of counter circuits storing the highest count value. In some embodiments, the address register can include the row address registers 50-57. In some embodiments, the method 600 can further include generating at least one refresh address based at least in part on the row address. In some embodiments, the refresh address can be generated by an address translator such as the address translator 45. In some embodiments, the method 600 can further include refreshing at least one word line corresponding to the at least one refresh address. In some embodiments, the refreshing can be responsive at least in part to a refresh command and an active refresh status signal. In some embodiments, the active refresh status signal can cause a target refresh / RHR operation to be performed responsive to the refresh command.

[0075] In some embodiments, the method 600 can further include receiving an active activation signal at the minimum / maximum control logic circuit. In some embodiments, the active activation signal can be provided responsive at least in part to an activation command. Responsive at least in part to the inactive refresh signal and the active activation signal, the method 600 can further include transitioning a selection signal from one state to another state by the minimum / maximum control logic circuit. In some embodiments, responsive at least in part to the transition of the selection signal from one state to the other state, the method 600 can further include determining a counter circuit of the plurality of counter circuits storing a lowest count value with the count comparison circuit.

[0076] In some embodiments, the method 600 can further include receiving an active timing control signal. In some embodiments, the timing control signal can be a sampling signal provided by an arm sample generator, such as the arm sample generator 42. In some embodiments, in response at least in part to the active timing control signal, the method 600 further includes determining, with a count comparison circuit, a counter circuit of the plurality of counter circuits that stores a lowest count value. In some embodiments, in response at least in part to the active timing control signal, the method 600 can further include comparing, with an address comparison circuit, such as the address comparison circuit 70, a sampled row address to a plurality of row addresses stored in a corresponding one of a plurality of address registers, such as the address registers 50-57. In some embodiments, the method 600 can include storing, in an address register of the plurality of address registers associated with the counter circuit of the plurality of counter circuits that stores the lowest count value, when the sampled row address does not match the plurality of row addresses. The method 600 can increment the counter circuit of the plurality of counter circuits associated with the address register of the plurality of address registers that stores the row address of the plurality of row addresses when the sampled row address matches a row address of the plurality of row addresses. In some embodiments, the active timing control signal can be provided multiple times during a time period between an activate command and a precharge command, and each time the active timing control signal is provided, the count comparison circuit determines the counter circuit of the plurality of counter circuits that stores the lowest count value.

[0077] Figure 7 is a flow diagram of a method in accordance with embodiments of the disclosure. In some embodiments, the method 700 can be performed by the device 10.

[0078] At block (702), a signal can be received. The signal can be received by a device, such as the device 10. In some embodiments, the signal can be received by a command control circuit, such as the command control circuit 33. In some embodiments, the signal can be a command, such as a precharge command. At block (704), an active refresh status signal can be received. In some embodiments, the refresh status signal can be provided by a command control circuit. In some embodiments, the refresh status signal can be provided by a component of a refresh control circuit. In some embodiments, the active refresh status signal can be associated with a row hammer refresh operation. In some embodiments, the refresh status signal can be received by a min / max control logic circuit, such as the min / max control logic circuit 38.

[0079] At block (706), responsive at least in part to the signal, "determining a counter circuit of the plurality of counter circuits that stores a highest count value" can be performed. In some embodiments, the determination can be performed by a row hammer address storage circuit, such as row hammer address storage circuit 44. More specifically, in some embodiments, the determination can be performed by a count comparison circuit, such as count comparison circuit 90. In some embodiments, the determination can be performed responsive to a transition of a select signal provided by a minimum / maximum control logic circuit. In some embodiments, the transition of the select signal is responsive to the signal, which, as described above, in some embodiments, can be a precharge command. In some embodiments, the counter circuits can include counter circuits 60-67. At block (708), "providing a row address from an address register associated with the counter circuit on an address bus" can be performed. In some embodiments, the address register can include one of address registers 50-57. In some embodiments, the address bus can be Figure 2 and Figure 4 address bus labeled RHR ADD.

[0080] In some embodiments, method 700 can further include generating a refresh address based on the row address. In some embodiments, the generating can be performed by an address translator, such as address translator 45. Method 700 can further include providing the refresh address on a second address bus. In some embodiments, the second address bus can include one or more address buses labeled RHR ADD.

[0081] In some embodiments, method 700 can further include receiving a refresh command. In some embodiments, the refresh command can be received by a command control circuit. In some embodiments, responsive at least in part to the refresh command, method 700 can include refreshing a word line corresponding to the refresh address. In some embodiments, the word line can be refreshed at least in part by a row address control circuit, such as row address control circuit 12.

[0082] The apparatuses, methods, and systems disclosed herein can allow for determining a counter of an address storage circuit having a highest count value that can be initiated by a signal received prior to an RHR operation. In some examples, the signal can be a command, such as a precharge command. This can allow for an additional period of time prior to the RHR operation to determine the counter having the highest count value, provide an address associated with the counter, and generate one or more refresh addresses from the address. The additional time can reduce or eliminate the risk of the refresh addresses not being available for the RHR operation.

[0083] While the application has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the application extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the application and obvious modifications and equivalents thereof. Further, it will be understood by those skilled in the art that other modifications beyond the specific embodiments disclosed can occur to persons of ordinary skill in the art upon reading the foregoing description. Also, various combinations of features and aspects of the disclosed embodiments can be made and still fall within the scope of the application. It is intended, therefore, to be limited only by the scope of the appended claims.

Claims

1. A device for memory operations, comprising: Multiple address registers, each configured to store a row address; Multiple counter circuits, each configured to store a count value corresponding to an associated one of the multiple address registers; A comparator circuit is configured to determine the counter circuit that stores the highest count value among the plurality of counter circuits; as well as A control logic circuit configured to control the comparison circuit to determine the counter circuit storing the highest count value among the plurality of counter circuits in response to a precharge command received by the device.

2. The device of claim 1, wherein the control logic circuitry is configured to provide a selection signal to the comparison circuitry, wherein the comparison circuitry is configured to determine, in response to the selection signal transitioning from a first state to a second state, the counter circuitry storing the highest count value among the plurality of counter circuitry, wherein the control logic circuitry is configured to transition the selection signal from the first state to the second state based at least in part on the precharge command.

3. The device of claim 2, wherein the comparison circuit is further configured to determine a counter circuit storing the lowest count value among the plurality of counter circuits in response to the selection signal transitioning from the second state to the first state, wherein the control logic circuit is configured to transition the selection signal from the second state to the first state based at least in part on an activation command received by the device.

4. The device of claim 3, further comprising a sampling generator circuit configured to provide a sampling signal to the comparison circuit, wherein the comparison circuit is further configured to determine, in response to activation of a timing control signal, the counter circuit storing the lowest count value among the plurality of counter circuits.

5. The device of claim 1, further comprising a storage control circuit coupled to the comparator circuit, the storage control circuit including a pointer, wherein the pointer stores a value of one of the plurality of address registers associated with the counter circuit that stores the highest count value determined by the comparator circuit.

6. The device of claim 5, further comprising an address converter, wherein the storage control circuitry is configured to provide a row address stored in one of the plurality of address registers associated with the counter circuitry storing the highest count value to the address converter, wherein the address converter is configured to generate one or more refresh addresses at least in part based on the row address.

7. The device of claim 2, wherein the control logic circuit is configured to receive an activation signal and a refresh signal, wherein the control logic circuit is configured to provide the selection signal in the first state when the activation signal is active and the refresh signal is inactive.

8. The device of claim 7, further comprising a command control circuit configured to provide the activation signal and the refresh signal.

9. A method for memory operations, comprising: Receive precharge commands at the memory location; and In at least a partial response to the precharge command, a counter circuit is used to determine the counter circuit that stores the highest count value among a plurality of counter circuits.

10. The method of claim 9, further comprising: The row address is provided from the address register associated with the counter circuit that stores the highest count value in the plurality of counter circuits; At least one refresh address is generated based, at least in part, on the row address; and Responding at least partially to a refresh command and an active refresh status signal, refresh at least one word line corresponding to the at least one refresh address.

11. The method of claim 9, further comprising at least partially responding to the precharge command by transitioning a selection signal from a first state to a second state, wherein, in response to the transition, the counter circuit is executed to determine the highest stored count value among the plurality of counter circuits.

12. The method of claim 11, further comprising: Receive activation command; At least in part in response to the activation command, the selection signal is transitioned from the first state to the second state; and At least in part in response to the transition of the selection signal from the first state to the second state, the counting comparison circuit determines the counter circuit among the plurality of counter circuits that stores the lowest count value.

13. The method of claim 12, further comprising: Receive active timing control signals; and In at least a partial response to the activity timing control signal, the counter circuit that stores the lowest count value among the plurality of counter circuits is determined by the counting comparison circuit.

14. The method of claim 13, further comprising at least partially responding to the activity timing control signal: The sampled row address is compared with multiple row addresses stored in one of multiple address registers using an address comparison circuit; When the sampled row address does not match the plurality of row addresses, the address registers stored in the plurality of address registers are associated with the counter circuit storing the lowest count value in the plurality of counter circuits; as well as When the sampled row address matches a row address among the plurality of row addresses, the counter circuit in the plurality of counter circuits associated with the address register storing the row address among the plurality of row addresses is incremented.

15. The method of claim 13, wherein the activity timing control signal is provided multiple times during a time period between the activation command and the precharge command, and each time the activity timing control signal is provided, the counting comparison circuit determines the counter circuit among the plurality of counter circuits that stores the lowest count value.

16. The method of claim 9, further comprising performing a row hammer refresh operation in response to a refresh command and an active refresh status signal.

17. A method for memory operations, comprising: Receive signal; Receive an active refresh status signal, wherein the active refresh status signal is associated with a row hammer refresh operation; At least partially in response to the signal, the counter circuit storing the highest count value among a plurality of counter circuits is determined; and The row address from the address register associated with the counter circuit is provided on the address bus. The determination is performed by a counting comparison circuit in response to a change in a selection signal provided by a control logic circuit, wherein the change in the selection signal is made in response to a signal, wherein the signal is a precharge command.

18. The method of claim 17, further comprising: Generate a refresh address based on the row address; and The refresh address is provided on the second address bus.

19. The method of claim 18, further comprising: Receive refresh command; and The word line corresponding to the refresh address is refreshed, at least in part in response to the refresh command and the active refresh status signal.

Images