Memory cell programming

Abstract

The present disclosure relates to memory cell programming. A memory having an array of memory cells and a plurality of access lines each connected to a respective plurality of memory cells in the array of memory cells can include a controller configured to cause the memory to: apply respective program pulses having a first target voltage level and a first pulse width to each access line in a first subset of the plurality of access lines; and apply respective program pulses having the first target voltage level and a second pulse width longer than the first pulse width to each access line in a second subset of the plurality of access lines, where each access line in the first subset is closer to a particular end of a series-connected string of memory cells than each access line in the second subset.

Description

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 072,259, filed August 31, 2020, which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates generally to integrated circuits, and in particular, in one or more embodiments, the present disclosure relates to apparatuses and methods for memory cell programming. BACKGROUND

[0003] Memory, e.g., a memory device, is typically provided as internal semiconductor integrated circuit devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random-access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0004] Flash memory has evolved into a popular nonvolatile memory source for a wide range of electronic applications. Flash memory typically uses a single transistor memory cell that allows high memory density, high reliability, and low power consumption. The change in threshold voltage (Vt) of the memory cell, by programming a charge storage structure (e.g., a floating gate or charge trap) or other physical phenomena (e.g., phase change or polarization), determines the data state (e.g., data value) of each memory cell. Common uses of flash memory and other nonvolatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile telephones, and removable memory modules, and the use of nonvolatile memory continues to expand.

[0005] NAND flash memory is a commonly used type of flash memory device, so named for the logical form in which the underlying memory cell configuration is arranged. Generally, an array of memory cells for NAND flash memory is arranged such that the control gates of each memory cell in a row in the array are connected together to form an access line, such as a word line. Columns in the array contain strings of memory cells (often referred to as NAND strings) connected together in series between a pair of select gates, such as between a source select transistor and a drain select transistor. Each source select transistor can be connected to a source, and each drain select transistor can be connected to a data line, such as a column bit line. Variations using more than one select gate between the string of memory cells and the source and / or between the string of memory cells and the data line are known.

[0006] When programming the memory, the memory cells can be programmed to what is commonly referred to as single level cells (SLCs). SLCs can use a single memory cell to represent a one-bit (e.g., one bit) of data. For example, in SLCs, a Vt of 2.5V or higher can indicate a programmed memory cell (e.g., representing a logical 0), and a Vt of -0.5V or lower can indicate an erased memory cell (e.g., representing a logical 1). Such memory can achieve higher levels of storage capacity by including multiple level cells (MLCs), triple level cells (TLCs), quad level cells (QLCs), etc., or combinations thereof, where the memory cells have multiple levels enabling more bits of data to be stored in each memory cell. For example, MLCs can be configured to store two bits of data per memory cell represented by four Vt ranges, TLCs can be configured to store three bits of data per memory cell represented by eight Vt ranges, QLCs can be configured to store four bits of data per memory cell represented by sixteen Vt ranges, etc.

[0007] Programming memory cells generally utilizes an iterative process of applying a program pulse to a memory cell and verifying whether the memory cell has reached its desired data state in response to the program pulse, and repeating the iterative process until the memory cell passes verification. Prior to each program pulse, the word line can be pre-charged, and after each program pulse, the word line can be discharged. Upon a memory cell passing verification, the memory cell can be inhibited from further programming. The iterative process can be repeated with varying (e.g., increasing) voltage levels of the program pulse until each memory cell selected for a program operation has reached its respective desired data state or some failure is declared (e.g., a maximum number of allowed program pulses is reached during the program operation). The iterative nature of a given program operation and the relatively high voltage levels used for each iteration can have a significant impact on both the speed and power consumption of the memory. SUMMARY

[0008] A memory is described. In some instances, the memory may include: a memory cell array comprising a plurality of serially connected memory cell strings; a plurality of access lines, wherein each of the plurality of access lines is connected to a corresponding plurality of memory cells in the memory cell array; and a controller for accessing the memory cell array, wherein the controller is configured to cause the memory to: apply a corresponding programming pulse having a first target voltage level and a first pulse width to each access line in a first subset of the plurality of access lines, wherein each access line in the first subset of access lines is connected to a corresponding memory cell in a serially connected memory cell string; and apply a corresponding programming pulse having the first target voltage level and a second pulse width longer than the first pulse width to each access line in a second subset of the plurality of access lines, wherein each access line in the second subset of access lines is connected to a corresponding memory cell in the serially connected memory cell string, and wherein each access line in the first subset of access lines is closer to a specific end of the serially connected memory cell string than each access line in the second subset of access lines.

[0009] A memory is described. In some instances, the memory may include: a memory cell array comprising a plurality of serially connected strings of memory cells; a plurality of access lines, each of which is connected to a corresponding plurality of memory cells in the memory cell array; and a controller for accessing the memory cell array, wherein the controller is configured to cause the memory to: apply a specific programming pulse from a plurality of programming pulses to an access line connected to each of the plurality of memory cells selected for programming operations, wherein each of the plurality of programming pulses has a corresponding target voltage level and a corresponding desired pulse width; after the application of the specific programming pulse, for each of the plurality of memory cell groups, determine the number of memory cells in the memory cell group that have not passed a verification operation of the programming operation; and adjust the corresponding desired pulse width of subsequent programming pulses from the plurality of programming pulses in response to the number of failed memory cells in any of the plurality of memory cell groups exceeding a threshold determined in response to the number of failed memory cells in the specific memory cell group of the plurality of memory cells.

[0010] A memory is described. In some instances, the memory may include: a memory cell array comprising a plurality of serially connected memory cell strings; a plurality of access lines, wherein each of the plurality of access lines is connected to a corresponding plurality of memory cells in the memory cell array; and a controller for accessing the memory cell array, wherein the controller is configured to cause the memory to: apply a corresponding first programming pulse having a first target voltage level and a first pulse width to each access line in a first subset of the plurality of access lines, wherein each access line in the first subset of the first access lines is connected to a serially connected memory cell string in the plurality of serially connected memory cell strings. The corresponding memory cell, wherein the corresponding first programming pulse for each access line in the first access line subset is a specific programming pulse among a plurality of programming pulses for a corresponding programming operation on the access line in the first access line subset; for the access line in the first access line subset: after applying the corresponding first programming pulse to the access line, determining a first number of memory cells in a specific memory cell group of the corresponding plurality of memory cells of the access line that have not passed the verification operation; after applying the corresponding first programming pulse to the access line, determining that different memory cell groups of the corresponding plurality of memory cells of the access line have not passed the verification. A second number of memory cells to be operated; determining a first threshold greater than or equal to the first number of memory cells in response to the first number of memory cells; and adjusting the pulse width of a corresponding second programming pulse among a plurality of programming pulses to be applied to each access line in the first subset of access lines for its corresponding programming operation in response to the second number of memory cells exceeding the first threshold; applying a corresponding first programming pulse having a first target voltage level and a second pulse width longer than the first pulse width to each access line in the second subset of the plurality of access lines, wherein each access line in the second subset of access lines is connected to the serially connected memory. The corresponding memory cells of the memory cell string, wherein each access line in the first access line subset is closer to a specific end of the serially connected memory cell string than each access line in the second access line subset, and wherein the corresponding first programming pulse for each access line in the second access line subset is a specific programming pulse among a plurality of programming pulses for a corresponding programming operation on the access line in the second access line subset; and for the access lines in the second access line subset: after applying the corresponding first programming pulse to the access line, determining a third number of memory cells in a specific group of the plurality of memory cells of the access line that have not passed the verification operation;After applying the corresponding first programming pulse to the access line, a fourth number of memory cells in different memory cell groups of the corresponding plurality of memory cells of the access line that have not passed the verification operation is determined; a second threshold greater than or equal to the third number of memory cells is determined in response to the third number of memory cells; and in response to the fourth number of memory cells exceeding the second threshold, the pulse width of the corresponding second programming pulse in the corresponding plurality of programming pulses of each access line to be applied to the second subset of access lines for its corresponding programming operation is adjusted. Attached Figure Description

[0011] Figure 1 This is a simplified block diagram of a memory according to an embodiment, which communicates with a processor as part of an electronic system.

[0012] Figures 2A-2B This can be used as a reference. Figure 1 A schematic diagram of a portion of the memory cell array in the described type of memory.

[0013] Figure 2C This can be used as a reference. Figure 1 A perspective view of a portion of the elements in a memory cell array of the described type of memory.

[0014] Figure 3A A portion of a semiconductor pillar having a cross-section of various sizes, according to an embodiment, and a plurality of access lines formed around the pillar are depicted.

[0015] Figure 3B Depicting Figure 3A A graph showing the relationship between the resistance levels that the access lines may have.

[0016] Figure 4A and 4B A timing diagram depicting the voltage levels of the access lines selected for programming operations during the initial programming pulse and subsequent higher programming pulses used in conjunction with the embodiments.

[0017] Figure 5 A graph depicting the resistance values ​​that can occur for N+1 access lines of a memory cell block according to an embodiment.

[0018] Figure 6A This is a representation of several groups of memory cells according to an embodiment, the memory cells being connected to a driver for providing an applied voltage level to an access line of each of the memory cells in the group of memory cells connected to the memory cells.

[0019] Figure 6B Conceptually depicting the target according to the embodiments Figure 6AThe number of memory cells in each group of memory cells that failed the verification operation.

[0020] Figure 7 A flowchart depicting a method for operating a memory according to an embodiment during several programming operations.

[0021] Figure 8 A flowchart depicting a method for operating a memory according to an embodiment during one or more programming operations. Detailed Implementation

[0022] In the following detailed description, reference is made to the accompanying drawings, which form part of the invention, and in which specific embodiments are illustrated by way of illustration. In the drawings, the same reference numerals in several views consistently describe substantially similar components. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0023] For example, the term "semiconductor" as used herein may refer to a layer of material, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referenced to a semiconductor in the following description, regions / junctions may have been formed in the substrate semiconductor structure using prior process steps, and the term semiconductor may include an underlying layer containing such regions / junctions.

[0024] Unless otherwise apparent from the context, the term "conductive" as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refer to electrical conductivity. Similarly, unless otherwise apparent from the context, the term "connecting" as used herein, and its various related forms (e.g., connect, connected, connection, etc.), refer to electrical connection.

[0025] This paper recognizes that even when values ​​are intended to be equal, the variability and precision of industrial processing and operation can still lead to differences from their intended values. These variability and precision typically depend on the techniques used in the manufacture and operation of integrated circuit devices. Therefore, if values ​​are intended to be equal, then those values ​​are considered equal regardless of their resulting values.

[0026] Figure 1 This is a simplified block diagram of a first device in the form of a memory (e.g., a memory device) 100 according to an embodiment, which communicates as part of a third device in the form of an electronic system with a second device in the form of a processor 130. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The processor 130, such as a controller external to the memory device 100, may be a memory controller or other external host device.

[0027] Memory device 100 includes an array 104 of memory cells that can be logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (often referred to as a word line), while memory cells in a logical column are typically selectively connected to the same data line (often referred to as a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (Not shown in the text) can be programmed to be one of at least two target data states.

[0028] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 to manage inputs of commands, addresses, and data to memory device 100, as well as outputs of data and status information from memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0029] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to the command and may generate status information for external processor 130, i.e., control logic 116 is configured to perform access operations (e.g., sensing operations [which may include read and verification operations], programming operations, and / or erase operations) on memory cell array 104. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control row decoding circuitry 108 and column decoding circuitry 110 in response to an address. Control logic 116 may include instruction register 128, which may represent computer-available memory for storing computer-readable instructions. In some embodiments, instruction register 128 may represent firmware. Alternatively, instruction register 128 may represent a grouping of memory cells in memory cell array 104, such as a reserved block of memory cells.

[0030] Control logic 116 can also communicate with cache register 118. Cache register 118 latches incoming or outgoing data, such as that guided by control logic 116, to temporarily store data while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 120 for transfer to memory cell array 104; subsequently, new data can be latched into cache register 118 from I / O control circuitry 112. During read operations, data can be transferred from cache register 118 to I / O control circuitry 112 for output to external processor 130; subsequently, new data can be transferred from data register 120 to cache register 118. Cache register 118 and / or data register 120 may form a page buffer of memory device 100 (e.g., may form a portion thereof). The page buffer may further include sensing devices ( Figure 1 (Not shown in the diagram) The data state of the memory cells can be sensed, for example, by sensing the state of the data lines of the memory cells connected to the memory cell array 104. The status register 122 can communicate with the I / O control circuitry 112 and the control logic 116 to latch status information for output to the processor 130.

[0031] The memory device 100 receives control signals from the processor 130 via control link 132 at control logic 116. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may be received further via control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via a multiplexed input / output (I / O) bus 134 and outputs data to the processor 130 via the I / O bus 134.

[0032] For example, a command can be received at I / O control circuit 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to command register 124. An address can be received at I / O control circuit 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to address register 114. Data can be received at I / O control circuit 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 118. The data can then be written to data register 120 for programming memory cell array 104. In another embodiment, cache register 118 can be omitted, and data can be written directly to data register 120. Data can also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may contain any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connections to the memory device 100 via external devices (e.g., processor 130).

[0033] Those skilled in the art will understand that additional circuitry and signals can be provided, and the process has been simplified. Figure 1 The memory device 100. It should be understood that, with reference to Figure 1 The functionality of the various block components described need not be separated from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1 The functionality of more than one block component. Alternatively, one or more components or component portions of the integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0034] Furthermore, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that combinations of other I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0035] Figure 2A It can be, for example, as part of memory cell array 104 in reference Figure 1 A schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array, used in the type of memory described. The memory array 200A includes access lines (e.g., word lines 2020 to 202). N ) and data lines (e.g., bit lines 2040 to 204) M Word line 202 can be connected in a many-to-one relationship. Figure 2A Global access lines (e.g., global word lines) not shown in the diagram. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity to form a p-well, or have n-type conductivity to form an n-well, for example.

[0036] The memory array 200A can be arranged in rows (each row corresponds to word lines 202) and columns (each column corresponds to bit lines 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cells 2080 to 208 N It may include memory cells intended for storing data, and may also include other memory cells not intended for storing data, such as dummy memory cells. Dummy memory cells are generally not accessible to the user of the memory and are often alternatively incorporated into a series-connected string of memory cells to obtain well-known operational advantages.

[0037] The memory cells 208 in each NAND string 206 may be connected in series to the select gate 210 (e.g., a field-effect transistor) (e.g., select gates 2100 to 210). M One of them (e.g., it may be a source-select transistor, often referred to as a select-gate source) and select-gate 212 (e.g., a field-effect transistor) (e.g., select-gate 2120 to 212). MOne of them (for example, it could be a drain-select transistor, often referred to as the select gate drain)). Select gate 2100 to 210 M They can be commonly connected to select line 214, such as source select line (SGS), and select gates 2120 to 212. M They can be commonly connected to select line 215, such as a drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent a plurality of select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0038] The source of each select gate 210 may be connected to a common source 216. The drain of each select gate 210 may be connected to a memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 may be connected to a memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 may be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 may be connected to a select line 214.

[0039] The drain of each select gate 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0040] Figure 2A The memory array in the array can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2A The memory array in the array may be a three-dimensional memory array, for example, in which the NAND string 206 may extend substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the bit line 204, which may be substantially parallel to the plane containing the common source 216.

[0041] like Figure 2AAs shown, a typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that determines the data state of the memory cell (e.g., by changing a threshold voltage), and a control gate 236. Data storage structure 234 may include both conductive and dielectric structures, while control gate 236 is generally formed of one or more conductive materials. In some cases, memory cell 208 may additionally have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The control gate 236 of memory cell 208 is connected to (and in some cases forms) a word line 202.

[0042] Columns of memory cells 208 may be NAND strings 206 or multiple NAND strings 206 selectively connected to a given positioning line 204. Rows of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. Rows of memory cells 208 may, but need not, contain all memory cells 208 commonly connected to a given word line 202. Rows of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 typically contain every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202 N Furthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202 N Furthermore, memory cells 208 selectively connected to odd-numbered bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.) can be another physical page of memory cell 208 (e.g., odd-numbered memory cells). Although in Figure 2A Bit lines 2043 to 2045 are not explicitly depicted in the figure, but it is evident from the figure that bit lines 204 of the memory cell array 200A can be connected from bit line 2040 to bit line 204. M Memory cells 208 that are commonly connected to a given word line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given word line may be considered physical pages of the memory cell. A portion of a physical page of a memory cell (which in some embodiments may still be an entire row) that is read during a single read operation or programmed during a single programmable operation (e.g., the upper or lower page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020 to 202. NAll memory cells (e.g., all NAND strings 206 sharing common word line 202). Unless explicitly distinguished, a reference to a memory cell page herein refers to the memory cell of the logical page of the memory cell.

[0043] Although discussing in conjunction with NAND flash memory Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS or other data storage structures configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0044] Figure 2B This is another schematic diagram of a portion of a memory cell array 200B, which may, for example, be used as part of a memory cell array 104 for reference. Figure 1 The type of memory described. Figure 2B Elements with the same number in the text correspond to elements about Figure 2A The description provided. Figure 2B Further details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may incorporate a vertical structure that may contain semiconductor pillars, a portion of which may serve as channel regions for the memory cells of NAND strings 206. Each of the NAND strings 206 may be selectively connected to bit lines 2040 to 2046 via a select transistor 212 (e.g., a drain select transistor, commonly referred to as a select gate drain). M And a selection transistor 210 (e.g., a source selection transistor, often referred to as a select gate source) is selectively connected to a common source 216. Multiple NAND strings 206 can be selectively connected to the same bit line 204. A subset of NAND strings 206 can be connected via selection lines 2150 to 2154. K A bias voltage is applied to its corresponding bit line 204 to selectively activate a specific selection transistor 212 located between the NAND string 206 and the bit line 204. A selection transistor 210 can be activated by applying a bias voltage to selection line 214. Each word line 202 can be connected to multiple rows of memory cells in the memory array 200B. Rows of memory cells commonly connected to each other via specific word lines 202 can be collectively referred to as a layer.

[0045] A three-dimensional NAND memory array 200B may be formed above peripheral circuitry 226. Peripheral circuitry 226 may represent various circuits used to access the memory array 200B. Peripheral circuitry 226 may include complementary circuit elements. For example, peripheral circuitry 226 may include both n-channel and p-channel transistors formed on the same semiconductor substrate; this process is commonly referred to as CMOS or Complementary Metal-Oxide-Semiconductor. Although CMOS often no longer utilizes a strictly metal-oxide-semiconductor construction due to advancements in integrated circuit manufacturing and design, the designation CMOS is retained for convenience.

[0046] Figure 2C This can be used as a reference. Figure 1 A perspective view of a portion of the elements in a memory cell array 200C of the described type of memory. Figure 2C The same numbered elements in the text correspond to, for example, regarding... Figure 2A The description provided. Figure 2C Alternative details are provided for one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200C may incorporate a vertical structure that may include semiconductor pillars 218, a portion of which may serve as channel regions for memory cells of a NAND string. Pillars 218 may each be connected in a many-to-one relationship to bit line 204 and source 216. In some embodiments, pillars 218 may have a hollow core. Select transistors (e.g., drain select transistors) 212 may be formed at each intersection of pillar 218 and select line (e.g., drain select line) 215. Figure 2C (Not identified in the text). A selection transistor (e.g., a source selection transistor) 210 may be formed at each intersection of pillar 218 and selection line (e.g., source selection line) 214. Figure 2C (Not identified in the text). Memory cells 208 may be formed at each intersection of the column and access line (e.g., word line) 202. Figure 2C (Not identified in the text). The three-dimensional NAND memory array 200C depicts word lines 202 which may be formed as conductive plates (e.g., parallel conductive plates), and each word line 202 may be adjacent to (e.g., adjacent to) at least one other word line 202.

[0047] although Figure 2C The column 218 is essentially depicted as cylindrical, but typical manufacturing techniques can produce columns 218 with various cross-sectional sizes. For example, while the column 218 can be manufactured by forming through holes using a circular mask, the resulting shape may not be cylindrical and may instead have a varying diameter along its length. Figure 3A A portion of a semiconductor pillar 218 having a cross-section of various sizes is depicted, along with a plurality of access lines 202 formed around the pillar 218. The access lines 202 may be, for example... Figure 2CThe conductive plate depicted. Therefore, the access line 202 intersecting the post 218 at a portion with a larger cross-section can have a greater resistance than the access line 202 intersecting the post 218 at a portion with a smaller cross-section. Figure 3A In this example, access line 2026 is expected to have a larger resistance than each of the remaining access lines 2020 to 2025 and 2027. Figure 3B A graph depicting the relationship between the possible resistance levels of access line 202.

[0048] Programming typically involves applying one or more programming pulses to a selected word line, and thus to the control gate of the row of memory cells connected to the selected word line (e.g., whose control gate is connected to the selected word line). A typical programming pulse may begin at or near 13V and tends to increase the amount applied by each subsequent programming pulse. While a program potential (e.g., the voltage level of the programming pulse) is applied to the selected word line, an enable voltage, such as a ground potential (e.g., 0V), may be applied to the channel of the memory cells selected for programming (i.e., those memory cells whose data state the programming operation intends to shift to a higher level). This can result in a charge transfer from the channel to the charge storage structure of these selected memory cells. For example, a floating gate is typically charged by direct injection of electrons from the channel to the floating gate or by Fowler-Nordheim tunneling, resulting in a threshold voltage that is typically greater than zero in the programmed state.

[0049] A disable voltage (e.g., Vcc) is typically applied to bit lines selectively connected to a NAND string containing memory cells connected to selected word lines and not selected for programming or no longer selected for programming. In addition to bit lines selectively connected to memory cells already in their target data state, these unselected bit lines may further include bit lines not addressed by programming operations. For example, a logical page of data may correspond to memory cells connected to a particular word line and selectively connected to a particular subset of bit lines (e.g., every other bit line), such that the remaining subset of bit lines will not be selected for programming operations and are therefore disabled.

[0050] Between the application of one or more programming pulses, a verification operation is typically performed to check each selected memory cell to determine whether it has reached its target data state. If a selected memory cell has reached its target data state, for example, by passing the verification operation, further programming can be prevented while other selected memory cells still require additional programming pulses to reach their target data state. After the verification operation, if there are memory cells that have not yet been programmed (e.g., failed the verification operation), additional programming pulses can be applied. This process of applying programming pulses followed by performing verification operations (e.g., the program verification phase of a programming operation) typically continues until all selected memory cells have reached their target data state. For example, if a certain number of programming pulses (e.g., a maximum number) have been applied, or a certain voltage level of programming pulses (e.g., a maximum voltage level) has been reached, and one or more selected memory cells have still not been programmed, then those memory cells can be marked as defective. Various embodiments attempt to reduce the number of these program verification phases of the programming operation.

[0051] Figure 4A and 4B Depicted in the initial programming pulse 4000 and subsequent higher programming pulses 400 X A timing diagram of the voltage levels of the access lines selected for programming operations during the period. Trace 4400 of programming pulse 4000 may represent the voltage level of the selected access line closest to the memory cell of the driver that applies various voltage levels to the selected access line during the programming operation, while trace 4420 of programming pulse 4000 may represent the voltage level of the selected access line furthest from the memory cell of the driver during the programming operation. Similarly, programming pulse 400... X trace 440 X It can represent the voltage level of the selected access line at the memory cell closest to the driver, while the programming pulse 400 X trace 442 X It can represent the voltage level of the selected access line at the memory cell furthest from the driver.

[0052] In typical programming operations, all access lines of the NAND string containing the selected access line are initially increased to a common voltage level, such as a pass voltage. Therefore, in Figure 4A The time interval between t0 and t1 depicts the first gradual increase in the voltage level of programming pulse 4000, and in Figure 4B The programming pulse 400 is depicted between time t0 and t1. X The first gradual increase in the voltage level can be called t. PCHG For two programming pulses, these voltage levels can be the same. For example... Figure 4A and 4BAs described, due to the RC time constant of the access lines, the response of access lines farther from the driver will be slower than that of those closer to the driver. Therefore, traces 4400 and 440... X At traces 4420 and 442 respectively X Previously, the desired voltage level was reached, for example, Vpass. In some cases, traces 4420 and 442... X Vpass was not reached before time t1.

[0053] For each programming pulse, the selected access line can then be increased from Vpass toward the programming voltage level, such as Vpgm0 for programming pulse 4000 and Vpgm0 for programming pulse 4000. X Vpgm X The non-selected access line can remain at the Vpass voltage level. RISE This time period can generally be defined as the time necessary to reach the desired voltage level at the output of the voltage generation system (e.g., a charge pump) and at the beginning of the selected access line used to represent the programming voltage level. The desired voltage level can be the programming voltage level, or it can be some intermediate voltage level, such as within 1% of the programming voltage level. Although this time period can generally be considered independent of the RC characteristics of the selected access line, the RC characteristics of the selected access line will affect its own response to the applied voltage. Thus, traces 4400 and 440 X At traces 4420 and 442 respectively X Previously, the voltage level reached or approached the desired programming voltage level, such as Vpgm0 and Vpgm. X Furthermore, these effects can become more pronounced at higher voltage levels, as seen in trace 442. X The trace 4420 at its corresponding time t2 is further away from the desired programming voltage level Vpgm. X Furthermore, if the time period t RISE For programming pulses 4000 and 400 X If the two are equal, then it is sufficient to make the trace 440. X The time period for obtaining the desired voltage level may not be sufficient for trace 440. X Obtain the desired voltage level.

[0054] For each programming pulse, the selected access line can then be maintained or further approached between time t2 and t3 (which may be referred to as t). FLAT The corresponding programming voltage level of the memory cell connected to the selected access line. Generally, this time period may refer to a period of time considered sufficient to affect a change (e.g., an increase) in the threshold voltage of the memory cell enabled for programming. However, due to traces 4400 and 440 XTypically above traces 4420 and 442 respectively. X Therefore, during this period, enabled memory cells closer to the driver are expected to experience more efficient changes in their threshold voltage compared to enabled memory cells farther from the driver. Furthermore, referencing programming pulse 400... X This effect may be more pronounced. As a result, memory cells closer to the driver can be programmed much faster than those farther from the driver, which may require additional programming pulses for all selected memory cells to obtain their desired data state.

[0055] For each programming pulse, the selected access line can then be allowed to discharge to a certain discharge voltage level, such as Vdis, between times t3 and t4, which may be referred to as t. FALL Because the verification operation (e.g., sensing operation) can be performed after the programming pulse, or a subsequent programming pulse can be applied without performing the verification operation, the discharge voltage level can be close to the pass voltage level Vpass.

[0056] The following discussion will focus on the time interval from time t1 to time t4 of the programming pulse. For this discussion, the voltage generation system can be a charge pump. The following parameters will be referenced:

[0057] Vmax = The maximum voltage generated by the voltage generating system.

[0058] Rpmp = Resistance level of the voltage generation system

[0059] Cpmp = Capacitance level of the voltage generation system

[0060] Rwl = Resistance level of the selected access line

[0061] Cwl = Capacitance level of the selected access line

[0062] Vstart = Voltage level at time t1

[0063] Vtarget = the desired voltage level of the programming pulse.

[0064] Vdis = Desired discharge voltage level

[0065] G = Percentage of the desired voltage level as close to the target

[0066] refer to Figure 4A and 4B The time period t discussed RISE This can be described by Equation 1. This time period can be governed by the RC characteristics of the voltage generating system and may not depend on any salience on the R or C of the access line.

[0067] t RISE=Rpmp*Cpmp*ln[(Vmax-Vstart) / (Vmax-Vtarget)] (Equation 1)

[0068] Although the near-end of the access line can be considered to have reached the target voltage level Vtarget at time t2, the far-end of the access line is expected to have a slower ramp-up and can typically reach the target voltage level Vtarget within a given time period t. RISE At time t2, the voltage reaches an intermediate level below Vtarget, for example, V RISE As described by Equation 2.

[0069] V RISE =Vstart+(Vmax-Vstart)*[1-exp(-t RISE / Rwl*Cwl)](Equation 2)

[0070] Although t RISE The value of t may not be expected to depend significantly on the RC characteristics of the access line, but it can depend on the target voltage level. For example, the initial programming pulse may have a target voltage level of Vtarget_init_pulse, while the Nth programming pulse may have a target voltage level of Vtarget_Nth_pulse that is higher than Vtarget_init_pulse. The t of the Nth programming pulse RISE The value of t, for example RISE(Nth) , can be expressed as t RISE(Nth) =Q RISE(Nth) *t RISE(init) Q RISE(Nth) This can be described by Equation 3:

[0071] Q RISE(Nth) =(ln[(Vmax-Vstart) / (Vmax-Vtarget_Nth_pulse)]) / (ln[(Vmax-Vstart) / (Vmax

[0072] -Vtarget_init_pulse)])(Equation 3)

[0073] refer to Figure 4A and 4B The time period t discussed FLAT This can be described by Equation 4. The time interval t... FLAT This can be defined as the time required for the access line to reach the intermediate voltage level Vint1, after the voltage generation system has reached the target voltage level Vtarget, for example, at t RISE Subsequently, the intermediate voltage level Vint1 can be expressed as a target percentage (e.g., 99%) of the target voltage level Vtarget. This time period can be governed by the RC characteristics of the access line.

[0074] t FLAT =Rwl*Cwl*ln[(Vtarget-V RISE [(Vtarget-Vint1)](Equation 4)

[0075] t FLAT The value of t can depend on the RC characteristics of the access line and the target voltage level of the programming pulse. FLAT The base value, for example, t FLAT(init) This can be based on specific resistances (e.g., Rdes) and specific capacitances (e.g., Cdes) of the access line and the initial target voltage level Vtarget_init_pulse. Therefore, the t of the Nth programming pulse... FLAT The value of t, for example FLAT(Nth) , can be expressed as t FLAT(Nth) =Q FLAT(Nth) *t FLAT(init) *B RC +Y Vtarget Q FLAT(Nth) B can be primarily determined by the multiplier relative to the target voltage level. RC It can be mainly determined by the multiplier of the relative RC characteristics, and Y Vtarget This can be a correction factor that primarily depends on the target voltage level. Multiplier B RC It may have a relatively weak dependence on a relative target voltage level, which can be returned to Y via a difference analysis set. Vtarget In the parameters, the values ​​of Rdes and Cdes can represent measured or expected values ​​for a specific access line of a memory cell block (e.g., the access line closest to one end of a series-connected string of memory cells), such as the end closest to the common source of the memory cell block. The value of Cwl for each access line can also be considered equal to Cdes.

[0076] Multiplier Q FLAT(Nth) This can be described by Equation 5:

[0077] Q FLAT(Nth) =(ln[(Vtarget_Nth_pulse-V RISE_Nth_pulse ) / (Vtarget_Nth_pulse-Vint1_Nth_pulse)]) / (ln[(Vtarget_init_pulse-V RISE_init_pulse ) / (Vtarget_init_pulse-Vint1_init_pulse)]) (Equation 5)

[0078] Multiplier B RC It can be described as t calculated using Vtarget of a specific programmed pulse targeting the RC characteristics of the access line (e.g., Rwl*Cwl).FLAT The value is the same as the t calculated for the same Vtarget for a specific RC characteristic (e.g., Rdes*Cdes). FLAT The ratio of the values. For example, the multiplier B can be calculated for programming pulses following the initial programming pulse. RC .

[0079] refer to Figure 4A and 4B The time period t discussed FALL This can be described by Equation 6. The time interval t... FALL This time period can be defined as the time required to discharge the access line to an intermediate voltage level Vint2, which can be expressed as a target percentage (e.g., 101%) of the discharge voltage level Vdis. This time period can be governed by the RC characteristics of the access line.

[0080] t FALL =Rwl*Cwl*ln[(Vtarget-Vdis) / (Vint2-Vdis)] (Equation 6)

[0081] t FALL The value of t can depend on the RC characteristics of the access line and the target voltage level of the programming pulse. FALL The base value, for example, t FALL(init) This can be based on specific resistances (e.g., Rdes) and specific capacitances (e.g., Cdes) of the access line and the initial target voltage level Vtarget_init_pulse. Therefore, the t of the Nth programming pulse... FALL The value of t, for example FALL(Nth) , can be expressed as t FALL(Nth) =Q FALL(Nth) *t FALL(init) *C RC Q FALL(Nth) It can be mainly determined by the multiplier relative to the target voltage level, and C RC It can be mainly determined by the multiplier of the relative RC characteristics.

[0082] Multiplier Q FALL(Nth) This can be described by Equation 7:

[0083] Q FALL(Nth) =(ln[(Vtarget_Nth_pulse-V RISE_Nth_pulse ) / (Vtarget_Nth_pulse-Vint1_Nth_pulse)]) / (ln[(Vtarget_init_pulse-V RISE_init_pulse ) / (Vtarget_init_pulse-Vint1_init_pulse)]) (Equation 7)

[0084] Multiplier CRC It can be described as the ratio of the RC characteristics of the access line (e.g., Rwl*Cwl) to a specific RC characteristic (e.g., Rdes*Cdes).

[0085] Figure 5 A graph depicting the resistance values ​​that can occur for the N+1 access lines of a memory cell block. This graph can be determined in response to the determination of resistance characteristics that can be determined experimentally, empirically, or by simulation in a known manner. See, for example, U.S. Patent Application No. 16 / 877,710 entitled “Apparatus and Methods for Determination of Capacitative and Resistive Characteristics of Access Lines”, issued to Dan Xu et al., and U.S. Provisional Patent Application No. 62 / 954,057 entitled “Memory Array Structures and Methods for Determination of Resistive Characteristics of Access Lines”, issued to Dan Xu et al. The characterization of a memory cell block can be considered to represent other memory cell blocks in the same or different memories. For example, the resistance value of an access line of a memory cell block at a specific location within that memory cell block can be considered as the resistance value of an access line of one or more other memory cell blocks in the same or different memory blocks at the same location within their respective memory cell blocks. Similarly, the resistance value of an access line of a memory cell block at a specific location within that memory cell block can be considered as the resistance value of other access lines (e.g., a consecutive subset of access lines containing the access line at the specific location) at different locations within that memory cell block.

[0086] Line 550 may represent the resistance value of an access line that varies with the access line's location, where access line 0 is at one end of a series-connected string of memory cells and access line N is at the other end. It has been found that the resistance value of an access line closer to the common source end of the series-connected string of memory cells is generally lower than the resistance value of an access line closer to the data line end of the series-connected string of memory cells. The resistance value of an access line may belong to one of several ranges 552 of resistance values, for example, ranges 5520 to 5522. Each range 552 may have a representative resistance value. Each representative resistance value may be the lower limit (e.g., lowest) value of its corresponding resistance value range 552, the upper limit (e.g., highest) value of its corresponding resistance value range 552, the average value of its corresponding resistance value range 552, or some other value from the lower limit to the upper limit of its corresponding resistance value range 552. As used herein, the average value will refer to any measure of the central tendency of the dataset, such as the mean, median, and / or pattern of the dataset. In some embodiments, the resistance value of the access line used in the aforementioned timing parameter equations can be considered equal to the representative resistance value of the range 552 in which the plotted resistance value of the access line resides. However, when individual resistance values ​​are determined, individual resistance values ​​can be used instead. A specific resistance value Rdes can be considered equal to the representative resistance value of the lowest range 5520.

[0087] Point 554 can represent the transition between range 5520 and range 5521, and point 556 can represent the transition between range 5521 and range 5522. For example, the groups of access lines 0 to α can each have resistance values ​​within range 5520, the groups of access lines α+1 to β can each have resistance values ​​within range 5521, and the groups of access lines β+1 to N can each have resistance values ​​within range 5522. Fewer or additional ranges 552 of resistance values ​​can be used. The representative resistance value of each of the ranges 552 can be used to determine the desired timing parameters for each access line in its corresponding access line group.

[0088] In some embodiments, the representative capacitance value of an access line can be considered to be the same for each access line in a memory cell block, and the representative capacitance value can be determined experimentally, empirically, or through simulation. In other embodiments, the representative capacitance value for each access line or subset of access lines can be determined in a manner similar to that of a representative resistance value.

[0089] Various embodiments allow for adjustment of timing parameters so that access lines closer to one end of the NAND string (e.g., due to typically lower resistance characteristics) can have shorter timing characteristics than access lines closer to the other end of the NAND string (e.g., due to typically higher resistance characteristics). Each access line within the resistance value range of 552 can utilize the same timing parameters, e.g., t RISE t FLAT and / or tFALL The same value.

[0090] It should be noted that in t FLAT If the value is insufficient to allow the distal end of the access line to reach its target voltage level sufficiently quickly for a given programming pulse, it is expected that memory cells at the proximal end of the access line will be programmed at a faster rate than memory cells at the distal end of the access line. In this case, for any given programming pulse, there may be more memory cells at the distal end of the access line that fail the verification operation than those at the proximal end, for example, failing to reach the threshold voltage level corresponding to the desired data state after the programming pulse.

[0091] Data randomization techniques are typically used during the programming of memory cells. Data randomization transforms raw data into encoded data during programming operations, storing it in a pattern different from the original data, and reverts the encoded data back to the original data during read operations. Generally, a function can be used to encode the raw data, and the inverse function can be used to decode the encoded data to recover the original data. Although this technique is broadly referred to as a data randomizer, it should be recognized that the data is not truly randomized mathematically. In practice, randomization as used herein refers to the reversible redistribution of data values. Data randomization is often used to mitigate the coupling effects of potentially interfering established data states between closely adjacent memory cells. With a sufficient sample size, such as 128 memory cells in a TLC memory cell, data randomization can roughly represent an equal number of every possible data state within each sample. Therefore, information about verification failures can be used to determine whether t should be increased (e.g., further increased) for subsequent programming pulses or for the same programming pulse in subsequent programming operations. FLAT The value of t. FLAT The adjustment of the value can also notify the timing parameter t. FALL and optional t RISE The decisions that need to be adjusted.

[0092] Figure 6A A number of groups 660 (e.g., groups 6600 to 660) of memory cells X This represents a block of memory cells connected to a driver 661 (e.g., a voltage generation system) for providing an applied voltage level to each of the memory cells in a block of memory cells connected to a group 660. Each block of memory cells 660 may represent a logical page of memory cells selected for access lines from the end of the access line closest to the driver 661 (e.g., the proximal end) (e.g., corresponding to block 6600 of memory cells) to the end of the access line furthest from the driver 661 (e.g., the distal end) (e.g., corresponding to block 660 of memory cells).X A subset of memory cells for sensing (e.g., verification) operations. Each group 660 of memory cells may contain the same number of memory cells, or may contain a different number of memory cells. The number of groups 660 of memory cells may be two or more. While a number of groups 660 of memory cells as few as two can provide information about whether memory cells at the distal end of the access line are programmed at a rate similar to that of memory cells at the proximal end of the access line, a higher number of groups 660 of memory cells can provide additional information about the amount of adjustment required to obtain the desired result.

[0093] Figure 6B Conceptually, this describes the number of memory cells (e.g., the number of fail bits) that fail the verification operation for each group 660 of memory cells, where a target voltage level is not applied long enough to effectively program the memory cells at the distal end of the access line to the same (e.g., similar) degree as those at the proximal end of the access line. The number of fail bits can be expressed as an integer value, such as the number of memory cells in the group that failed the verification operation, or it can be expressed as a ratio, such as a fraction or percentage, to the total number of memory cells in the group. When the groups 660 of memory cells each contain the same number of memory cells, the number of fail bits can be expressed as an integer value or as a ratio. When the groups 660 of memory cells each contain different numbers of memory cells, expressing it as a ratio provides more meaningful information.

[0094] exist Figure 6B In this diagram, trace 662 can represent a curve showing the number of failed bits, while line 664 can represent a threshold. For example, the threshold can be a number of failed bits greater than the number of failed bits in the group 6600 of memory cells. Adjustment can be indicated if the group 660 of memory cells has a number of failed bits higher than the threshold 664. The value of threshold 664 can be selected to be greater than the number of failed bits in the group 6600 of memory cells to reduce the risk of unauthorized adjustments due to normal statistical variations. It should be noted that the expected number of failed bits can change during programming operations and can be expected to decrease as programming pulses with increasing voltage levels are applied and more memory cells reach their desired data state. Therefore, for each verification operation, a change in the value of threshold 664 can also be expected. For example, threshold 664 can have a value 10% higher than the number of failed bits in the group 6600 of memory cells. However, the relative difference between the number of fault bits in group 6600 of memory cells and the number of fault bits in group 660 of memory cells further away from driver 661 can still be a useful guide for determining whether to adjust this timing parameter.

[0095] Figure 7 A flowchart depicts a method for operating a memory according to an embodiment, for example, during several programming operations. The method may be in the form of computer-readable instructions, for example, stored in instruction register 128. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause the memory (e.g., associated components of the memory) to perform the method.

[0096] At point 701, a corresponding programming pulse having a first target voltage level and a first pulse width can be applied to each access line in a first subset of multiple access lines. For example, the memory cells of a serially connected string of memory cells are typically programmed sequentially from one end of the string (e.g., one end selectively connected to a common source) to the other end of the string (e.g., one end selectively connected to a data line). Thus, the corresponding programming pulse having the first target voltage level and the first pulse width can each represent a programming pulse on a corresponding access line of the first subset of access lines for multiple programming operations, e.g., the Xth programming pulse, each programming operation for programming a corresponding memory cell of one or more serially connected strings of memory cells. Each of the multiple programming operations can have Y (e.g., a maximum value Y) programming pulses, where X is an integer value greater than or equal to one, and Y is an integer value greater than X.

[0097] The pulse width can represent the time length from the application of the programming pulse to the access line to the start of the discharge of the programming pulse, for example, t. RISE +t FLAT The first subset of access lines can represent a contiguous grouping of two or more access lines. For example, in the case of multiple access lines containing N+1 access lines, such as in... Figure 5 In this context, the first subset of access lines may include access lines 2020 to 202... α For each access line, α is greater than zero and less than N.

[0098] At 703, a corresponding programming pulse having a first target voltage level and a second pulse width longer than the first pulse width can be applied to each access line in a second subset of multiple access lines. The corresponding programming pulse having the first target voltage level and the second pulse width can each represent a programming pulse on a corresponding access line in the second subset of multiple programming operations, for example, the Xth programming pulse.

[0099] The second subset of access lines can represent a consecutive grouping of two or more access lines. Continuing with the previous example, the second subset of access lines can include access lines 202. α+1 Access Line 202 β For each access line, β is less than N.

[0100] The aforementioned process can be repeated for one or more additional consecutive groups of access lines. For example, at 705, a corresponding programming pulse having a first target voltage level and a third pulse width longer than the second pulse width can be applied to each access line in a third subset of multiple access lines. The corresponding programming pulse having the first target voltage level and the third pulse width can each represent a programming pulse on a corresponding access line in the third subset of multiple programming operations, for example, the Xth programming pulse.

[0101] The third access line subset can represent a consecutive grouping of two or more access lines. Continuing with the previous example, the third access line subset can include access lines 202. β+1 Access Line 202 N Each access line. Although reference Figure 7 The three subsets of access lines are described, but fewer or more subsets of access lines corresponding to other mutually exclusive ranges of resistance values ​​may be used. In the case of additional subsets of access lines, the union of the first, second, and third subsets of access lines may contain all access lines less than a memory cell block.

[0102] Figure 7 The method can be repeated for additional programming pulses for the corresponding programming operation on each of the multiple access lines. The pulse width of each programming pulse applied to the second subset of access lines may be longer than the pulse width of each corresponding programming pulse applied to the first subset of access lines (e.g., having the same target voltage level), the pulse width of each programming pulse applied to the third subset of access lines may be longer than the pulse width of each corresponding programming pulse applied to the second subset of access lines (e.g., having the same target voltage level), and so on.

[0103] As previously described, various pulse widths can depend on the target voltage level and resistance characteristics of a subset of access lines. As an example, timing parameters corresponding to the pulse width can be selected from a lookup table. Table 1 is an example of a lookup table that can be used with the embodiments. Table 1 depicts only two target voltage levels, such as V1, which can be the target voltage level of the initial programming pulse of the programming operation, and V2, which can be the target voltage level of subsequent (e.g., higher) programming pulses of the programming operation. Although Table 1 depicts only two target voltage levels, additional (e.g., consecutively higher) target voltage levels can be added using the same bootstrap. Additionally, when the RC characteristics of the first subset of memory cells are equal to a specific RC characteristic (e.g., Rdes*Cdes), the multiplier B... RC(First) It can be equal to one.

[0104] Table 1

[0105]

[0106] For referenceFigure 7 The described timing parameter assignment for each target voltage level of the programming operation and for consecutive subsets of memory cells simplifies the control scheme for adjusting timing parameters in response to the RC characteristics of different access lines.

[0107] Figure 8 A flowchart depicts a method for operating a memory according to an embodiment, for example, during one or more programming operations. The method may be in the form of computer-readable instructions, for example, stored in instruction register 128. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause the memory (e.g., an associated component of the memory) to perform the method.

[0108] At 811, a specific programming pulse from a plurality of programming pulses, each having a corresponding target voltage level and a corresponding desired pulse width, can be applied to an access line connected to each of the plurality of memory cells selected for programming operations.

[0109] At 813, for example, after applying a specific programming pulse having its corresponding target voltage level and corresponding pulse width, for each of the multiple memory cell groups of multiple memory cells, the number of memory cells that failed the verification operation due to the programming operation can be determined. The number of memory cells that failed the verification operation can be expressed as an integer value or as a ratio. Each group of memory cells can have the same number of memory cells. Alternatively, the groups of memory cells can contain different numbers of memory cells. For some embodiments, the multiple groups of memory cells can include each of the multiple memory cells. For other embodiments, the multiple groups of memory cells can contain fewer than all of the multiple memory cells. For example, the number of memory cells that failed the verification operation can be determined only for the group of memory cells closest to the driver to which the specific programming pulse was applied to the access line and the group of memory cells furthest from the driver to which the specific programming pulse was applied to the access line. Reference Figure 6A This may include a group of memory cells 6600 and a group of memory cells 660. X .

[0110] At 815, in response to the number of failed memory cells in any of the multiple memory cell groups exceeding a threshold determined in response to the number of failed memory cells (e.g., failed bits) in a particular memory cell group, the desired pulse width of subsequent programming pulses in the multiple programming pulses can be adjusted (e.g., increased). This increase may include increasing the timing parameter t for subsequent programming pulses. RISE and t FLAT One or more of them. In some embodiments, this increase may be included without increasing the timing parameter t.RISE In this case, add the timing parameter t for subsequent programming pulses. FLAT .

[0111] Optionally, at 817, in response to the number of failed memory cells in any memory cell group exceeding a threshold, the desired pulse width of the specific programming pulse to be applied to the access line for subsequent programming operations can be adjusted, either additionally or in an alternative.

[0112] Although the timing parameter t FLAT This may not have the intended effect on the rate of the programmable memory cell, but adding an indication of the pulse width can further indicate the timing parameter t. FLAT This also ensures that an increase is made to provide sufficient time for the access line to discharge.

[0113] It should be noted that Figure 8 The method can be with Figure 7 These methods are used in combination. For example, in Figure 8 In the method indicating timing adjustments, adjustments can be made for subsequent programming pulses on those access lines or for subsequent programming operations on those access lines to determine the timing for any one of multiple access lines. Figure 7 The method involves a lookup table or calculation of the pulse width.

[0114] in conclusion

[0115] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that any arrangement is expected to achieve the same purpose in lieu of the specific embodiments shown. Many adaptations to the embodiments will be apparent to those skilled in the art. Therefore, this application is intended to cover any adaptations or variations of the embodiments.

Claims

1. A memory, comprising: an array of memory cells including a plurality of strings of series-connected memory cells; a plurality of access lines, wherein each access line of the plurality of access lines is connected to a respective plurality of memory cells in the array of memory cells; and a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to: apply, during programming of the respective plurality of memory cells of each access line of the plurality of access lines, a respective program pulse having a first target voltage level and a first pulse width to each access line of a first subset of access lines of the plurality of access lines, wherein each access line of the first subset of access lines is connected to a respective memory cell of a string of series-connected memory cells of the plurality of strings of series-connected memory cells; and apply, during the programming of the respective plurality of memory cells of each access line of the plurality of access lines, a respective program pulse having the first target voltage level and a second pulse width that is longer than the first pulse width to each access line of a second subset of access lines of the plurality of access lines, wherein each access line of the second subset of access lines is connected to a respective memory cell of the string of series-connected memory cells, and wherein each access line of the first subset of access lines is closer to a particular end of the string of series-connected memory cells than each access line of the second subset of access lines.

2. The memory of claim 1, wherein the first pulse width and the second pulse width each correspond to a respective first timing parameter t RISE and a respective second timing parameter t FLAT , and wherein the respective second timing parameter t FLAT of the second pulse width is greater than the respective second timing parameter t FLAT of the first pulse width.

3. The memory of claim 2, wherein the respective first timing parameter t RISE of the second pulse width equals the respective first timing parameter t RISE of the first pulse width.

4. The memory of claim 1, wherein the particular end of the string of series-connected memory cells is an end of the string of series-connected memory cells that is selectively connected to a common source of the plurality of strings of series-connected memory cells.

5. The memory of claim 1, wherein the respective program pulse for each access line of the plurality of access lines is a respective first program pulse for a respective program operation of its respective access line, and wherein the controller is further configured to cause the memory to: apply, during the programming of the respective plurality of memory cells of each access line of the plurality of access lines, a respective second program pulse having a second target voltage level that is higher than the first target voltage level and a third pulse width that is longer than the first pulse width to each access line of the first subset of access lines of the plurality of access lines; and apply, during the programming of the respective plurality of memory cells of each access line of the plurality of access lines, a respective second program pulse having the second target voltage level and a fourth pulse width that is longer than the third pulse width and longer than the second pulse width to each access line of the second subset of access lines of the plurality of access lines.

6. A memory, comprising: an array of memory cells including a plurality of strings of series-connected memory cells; a plurality of access lines, wherein each access line of the plurality of access lines is connected to a respective plurality of memory cells in the array of memory cells; and a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to: apply, during programming of the respective plurality of memory cells of each access line of the plurality of access lines, a respective program pulse having a first target voltage level and a first pulse width to each access line of a first subset of access lines of the plurality of access lines, wherein each access line of the first subset of access lines is connected to a respective memory cell of a string of series-connected memory cells of the plurality of strings of series-connected memory cells; and apply, during the programming of the respective plurality of memory cells of each access line of the plurality of access lines, a respective program pulse having the first target voltage level and a second pulse width that is longer than the first pulse width to each access line of a second subset of access lines of the plurality of access lines, wherein each access line of the second subset of access lines is connected to a respective memory cell of the string of series-connected memory cells, and wherein each access line of the first subset of access lines is closer to a particular end of the string of series-connected memory cells than each access line of the second subset of access lines. a controller for accesses of the memory cell array, wherein the controller is configured to cause the memory to: apply a respective program pulse having a first target voltage level and a first pulse width to each access line in a first subset of the plurality of access lines, wherein each access line in the first subset of access lines is connected to a respective memory cell of a series-connected string of memory cells in the plurality of series-connected strings of memory cells; apply a respective program pulse having the first target voltage level and a second pulse width that is longer than the first pulse width to each access line in a second subset of the plurality of access lines, wherein each access line in the second subset of access lines is connected to a respective memory cell of the series-connected string of memory cells, and wherein each access line in the first subset of access lines is closer to a particular end of the series-connected string of memory cells than each access line in the second subset of access lines; and apply a respective program pulse having the first target voltage level and a third pulse width that is longer than the second pulse width to each access line in a third subset of the plurality of access lines, wherein each access line in the third subset of access lines is connected to a respective memory cell of the series-connected string of memory cells, and wherein each access line in the second subset of access lines is closer to the particular end of the series-connected string of memory cells than each access line in the third subset of access lines.

7. The memory of claim 6, wherein a union of the first subset of access lines, the second subset of access lines, and the third subset of access lines contains each access line in the plurality of access lines.

8. The memory of claim 6, wherein the controller is further configured to cause the memory to apply a respective program pulse having the first target voltage level and a fourth pulse width that is longer than the third pulse width to each access line in a fourth subset of the plurality of access lines, wherein each access line in the fourth subset of access lines is connected to a respective memory cell of the series-connected string of memory cells, and wherein each access line in the third subset of access lines is closer to the particular end of the series-connected string of memory cells than each access line in the fourth subset of access lines.

9. The memory of claim 8, wherein the first pulse width, the second pulse width, the third pulse width, and the fourth pulse width each correspond to a respective first timing parameter t RISE and a respective second timing parameter t FLAT , and wherein the respective second timing parameter t FLAT of the second pulse width is greater than the respective second timing parameter t FLAT of the first pulse width, the respective second timing parameter t FLAT of the third pulse width is greater than the respective second timing parameter t FLAT of the second pulse width, and the respective second timing parameter t FLAT of the fourth pulse width is greater than the respective second timing parameter t FLAT of the third pulse width.

10. The memory of claim 6, wherein the first pulse width, the second pulse width, and the third pulse width each correspond to a respective first timing parameter t RISE and a respective second timing parameter t FLAT , and wherein the respective second timing parameter t FLAT of the second pulse width is greater than the respective second timing parameter t FLAT of the first pulse width, and the respective second timing parameter t FLAT of the third pulse width is greater than the respective second timing parameter t FLAT of the second pulse width.

11. The memory of claim 10, wherein the respective first timing parameter t RISE of the first pulse width is equal to the respective first timing parameter t RISE of the second pulse width and is equal to the respective first timing parameter t RISE of the third pulse width.

12. The memory of claim 6, wherein the particular end of the series-connected string of memory cells is an end of the series-connected string of memory cells that is selectively connected to a common source of the plurality of series-connected strings of memory cells.

13. A memory, comprising: a memory cell array comprising a plurality of series-connected strings of memory cells; a plurality of access lines, wherein each access line in the plurality of access lines is connected to a respective plurality of memory cells in the memory cell array; and a controller for accesses of the memory cell array, wherein the controller is configured to cause the memory to: apply a respective program pulse having a first target voltage level and a first pulse width to each access line in a first subset of the plurality of access lines, wherein each access line in the first subset of access lines is connected to a respective memory cell of a series-connected string of memory cells in the plurality of series-connected strings of memory cells; apply a respective program pulse having the first target voltage level and a second pulse width that is longer than the first pulse width to each access line in a second subset of the plurality of access lines, wherein each access line in the second subset of access lines is connected to a respective memory cell of the series-connected string of memory cells, and wherein each access line in the first subset of access lines is closer to a particular end of the series-connected string of memory cells than each access line in the second subset of access lines; and apply a respective program pulse having the first target voltage level and a third pulse width that is longer than the second pulse width to each access line in a third subset of the plurality of access lines, wherein each access line in the third subset of access lines is connected to a respective memory cell of the series-connected string of memory cells, and wherein each access line in the second subset of access lines is closer to the particular end of the series-connected string of memory cells than each access line in the third subset of access lines. during the programming of the respective plurality of memory cells of each of the plurality of access lines, a respective first program pulse having a first target voltage level and a first pulse width is applied to each of a first subset of access lines of the plurality of access lines, wherein each of the first subset of access lines is connected to a respective memory cell of a series-connected string of memory cells of the plurality of series-connected strings of memory cells, and wherein the respective first program pulse for each of the first subset of access lines is a particular program pulse of a respective plurality of program pulses of a respective program operation on the access line of the first subset of access lines; for an access line of the first subset of access lines: after applying the respective first program pulse to the access line, a first number of memory cells of a particular memory cell grouping of the respective plurality of memory cells of the access line that fail a verify operation is determined; after applying the respective first program pulse to the access line, a second number of memory cells of a different memory cell grouping of the respective plurality of memory cells of the access line that fail the verify operation is determined; in response to the first number of memory cells, a first threshold greater than or equal to the first number of memory cells is determined; and in response to the second number of memory cells exceeding the first threshold, a pulse width of a respective second program pulse of the respective plurality of program pulses to be applied to each of the first subset of access lines for their respective program operations is adjusted; during the programming of the respective plurality of memory cells of each of the plurality of access lines, a respective first program pulse having the first target voltage level and a second pulse width longer than the first pulse width is applied to each of a second subset of access lines of the plurality of access lines, wherein each of the second subset of access lines is connected to a respective memory cell of the series-connected string of memory cells, wherein each of the first subset of access lines is closer to a particular end of the series-connected string of memory cells than each of the second subset of access lines, and wherein the respective first program pulse for each of the second subset of access lines is a particular program pulse of a respective plurality of program pulses of a respective program operation on the access line of the second subset of access lines; and for an access line of the second subset of access lines: after applying the respective first program pulse to the access line, a third number of memory cells of a particular memory cell grouping of the respective plurality of memory cells of the access line that fail a verify operation is determined; after applying the respective first program pulse to the access line, a fourth number of memory cells of a different memory cell grouping of the respective plurality of memory cells of the access line that fail the verify operation is determined; in response to the third number of memory cells, a second threshold greater than or equal to the third number of memory cells is determined; and in response to the fourth number of memory cells exceeding the second threshold, a pulse width of a respective second program pulse of the respective plurality of program pulses to be applied to each of the second subset of access lines for their respective program operations is adjusted; adjusting a pulse width of a respective second programming pulse of a respective plurality of programming pulses to be applied to each access line in the second subset of access lines for its respective programming operation.

14. The memory of claim 13, wherein, for each access line in the first subset of access lines and the second subset of access lines, the particular programming pulse of the respective plurality of programming pulses of the respective programming operation on the access line is a programming pulse of the respective plurality of programming pulses of the access line other than an initial programming pulse of the respective plurality of programming pulses of the access line.

15. The memory of claim 14, wherein, for each access line in the first subset of access lines and the second subset of access lines, the second programming pulse of the respective plurality of programming pulses is a programming pulse of the respective plurality of programming pulses of the access line immediately following the first programming pulse of the respective plurality of programming pulses of the access line.

16. The memory of claim 13, wherein the controller configured to adjust a pulse width of a respective second programming pulse of a respective plurality of programming pulses to be applied to an access line comprises the controller configured to adjust a respective pulse width of each programming pulse of the respective plurality of programming pulses following the first programming pulse of the respective plurality of programming pulses.

17. A memory comprising: a plurality of data lines; a common source; an array of memory cells comprising a plurality of strings of serially connected memory cells, wherein each string of the plurality of strings of serially connected memory cells has a respective first end selectively connected to the common source and a respective second end selectively connected to a respective data line of the plurality of data lines; a plurality of access lines, wherein each access line of the plurality of access lines is connected to a respective plurality of memory cells of a respective string of the plurality of strings of serially connected memory cells in the array of memory cells; and a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to: apply a respective programming pulse having a first target voltage level and a first pulse width to each access line in a first subset of access lines of the plurality of access lines, wherein each access line in the first subset of access lines is connected to a respective memory cell of a string of serially connected memory cells in the plurality of strings of serially connected memory cells; and apply a respective programming pulse having the first target voltage level and a second pulse width longer than the first pulse width to each access line in a second subset of access lines of the plurality of access lines, wherein each access line in the second subset of access lines is connected to the respective memory cell of the string of serially connected memory cells, and wherein each access line in the first subset of access lines is closer to the respective first end of each string of serially connected memory cells than each access line in the second subset of access lines.

18. The memory of claim 17, wherein each respective program pulse for each access line of the first subset of access lines is a respective first program pulse for each access line of the first subset of access lines, wherein the respective first program pulse for each access line of the first subset of access lines is an Xth program pulse of a respective plurality of program pulses for a respective program operation on the access line of the first subset of access lines, wherein each respective program pulse for each access line of the second subset of access lines is a respective first program pulse for each access line of the second subset of access lines, wherein the respective first program pulse for each access line of the second subset of access lines is an Xth program pulse of a respective plurality of program pulses for a respective program operation on the access line of the second subset of access lines, and wherein X is an integer value greater than or equal to one.

19. The memory of claim 18, wherein the controller is further configured to cause the memory to, during programming of the respective plurality of memory cells of each access line of the plurality of access lines in a direction from the common source to the data lines: for an access line of the first subset of access lines: determine, after applying the respective first program pulse to the access line, a first number of memory cells of a particular memory cell group of the respective plurality of memory cells of the access line that fail a verify operation; determine, after applying the respective first program pulse to the access line, a second number of memory cells of a different memory cell group of the respective plurality of memory cells of the access line that fail the verify operation; determine, in response to the first number of memory cells, a first threshold value that is greater than or equal to the first number of memory cells; and in response to the second number of memory cells exceeding the first threshold value, increase a pulse width of a respective X+1th program pulse of the respective plurality of program pulses to be applied to each access line of the first subset of access lines for its respective program operation.

20. The memory of claim 19, wherein the controller is further configured to cause the memory to, during programming of the respective plurality of memory cells of each access line of the plurality of access lines in a direction from the common source to the data lines: for an access line of the second subset of access lines: determine, after applying the respective first program pulse to the access line, a third number of memory cells of a particular memory cell group of the respective plurality of memory cells of the access line that fail a verify operation; determine, after applying the respective first program pulse to the access line, a fourth number of memory cells of a different memory cell group of the respective plurality of memory cells of the access line that fail the verify operation; determine, in response to the third number of memory cells, a second threshold value that is greater than or equal to the third number of memory cells; and in response to the fourth number of memory cells exceeding the second threshold value, increase a pulse width of a respective X+1th program pulse of the respective plurality of program pulses to be applied to each access line of the second subset of access lines for its respective program operation. in response to the fourth number of memory cells exceeding the second threshold, increasing a pulse width of a respective X+1th programming pulse of a respective plurality of programming pulses to be applied to each access line in the second subset of access lines for its respective programming operation.

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