Method of manufacturing a semiconductor device

Abstract

The present invention discloses a method for manufacturing a semiconductor device, comprising the following steps: Step S1, performing the processes before the opening etching of the contact hole, and the formed device structure includes: a gate structure formed on the surface of a semiconductor substrate; an oxide layer formed covering the source region, the drain region, and the gate structure, and a patterned first hard mask layer is formed on the oxide layer; a TEOS oxide layer is formed under the oxide layer; Step S2, lithographically defining the formation region of the contact hole; Step S3, using an ion implantation process to form a doped layer on the surface of the embedded epitaxial layer in the bottom region of the opening. The present invention solves the loss of the epitaxial layer caused by the etching process, increases the volume and the top doping concentration of the embedded epitaxial layer, thereby improving the source-drain contact resistance and the channel conduction resistance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a method for manufacturing a semiconductor device. Background Art

[0002] Metal silicide plays a very important role in the integrated circuit manufacturing technology. Metal silicide is mainly applied to the contact between the source / drain electrodes and the metal of the silicon gate electrode. Among them, the self-aligned silicide process has become one of the key manufacturing processes for recent ultra-high-speed CMOS logic large-scale integrated circuits. This process reduces the sheet resistance of the source / drain electrodes and the gate electrode, reduces the contact resistance, and shortens the resistance-capacitance delay (RC delay) related to the gate. With the continuous development of semiconductor device technology. In order to meet the continuously shrinking line width dimensions, the metal silicide process is also constantly improving.

[0003] In the existing manufacturing method of semiconductor device salicide, the following steps are included:

[0004] Step 1, source / drain ion implantation.

[0005] Step 2, complete the replacement gate process, and form an embedded epitaxial layer in the semiconductor substrate on both sides of the gate structure.

[0006] Step 3, photolithographically define the formation region of the contact hole, and etch the interlayer film to form an opening of the contact hole passing through the interlayer film; the contact hole includes contact holes located on the top of the source region, the drain region, and the gate structure. The opening exposes the embedded epitaxial layer at the bottom.

[0007] Step 4, fill a metal layer in the opening to form each contact hole.

[0008] Subsequently, the subsequent back-end process (BEOL) is carried out.

[0009] However, the etching process of the opening will cause loss to the embedded epitaxial layer, which will reduce the volume and top doping concentration of the embedded epitaxial layer, and reduce the source / drain contact resistance and channel conduction resistance of the device. Summary of the Invention

[0010] The technical problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device, which solves the loss caused to the epitaxial layer by the etching process, improves the volume and top doping concentration of the embedded epitaxial layer, and thus improves the source / drain contact resistance and channel conduction resistance of the device.

[0011] In order to solve the above technical problem, the invention provides a method for manufacturing a semiconductor device, including the following steps:

[0012] Step S1, complete the processes before the opening etching of the contact hole, and the formed device structure includes:

[0013] A gate structure formed on the surface of the semiconductor substrate;

[0014] Embedded epitaxial layers are formed in the semiconductor substrate on both sides of the gate structure; active regions and drain regions are formed in the embedded epitaxial layers;

[0015] An oxide layer is formed covering the source region, drain region and the gate structure, and a patterned first hard mask layer is formed on the oxide layer; a TEOS oxide layer is formed under the oxide layer;

[0016] Step S2, lithographically define the formation region of the contact hole, and etch the first hard mask layer to form an opening of the contact hole passing through the oxide layer and the TEOS oxide layer; the opening exposes the bottom embedded epitaxial layer;

[0017] Step S3, use an ion implantation process to form a doped layer on the surface of the embedded epitaxial layer in the bottom region of the opening, a channel region is formed in the semiconductor substrate between the embedded epitaxial layers, the embedded silicon epitaxial layer generates tensile stress on the channel region, and the doped layer increases the tensile stress on the channel region.

[0018] Preferably, it further includes:

[0019] Step S4, fill a metal layer in the top region of the opening; the metal layer is stacked on the doped layer;

[0020] The metal layer and the doped layer form a Schottky contact, and the doped layer reduces the depletion layer width in the Schottky contact, thereby reducing the barrier height of the Schottky contact and thus reducing the contact resistance.

[0021] Preferably, the ions implanted in step S3 are P ions or B ions.

[0022] Preferably, the first hard mask layer is an NCA layer, an SHB layer and a PR layer.

[0023] Preferably, a second hard mask layer is further formed above the TEOS oxide layer, the second hard mask layer is TiN, and SiN is further formed on the second hard mask layer TiN.

[0024] Preferably, the metal layer includes a TiN and Ti stack layer and a tungsten layer, and the method for filling the metal layer is:

[0025] Form a TiN and Ti stack layer on the bottom surface and side surfaces of the top region in the opening;

[0026] The tungsten layer completely fills the top region in the first opening formed with the TiN and Ti stacked layers.

[0027] Preferably, the semiconductor device is a fin transistor, and the gate structure covers the top surface and side surfaces of the fin body at a partial length;

[0028] The embedded epitaxial layer is formed in the fin body on both sides of the gate structure.

[0029] Preferably, the gate structure includes:

[0030] A stacked gate dielectric layer and a gate conductive material layer;

[0031] The material of the gate dielectric layer is a gate oxide layer; alternatively, the material of the gate dielectric layer includes a high-k material;

[0032] The gate conductive material layer is a polysilicon gate;

[0033] Alternatively, the gate conductive material layer is a metal gate, a dummy gate structure is adopted during the formation of the metal gate, the embedded epitaxial layer, the source region, and the drain region are self-aligned and formed on both sides of the dummy gate structure, and removing the dummy gate structure is further included after forming the first hard mask layer and before performing step two, and then forming the metal gate in the removal region of the dummy gate structure.

[0034] Preferably, the semiconductor device is a nanosheet transistor or a nanowire transistor. Description of the Drawings

[0035] Figure 1 It is a schematic flowchart of the method for manufacturing a semiconductor device according to the present invention.

[0036] Figure 2 It is a schematic diagram of the semiconductor device formed after step S1 of the method for manufacturing a semiconductor device according to the present invention;

[0037] Figures 3 - 4 It is a schematic diagram of the semiconductor device formed after step S2 of the method for manufacturing a semiconductor device according to the present invention;

[0038] Figure 5 It is a schematic diagram of the semiconductor device formed after step S3 of the method for manufacturing a semiconductor device according to the present invention;

[0039] Figure 6 It is a schematic diagram of the semiconductor device formed after step S4 of the method for manufacturing a semiconductor device according to the present invention.

[0040] Description of the Reference Numerals

[0041] 10 Gate structure 11 Embedded epitaxial layer

[0042] 20 Oxide layer 21 TEOS oxide layer

[0043] 22 Opening 24 Doped layer

[0044] 30 First hard mask layer 31 NCA layer

[0045] 32 SHB layer 33 PR layer

[0046] 40 Metal layer 41 Stacked layer of TiN and Ti

[0047] 42 Tungsten layer 51 Second hard mask layer

[0048] 52 SiN layer Detailed implementation manners

[0049] The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in conjunction with illustrative embodiments. It should be noted that similar reference numerals represent similar structures. The terms "first", "second", "upper", "lower", etc. used in this application can be used to modify various device structures or manufacturing processes. Unless otherwise specified, these modifications do not imply a spatial, sequential, or hierarchical relationship of the modified device structures or manufacturing processes.

[0050] As Figures 1 - 6 shown, a method for manufacturing a semiconductor device according to the present invention includes the following steps:

[0051] Step S1, completing the process before the opening etching of the contact hole, and the formed device structure includes:

[0052] A gate structure 10 formed on the surface of the semiconductor substrate;

[0053] Embedded epitaxial layers 11 are formed in the semiconductor substrate on both sides of the gate structure 10; active regions and drain regions are formed in the embedded epitaxial layers;

[0054] An oxide layer 20 is formed covering the source region, the drain region, and the gate structure 10, and a patterned first hard mask layer 30 is formed on the oxide layer; a TEOS oxide layer 21 is formed below the oxide layer;

[0055] Preferably, the first hard mask layer is an NCA layer 31, an SHB layer 32, and a PR layer 33.

[0056] In this embodiment, the semiconductor device is a fin transistor, and the gate structure covers the top surface and the side surface of a part of the length of the fin body;

[0057] The embedded epitaxial layer is formed in the fin bodies on both sides of the gate structure.

[0058] Preferably, the gate structure includes:

[0059] a gate dielectric layer and a gate conductive material layer formed by stacking;

[0060] the material of the gate dielectric layer is a gate oxide layer; or, the material of the gate dielectric layer includes a high-k material;

[0061] the gate conductive material layer is a polysilicon gate;

[0062] or, the gate conductive material layer is a metal gate, a dummy gate structure is adopted in the formation process of the metal gate, the embedded epitaxial layer, the source region and the drain region are self-aligned and formed on both sides of the dummy gate structure, and before forming the first hard mask layer and before performing step two, removing the dummy gate structure is further included, and then forming the metal gate in the removal region of the dummy gate structure.

[0063] Step S2, photolithographically define the formation region of the contact hole, etch the first hard mask layer to form an opening 22 of the contact hole passing through the oxide layer and the TEOS oxide layer 21; the opening exposes the embedded epitaxial layer 11 at the bottom.

[0064] Preferably, a second hard mask layer 51 is further formed above the TEOS oxide layer, the second hard mask layer is TiN, and a SiN layer 52 is further formed on the second hard mask layer TiN.

[0065] Step S3, use an ion implantation process to form a doped layer 24 on the surface of the embedded epitaxial layer in the bottom region of the opening, a channel region is formed in the semiconductor substrate between the embedded epitaxial layers, the embedded silicon epitaxial layer generates tensile stress on the channel region, and the doped layer increases the tensile stress on the channel region.

[0066] Preferably, the ions implanted in step S3 are P ions or B ions.

[0067] Step S4, fill a metal layer 40 in the top region of the opening 22; the metal layer 40 is stacked on the doped layer 24;

[0068] The metal layer 40 and the doped layer 24 form a Schottky contact, and the doped layer 24 reduces the depletion layer width in the Schottky contact, thereby reducing the barrier height of the Schottky contact and thus reducing the contact resistance.

[0069] Preferably, the metal layer includes a TiN and Ti stack layer 41 and a tungsten layer 42, and the method for filling the metal layer is:

[0070] A TiN and Ti stacked layer 41 is formed on the bottom surface and the side surface of the top region in the opening;

[0071] A tungsten layer 42 completely fills the top region in the first opening where the TiN and Ti stacked layer is formed.

[0072] Embodiment 2

[0073] Differing from Embodiment 1, the semiconductor device is a nanosheet transistor or a nanowire transistor.

[0074] Although the present invention has been described with reference to one or more exemplary embodiments, those skilled in the art will appreciate that various suitable changes and equivalent means can be made to the device structure without departing from the scope of the present invention. In addition, many modifications that may be suitable for a particular situation or material can be made from the disclosed teachings without departing from the scope of the present invention. Therefore, the object of the present invention is not to be limited to the specific embodiments disclosed as the best mode for carrying out the present invention, and the disclosed device structure and its manufacturing method will include all embodiments falling within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, It includes the following steps: Step S1, complete the processes before the opening etching of the contact hole, and the formed device structure includes: A gate structure formed on the surface of the semiconductor substrate; Embedded epitaxial layers are formed in the semiconductor substrate on both sides of the gate structure; active regions and drain regions are formed in the embedded epitaxial layers; An oxide layer is formed covering the source region, drain region and the gate structure, and a patterned first hard mask layer is formed on the oxide layer; a TEOS oxide layer is formed under the oxide layer; Step S2, lithographically define the formation region of the contact hole, etch the first hard mask layer to form the opening of the contact hole passing through the oxide layer and the TEOS oxide layer; the opening exposes the bottom embedded epitaxial layer; Step S3, use an ion implantation process to form a doped layer on the surface of the embedded epitaxial layer in the bottom region of the opening, a channel region is formed in the semiconductor substrate between the embedded epitaxial layers, the embedded silicon epitaxial layer generates tensile stress on the channel region, and the doped layer increases the tensile stress on the channel region.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, It further includes: Step S4, fill a metal layer in the top region of the opening; the metal layer is stacked on the doped layer; The metal layer and the doped layer form a Schottky contact, and the doped layer reduces the depletion layer width in the Schottky contact, thereby reducing the barrier height of the Schottky contact and thus reducing the contact resistance.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The ions implanted in step S3 are P ions or B ions.

4. The method for manufacturing a semiconductor device according to claim 1, wherein, The first hard mask layer is an NCA layer, an SHB layer and a PR layer.

5. The method for manufacturing a semiconductor device according to claim 1, wherein A second hard mask layer is further formed above the TEOS oxide layer, the second hard mask layer is TiN, and SiN is further formed on the second hard mask layer TiN.

6. The method for manufacturing a semiconductor device according to claim 1, wherein, The metal layer includes a TiN and Ti stack layer and a tungsten layer, and the method for filling the metal layer is: Form a TiN and Ti stack layer on the bottom surface and side surface of the top region in the opening; The tungsten layer completely fills the top region in the first opening where the TiN and Ti stack layer is formed.

7. The method for manufacturing a semiconductor device according to claim 1, wherein, The semiconductor device is a fin transistor, and the gate structure covers the top surface and side surface of a part of the fin body; The embedded epitaxial layer is formed in the fin bodies on both sides of the gate structure.

8. The method for manufacturing a semiconductor device according to claim 2, wherein, The gate structure includes: A stacked gate dielectric layer and a gate conductive material layer; The material of the gate dielectric layer is a gate oxide layer; or, the material of the gate dielectric layer includes a high-k material; The gate conductive material layer is a polysilicon gate; Or, the gate conductive material layer is a metal gate, and a pseudo-gate structure is adopted in the formation process of the metal gate. The embedded epitaxial layer, the source region and the drain region are self-aligned and formed on both sides of the pseudo-gate structure. Before forming the first hard mask layer and before performing step two, it further includes removing the pseudo-gate structure, and then forming the metal gate in the removal region of the pseudo-gate structure.

9. The method for manufacturing a semiconductor device according to claim 1, wherein, The semiconductor device is a nanosheet transistor or a nanowire transistor.

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