Semiconductor element and method for producing the same

Abstract

The present disclosure relates to a semiconductor device with an interposer and a method of manufacturing the same. The semiconductor device includes a substrate, a bottom conductive plug on the substrate, an interposer conductive layer on the bottom conductive plug, and a top conductive plug on the interposer conductive layer. A top surface of the interposer conductive layer is non-planar.

Description

TECHNICAL FIELD

[0001] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 004,902, filed August 27, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method of fabricating the same. In particular, the present disclosure relates to a semiconductor device having an interlayer and a method of fabricating the same. BACKGROUND

[0003] Semiconductor devices have been used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. The size of semiconductor devices continues to shrink to meet the demand for increasing computing power. However, various problems arise during the shrinking process, which continue to increase. Thus, there remain challenges in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The foregoing “background” description is for the purpose of generally presenting the context of the disclosure. The background description is not and should not be taken to be the acknowledgement that any of the foregoing “background” information necessarily forms a prior art of the present disclosure, and no admission is made that any of the foregoing “background” information was known both in the United States and in other jurisdictions prior to the filing date of the disclosure. The background section is intended to provide related art information only and is not intended to limit the scope of the disclosure. SUMMARY

[0005] One aspect of the present disclosure provides a semiconductor device, comprising: a substrate; a bottom conductive plug on the substrate; an interlayer conductive layer on the bottom conductive plug; and a top conductive plug on the interlayer conductive layer. A top surface of the interlayer conductive layer is non-planar.

[0006] In some embodiments, a bottom surface of the top conductive plug is complementary to the top surface of the interlayer conductive layer.

[0007] In some embodiments, the top surface of the interlayer conductive layer is convex, and the bottom surface of the top conductive plug is concave.

[0008] In some embodiments, the top surface of the interlayer conductive layer is concave, and the bottom surface of the top conductive plug is convex.

[0009] In some embodiments, a bottom surface of the interlayer conductive layer is substantially planar, and sidewalls of the interlayer conductive layer are tapered along a vertical direction.

[0010] In some embodiments, an angle between the sidewalls of the interlayer conductive layer and the bottom surface of the interlayer conductive layer is between about 60 degrees and about 80 degrees.

[0011] In some embodiments, the intermediate electrically conductive layer is formed of a metal silicide.

[0012] In some embodiments, a width of the intermediate electrically conductive layer is equal to or less than a width of the bottom electrically conductive plug.

[0013] In some embodiments, a width of the top electrically conductive plug is equal to or less than the width of the intermediate electrically conductive layer.

[0014] In some embodiments, an aspect ratio of the bottom electrically conductive plug is less than about 1 :4.

[0015] In some embodiments, an aspect ratio of the top electrically conductive plug is less than about 1 :4.

[0016] In some embodiments, a ratio of a radius of curvature of the top surface of the intermediate electrically conductive layer to a height of the intermediate electrically conductive layer is between about 1 : 1 and about 1 :4.

[0017] In some embodiments, a ratio of the height of the intermediate electrically conductive layer to a height of the top electrically conductive plug is between about 1 :3 and about 1 :6.

[0018] In some embodiments, the intermediate electrically conductive layer includes a lower portion on the bottom electrically conductive plug and an upper portion on the lower portion. A top surface of the upper portion is concave, and a bottom surface of the upper portion is concave.

[0019] In some embodiments, a centerline of the top electrically conductive plug is offset from a centerline of the intermediate electrically conductive layer.

[0020] Another aspect of the present disclosure provides a method of fabricating a semiconductor element, comprising: providing a substrate; forming a bottom electrically conductive plug on the substrate; forming a semiconductor layer on the bottom electrically conductive plug; rounding a top surface of the semiconductor layer; converting the semiconductor layer into an intermediate electrically conductive layer; and forming a top electrically conductive plug on the intermediate electrically conductive layer.

[0021] In some embodiments, the semiconductor layer includes polysilicon, polygermanium, or polysilicon-germanium.

[0022] In some embodiments, the intermediate electrically conductive layer is formed of a metal silicide.

[0023] In some embodiments, the step of converting the semiconductor layer into the intermediate electrically conductive layer includes: forming a layer of electrically conductive material over the semiconductor layer; and performing a heat treatment to cause the layer of electrically conductive material and the semiconductor layer to react and convert the semiconductor layer into the intermediate electrically conductive layer.

[0024] In some embodiments, a non-isotropic etching process is performed to round the top surface of the semiconductor layer.

[0025] Due to the design of the semiconductor element of the present disclosure, the semiconductor element including the intermediate conductive layer can have a higher pattern density. In addition, the non-planar top surface of the intermediate conductive layer can also reduce the contact resistance between the intermediate conductive layer and the top conductive plug. Therefore, the power consumption of the semiconductor element can be reduced. As a result, the performance of the semiconductor element can be improved.

[0026] The foregoing has outlined rather broadly the technical features of the present disclosure in order that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described hereinafter. The foregoing summary of the technical features of the present disclosure should not be considered complete with respect to the disclosure. For complete understanding, one should also refer to the detailed description of the disclosure, which follows herein. It should be apparent to those with ordinary skill in the art that the concepts and specific embodiments disclosed can be readily used as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0027] The aspects of the present disclosure can be better understood with respect to the following drawings and detailed description. It is emphasized that each of the various features illustrated in the drawings is not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily expanded or reduced for the clarity of discussion.

[0028] Figure 1 A cross-sectional schematic view of a semiconductor element according to an embodiment of the present disclosure.

[0029] Figures 2 to 8 A cross-sectional schematic view of a semiconductor element according to some embodiments of the present disclosure.

[0030] Figure 9 A flowchart of a method of manufacturing a semiconductor element according to an embodiment of the present disclosure.

[0031] Figures 10 to 15 A cross-sectional schematic view of a partial flow of a method of manufacturing a semiconductor element according to an embodiment of the present disclosure.

[0032] Figure 16 A partial enlarged view of Figure 15 .

[0033] Figure 17 and Figure 18 A cross-sectional schematic view of a partial flow of a method of manufacturing a semiconductor element according to an embodiment of the present disclosure.

[0034] Figures 19 to 22 A cross-sectional schematic view of a partial flow of a method of manufacturing a semiconductor element according to an embodiment of the present disclosure.

[0035] Figures 23 to 26A cross-sectional schematic view illustrating a part of a flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0036] Figures 27 to 31 A cross-sectional schematic view illustrating a part of a flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0037] In the drawings:

[0038] 1A: Semiconductor device

[0039] 1B: Semiconductor device

[0040] 1C: Semiconductor device

[0041] 1D: Semiconductor device

[0042] 1E: Semiconductor device

[0043] 1F: Semiconductor device

[0044] 1G: Semiconductor device

[0045] 1H: Semiconductor device

[0046] 10: Method of manufacturing

[0047] 101: Substrate

[0048] 101TS: Top surface

[0049] 103: First insulating layer

[0050] 103TS: Top surface

[0051] 105: Second insulating layer

[0052] 105TS: Top surface

[0053] 107: Third insulating layer

[0054] 201: Bottom conductive plug

[0055] 201-1: First conductive layer

[0056] 201-2: Second conductive layer

[0057] 201-3: First conductive layer

[0058] 201-4: Second conductive layer

[0059] 201-5: First conductive layer

[0060] 201-6: Second conductive layer

[0061] 201BS: Bottom surface

[0062] 201TS: top surface

[0063] 203: top conductive plug

[0064] 203BS: bottom surface

[0065] 203TS: top surface

[0066] 205: spacer

[0067] 301: intervening conductive layer

[0068] 301BS: bottom surface

[0069] 301SW: sidewall

[0070] 301TS: top surface

[0071] 301-1: outer portion

[0072] 301-1BS: bottom surface

[0073] 301-1E: end

[0074] 301-1TS: top surface

[0075] 301-3: center portion

[0076] 301-3BS: bottom surface

[0077] 301-3TS: top surface

[0078] 301-5: higher portion

[0079] 301-5BS: bottom surface

[0080] 301-5E: end

[0081] 301-5TS: top surface

[0082] 301-7: lower portion

[0083] 301-7BS: bottom surface

[0084] 301-7TS: top surface

[0085] 401: semiconductor material

[0086] 403: first hard mask layer

[0087] 403C: chamfered edge

[0088] 405: first mask layer

[0089] 407: semiconductor layer

[0090] 407 TS: top surface

[0091] 409: conductive material

[0092] 411: plug opening

[0093] 413: second hard mask layer

[0094] 415: second mask layer

[0095] CL1: center line

[0096] CL2: center line

[0097] H1: height

[0098] H2: height

[0099] H3: height

[0100] S11: step

[0101] S13: step

[0102] S15: step

[0103] R1: radius of curvature

[0104] W1: width

[0105] W2: width

[0106] W3: width

[0107] Z: direction

[0108] a: angle DETAILED DESCRIPTION

[0109] The following disclosure provides many different embodiments, or examples, for implementing different components of the present disclosure. Some of these embodiments are like the embodiments described in the background section above. The following description of examples of specific elements and arrangements is intended to simplify the present disclosure. These are not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. For example, although the description refers to a first element being formed "on" or "over" a second element, this can include embodiments where the first element is in direct contact with the second element, as well as embodiments where additional elements are formed between the first element and the second element without direct contact. Furthermore, the present disclosure can refer to a number of different embodiments using reference numerals and / or letters. These repetitions are for the sake of simplicity and clarity, and are not intended to limit the relationship between the different embodiments and / or structures being discussed.

[0110] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or component's or portion's relationship to another element, component or portion as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors can be interpreted accordingly.

[0111] It will be understood that when an element or layer is referred to as being "on" or "coupled to" another element or layer, it can be directly on or coupled to the other element or layer or intervening elements or layers can be present.

[0112] It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below could be termed a second element, and, similarly, a second element discussed below could be termed a first element without departing from the teachings of the present disclosure.

[0113] Unless context dictates otherwise, use of the word "about" or "approximately" when used in this document means within 10% or within the normal or acceptable range of values or limits, for example, and does not exclude the value itself, merely allowing for measurement errors, measurement precision and variations associated with manufacture, assembly and use of the devices and materials described in this document. The word "substantially" can be used herein to reflect this intended meaning. For example, items described as "substantially the same", "substantially equal" or "substantially planar" can be exactly the same, equal or planar, or can be the same, equal or planar within an acceptable range of variation, for example, due to manufacturing processes.

[0114] In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing a semiconductor property, and an electro-optical element, a light-emitting display element, a semiconductor circuit, and an electronic element are included in the category of semiconductor elements.

[0115] Note that in the description of the present disclosure, above or up corresponds to the direction of the arrow of the direction Z, and below or down corresponds to the direction opposite to the direction of the arrow of the direction Z.

[0116] Figure 1 A cross-sectional view of a semiconductor element 1A according to an embodiment of the present disclosure is illustrated. Referring toFigure 1 The semiconductor element 1A can include a substrate 101, a first insulating layer 103, a second insulating layer 105, a plurality of bottom conductive plugs 201, a plurality of top conductive plugs 203, and a plurality of intermediate conductive layers 301.

[0117] Referring to Figure 1 In some embodiments, the substrate 101 can be a bulk semiconductor substrate composed entirely of at least one semiconductor material; the bulk semiconductor substrate does not contain any dielectric, insulating layer, or conductive component. For example, the bulk semiconductor substrate can be formed of an elemental semiconductor, such as silicon or germanium; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other Group III-V compound semiconductor or Group II-VI compound semiconductor; or a combination of the foregoing.

[0118] In some embodiments, the substrate 101 can include a semiconductor-on-insulator structure that includes, from bottom to top, a handle substrate, an insulator layer, and a topmost semiconductor material layer. The handle substrate and the topmost semiconductor material layer can include the same materials as the bulk semiconductor substrate described above. The insulator layer can be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulator layer can be a dielectric oxide, such as silicon oxide. For another example, the insulator layer can be a dielectric nitride, such as silicon nitride or boron nitride. For yet another example, the insulator layer can include a stack of a dielectric oxide and a dielectric nitride, such as silicon oxide and silicon nitride or boron nitride stacked in any order. The thickness of the insulator layer can be between about 10 nm and 200 nm.

[0119] In some embodiments, the substrate 101 can include a dielectric, insulating layer, or conductive component disposed on the bulk semiconductor substrate or the topmost semiconductor material layer. The dielectric or insulating layer can include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicon glass, low-k dielectric material, a similar material thereof, or a combination of the foregoing. The thickness of each dielectric or each insulating layer can be between about 0.5 microns and about 3.0 microns. The low-k dielectric material can have a dielectric constant less than 3.0 or even less than 2.5. The conductive component can be a wire, a conductive via, a conductive contact, or the like.

[0120] In some embodiments, the substrate 101 can include circuit elements (not shown). The circuit elements can be, for example, bipolar junction transistors, metal-oxide semiconductor field-effect transistors, diodes, system large-scale integration, flash memory, dynamic random access memory, static random access memory, electrically erasable programmable read-only memories, image sensors, micro-electro-mechanical systems, active elements, or passive elements. The circuit elements can be electrically isolated from adjacent device elements by insulating structures such as shallow trench isolation.

[0121] Referring to Figure 1 , a first insulating layer 103 can be disposed on the substrate 101. The first insulating layer 103 can include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorosilicate glass, low dielectric constant dielectric materials, similar materials thereof, or combinations of the foregoing. The first insulating layer 103 can have a thickness between about 0.5 micrometers and about 3.0 micrometers.

[0122] Referring to Figure 1 , a second insulating layer 105 can be disposed on the first insulating layer 103. The second insulating layer 105 can include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorosilicate glass, low dielectric constant dielectric materials, similar materials thereof, or combinations of the foregoing. The second insulating layer 105 can have a thickness between about 0.5 micrometers and about 3.0 micrometers.

[0123] In Figure 1In some embodiments, a bottom conductive plug 201 can be disposed in the first insulating layer 103. For ease of description, only one bottom conductive plug 201 is described. A top surface 201TS of the bottom conductive plug 201 can be substantially coplanar with the top surface 103TS. A bottom surface 201BS of the bottom conductive plug 201 can be substantially coplanar with the top surface 101TS of the substrate 101. In other words, a height H1 of the bottom conductive plug 201 can be equal to a height of the first insulating layer 103. A ratio of a width W1 of the bottom conductive plug 201 to the height H1 of the bottom conductive plug 201 (i.e., an aspect ratio of the bottom conductive plug 201) can be less than about 1:4; in particular, can be less than 1:2. The bottom conductive plug 201 can include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination thereof.

[0124] It should be noted that in the description of the present disclosure, "height" refers to a vertical dimension measured in a cross-sectional perspective view from a top surface to a bottom surface of an element (e.g., a layer, a plug, a trench, a hole, an opening, etc.); "width" refers to a dimension measured in a cross-sectional perspective view from a side surface to an opposite surface of an element (e.g., a layer, a plug, a trench, a hole, an opening, etc.). Where indicated, the term "thickness" can be used in place of "width" and / or "height."

[0125] Referring to Figure 1 In some embodiments, a top conductive plug 203 can be disposed in the second insulating layer 105. For ease of description, only one top conductive plug 203 is described. A top surface 203TS of the top conductive plug 203 can be substantially coplanar with the top surface 105TS. A bottom surface 203BS of the top conductive plug 203 can be substantially coplanar with the top surface 103TS of the first insulating layer 103. In other words, a height H2 of the top conductive plug 203 can be equal to a height of the second insulating layer 105. A ratio of a width W3 of the top conductive plug 203 to the height H2 of the top conductive plug 203 (i.e., an aspect ratio of the top conductive plug 203) can be less than about 1:4; in particular, can be less than 1:2. The top conductive plug 203 can include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination thereof.

[0126] In some embodiments, the intermediate conductive layer 301 can have a semi-circular cross-sectional profile or a semi-elliptical cross-sectional profile in a cross-sectional perspective view. In some embodiments, the intermediate conductive layer 301 can taper in the Z-direction. A width W2 of the intermediate conductive layer 301 can taper from bottom to top. In some embodiments, the width W2 of the intermediate conductive layer 301 can be equal to or less than the width W1 of the bottom conductive plug 201.

[0127] It should be noted that in the description of the present disclosure, a surface is "substantially planar" if it deviates from a horizontal plane by no more than three times the root mean square roughness of the surface.

[0128] In some embodiments, the intermediate conductive layer 301 can comprise, for example, a metal silicide. The metal silicide can be, for example, titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. In some embodiments, the intermediate conductive layer 301 can comprise an impurity such as phosphorus, arsenic, antimony, or boron.

[0129] Referring to Figure 1 The top conductive plug 203 can be disposed on the intermediate conductive layer 301 and in the second insulating layer 105, respectively. For ease of description, only one top conductive plug 203 is described. A top surface 203TS of the top conductive plug 203 can be substantially coplanar with a top surface 105TS of the second insulating layer 105. A width W3 of the top conductive plug 203 can be equal to or less than a width W2 of the intermediate conductive layer 301. A bottom surface 203BS of the top conductive plug 203 can be non-planar and can be complementary to a top surface 301TS of the intermediate conductive layer 301. In the depicted embodiment, the bottom surface 203BS of the top conductive plug 203 is concave.

[0130] In some embodiments, a ratio of a height H2 of the intermediate conductive layer 301 to a height H3 of the top conductive plug 203 can be between about 1 :3 and about 1 :6. In some embodiments, a ratio of the width W3 of the top conductive plug 203 to the height H3 of the top conductive plug 203 (i.e., the aspect ratio of the top conductive plug 203) can be less than about 1 :4; specifically, less than 1 :2. In some embodiments, a centerline CL1 of the top conductive plug 203 can be aligned with a centerline CL2 of the intermediate conductive layer 301. In other words, the top conductive plug 203 can be symmetrically disposed on the intermediate conductive layer 301.

[0131] The top conductive plug 203 can comprise, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination of the foregoing.

[0132] In some embodiments, the bottom conductive plug 201, the intermediate conductive layer 301, and the top conductive plug 203 can together electrically connect a circuit element disposed on the second insulating layer 105 with a circuit element disposed in the substrate 101. For example, the bottom conductive plug 201, the intermediate conductive layer 301, and the top conductive plug 203 can together function as a bit line contact in a dynamic random access memory.

[0133] Conventionally, to electrically connect the circuit elements disposed above the second insulating layer 105 and the circuit elements disposed in the substrate 101, a conventional plug disposed along the second insulating layer 105 and the first insulating layer 103 can be used to electrically connect the above-mentioned circuit elements. However, as the size of the semiconductor elements is continuously reduced, the width of the conventional plug is continuously reduced while the height of the conventional plug remains unchanged. As a result, the aspect ratio of the conventional plug can be greater than 1:6, or even greater than 1:8, which makes the manufacturing of such conventional plug difficult.

[0134] To overcome this problem, the conventional plug can be divided into two separately fabricated plugs to avoid the high aspect ratio of the conventional plug, and a spacer having a width greater than the two plugs must be disposed between the two plugs to ensure the electrical connection of the two plugs. However, as the size of the semiconductor elements is continuously reduced, the spacer having a greater width can become a limitation of the design rule.

[0135] In contrast, in the depicted embodiment, the semiconductor element 1A uses the intermediate conductive layer 301 having about the same width as compared to the width of the bottom conductive plug 201 and the top conductive plug 203 to electrically connect the bottom conductive plug 201 and the top conductive plug 203; therefore, the pattern density of the semiconductor element 1A can be increased. In addition, the non-planar top surface 301TS of the intermediate conductive layer 301 can reduce the contact resistance between the top conductive plug 203 and the intermediate conductive layer 301, can ensure the electrical connection thereof and can reduce the power consumption of the semiconductor element 1A.

[0136] Figures 2 to 8 FIGS. 1B, 1C, 1D, 1E, 1F, 1G, and 1H are cross-sectional schematic views showing semiconductor elements 1B, 1C, 1D, 1E, 1F, 1G, and 1H, respectively, according to some embodiments of the present disclosure.

[0137] Reference will now be made to Figure 2 FIG. 1B, which shows a structure similar to that shown in FIG. 1A. Figure 1 Figure 2 Elements in the various figures have the same or similar designations regardless of whether they are Figure 1 Figure 2 ​​The intermediate conductive layer 301 can include an outer portion 301-1 and a center portion 301-3. The center portion 301-3 can be disposed on the bottom conductive plug 201 and can have a semi-circular cross-sectional profile or a semi-elliptical cross-sectional profile. The outer portion 301-1 can be disposed to cover the top surface 301-3TS of the center portion 301-3 and can have a circular-arc cross-sectional profile. The top surface 301-1TS and the bottom surface 301-1BS of the outer portion 301-1 can be convex. The two ends 301-1E of the outer portion 301-1, the bottom surface 301-3BS of the center portion 301-3, and the top surface 103TS of the first insulating layer 103 can be substantially coplanar. The outer portion 301-1 can have a substantially uniform thickness. The top conductive plug 203 can be disposed on the top surface 301-1TS of the outer portion 301-1.

[0138] The outer portion 301-1 of the intermediate conductive layer 301 can include, for example, a metal silicide. In some embodiments, the outer portion 301-1 of the intermediate conductive layer 301 can include an impurity such as phosphorus, arsenic, antimony, or boron. The center portion 301-3 of the intermediate conductive layer 301 can include, for example, polysilicon, polygermanium, polysilicon-germanium, or the like. In some embodiments, the center portion 301-3 of the intermediate conductive layer 301 can include an impurity such as phosphorus, arsenic, antimony, or boron.

[0139] Referring to Figure 3 , the semiconductor element 1C can have a structure similar to that shown in Figure 1 . Figure 3 The elements in Figure 1 are the same as or similar to those in Figure 3 , the intermediate conductive layer 301 can have a triangular cross-sectional profile. The sidewall 301SW of the intermediate conductive layer 301 can taper along the Z direction. The width W2 of the intermediate conductive layer 301 can gradually decrease from the bottom to the top along the Z direction. The sidewall 301SW of the intermediate conductive layer 301 can have a <111> crystal orientation. The angle a between the sidewall 301SW of the intermediate conductive layer 301 and the bottom surface 301BS of the intermediate conductive layer 301 can be between about 60 degrees and about 80 degrees.

[0140] Referring to Figure 4 , the semiconductor element 1D can have a structure similar to that shown in Figure 3 . Figure 4 The elements in Figure 3 are the same as or similar to those in Figure 4The intermediate conductive layer 301 can include a higher portion 301-5 and a lower portion 301-7. The lower portion 301-7 can be disposed on the bottom conductive plug 201 and can have a triangular cross-sectional profile. The higher portion 301-5 can be disposed to cover a top surface 301-7TS of the lower portion 301-7 and can have an inverted V-shaped cross-sectional profile. A top surface 301-5TS and a bottom surface 301-5BS of the higher portion 301-5 can be inverted V-shaped. The two ends 301-5E of the higher portion 301-5, the bottom surface 301-7BS of the lower portion 301-7, and the top surface 103TS of the first insulating layer 103 can be substantially coplanar. The higher portion 301-5 can have a substantially uniform thickness. The top conductive plug 203 can be disposed on the top surface 301-5TS of the higher portion 301-5.

[0141] The higher portion 301-5 of the intermediate conductive layer 301 can include, for example, a metal silicide. In some embodiments, the higher portion 301-5 of the intermediate conductive layer 301 can include an impurity such as phosphorus, arsenic, antimony, or boron. The lower portion 301-7 of the intermediate conductive layer 301 can include, for example, polysilicon, polygermanium, polysilicon germanium, or the like. In some embodiments, the lower portion 301-7 of the intermediate conductive layer 301 can include an impurity such as phosphorus, arsenic, antimony, or boron.

[0142] Referring to Figure 5 , the semiconductor element 1E can have a structure similar to that shown in Figure 1 . Figure 5 Elements in common or similar to those in Figure 1 have been labeled with similar reference numerals and repetitive description is omitted. Referring to Figure 5 , the third insulating layer 107 can be disposed between the first insulating layer 103 and the second insulating layer 105. The third insulating layer 107 can include the same material as the second insulating layer 105, but is not limited thereto. The intermediate conductive layer 301 can be disposed in the third insulating layer 107. A top surface 301TS of the intermediate conductive layer 301 can be concave. A bottom surface 203BS of the top conductive plug 203 can be convex.

[0143] Referring to Figure 6 , the semiconductor element 1F can have a structure similar to that shown in Figure 5 . Figure 6 Elements in common or similar to those in Figure 5 have been labeled with similar reference numerals and repetitive description is omitted. Referring to Figure 6The intermediate conductive layer 301 can include a higher portion 301-5 and a lower portion 301-7. The lower portion 301-7 can be disposed on the bottom conductive plug 201. A top surface 301-7TS of the lower portion 301-7 can be concave. The higher portion 301-5 can be disposed on the top surface 301-7TS of the lower portion 301-7 and can have a rounded profile. A top surface 301-5TS and a bottom surface 301-5BS of the higher portion 301-5 can be concave. A bottom surface 301-7BS of the lower portion 301-7 and a top surface 103TS of the first insulating layer 103 can be substantially coplanar. The higher portion 301-5 can have a substantially uniform thickness. The top conductive plug 203 can be disposed on the top surface 301-5TS of the higher portion 301-5.

[0144] The higher portion 301-5 of the intermediate conductive layer 301 can include, for example, a metal silicide. In some embodiments, the higher portion 301-5 of the intermediate conductive layer 301 can include an impurity such as phosphorus, arsenic, antimony, or boron. The lower portion 301-7 of the intermediate conductive layer 301 can include, for example, polysilicon, polygermanium, polysilicon germanium, or the like. In some embodiments, the lower portion 301-7 of the intermediate conductive layer 301 can include an impurity such as phosphorus, arsenic, antimony, or boron.

[0145] Referring to Figure 7 , the semiconductor device 1G can have a structure similar to that shown in Figure 1 . Figure 7 The same or similar elements in Figure 1 are labeled with similar reference numerals and repetitive description is omitted.

[0146] Referring to Figure 7The bottom conductive plug 201 can include a plurality of first conductive layers 201-1, 201-3, 201-5 and a plurality of second conductive layers 201-2, 201-4, 201-6. The first conductive layers 201-1, 201-3, 201-5 and the second conductive layers 201-2, 201-4, 201-6 can be alternately stacked. In some embodiments, the first conductive layers 201-1, 201-3, 201-5 and the second conductive layers 201-2, 201-4, 201-6 can have different stress states. For example, the first conductive layers 201-1, 201-3, 201-5 can have tensile stress, while the second conductive layers 201-2, 201-4, 201-6 can have compressive stress, or vice versa. The first conductive layers 201-1, 201-3, 201-5 and the second conductive layers 201-2, 201-4, 201-6 can include, for example, titanium, titanium nitride, ruthenium, molybdenum, chromium, vanadium, palladium, platinum, rhodium, scandium, aluminum, niobium, niobium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, or silicides thereof.

[0147] The stress states of the first conductive layers 201-1, 201-3, 201-5 and the second conductive layers 201-2, 201-4, 201-6 can be controlled by including different materials in the first conductive layers 201-1, 201-3, 201-5 and the second conductive layers 201-2, 201-4, 201-6. Specifically, the first conductive layers 201-1, 201-3, 201-5 include a material having a higher stress state, and the second conductive layers 201-2, 201-4, 201-6 include a material having a lower stress state. The second conductive layers 201-2, 201-4, 201-6 having a lower stress state can be thicker in thickness than the first conductive layers 201-1, 201-3, 201-5 having a higher stress state to compensate for the stress of the first conductive layers 201-1, 201-3, 201-5 having a higher stress state. Specifically, the first conductive layers 201-1, 201-3, 201-5 can have a thickness of between about 5 nm and 50 nm. The second conductive layers 201-2, 201-4, 201-6 can have a thickness of between about 10 nm and about 150 nm.

[0148] In some embodiments, the first conductive layers 201-1, 201-3, 201-5 can be large grain layers, and the second conductive layers 201-2, 201-4, 201-6 can be buffer layers. The large grain layers and the buffer layers can include, for example, titanium, titanium nitride, ruthenium, molybdenum, chromium, vanadium, palladium, platinum, rhodium, scandium, aluminum, niobium, niobium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, tantalum oxide, or silicides of the foregoing. For example, the large grain layers can include a pure metal (e.g., tantalum), and the buffer layers can include a metal nitride (e.g., tantalum nitride) or a metal oxide (e.g., tantalum oxide) of the pure metal. The thickness of the large grain layers can be between about 10 nm and about 30 nm. The thickness of the buffer layers can be between about 1 nm and about 5 nm. The buffer layers can block the crystal structure of the underlying large grain layers from extending upward in the Z direction, preventing the grain structure from propagating through the bottom conductive plug 201. As a result, the stress of the bottom conductive plug 201 can be reduced, and wafer bowing can be reduced or avoided.

[0149] Referring to Figure 7 , spacers 205 can be disposed on the sidewalls of the bottom conductive plug 201. The spacers 205 can include, for example, silicon oxide, silicon nitride, silicon carbon nitride, silicon nitride oxide, or silicon oxynitride. The spacers 205 can electrically isolate the bottom conductive plug 201 from adjacent conductive elements disposed adjacent to both sides of the bottom conductive plug 201. In some embodiments, the spacers 205 can be optional.

[0150] It should be noted that, in the description of the present disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen, and oxygen, and in which the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, and in which the proportion of nitrogen is greater than the proportion of oxygen.

[0151] Referring to Figure 8 , the semiconductor element 1H can have a structure similar to that shown in Figure 1 . Figure 8 Elements in Figure 1 that are the same as or similar to those in Figure 8 , have been labeled with like reference numerals and repetitive description is omitted. Referring to , the center line CL1 of the top conductive plug 203 can be offset from the center line CL2 of the intermediate conductive layer 301. In other words, the top conductive plug 203 can be asymmetrically disposed on the intermediate conductive layer 301. The non-planar top surface 301TS of the intermediate conductive layer 301 can increase the contact surface between the top conductive plug 203 and the intermediate conductive layer 301.

[0152] The contact resistance between the top conductive plug 203 and the intermediate conductive layer 301 is inversely proportional to the contact surface between the top conductive plug 203 and the intermediate conductive layer 301. Due to the low contact resistance originating from the non-planar top surface 301TS of the intermediate conductive layer 301, the non-planar top surface 301TS of the intermediate conductive layer 301 can still provide a firm electrical connection between the top conductive plug 203 and the intermediate conductive layer 301 even if the top conductive plug 203 can be asymmetrically disposed on the intermediate conductive layer 301. In other words, the non-planar top surface 301TS of the intermediate conductive layer 301 can expand the tolerance window of the photolithography process during the fabrication of the top conductive plug 203. As a result, the manufacturing yield of the semiconductor device 1H can be increased.

[0153] It should be noted that the functions or steps mentioned herein can occur in an order different from that shown in the figures. For example, two figures shown in succession can actually be performed substantially simultaneously or sometimes in reverse order, depending on the functions or steps involved.

[0154] It should be noted that the words "forming", "formed", and "form" can mean and include any method of creating, building, patterning, implanting, or depositing an element, dopant, or material. Examples of forming methods can include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, photolithography, dry etching, and wet etching.

[0155] Figure 9 A flowchart of a method 10 of fabricating a semiconductor device 1A according to an embodiment of the present disclosure. Figures 10 to 15 A cross-sectional schematic view of a partial process of fabricating a semiconductor device 1A according to an embodiment of the present disclosure. Figure 16 is Figure 15 A close-up view of Figure 17 and Figure 18 A cross-sectional schematic view of a partial process of fabricating a semiconductor device 1A according to an embodiment of the present disclosure.

[0156] Referring to Figures 9 to 13At step Sll, a substrate 101 can be provided, a first insulating layer 103 can be formed on the substrate 101, a plurality of bottom conductive plugs 201 can be formed in the first insulating layer 103, and a plurality of semiconductor layers 407 can be formed on the bottom conductive plugs 201.

[0157] Referring to Figure 10 Fabrication techniques for forming the first insulating layer 103 on the substrate 101 can include deposition processes such as chemical vapor deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, or the like. Fabrication techniques for forming the bottom conductive plugs 201 in the first insulating layer 103 can include a damascene process.

[0158] Referring to Figure 10 A layer of semiconductor material 401 can be formed on the first insulating layer 103. A first hard mask layer 403 can be formed on the layer of semiconductor material 401. The semiconductor material 401 can be, for example, polysilicon, polygermanium, polysilicon germanium, or the like. In some embodiments, the layer of semiconductor material 401 can be doped with an impurity such as phosphorous, arsenic, antimony, or boron. The first hard mask layer 403 can include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like, or a combination of the foregoing. Fabrication techniques for the layer of semiconductor material 401 and the first hard mask layer 403 can include deposition processes such as chemical vapor deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, or the like.

[0159] Referring to Figure 10 A first mask layer 405 can be formed on the first hard mask layer 403. The first mask layer 405 can be a photoresist layer. The first mask layer 405 can be patterned to define a pattern of semiconductor layers 407.

[0160] Referring to Figure 11 A hard mask etch process can be performed to remove portions of the first hard mask layer 403 and transfer the pattern of the first mask layer 405 to the first hard mask layer 403. The hard mask etch process can have a faster etch rate for the first mask layer 405 than for the layer of semiconductor material 401. For example, the etch rate ratio of the first mask layer 405 to the layer of semiconductor material 401 during the hard mask etch process can be between about 100: 1 and about 1.05: 1. For another example, the etch rate ratio of the first mask layer 405 to the layer of semiconductor material 401 during the hard mask etch process can be between about 100: 1 and about 10: 1. After the hard mask etch process, the first mask layer 405 can be removed.

[0161] Referring to Figure 12A main etching process can be performed to remove a portion of the semiconductor material 401 and convert the semiconductor material 401 into multiple semiconductor layers 407. The pressure of the main etching process can be between about 2 mTorr and about 10 mTorr. The power supply of the main etching process can be between about 300 W and about 450 W. The bias power of the main etching process can be between about 20 W and about 150 W. In some embodiments, the main etching process can be performed using gases such as oxygen, chlorine, fluorocarbons, and hydrogen bromide. The etching rate of the semiconductor material 401 in the main etching process can be faster than the etching rate of the first insulating layer 103 in the main etching process. For example, during the main etching process, the etching rate ratio of the semiconductor material 401 to the first insulating layer 103 can be between about 100:1 and about 1.05:1. For example, during the main etching process, the etching rate ratio of the semiconductor material 401 to the first insulating layer 103 may be between about 100:1 and about 10:1.

[0162] During the main etching process, the first hard mask layer 403 can be gradually etched, and the end of the top surface of the first hard mask layer 403 can be chamfered by impact with the etchant. Hereinafter, the end of the top surface of the first hard mask layer 403 may be referred to as a chamfered edge 403C. Each chamfered edge 403C of the first hard mask layer 403 may have a taper angle of approximately 45 degrees. The main etching process may, for example, be an isotropic etching process.

[0163] Reference Figure 13 An over-etching process can be performed. The pressure of the over-etching process can be between about 5 Pa and about 20 Pa. The power of the over-etching process can be between about 100 W and about 200 W. In some embodiments, the over-etching process can be performed using gases such as oxygen and fluoroform. Since the corners of the top surface 407TS of the semiconductor layer 407 can be etched faster than the flat center portion of the top surface 407TS of the semiconductor layer 407, and the semiconductor layer 407 can be etched according to the shape of the chamfered edge 403C of the first hard mask layer 403, the top surface 407TS of the semiconductor layer 407 can be rounded by the over-etching process. The over-etching process can be, for example, an isotropic etching process.

[0164] Reference Figure 9 and Figures 14 to 16 In step S13, the semiconductor layer 407 can be converted into a plurality of intermediate conductive layers 301.

[0165] Reference Figure 14 A layer of conductive material 409 can be formed. Figure 13 Above the intermediate semiconductor element shown. The conductive material 409 may include, for example, titanium, nickel, platinum, tantalum, or cobalt.

[0166] Referring to Figure 15 A thermal treatment can be performed. During the thermal treatment, the metal atoms of the layer of conductive material 409 can chemically react with the silicon atoms of the semiconductor layer 407 to form the intermediate conductive layer 301. The intermediate conductive layer 301 can include a metal silicide, such as titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The thermal treatment can be a dynamic surface anneal process. After the thermal treatment, a cleaning process can be performed to remove unreacted conductive material 409. The cleaning process can use an etchant such as hydrogen peroxide and SC-1 solution. The shape of the intermediate conductive layer 301 can be inherited from the semiconductor layer 407. That is, the intermediate conductive layer 301 can have a rounded top surface 301TS.

[0167] Referring to Figure 16 For each intermediate conductive layer 301, the ratio of the radius of curvature Rl of the top surface 301TS of the intermediate conductive layer 301 to the height H2 of the intermediate conductive layer 301 can be between about 1: 1 and about 1:4.

[0168] In some embodiments, only a portion of the semiconductor layer 407 exposed to the layer of conductive material 409 can be converted to a metal silicide.

[0169] Referring to Figure 9 , Figure 17 and Figure 18 In step S15, a plurality of top conductive plugs 203 can be formed on the intermediate conductive layer 301.

[0170] Referring to Figure 17 A second insulating layer 105 can be formed to cover the intermediate conductive layer 301. A planarization process such as chemical mechanical polishing can be performed to provide a substantially planar surface for subsequent process steps. Subsequently, plug openings 411 can be formed through the second insulating layer 105 by a litho-etch process. The plug openings 411 can expose the top surface 301TS of the intermediate conductive layer 301.

[0171] Referring to Figure 18 A conductive material such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide, a metal nitride, or a transition metal aluminide can be deposited into the plug openings 411 by a deposition process. After the deposition process, a planarization process such as chemical mechanical polishing can be performed to remove excess material, to provide a substantially planar surface for subsequent process steps, and to conformally form the top conductive plugs 203.

[0172] Figures 19 to 22 is a cross-sectional schematic diagram showing part of a flow of fabricating a semiconductor device 1C according to another embodiment of the present disclosure.

[0173] Referring to Figure 19It can provide Figure 12 The intermediate semiconductor element shown. The first hard mask layer 403 can be removed.

[0174] Reference Figure 20 A wet etching process can then be performed to chamfer the semiconductor layer 407. The wet etching process can be performed at a temperature between approximately 80°C and 82°C using a mixture comprising potassium hydroxide, isopropanol, and water.

[0175] Reference Figure 21 It can be done through something like Figure 14 and Figure 15 The steps shown transform the chamfered semiconductor layer 407 into an intermediate conductive layer 301.

[0176] Reference Figure 22 It can be done through something like Figure 17 and Figure 18 The steps shown form the second insulating layer 105 and the top conductive plug 203.

[0177] Figures 23 to 26 This is a cross-sectional schematic diagram showing a portion of the process for fabricating a semiconductor device 1E according to another embodiment of this disclosure.

[0178] Reference Figure 23 It can provide Figure 12 The intermediate semiconductor element shown. The first hard mask layer 403 can be removed. A third insulating layer 107 can be formed to cover the semiconductor layer 407. A planarization process, such as chemical mechanical polishing, can be performed until the top surface 407TS of the semiconductor layer 407 is exposed to provide a substantially flat surface for subsequent process steps.

[0179] Reference Figure 24 An isotropic etching process can be performed to remove a portion of the semiconductor layer 407 and recess the top surface 407TS of the semiconductor layer 407. The etching rate of the semiconductor layer 407 in the isotropic etching process can be faster than the etching rate of the third insulating layer 107 in the isotropic etching process. For example, during the isotropic etching process, the etching rate ratio of the semiconductor layer 407 to the third insulating layer 107 can be between about 100:1 and about 1.05:1. As another example, during the isotropic etching process, the etching rate ratio of the semiconductor layer 407 to the third insulating layer 107 can be between about 100:1 and about 10:1.

[0180] Reference Figure 25 It can be done through something like Figure 14 and Figure 15 The steps shown convert the semiconductor layer 407 with a recessed top surface into an intermediate conductive layer 301.

[0181] Reference Figure 26The second insulating layer 105 and the top conductive plug 203 can be formed by steps similar to those shown in Figure 17 and Figure 18

[0182] Figures 27 to 31 is a cross-sectional schematic diagram showing part of a flow of manufacturing a semiconductor device 1G according to another embodiment of the present disclosure.

[0183] Referring to Figure 27 The substrate 101 can be provided, a plurality of first conductive layers 201-1, 201-3, 201-5 and a plurality of second conductive layers 201-2, 201-4, 201-6 can be alternately formed on the substrate 101, a second hard mask layer 413 can be formed on the first conductive layers 201-1, 201-3, 201-5 and the second conductive layers 201-2, 201-4, 201-6, and a second mask layer 415 can be formed on the second hard mask layer 413. The manufacturing technique of the first conductive layers 201-1, 201-3, 201-5 and the second conductive layers 201-2, 201-4, 201-6 can include chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, ionized physical vapor deposition, atomic layer deposition, electroplating, or electroless plating, but is not limited thereto. It should be noted that the term "stacked layer" can be used interchangeably with the first conductive layers 201-1, 201-3, 201-5 and the second conductive layers 201-2, 201-4, 201-6.

[0184] ​In some embodiments, the first conductive layers 201-1, 201-3, 201-5 and the second conductive layers 201-2, 201-4, 201-6 can have different stress states. For example, the first conductive layers 201-1, 201-3, 201-5 can have tensile stress, while the second conductive layers 201-2, 201-4, 201-6 can have compressive stress, or vice versa. The stress states of the first conductive layers 201-1, 201-3, 201-5 and the second conductive layers 201-2, 201-4, 201-6 can be controlled by including different materials in the first conductive layers 201-1, 201-3, 201-5 and the second conductive layers 201-2, 201-4, 201-6. Specifically, the first conductive layers 201-1, 201-3, 201-5 include materials having higher stress states, and the second conductive layers 201-2, 201-4, 201-6 include materials having lower stress states. The thickness of the second conductive layers 201-2, 201-4, 201-6 having lower stress states can be thicker than the thickness of the first conductive layers 201-1, 201-3, 201-5 having higher stress states to compensate for the stress of the first conductive layers 201-1, 201-3, 201-5 having higher stress states. Specifically, the thickness of the first conductive layers 201-1, 201-3, 201-5 can be between about 5 nm to 50 nm. The thickness of the second conductive layers 201-2, 201-4, 201-6 can be between about 10 nm to about 150 nm.

[0185] For another example, the stress states of the stack layers can be controlled by forming the stack layers as nitrides having different nitrogen contents. Specifically, the first conductive layers 201-1, 201-3, 201-5 can include nitrides having higher nitrogen contents, thereby having higher stress states due to having more disrupted crystallization. Conversely, the second conductive layers 201-2, 201-4, 201-6 can include nitrides having lower nitrogen contents to have lower stress states. The different nitrogen contents of the stack layers can be controlled by the amounts of reactants during deposition processes of the stack layers.

[0186] The first conductive layers 201-1, 201-3, 201-5 and the second conductive layers 201-2, 201-4, 201-6 having different stress states can cancel or at least reduce the stress of the stack layers to a desired amount. Therefore, wafer bowing can be reduced or avoided.

[0187] In some embodiments, the first conductive layers 201-1, 201-3, 201-5 can be large grain layers, and the second conductive layers 201-2, 201-4, 201-6 can be buffer layers. The thickness of the large grain layers can be between about 10 nm and about 30 nm. The thickness of the buffer layers can be between about 1 nm and about 5 nm. The buffer layers can prevent the crystal structure of the underlying large grain layers from extending upward in the Z direction, preventing the grain structure from propagating through the stack. As a result, the stress of the stack can be reduced. Thus, wafer bow can be reduced or avoided.

[0188] The second hard mask layer 413 can comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride. A lithography process can be performed to transfer a desired pattern to the second mask layer 415 and define the pattern of the bottom conductive plug 201, which will be shown later.

[0189] Referring to Figure 28 An etching process can be performed to remove the exposed portions of the second hard mask layer 413, thereby transferring the pattern of the bottom conductive plug 201 to the second hard mask layer 413. After the etching process, the second mask layer 415 can be removed.

[0190] Referring to Figure 29 Subsequently, an etching process can be performed to remove the exposed portions of the stack. Depending on the etch selectivity of the first conductive layers 201-1, 201-3, 201-5 and the second conductive layers 201-2, 201-4, 201-6 relative to each other, the etching process can be completed using the same chemistry to remove both stacks, or cycling between processes tailored to each respective material of the first conductive layers 201-1, 201-3, 201-5 and the second conductive layers 201-2, 201-4, 201-6. For example, fluorine-based etching can be used to remove the exposed portions of the first conductive layers 201-1, 201-3, 201-5, and chlorine-based etching can be used to remove the exposed portions of the second conductive layers 201-2, 201-4, 201-6. After the etching process, the remaining portions of the stack can together form the bottom conductive plug 201. After the bottom conductive plug 201 is formed, the second hard mask layer 413 can be removed.

[0191] Referring to Figure 30 A spacer 205 can be formed on the sides of the bottom conductive plug 201. The fabrication technique of the spacer 205 can include depositing an insulating material over the bottom conductive plug 201, and subsequently performing a non-isotropic etching process to remove portions of the insulating material. The insulating material can be, for example, silicon oxide, silicon nitride, silicon carbon nitride, silicon oxynitride, or silicon oxynitride.

[0192] Referring to Figure 31 The first insulating layer 103, the second insulating layer 105, the intermediate conductive layer 301, and the top conductive plug 203 can be formed by similar steps as shown in Figures 10 to 18 The bottom conductive plug 201 formed by the stack layer can be more suitable for semiconductor elements with smaller technology nodes (e.g., 20 nm, 14 nm, 7 nm or below).

[0193] One aspect of the present disclosure provides a semiconductor element, comprising: a substrate; a bottom conductive plug on the substrate; an intermediate conductive layer on the bottom conductive plug; and a top conductive plug on the intermediate conductive layer. A top surface of the intermediate conductive layer is non-planar.

[0194] Another aspect of the present disclosure provides a method of manufacturing a semiconductor element, comprising: providing a substrate; forming a bottom conductive plug on the substrate; forming a semiconductor layer on the bottom conductive plug; rounding a top surface of the semiconductor layer; converting the semiconductor layer into an intermediate conductive layer; and forming a top conductive plug on the intermediate conductive layer.

[0195] Due to the design of the semiconductor element of the present disclosure, the semiconductor element 1A including the intermediate conductive layer 301 can have a higher pattern density. In addition, the non-planar top surface of the intermediate conductive layer 301 can also reduce the contact resistance between the intermediate conductive layer 301 and the top conductive plug 203. Therefore, the power consumption of the semiconductor element 1A can be reduced. As a result, the performance of the semiconductor element 1A can be improved.

[0196] While the present disclosure and its advantages have been disclosed in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above can be implemented in different methodologies than those described above, and the methodologies described above can be implemented in other than the order described above. Accordingly, the disclosure is not limited to the above-described embodiments and modifications thereof.

[0197] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the disclosure is intended to embrace all known and later-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functionality or serve the same purpose described and claimed in the disclosure. Accordingly, the disclosure is intended to embrace all alternatives, modifications and variations of these processes, machines, manufactures, compositions of matter, means, methods, and steps that have the same purpose or serve the same function in the disclosure, and that are within the scope of the claims.

Claims

1. A semiconductor device, comprising: a substrate; a bottom conductive plug on the substrate; an intermediate conductive layer on the bottom conductive plug; and a top conductive plug on the intermediate conductive layer; wherein a top surface of the intermediate conductive layer is non-planar; wherein a bottom surface of the top conductive plug is complementary to the top surface of the intermediate conductive layer; wherein the top surface of the intermediate conductive layer is concave and the bottom surface of the top conductive plug is convex.

2. The semiconductor device of claim 1, wherein a bottom surface of the intermediate conductive layer is substantially planar and sidewalls of the intermediate conductive layer taper along a vertical direction.

3. The semiconductor device of claim 2, wherein an angle between the sidewalls of the intermediate conductive layer and the bottom surface of the intermediate conductive layer is between about 60 degrees and about 80 degrees.

4. The semiconductor device of claim 1, wherein the intermediate conductive layer comprises a metal silicide.

5. The semiconductor device of claim 4, wherein a width of the intermediate conductive layer is equal to or less than a width of the bottom conductive plug.

6. The semiconductor device of claim 4, wherein a width of the top conductive plug is equal to or less than the width of the intermediate conductive layer.

7. The semiconductor device of claim 6, wherein an aspect ratio of the bottom conductive plug is less than about 1 :

4.

8. The semiconductor device of claim 7, wherein an aspect ratio of the top conductive plug is less than about 1 :

4.

9. The semiconductor device of claim 8, wherein a ratio of a radius of curvature of the top surface of the intermediate conductive layer to a height of the intermediate conductive layer is between about 1 : 1 and about 1 :

4.

10. The semiconductor device of claim 9, wherein a ratio of the height of the intermediate conductive layer to a height of the top conductive plug is between about 1 :3 and about 1 :

6.

11. The semiconductor device of claim 1, wherein the intermediate conductive layer comprises a lower portion on the bottom conductive plug and an upper portion on the lower portion, wherein a top surface of the upper portion is concave and a bottom surface of the upper portion is concave.

12. The semiconductor device of claim 1, wherein a centerline of the top conductive plug is offset from a centerline of the intermediate conductive layer.

13. A method of fabricating a semiconductor device, comprising: providing a substrate; forming a bottom conductive plug on the substrate; forming a semiconductor layer on the bottom conductive plug; rounding a top surface of the semiconductor layer; converting the semiconductor layer to an intermediate conductive layer; and forming a top conductive plug on the intermediate conductive layer; wherein the intermediate conductive layer comprises a metal silicide; wherein the semiconductor layer comprises polysilicon, polygermanium, or polysilicon germanium; wherein a non-isotropic etch process is performed to round the top surface of the semiconductor layer.

14. The method of fabricating a semiconductor device of claim 13, wherein converting the semiconductor layer to the intermediate conductive layer comprises: forming a layer of conductive material over the semiconductor layer; and ​ ​ a heat treatment is performed to convert the semiconductor layer into the intermediate conductive layer by a reaction of the layer of conductive material and the semiconductor layer.

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