SRAM and its layout design methodology

Abstract

This invention provides an SRAM and its layout design method. The SRAM layout design method includes: forming delay chain cells and memory cells in the SRAM circuit layout design in the memory area; and forming decoders and sensitive amplifiers in the SRAM circuit layout design in the logic area. This invention can avoid process differences between delay chain cells and memory cells. Therefore, the delay chain cells located in the memory area can precisely control the generation time of the sensitive amplifier's turn-on signal, thereby improving the storage speed of the memory cells, i.e., improving the storage speed of the SRAM.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an SRAM and its layout design method. Background Technology

[0002] With the widespread application of semiconductor devices, they have penetrated into many fields such as computers, communications, medical devices, and automobiles. Static Random-Access Memory (SRAM) has become an indispensable and important component of semiconductor devices as a random data storage chip. Figure 1 This is a schematic diagram of the main components of an SRAM circuit; please refer to it. Figure 1 The existing SRAM structure includes logic cells located in the logic region (decoder, delay chain cells, sensitive amplifier, etc.) and memory cells located in the memory region. Due to the process differences between the logic region and the memory region in semiconductor manufacturing, there are also process differences between the delay chain cells in the logic region and the memory cells in the memory region. Therefore, the delay chain cells in the logic region cannot accurately track the discharge time of the memory cells in the memory region; that is, they cannot track the voltage difference on their bit lines. Consequently, the voltage difference output by the delay chain cells cannot accurately control the turn-on signal of the sensitive amplifier, thus affecting the SRAM's storage speed. In other words, the delay chain cells in the logic region cannot accurately control the generation time of the turn-on signal of the sensitive amplifier, causing the sensitive amplifier to fail to turn on the memory cells in the memory region in a timely manner, thus affecting the SRAM's storage speed. Summary of the Invention

[0003] The purpose of this invention is to provide an SRAM and its layout design method to solve the problem of slow SRAM storage speed caused by the delay chain unit's inability to accurately control the generation time of the sensitive amplifier's turn-on signal.

[0004] To achieve the above objectives, the present invention provides an SRAM layout design method, comprising:

[0005] In the SRAM circuit layout design, delay chain cells and memory cells are formed in the memory area;

[0006] In SRAM circuit layout design, the decoder and sensitive amplifier are formed in the logic area.

[0007] Furthermore, in the SRAM layout design method provided by the present invention, the delay chain unit is composed of an odd number of inverters connected end to end.

[0008] Furthermore, in the SRAM layout design method provided by the present invention, the inverters are an odd number of three or more.

[0009] Furthermore, the SRAM layout design method provided by the present invention removes the delay chain cells located in the logic area and forms delay chain cells in the storage area in the traditional SRAM circuit structure layout design.

[0010] Furthermore, the SRAM layout design method provided by the present invention removes the delay chain cells located in the logic area and modifies some of the memory cells in the storage area into delay chain cells in the traditional SRAM circuit structure layout design, so as to form delay chain cells and memory cells in the storage area.

[0011] Furthermore, the SRAM layout design method provided by this invention includes the method of modifying a portion of the memory cells in the memory area into delay chain cells, comprising:

[0012] Find an odd number of memory cells in a subset of memory cells;

[0013] The metal wires connecting the two inverters in each cell memory are disconnected to form two independent inverters;

[0014] In an odd number of memory cells, one inverter from each of the two independent inverters is connected end-to-end by a metal wire to form a delay chain cell, thus forming a delay chain cell in the memory area.

[0015] Furthermore, the SRAM layout design method provided by this invention, wherein the metal lines connecting the two inverters in each cell memory are disconnected to form two independent inverters; and the method of connecting one of the two independent inverters in each cell memory in an odd number of cell memories end-to-end with metal lines to form a delay chain cell includes:

[0016] Retain the contact hole of one inverter in each cell memory, and remove the contact holes of the remaining devices in each cell memory;

[0017] By connecting the inverters with reserved contact holes in an odd number of cell memory units end to end using metal wires, a delay chain unit consisting of an odd number of inverters is formed.

[0018] To achieve the above objectives, the present invention also provides an SRAM including a logic area and a storage area, wherein the logic area includes a decoder and a sensitive amplifier, and the storage area includes a delay chain unit and a storage unit.

[0019] Furthermore, in the SRAM provided by the present invention, the delay chain unit is an odd number of inverters connected end to end.

[0020] Furthermore, in the SRAM provided by the present invention, the inverters are an odd number of three or more.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] The SRAM and its layout design method provided by this invention form delay chain cells in the memory area of ​​the SRAM circuit layout design. By changing the position of the delay chain cells in the SRAM circuit layout design, the positions and circuit connections of the memory cells, decoders, and sensitive amplifiers in the SRAM circuit layout design are not changed. This adjusts the delay chain cells located in the logic area of ​​the traditional SRAM circuit layout design to the memory area. The delay chain cells located in the memory area can be fabricated in the same semiconductor process conditions as the memory cells in the memory area, avoiding process differences between the delay chain cells and the memory cells. The delay chain cells located in the memory area can precisely control the generation time of the sensitive amplifier's turn-on signal, thereby improving the storage speed of the memory cells, that is, improving the storage speed of the SRAM. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the main components of a traditional SRAM circuit structure.

[0024] Figure 2 This is the circuit schematic of a delay chain unit;

[0025] Figure 3 This is a magnified electron microscope diagram of the layout structure of a traditional SRAM circuit structure where an inverter is reserved in part of the memory cell of the memory area.

[0026] Figure 4 This is a magnified electron microscope schematic diagram of the layout structure of the delay chain unit and the memory unit located in the memory area in the SRAM circuit structure layout design of an embodiment of the present invention. Detailed Implementation

[0027] The hole-punching structure and method for metal wires proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0028] Please refer to Figures 1 to 4 This invention provides an SRAM layout design method, comprising:

[0029] The delay chain and memory cell 100 in the SRAM circuit layout design are formed in the memory area; the decoder and sense amplifiers in the SRAM circuit layout design are formed in the logic area.

[0030] Please refer to Figure 2 The SRAM layout design method provided in this embodiment of the invention comprises a delay chain unit consisting of an odd number of inverters connected end to end. Figure 2 The example shows a delay chain unit consisting of 3 inverters, but it is not limited to 3; it can also be an odd number of more than 3 inverters.

[0031] Please refer to Figures 3 to 4 To avoid affecting the layout design of the memory cells in the storage area, the SRAM layout design method provided in this embodiment of the invention can remove the delay chain cells located in the logic area in the traditional SRAM circuit structure layout design, and form a delay chain cell in the storage area. By removing the delay chain cells located in the logic area in the traditional SRAM circuit structure layout design and adding a delay chain cell in the storage area, the delay chain cells are adjusted to be located in the storage area. The advantage of this design is that it does not affect the original layout design of the memory cells 100 in the storage area.

[0032] Please refer to Figures 3 to 4 To ensure that the delay chain units are consistent with the process conditions of the memory cell 100, thus eliminating process discrepancies, the SRAM layout design method provided in this embodiment of the invention removes the delay chain units located in the logic area from the traditional SRAM circuit structure layout design, and modifies a portion of the memory cells 100 in the memory area into delay chain units, thereby forming both delay chain units and memory cells 100 within the memory area. By modifying a portion of the memory cells 100 into delay chain units, the process conditions of the delay chain units, including but not limited to critical dimensions, dielectric layers, and the thickness of metal lines, are made consistent with those of the memory cell 100, thereby eliminating process corners in the delay chain unit memory cell 100.

[0033] Please refer to Figures 3 to 4 To eliminate process corners, the SRAM layout design method provided in this embodiment of the invention includes the method of modifying a portion of the memory cells 100 in the memory area into delay chain cells, which may include:

[0034] Step 201: Identify an odd number of memory cells in a subset of memory cells 100.

[0035] Step 202: Disconnect the metal wires of the two inverters connected end to end in each cell memory to form two independent inverters.

[0036] Step 203 involves connecting one of the two independent inverters in each of the odd-numbered memory cells via metal wires to form a delay chain, thus creating a delay chain in the memory area. The specific methods for steps 202 to 203 in the layout design include:

[0037] The contact holes of one inverter in each cell memory are retained, and the contact holes of the remaining devices in each cell memory are removed; the inverters with retained contact holes in an odd number of cell memories are connected end to end by metal wires to form a delay chain unit composed of an odd number of inverters. Figure 3 The example illustrates four inverters INV1-INV4, i.e., four memory cells. These four memory cells are merely illustrative; in practice, there is an odd number, and they should not be construed as limiting the understanding of the invention. Figure 4 The example illustrates a partial layout of a delay chain unit and memory cell 100 within the memory area. Figure 4 It can be seen that the delay chain unit maintains its critical dimensions, shape, and metal connection with the memory cell 100 as much as possible. This design allows for better matching of the potential difference ΔV between the BL and BLB bit lines in the delay chain unit. Specifically, it can coordinate with the potential difference ΔV between the BL and BLB bit lines in the delay chain unit located in the memory area to feed the signal amplifiers. This allows for timely control of the signal amplifiers' control ports, amplifying the potential difference ΔV and outputting it promptly to control the storage speed of the memory cell 100. In other words, by tracking the voltage difference between the bit lines of the delay chain unit in the memory area, the precise control of the signal amplifiers' activation is achieved.

[0038] This invention provides an SRAM including a logic area and a storage area. The logic area includes a decoder and sense amplifiers, and the storage area includes delay chains and storage cells 100. The delay chains consist of an odd number of inverters connected end-to-end. The number of inverters is an odd number, typically three or more.

[0039] The SRAM and its layout design method provided in this invention form the delay chain in the memory area of ​​the SRAM circuit layout design. By changing the position of the delay chain in the SRAM circuit layout design without altering the position and circuit connections of the memory cell 100, decoder, and sense amplifiers, the delay chain, located in the logic area in the traditional SRAM circuit layout design, is moved to the memory area. This allows the delay chain in the memory area to be fabricated using the same process conditions as the memory cell 100 in the semiconductor manufacturing process, avoiding process differences between the delay chain and the memory cell 100. Consequently, the delay chain in the memory area can precisely control the generation time of the turn-on signal of the sense amplifiers, thereby improving the storage speed of the memory cell 100, and thus improving the storage speed of the SRAM.

[0040] The SRAM and its layout design method provided in this invention can precisely control the timing of its bit lines by changing the delay chain in the memory area, thereby providing a precise control signal for the enable signal of the sense amplifiers.

[0041] The term "above" as used in the embodiments of this invention includes the stated number.

[0042] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims of the present invention.

Claims

1. An SRAM layout design method, characterized in that, include: In the SRAM circuit layout design, delay chain cells and memory cells are formed in the memory area; In the SRAM circuit layout design, the decoder and sensitive amplifier are formed in the logic area; Modifying some storage units in the aforementioned storage area into delayed chain units includes: Identify an odd number of memory cells in a subset of the aforementioned memory cells; The metal wires connecting the two inverters in each of the cell memories are disconnected to form two independent inverters; The delay chain unit is formed by connecting one of the two independent inverters in each of the odd number of cell memories end to end with a metal wire.

2. The SRAM layout design method as described in claim 1, characterized in that, The delay chain unit consists of an odd number of inverters connected end to end.

3. The SRAM layout design method as described in claim 2, characterized in that, The inverters are an odd number of three or more.

4. The SRAM layout design method as described in claim 1, characterized in that, In traditional SRAM circuit layout design, delay chain cells located in the logic area are removed, and delay chain cells are formed in the memory area.

5. The SRAM layout design method as described in claim 1, characterized in that, In traditional SRAM circuit layout design, the delay chain cells located in the logic area are removed, and the delay chain cells and the memory cells are formed in the memory area.

6. The SRAM layout design method as described in claim 1, characterized in that, The method of disconnecting the metal wires connecting the two inverters in each cell memory to form two independent inverters; and connecting one of the two independent inverters in each cell memory of an odd number of cell memories end-to-end with metal wires to form a delay chain cell includes: Retain the contact hole of one inverter in each cell memory, and remove the contact holes of the remaining devices in each cell memory; By connecting the inverters with reserved contact holes in an odd number of cell memory units end to end using metal wires, a delay chain unit consisting of an odd number of inverters is formed.

7. An SRAM, characterized in that, It includes a logic area and a storage area. The logic area includes a decoder and a sensitive amplifier, and the storage area includes a delay chain unit and a storage unit. Modifying some storage units in the aforementioned storage area into delayed chain units includes: Identify an odd number of memory cells in a subset of the aforementioned memory cells; The metal wires connecting the two inverters in each of the cell memories are disconnected to form two independent inverters; The delay chain unit is formed by connecting one of the two independent inverters in each of the odd number of cell memories end to end with a metal wire.

8. The SRAM as claimed in claim 7, characterized in that, The delay chain unit consists of an odd number of inverters connected end-to-end.

9. The SRAM as claimed in claim 8, characterized in that, The inverters are an odd number of three or more.

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