Three-dimensional semiconductor memory device

Abstract

Three-dimensional semiconductor memory devices are provided. The three-dimensional semiconductor memory devices can include a first substrate including a bit line connection region and a word line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, the first core region being superposed with the bit line connection region, the second core region being superposed with the word line connection region, and a peripheral circuit structure on the second substrate.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0107326, filed on August 25, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a three-dimensional semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device having improved reliability and increased integration density. BACKGROUND

[0003] Higher integration of semiconductor devices is required to meet consumers' demand for excellent performance and inexpensive prices. In the case of semiconductor devices, increased integration is particularly required because their integration density is an important factor in determining product prices. In the case of two-dimensional or planar semiconductor devices, because their integration density is mainly determined by the area occupied by a unit memory cell, the integration density is greatly affected by the level of fine patterning technology. However, extremely expensive process equipment required to increase the pattern fineness sets a practical limit to increasing the integration density of two-dimensional or planar semiconductor devices. To overcome such a limitation, three-dimensional semiconductor memory devices including memory cells arranged three-dimensionally have recently been proposed. SUMMARY

[0004] An aspect is to provide a three-dimensional semiconductor memory device having improved reliability and increased integration density.

[0005] According to an aspect of an example embodiment, a three-dimensional semiconductor memory device can include a first substrate including a bit line connection region and a word line connection region; a cell array structure on the first substrate; a second substrate including a first core region and a second core region, the first core region overlapping the bit line connection region, the second core region overlapping the word line connection region; and a peripheral circuit structure on the second substrate. The cell array structure can include word lines stacked on the first substrate; bit lines crossing the word lines in a first direction perpendicular to a top surface of the first substrate; first lower metal pads disposed on the bit line connection region and connected to the bit lines; and second lower metal pads disposed on the word line connection region and connected to the word lines. The peripheral circuit structure can include sense amplifiers disposed on the first core region; sub word line drivers disposed on the second core region; first upper metal pads disposed on the first core region and connected to the sense amplifiers; and second upper metal pads disposed on the second core region and connected to the sub word line drivers. The first lower metal pads can be bonded to the first upper metal pads, and the second lower metal pads can be bonded to the second upper metal pads.

[0006] According to another aspect of example embodiments, a three-dimensional semiconductor memory device can include: a first base including a bit line connection region, a word line connection region, and a first peripheral region; a cell array structure including a memory cell array, the memory cell array including memory cells arranged three-dimensionally on the bit line connection region and the word line connection region of the first base, and the cell array structure including a lower control circuit provided on the first peripheral region of the first base; a second base including a first core region, a second core region, and a second peripheral region, the first core region being superposed with the bit line connection region, the second core region being superposed with the word line connection region, and the second peripheral region being superposed with the first peripheral region; and a peripheral circuit structure including a sense amplifier provided on the first core region of the second base, a sub word line driver provided on the second core region of the second base, and an upper control circuit provided on the second peripheral region of the second base.

[0007] According to yet another aspect of example embodiments, a three-dimensional semiconductor memory device can include: a first base including a bit line connection region, a word line connection region, and a first peripheral region; a cell array structure on the first base, the cell array structure including bit lines, word lines, memory cells, a first lower metal pad, a second lower metal pad, and a third lower metal pad, the bit lines extending in a first direction perpendicular to a top surface of the first base, the word lines extending in a second direction parallel to the top surface of the first base to cross the bit lines, the memory cells provided at intersections of the bit lines and the word lines, the first lower metal pad provided on the bit line connection region and connected to the bit lines, the second lower metal pad provided on the word line connection region and connected to the word lines, and the third lower metal pad provided on the first peripheral region and connected to a lower control circuit; a second base including a first core region, a second core region, and a second peripheral region, the first core region being superposed with the bit line connection region, the second core region being superposed with the word line connection region, and the second peripheral region being superposed with the first peripheral region; and a peripheral circuit structure on the second base. The peripheral circuit structure can include: a first upper metal pad provided on the first core region and connected to a sense amplifier; a second upper metal pad provided on the second core region and connected to a sub word line driver; and a third upper metal pad provided on the second peripheral region and connected to an upper control circuit. The first lower metal pad can be bonded to the first upper metal pad, the second lower metal pad can be bonded to the second upper metal pad, and the third lower metal pad can be bonded to the third upper metal pad. BRIEF DESCRIPTION OF DRAWINGS

[0008] Example embodiments will become more fully understood from the detailed description and accompanying drawings, wherein:

[0009] Figure 1 is a block diagram illustrating a three-dimensional semiconductor memory device according to an example embodiment;

[0010] Figure 2 is a cross-sectional view schematically illustrating a three-dimensional semiconductor memory device according to an example embodiment;

[0011] Figure 3 is a perspective view schematically showing a three-dimensional semiconductor memory device according to an example embodiment;

[0012] Figure 4 is a diagram showing an example of a cell array structure and a peripheral circuit structure provided in a three-dimensional semiconductor memory device according to an example embodiment;

[0013] Figure 5A and Figure 5B is a plan view showing a cell array structure of a three-dimensional semiconductor memory device according to an example embodiment;

[0014] Figure 6A and Figure 6B are cross-sectional views each showing a cross section taken along a line I-I', a line II-II', and a line III-III' of Figure 5A and Figure 5B , respectively;

[0015] Figure 7 is a diagram exemplarily showing a connection structure between a bit line and a bit line connection line in a three-dimensional semiconductor memory device according to an example embodiment;

[0016] Figure 8 is a diagram exemplarily showing a connection structure between a bit line and a lower metal pad in a three-dimensional semiconductor memory device according to an example embodiment;

[0017] Figure 9 is a plan view schematically showing a three-dimensional semiconductor memory device according to an example embodiment;

[0018] Figure 10 is a diagram showing a connection structure between a cell array structure and a peripheral circuit structure in a region A of Figure 9 ;

[0019] Figure 11A and Figure 11B are diagrams showing a connection structure between a cell array structure and a peripheral circuit structure in a region B of Figure 9 according to various example embodiments;

[0020] Figures 12 to 16 is a cross-sectional view showing a three-dimensional semiconductor memory device according to various example embodiments; and

[0021] Figures 17 to 22 is a diagram showing an example of a lower metal pad and an upper metal pad arranged in a three-dimensional semiconductor memory device according to various example embodiments. DETAILED DESCRIPTION

[0022] Example embodiments will now be described more fully with reference to the accompanying drawings in which example embodiments are shown. The example embodiments are indicated as non-limiting examples as described herein.

[0023] Figure 1 is a block diagram illustrating a three-dimensional semiconductor memory device according to an example embodiment.

[0024] Referring to Figure 1 , the three-dimensional semiconductor memory device can include a memory cell array 1, a row decoder 2, a sense amplifier (Sense Amp) 3, a column decoder 4, and control logic 5.

[0025] The memory cell array 1 can include a plurality of memory cells MC arranged three-dimensionally. Each memory cell MC can be disposed between and connected to a word line WL and a bit line BL, which are disposed to cross each other.

[0026] Each memory cell MC can include a selection element TR and a data storage element CAP electrically connected in series to each other. The data storage element CAP can be connected to the bit line BL through the selection element TR, which can be disposed between and connected to the data storage element CAP and the word line WL. The selection element TR can be a field effect transistor (FET), and the data storage element CAP can be implemented with a capacitor, a variable resistor, or the like. As an example, the selection element TR can include a transistor having a gate electrode connected to the word line WL and drain / source terminals connected to the bit line BL and the data storage element CAP, respectively.

[0027] The row decoder 2 can be configured to decode address information input from the outside of the three-dimensional semiconductor memory device and select one of the word lines WL of the memory cell array 1 based on the decoded address information. The address information decoded by the row decoder 2 can be provided to a row driver (not shown), in which case the row driver can provide a predetermined voltage to the selected one of the word lines WL and the unselected ones of the word lines WL, respectively, in response to control by the control circuit.

[0028] The sense amplifier (Sense Amp) 3 can be configured to sense, amplify, and output a voltage difference between one of the bit lines BL selected based on address information decoded by the column decoder 4 and a reference bit line.

[0029] The column decoder 4 can provide a data transfer path between the sense amplifier 3 and an external device (e.g., a memory controller). The column decoder 4 can be configured to decode address information input from outside of the three-dimensional semiconductor memory device, and select one of the bit lines BL based on the decoded address information.

[0030] The control logic 5 can be configured to generate a control signal for controlling a data write operation or a data read operation to the memory cell array 1.

[0031] Figure 2 is a cross-sectional view schematically showing a three-dimensional semiconductor memory device according to an example embodiment.

[0032] Referring to Figure 2 , the three-dimensional semiconductor memory device can include a cell array structure CS and a peripheral circuit structure PS on the cell array structure CS.

[0033] The cell array structure CS can include a memory cell array including memory cells arranged three-dimensionally on a first substrate 100. For example, the cell array structure CS can include the memory cell array 1 described with reference to Figure 1 The memory cell array can include a horizontal pattern stacked sequentially on the first substrate 100, a vertical pattern disposed to cross the horizontal pattern vertically, and a memory element interposed between the horizontal pattern and the vertical pattern. For example, as discussed later, the horizontal pattern can be disposed along a first direction D1 and / or a second direction D2, and the vertical pattern can be disposed along a third direction D3. However, this is merely an example.

[0034] The peripheral circuit structure PS can include a core circuit and a peripheral circuit formed on a second substrate 200. The core circuit and the peripheral circuit can include the row decoder 2 and the column decoder 4, the sense amplifier (Sense Amp) 3, and the control logic 5 described with reference to Figure 1

[0035] A lower metal pad (or "land" or "pad") LMP can be disposed at a topmost level of the cell array structure CS. The lower metal pad LMP can be electrically connected to the memory cell array. An upper metal pad UMP can be disposed at a topmost level of the peripheral circuit structure PS. The upper metal pad UMP can be electrically connected to the core circuit and the peripheral circuit.

[0036] ​The lower metal pad LMP and the upper metal pad UMP can have substantially the same size and arrangement. For example, the lower metal pad LMP and the upper metal pad UMP can be formed of, or include, at least one of copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn), and alloys thereof.

[0037] According to an example embodiment, a three-dimensional semiconductor memory device can be manufactured by forming a cell array structure CS including memory cells arranged three-dimensionally on a first substrate 100, forming a peripheral circuit structure PS including core circuits and peripheral circuits formed on a second substrate 200 different from the first substrate 100, and then connecting the first substrate 100 to the second substrate 200 in a bonded manner. That is, the lower metal pad LMP of the cell array structure CS and the upper metal pad UMP of the peripheral circuit structure PS can be electrically and physically connected to each other in a bonded manner. In other words, the lower metal pad LMP can be in direct contact with the upper metal pad UMP.

[0038] Figure 3 is a perspective view schematically showing a three-dimensional semiconductor memory device according to an example embodiment.

[0039] Referring to Figure 3 The cell array structure CS can include a memory cell array region MCA and a first peripheral region PR1. The peripheral circuit structure PS can include a first core region CR1, a second core region CR2, and a second peripheral region PR2. The first core region CR1 and the second core region CR2 can be overlapped with the memory cell array region MCA when viewed in a plan view. The first peripheral region PR1 can be disposed at a side of the memory cell array region MCA, and the second peripheral region PR2 can be disposed at a side of the second core region CR2. The second peripheral region PR2 can be overlapped with the first peripheral region PR1 when viewed in a plan view.

[0040] A memory cell array including memory cells arranged three-dimensionally can be disposed in the memory cell array region MCA. In other words, word lines and bit lines disposed to cross each other and memory cells disposed between the word lines and the bit lines can be disposed in the memory cell array region MCA.

[0041] A plurality of sense amplifiers can be disposed in the first core region CR1, and a plurality of sub word line drivers can be disposed in the second core region CR2.

[0042] The control signal generation circuit that controls the sub word line driver and the control signal generation circuit that controls the sense amplifier can be disposed in the first peripheral region PR1 and the second peripheral region PR2. Also, the voltage generator that supplies an operating voltage to the sense amplifier and the sub word line driver can be disposed in the first peripheral region PR1 and the second peripheral region PR2.

[0043] Figure 4 is a cross-sectional view schematically illustrating an example of a cell array structure and a peripheral circuit structure disposed in a three-dimensional semiconductor memory device according to an example embodiment.

[0044] Referring to Figure 4 In the cell array structure CS, the memory cell array region can include a bit line connection region BLB and a word line connection region WLB disposed on both sides of the bit line connection region BLB.

[0045] The cell array structure CS can include word lines WL disposed in parallel with a top surface of the first base 100 and bit lines BL disposed perpendicular to the top surface of the first base 100. Memory cells MC can be disposed at each intersection of the word lines WL and the bit lines BL.

[0046] The bit lines BL can be disposed in the bit line connection region BLB, and the word lines WL can extend from the bit line connection region BLB to the word line connection region WLB.

[0047] The cell array structure CS can include a first lower metal pad LMP1 disposed in the bit line connection region BLB and a second lower metal pad LMP2 disposed in the word line connection region WLB. The first lower metal pad LMP1 can be electrically connected to the bit lines BL, and the second lower metal pad LMP2 can be electrically connected to the word lines WL.

[0048] As shown in an example illustrated in Figure 4 The peripheral circuit structure PS can include a first core region CR1 and a second core region CR2 disposed on both sides of the first core region CR1. The first core region CR1 can overlap the bit line connection region BLB, and the second core region CR2 can overlap the word line connection region WLB, respectively, when viewed in a plan view.

[0049] A plurality of sense amplifiers SA0 to SAn (where n is a positive integer) can be disposed in the first core region CR1, each of the sense amplifiers SA0 to SAn can be disposed to correspond to a pair of bit lines BL. That is, each of the sense amplifiers SA0 to SAn can be disposed to correspond to two bit lines BL. A plurality of sub word line drivers SWD0 to SWDn (where n is a positive integer) can be disposed in each of the second core regions CR2.

[0050] The peripheral circuit structure PS can include a first upper metal pad UMP1 disposed in the first core region CR1 and a second upper metal pad UMP2 disposed in the second core region CR2. The first upper metal pad UMP1 can be connected to the sense amplifiers SA0 to SAn, and the second upper metal pad UMP2 can be connected to the sub word line drivers SWD0 to SWDn.

[0051] The first upper metal pad UMP1 can be directly connected to the first lower metal pad LMP1, and the second upper metal pad UMP2 can be directly connected to the second lower metal pad LMP2. The first upper metal pad UMP1 can have substantially the same size and arrangement as those of the first lower metal pad LMP1. The second upper metal pad UMP2 can have substantially the same size and arrangement as those of the second lower metal pad LMP2. The first lower metal pad LMP1, the second lower metal pad LMP2, the first upper metal pad UMP1, and the second upper metal pad UMP2 can include the same metal material, and can have substantially the same size or area. For example, the first lower metal pad LMP1, the second lower metal pad LMP2, the first upper metal pad UMP1, and the second upper metal pad UMP2 can be formed of, or include at least one of copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn), and alloys thereof.

[0052] Figure 5A and Figure 5B is a plan view showing a unit array structure of a three-dimensional semiconductor memory device according to an example embodiment. Figure 6A and Figure 6B are each a cross-sectional view showing a cross-section taken along Figure 5A and Figure 5B lines I-I', line II-II', and line III-III' of Figure 7 is a diagram exemplarily showing a connection structure between a bit line and a bit line connection line in a three-dimensional semiconductor memory device according to an example embodiment. Figure 8 is a diagram exemplarily showing a connection structure between a bit line and a lower metal pad in a three-dimensional semiconductor memory device according to an example embodiment.

[0053] Referring to Figure 5A and Figure 6A , the unit array structure of the three-dimensional semiconductor memory device can include a bit line connection region BLB and a word line connection region WLB.

[0054] The word line structures can be disposed on the first base 100, and in an example embodiment, the word line structures can include word lines WL vertically stacked on the first base 100. The first base 100 can be formed of or include a semiconductor material. For example, the first base 100 can be a single crystalline silicon base or a silicon-on-insulator (SOI) base.

[0055] The word line structures can extend from the bit line connection regions BLB to the word line connection regions WLB. The word line structures can extend along a first direction D1, and can be spaced apart from each other along a second direction D2 that intersects the first direction D1. The first direction D1 and the second direction D2 can be parallel to a top surface of the first base 100.

[0056] Each of the word line structures can include interlayer insulating layers and word lines WL alternately stacked along a third direction D3 (i.e., a vertical direction) that is perpendicular to the first direction D1 and the second direction D2.

[0057] Referring to Figure 5A A pair of the word line structures can be connected to each other in the bit line connection region BLB. For example, two word lines WL located at the same level can be connected to each other in the bit line connection region BLB.

[0058] The word line pads WLP can be disposed in the word line connection regions WLB. Each of the word line pads WLP can be commonly shared by a corresponding pair of the word lines WL. The word line pads WLP can be stacked on the first base 100 such that the word line pads WLP form a stepped structure in the word line connection regions WLB. The word line pads WLP can be disposed at positions that are horizontally and vertically different from each other.

[0059] In another example embodiment, as Figure 5B indicated in Each of the word lines WL in each of the word line structures can have a word line pad WLP in the word line connection region WLB. For example, the word line pads WLP located at the same level and adjacent to each other along the second direction D2 can be spaced apart from each other. Each of the word line structures can have a stepped structure in the word line connection region WLB, which can include the word line pads WLP of the word lines WL located at different levels.

[0060] Figure 5A and Figure 5BAs shown in the middle, each word line WL can include a line portion extending in the first direction Dl and a gate electrode portion GE extending from the line portion in the second direction D2 to have a protruding shape. Each pair of word lines WL can be arranged such that their gate electrode portions GE have mirror symmetry when viewed in a plan view. The word lines WL can be formed of, or include, at least one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metallic material (e.g., tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0061] The semiconductor patterns SP arranged in three dimensions can be provided in the bit line connection region BLB. The semiconductor patterns SP can be stacked along the third direction D3 and can be spaced apart from each other along both the first direction Dl and the second direction D2.

[0062] Each semiconductor pattern SP can be a strip-shaped pattern elongated in the second direction D2. Each semiconductor pattern SP can include first and second end portions spaced apart from each other and a channel portion provided between the first and second end portions. The semiconductor pattern SP can be formed of, or include, at least one of silicon and germanium. The first and second end portions of each semiconductor pattern SP can be doped with impurities. In an example embodiment, the semiconductor pattern SP can be formed of, or include, an oxide semiconductor material. As an example, the oxide semiconductor material can include at least one of indium (In), gallium (Ga), zinc (Zn), and tin (Sn). The oxide semiconductor material can be indium gallium zinc oxide (IGZO) containing indium (In), gallium (Ga), and zinc (Zn).

[0063] The semiconductor patterns SP can be respectively provided to penetrate the gate electrode portions GE of the word lines WL in the second direction D2. Each word line WL can be arranged to completely surround the channel portion of the semiconductor pattern SP (e.g., having a ring gate structure). A gate insulating layer GI can be interposed between the channel portion of the semiconductor pattern SP and the word line WL.

[0064] In the bit line connection region BLB, the bit lines BL can extend in the third direction D3 to cross the word line structure. The bit lines BL can have substantially the same length when measured in the third direction D3. The bit lines BL can be arranged to be spaced apart from each other along the first direction Dl and the second direction D2.

[0065] The lower insulating layer 101 can be provided between the bit line BL and the first base 100. Each bit line BL can be connected to the first end portion of the semiconductor pattern SP stacked in the third direction D3. The bit line BL can be formed of or include at least one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0066] The data storage element CAP can be connected to the second end portion of each semiconductor pattern SP. In an example embodiment, the data storage element CAP can be a capacitor. In other words, the storage electrode SE of the capacitor can be connected to the second end portion of each semiconductor pattern SP.

[0067] Referring to Figure 6A The data storage element CAP can be provided at substantially the same level as the semiconductor pattern SP. In other words, the storage electrode SE can be stacked in the third direction D3 and can be elongated in the second direction D2. In some example embodiments, the storage electrode SE of each data storage element CAP can have a hollow cylindrical shape. Alternatively, in other example embodiments, the storage electrode SE can be a pillar-shaped pattern elongated in the second direction D2. The storage electrode SE can be formed of or include at least one of a metal material, a metal nitride, and a metal silicide.

[0068] The dielectric layer IL can be provided to conformally cover the surface of each storage electrode SE, and the plate electrode PE can be provided on the dielectric layer IL. The plate electrode PE can be provided to cover the inner and outer surfaces of the storage electrode SE on which the dielectric layer IL is provided. The dielectric layer IL can be formed of or include at least one of a metal oxide (e.g., hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, and titanium oxide) and a perovskite dielectric material (e.g., SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and PLZT).

[0069] The plate electrode PE can be disposed to fill the inner space of the storage electrode SE provided with the dielectric layer IL. Also, the plate electrode PE can be disposed to cover the outer side surface of the storage electrode SE, where the dielectric layer IL can be interposed between the plate electrode PE and the storage electrode SE. The plate electrode PE can be commonly connected to the common wire CL. The common wire CL can extend along the first direction D1 and the third direction D3. In other words, the common wire CL can be commonly connected to the plate electrodes PE arranged along the first direction D1 and the third direction D3. Also, the plate electrodes PE adjacent to each other along the second direction D2 can be commonly connected to the common wire CL. In an example embodiment, the plate electrode PE and the common wire CL can be formed at the same time, and can be formed of the same material without any internal interface.

[0070] According to Figure 6B the embodiment shown in FIG. 1, the storage electrode SE of each data storage element CAP can include a first storage electrode SE1 and a second storage electrode SE2, the first storage electrode SE1 being in contact with a top surface of the second end portion of the semiconductor pattern SP, and the second storage electrode SE2 being in contact with a bottom surface of the second end portion of the semiconductor pattern SP. In other words, the second end portion of the semiconductor pattern SP can be disposed between the first storage electrode SE1 and the second storage electrode SE2 along the third direction D3.

[0071] The dielectric layer IL can be disposed to conformally cover the surfaces of the first storage electrode SE1 and the second storage electrode SE2. The plate electrode PE can be disposed to fill the inner space of the first storage electrode SE1 and the second storage electrode SE2 provided with the dielectric layer IL. Also, the plate electrode PE can be disposed to cover the outer side surface of the first storage electrode SE1 and the second storage electrode SE2.

[0072] Referring back to Figure 6A and Figure 6B , the bit line contact plug BCP can be bonded to the bit line BL, respectively. The bit line connection line BCL can extend in parallel to each other along the second direction D2, and can be connected to the bit line BL through the bit line contact plug BCP.

[0073] The connection structure between the bit line BL and the bit line connection line BCL will be described in more detail with reference to Figure 7 .

[0074] Figure 7 is an exemplary view illustrating a connection structure between a bit line and a bit line connection line in a three-dimensional semiconductor memory device according to an example embodiment. Although the semiconductor pattern and the data storage element are briefly shown in Figure 7 , the semiconductor pattern and the data storage element can be the same as those described with reference to Figure 5A , Figure 5B , Figure 6A and Figure 6BThe semiconductor pattern and the data storage element are substantially the same.

[0075] Referring to Figure 7 Two bit lines BL can be disposed between each pair of word lines WL. The bit lines BL can include first bit lines BL0 and second bit lines BL1 alternately arranged along the second direction D2.

[0076] The bit line connection lines BCL can extend along the second direction D2 to cross the word lines WL and the common conductor lines CL. Two or more of the bit line connection lines BCL can cross the first bit lines BL0 and the second bit lines BL1 when viewed in a plan view. For example, two or more of the bit line connection lines BCL0 to BCL7 can be superposed with each of the bit lines BL.

[0077] The bit line connection lines BCL can include odd-numbered bit line connection lines BCL1, BCL3, BCL5, and BCL7 and even-numbered bit line connection lines BCL0, BCL2, BCL4, and BCL6 alternately arranged along the first direction D1. In an example embodiment, dummy connection lines can be disposed between the odd-numbered bit line connection lines BCL1, BCL3, BCL5, and BCL7 and the even-numbered bit line connection lines BCL0, BCL2, BCL4, and BCL6, respectively.

[0078] Each of the odd-numbered bit line connection lines BCL1, BCL3, BCL5, and BCL7 can be connected to the first bit line BL0 arranged along the second direction D2 through a bit line contact plug BCP.

[0079] Each of the even-numbered bit line connection lines BCL0, BCL2, BCL4, and BCL6 can be connected to the second bit line BL1 arranged along the second direction D2 through a bit line contact plug BCP.

[0080] Figure 8 FIG. 2 is a diagram exemplarily illustrating a connection structure between a bit line and a lower metal pad in a three-dimensional semiconductor memory device according to an example embodiment.

[0081] Referring to Figure 8 Landing conductive patterns LP can be disposed on the bit line connection lines BCL0 to BCL7. The landing conductive patterns LP can extend along the first direction D1 to cross the bit line connection lines BCL0 to BCL7 and can be spaced apart from each other on the bit line connection lines BCL0 to BCL7 along the second direction D2. Each of the landing conductive patterns LP can be superposed with a predetermined number of the bit line connection lines BCL0 to BCL7. Each of the landing conductive patterns LP can be connected to a corresponding one of the bit line connection lines BCL0 to BCL7 through a contact plug LCP.

[0082] A first lower metal pad LMP1 can be disposed on the bonding conductive pattern LP, respectively. In some example embodiments, the first lower metal pad LMP1 can be connected to the bonding conductive pattern LP by a bonding contact plug (not shown). Alternatively, in other example embodiments, the first lower metal pad LMP1 can be in direct contact with a top surface of the bonding conductive pattern LP. Each first lower metal pad LMP1 can have a second width Wb greater than a first width Wa of the bonding conductive pattern LP when measured along the second direction D2. A distance between adjacent ones of the first lower metal pads LMP1 can be smaller than a distance between adjacent ones of the bonding conductive patterns LP when measured along the second direction D2. Each first lower metal pad LMP1 can have a second length smaller than a first length of the bonding conductive pattern LP when measured along the first direction D1.

[0083] According to various example embodiments, reference is made to Figure 4 Each first upper metal pad UMP1 of the peripheral circuit structure PS described above can be bonded to Figure 8 a corresponding one of the first lower metal pads LMP1 shown in FIGS. 1A and 1B.

[0084] Figure 9 FIG. 1C is a plan view schematically showing a three-dimensional semiconductor memory device according to an example embodiment.

[0085] Figure 10 FIG. 1D is a plan view showing a connection structure between a cell array structure and a peripheral circuit structure in a region A of Figure 9 FIG. 1E is a plan view showing a connection structure between a cell array structure and a peripheral circuit structure in a region B of Figure 11A and Figure 11B FIG. 1F is a plan view showing a connection structure between a cell array structure and a peripheral circuit structure in a region B of Figure 9 FIG. 1G is a plan view showing a connection structure between a cell array structure and a peripheral circuit structure in a region B of

[0086] Reference is made to Figure 9 , Figure 10 and Figure 11A A three-dimensional semiconductor memory device according to an example embodiment can include a plurality of memory blocks disposed along a second direction D2. As an example, the three-dimensional semiconductor memory device can include a first memory block MB1 and a second memory block MB2.

[0087] Each of the first memory block MB1 and the second memory block MB2 can include a cell array structure CS including a bit line connection region BLB and a word line connection region WLB, and a peripheral circuit structure PS including a first core region CR1 and a second core region CR2, as described above. The first core region CR1 can overlap the bit line connection region BLB when viewed in a plan view, and the second core region CR2 can overlap the word line connection region WLB when viewed in a plan view. In the first core region CR1, a sense amplifier SA can overlap a portion of the bit line connection region BLB of each of the memory blocks MB1 and MB2 when viewed in a plan view.

[0088] As previously described with reference to Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7 and Figure 8 , the bit lines BL, the bit line connection lines BCL, the junction conductive patterns LP, and the lower metal pads LMP1 and LMP2 of the cell array structure can be provided in each of the first memory block MB1 and the second memory block MB2. Further, the upper metal pads UMP1 and UMP2 of the peripheral circuit structure PS can be provided corresponding to the lower metal pads LMP1 and LMP2.

[0089] In the bit line connection region BLB, the first lower metal pad LMP1 and the first upper metal pad UMP1 can be arranged to be spaced apart from each other by a constant distance along the first direction D1 and the second direction D2. However, this is merely an example, and in some example embodiments, the distance in the first direction D1 and the second direction D2 can vary. In the word line connection region WLB, the second lower metal pad LMP2 and the second upper metal pad UMP2 can be arranged to be spaced apart from each other by a constant distance along the first direction D1 and the second direction D2. However, this is merely an example, and in some example embodiments, the distance in the first direction D1 and the second direction D2 can vary. Further, the first lower metal pad LMP1 and the first upper metal pad UMP1 can have substantially the same size and area as each other, and the second lower metal pad LMP2 and the second upper metal pad UMP2 can have substantially the same size and area as each other. In some example embodiments, the size and / or area of some or all of the first lower metal pad LMP1 and the first upper metal pad UMP1 can be different from the size and / or area of some or all of the second lower metal pad LMP2 and the second upper metal pad UMP2.

[0090] Referring to Figure 9 and Figure 10The bit line connection lines BCL0a to BCL7a of the first memory block MB1 can be spaced apart from the bit line connection lines BCL0b to BCL7b of the second memory block MB2. In other words, the bit line connection lines BCL0a to BCL7a of the first memory block MB1 can be separated from the bit line connection lines BCL0b to BCL7b of the second memory block MB2.

[0091] As an example, the even-numbered sense amplifiers SA0, SA2, SA4, and SA6 can be disposed in the first memory block MB1, and the odd-numbered sense amplifiers SA1, SA3, SA5, and SA7 can be disposed in the second memory block MB2. Bit line connection lines (e.g., a pair of bit line connection lines) among the bit line connection lines BCL0a to BCL7a and BCL0b to BCL7b of the first memory block MB1 and the second memory block MB2 that are adjacent to each other in the first direction D1 can share a corresponding one of the sense amplifiers SA0 to SA7.

[0092] Referring to Figure 9 and Figure 11A As previously described with reference to Figure 5A , the word line structures of the cell array structure can be disposed such that a pair of word lines WL located at the same level share a corresponding one of the word line pads WLP. The number of the word line pads WLP can be equal to the number of the stacks of the word lines WL. The sub word line drivers SWD can be disposed corresponding to each of the word line pads WLP. In other words, the sub word line drivers SWD can be electrically connected to the word line pads WLP through the second lower metal pads LMP2 and the second upper metal pads UMP2, respectively.

[0093] Each of the second lower metal pads LMP2 and the second upper metal pads UMP2 can have a second width W2 greater than a first width W1 of the word line pads WLP. The first lower metal pads LMP1 and the first upper metal pads UMP1 can be arranged at a first pitch P1, and the second lower metal pads LMP2 and the second upper metal pads UMP2 can be arranged at a second pitch P2 substantially the same as the first pitch P1.

[0094] Referring to Figure 9 and 11B As previously described with reference to Figure 5B , in each of the word line structures of the cell array structure, the word line pads WLP can be disposed at end portions of the word lines WL, respectively. For example, the word line pads WLP of the word line structures adjacent to each other along the second direction D2 can be spaced apart from each other along the second direction D2. The word line landing pads WLLP can be disposed corresponding to a pair of the word line pads WLP adjacent to each other along the second direction D2. The number of the word line landing pads WLLP can be equal to the number of the stacks of the word lines WL. The word line landing pads WLLP can be electrically connected to the sub word line drivers SWD through the second lower metal pads LMP2 and the second upper metal pads UMP2, respectively. Figure 8The described landing conductive pattern LP is located at substantially the same level. The word line landing pad WLLP can be formed of, or include, the same conductive material as the landing conductive pattern LP. In some example embodiments, the second lower metal pad LMP2 can be connected to the word line landing pad WLLP by a contact plug LPLG. Optionally, in other example embodiments, the second lower metal pad LMP2 can be in direct contact with a top surface of the word line landing pad WLLP. The word line landing pad WLLP can be electrically connected to a word line pad WLP by a word line contact plug WPLG. A sub word line driver SWD can be provided corresponding to each word line landing pad WLLP.

[0095] Figure 12 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an example embodiment.

[0096] Referring to Figure 12 As described above, the three-dimensional semiconductor memory device according to an example embodiment can include a cell array structure CS and a peripheral circuit structure PS. The cell array structure CS can include memory cells arranged three-dimensionally on a first base 100, and the peripheral circuit structure PS can include a core circuit and a peripheral circuit including a sense amplifier SA, a sub word line driver SWD, and an upper control circuit PP formed on a second base 200 and used to control the array of memory cells.

[0097] The detailed structure of the array of memory cells has been described with reference to Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7 and Figure 8 , and thus, only the bit lines BL and the word lines WL of the cell array structure CS are briefly illustrated in Figure 12 .

[0098] In detail, the cell array structure CS can include a bit line connection region BLB, a word line connection region WLB disposed at both sides of the bit line connection region BLB, and a first peripheral region PR1.

[0099] The word lines WL can be stacked along a third direction D3 perpendicular to a top surface of the first base 100. The word lines WL can be disposed on the bit line connection region BLB and the word line connection region WLB. The word lines WL can extend along a first direction D1 parallel to the top surface of the first base 100. Some of the word lines WL can have substantially the same length when measured along the first direction D1.

[0100] Word line pads (WLPs) can be positioned at opposite ends of each word line (WL). The word line pads (WLPs) can be stacked on the first substrate 100, forming a stepped structure within the word line connection area (WLB). The word line pads (WLPs) can be positioned at different horizontal and vertical locations relative to each other.

[0101] Bit line BL can extend along third direction D3 to intersect word line WL in bit line connection region BLB. Semiconductor pattern SP (e.g., see...) Figure 5A and 5B ) and data storage elements CAP (e.g., capacitors) (e.g., see Figures 13 to 16 and 5B This can be set at each intersection of the word line WL and the bit line BL. When measured along the third direction D3, the bit line BL can have substantially the same length.

[0102] As described above, the bit line connector BCL can be bonded to each bit line BL via a bit line contact plug BCP. A first lower metal pattern LM1 can be disposed on the bit line BL. Each bit line BL can be electrically connected to a first lower metal pad LMP1 via the first lower metal pattern LM1. The first lower metal pattern LM1 may include at least two metal patterns that are vertically stacked and connected to each other. In an example embodiment, the first lower metal pattern LM1 may include the bit line connector BCL described above and a bonding conductive pattern LP.

[0103] In the word line connection area WLB, word line contact plugs WPLG can be individually coupled to word line pads WLP. A second lower metal pattern LM2 can be coupled to a word line contact plug WPLG. The second lower metal pattern LM2 may comprise at least two metal patterns that are vertically stacked and connected to each other. Although the second lower metal pattern LM2 is illustrated as coupled to a single word line contact plug WPLG for clarity, it will be understood that the second lower metal pattern LM2 can be individually coupled to a word line contact plug WPLG. Each word line pad WLP can be electrically connected to a second lower metal pad LMP2 via the word line contact plug WPLG and the second lower metal pattern LM2.

[0104] In an example embodiment, a power capacitor PC used as a part of a lower control circuit that controls a sense amplifier and a sub word line driver can be disposed in the first peripheral region PR1 of the cell array structure CS. The power capacitor PC can constitute a voltage generator that receives a power supply voltage supplied through the input / output pad IOP and outputs an operating voltage to operate the memory cell array. In detail, the power capacitor PC can be a metal-insulator-metal (MIM) capacitor including a first electrode M1 and a second electrode M2 on the first base 100 and a dielectric layer MI between the first electrode M1 and the second electrode M2. A third lower metal pattern LM3, which can include at least two metal patterns stacked vertically and connected to each other, can be bonded to the power capacitor PC. The power capacitor PC can be electrically connected to the third lower metal pad LMP3 through a contact plug PLG and the third lower metal pattern LM3.

[0105] The first lower metal pattern LM1, the second lower metal pattern LM2, and the third lower metal pattern LM3 can be located at substantially the same level and can be formed of or include the same metal material (hereinafter, a first metal material). The first lower metal pad LMP1, the second lower metal pad LMP2, and the third lower metal pad LMP3 can be located at substantially the same level and can be formed of or include the same metal material (hereinafter, a second metal material). In some example embodiments, upper surfaces of the first lower metal pad LMP1, the second lower metal pad LMP2, and the third lower metal pad LMP3 can be coplanar. The second metal material can be different from the first metal material.

[0106] The peripheral circuit structure PS can include core circuits and peripheral circuits (e.g., the sense amplifiers SA, the sub word line drivers SWD, and the upper control circuit PP) formed on the second base 200 and used to control the memory cell array.

[0107] In detail, the peripheral circuit structure PS can include a first core region CR1, a second core region CR2, and a second peripheral region PR2.

[0108] The sense amplifiers SA can be disposed in the first core region CR1. Each sense amplifier SA can include NMOS transistors and PMOS transistors formed on the second base 200 and can be electrically connected to a pair of bit lines BL. Each sense amplifier SA can be configured to amplify a difference between voltages sensed through the pair of bit lines BL and provide the amplified voltage difference to a pair of local input / output lines.

[0109] Each sense amplifier SA can be electrically connected to a first upper metal pattern UM1. The first upper metal pattern UM1 can include at least two metal patterns which are vertically stacked and connected to each other. Each sense amplifier SA can be electrically connected to a first upper metal pad UMP1 through the first upper metal pattern UM1.

[0110] Sub word line drivers SWD for driving word lines WL, respectively, can be disposed in the second core region CR2. Each sub word line driver SWD can include an NMOS transistor and a PMOS transistor. A second upper metal pattern UM2 can be electrically connected to each sub word line driver SWD.

[0111] Each sub word line driver SWD can be electrically connected to the second upper metal pattern UM2. The second upper metal pattern UM2 can include at least two metal patterns which are vertically stacked and connected to each other. Each sub word line driver SWD can be electrically connected to a second upper metal pad UMP2 through the second upper metal pattern UM2.

[0112] Further, an upper control circuit PP which controls the sub word line drivers SWD and the sense amplifiers SA can be disposed in a second peripheral region PR2 of the peripheral circuit structure PS. The upper control circuit PP can be electrically connected to a third upper metal pattern UM3. The third upper metal pattern UM3 can include at least two metal patterns which are vertically stacked and connected to each other. The upper control circuit PP can be electrically connected to a third upper metal pad UMP3 through the third upper metal pattern UM3.

[0113] An input / output pad IOP can be disposed in the second peripheral region PR2 of the peripheral circuit structure PS. In detail, a passivation layer 201 can be disposed on a bottom surface (e.g., an outer lateral surface) of the second base 200, and the input / output pad IOP can be disposed on the passivation layer 201. The input / output pad IOP can be bonded to a portion of the third upper metal pattern UM3 through a through-silicon via TSV which penetrates the second base 200. A sidewall insulating layer TSI can be disposed between a sidewall of the through-silicon via TSV and the second base 200. The input / output pad IOP can be electrically connected to the upper control circuit PP through the through-silicon via TSV and the third upper metal pattern UM3.

[0114] The first, second, and third upper metal patterns UM1, UM2, and UM3 can be located at substantially the same level, and can be formed of or include the same metal material (hereinafter, a first metal material). The first, second, and third upper metal pads UMP1, UMP2, and UMP3 can be located at substantially the same level, and can be formed of or include the same metal material (hereinafter, a second metal material). In some example embodiments, lower surfaces of the first, second, and third upper metal pads UMP1, UMP2, and UMP3 can be coplanar. The second metal material can be different from the first metal material.

[0115] The first, second, and third upper metal pads UMP1, UMP2, and UMP3 can be in direct contact with the first, second, and third lower metal pads LMP1, LMP2, and LMP3, respectively. The first, second, and third upper metal pads UMP1, UMP2, and UMP3 can be formed of or include the same metal material as the metal material of the first, second, and third lower metal pads LMP1, LMP2, and LMP3. The first, second, and third upper metal pads UMP1, UMP2, and UMP3 can have substantially the same width as the width of the first, second, and third lower metal pads LMP1, LMP2, and LMP3, or can have substantially the same area as the area of the first, second, and third lower metal pads LMP1, LMP2, and LMP3.

[0116] Figure 12 FIG. 1 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to various example embodiments. For a brief description, reference is made to the previously described FIG. 1. Figure 13 The described elements can be identified, for brevity, through the use of the same reference numbers throughout the various figures and the text without repeated textual description of these elements.

[0117] Referring to Figure 14 The first, second, and third lower metal pads LMP1, LMP2, and LMP3 of the cell array structure CS can have different sizes from the sizes of the first, second, and third upper metal pads UMP1, UMP2, and UMP3. As an example, the sizes of the first, second, and third lower metal pads LMP1, LMP2, and LMP3 can be smaller than the sizes of the first, second, and third upper metal pads UMP1, UMP2, and UMP3.

[0118] Referring toFigure 15 The cell array structure CS can be combined to the peripheral circuit structure PS in such a way that the first, second, and third lower metal pads LMP1, LMP2, and LMP3 are slightly misaligned with the first, second, and third upper metal pads UMP1, UMP2, and UMP3. For example, portions of the first, second, and third lower metal pads LMP1, LMP2, and LMP3 can be in direct contact with portions of the first, second, and third upper metal pads UMP1, UMP2, and UMP3, respectively.

[0119] Referring to Figure 16 An input / output pad IOP can be disposed in the first peripheral region PR1 of the cell array structure CS. In detail, a passivation layer 102 can be disposed on a bottom surface (e.g., an outer lateral surface) of the first base 100, and the input / output pad IOP can be disposed on the passivation layer 102. The input / output pad IOP can be combined to a portion of the third lower metal pattern LM3 through a through-silicon via TSV that penetrates the first base 100. A sidewall insulating layer TSI can be disposed between sidewalls of the through-silicon via TSV and the first base 100. The input / output pad IOP can be electrically connected to a lower control circuit (e.g., a power capacitor PC) through the through-silicon via TSV and the third lower metal pattern LM3.

[0120] Referring to Figures 12 to 16 A lower input / output pad IOPa can be disposed on a back surface (e.g., an outer lateral surface) of the first base 100 and in the first peripheral region PR1. An upper input / output pad IOPb can be disposed on a back surface (e.g., an outer lateral surface) of the second base 200 and in the second peripheral region PR2.

[0121] A lower through-silicon via TSVa can be disposed to penetrate the first base 100 and connect the third lower metal pattern LM3 to the lower input / output pad IOPa. An upper through-silicon via TSVb can be disposed to penetrate the second base 200 and connect the third upper metal pattern UM3 to the upper input / output pad IOPb. A lower sidewall insulating layer TSIa can be disposed to enclose sidewalls of the lower through-silicon via TSVa, and an upper sidewall insulating layer TSIb can be disposed to enclose sidewalls of the upper through-silicon via TSVb.

[0122] In the example embodiment described with reference to Figures 17 to 22 The power capacitor PC is shown as being disposed on the first base 100 in the example embodiment described with reference to, but example embodiments are not limited to this example. For example, in some example embodiments, the power capacitor PC can be disposed on the second base 200, and the peripheral circuit (e.g., the upper control circuit PP) can be disposed on the first base 100. Alternatively, the upper control circuit PP can include the power capacitor PC.

[0123] Figures 17 to 22 is a diagram illustrating an example of the arrangement of lower and upper metal pads in a three-dimensional semiconductor memory device according to various example embodiments. Figures 17 to 22 An example of the arrangement of second lower and upper metal pads in a word line connection region of a three-dimensional semiconductor memory device according to example embodiments is shown. Although only the word line connection region is shown in Figures 17 to 22 , the first lower and upper metal pads in a bit line connection region can be arranged to have a similar arrangement to the second lower and upper metal pads to be described below. Figures 17 to 22 The first lower and upper metal pads in the bit line connection region can be arranged to have a similar arrangement to the second lower and upper metal pads to be described below.

[0124] In detail, reference is made to Figure 12 As previously described with reference to Figure 17 , the word line pads WLP can be arranged to form a stepped structure in the word line connection region WLB. When viewed in a plan view, the word line pads WLP can be arranged along a first direction D1 and can be spaced apart from each other along a second direction D2. The word line contact plugs WPLG can be respectively joined to the word line pads WLP.

[0125] As described above, the second lower and upper metal pads LMP2 and UMP2 can be electrically connected to the word line pads WLP respectively through the word line contact plugs WPLG. In some example embodiments, the second lower and upper metal pads LMP2 and UMP2 can be connected to the word line contact plugs WPLG in a one-to-one manner. However, in other example embodiments, some of the second lower and upper metal pads LMP2 and UMP2 can be connected to a plurality of word line contact plugs WPLG. The area of each of the second lower and upper metal pads LMP2 and UMP2 can be larger than the area of the word line contact plugs WPLG.

[0126] As shown in Figure 18 , Figure 19 and Figure 20 , each of the second lower and upper metal pads LMP2 and UMP2 can have a square shape or a rectangular shape. Alternatively, as shown in Figure 21 and Figure 22 , each of the second lower and upper metal pads LMP2 and UMP2 can have a circular shape. Alternatively, as shown in Figure 17 , each of the second lower and upper metal pads LMP2 and UMP2 can have a hexagonal shape.

[0127] Reference is made to Figure 18When viewed in plan view, the word line contact plugs WPLG can be arranged to be spaced apart from each other along the first direction D1 and the second direction D2, and the second lower metal pads LMP2 and the second upper metal pads UMP2 can be arranged to be spaced apart from each other along directions diagonal to the first direction D1 and the second direction D2. Portions of the second lower metal pads LMP2 and the second upper metal pads UMP2 can be respectively in contact with the word line contact plugs WPLG.

[0128] Referring to Figure 19 , the second lower metal pads LMP2 and the second upper metal pads UMP2 can be arranged to have substantially the same arrangement as the arrangement of the word line contact plugs WPLG. In other words, the second lower metal pads LMP2 and the second upper metal pads UMP2 can be arranged to be spaced apart from each other along the first direction D1 and the second direction D2, and the distance between the second lower metal pads LMP2 and the second upper metal pads UMP2 can be smaller than the distance between the word line contact plugs WPLG.

[0129] Referring to Figure 20 , the second lower metal pads LMP2 and the second upper metal pads UMP2 can be arranged to be spaced apart from each other along directions diagonal to the first direction D1 and the second direction D2. Some of the second lower metal pads LMP2 and the second upper metal pads UMP2 can not be overlapped with the word line contact plugs WPLG. Such second lower metal pads and second upper metal pads of the second lower metal pads LMP2 and the second upper metal pads UMP2 that are not overlapped with the word line contact plugs WPLG can be connected to the word line contact plugs WPLG through interconnection lines ICL.

[0130] Referring to Figure 21 , when viewed in plan view, the second lower metal pads LMP2 and the second upper metal pads UMP2 can be arranged in a honeycomb shape, but can not be overlapped with the word line contact plugs WPLG. The second lower metal pads LMP2 and the second upper metal pads UMP2 can be respectively electrically connected to the word line contact plugs WPLG through interconnection lines ICL.

[0131] Referring to Figure 22 , when viewed in plan view, the second lower metal pads LMP2 and the second upper metal pads UMP2 can be arranged in a honeycomb shape, and portions of the second lower metal pads LMP2 and the second upper metal pads UMP2 can be respectively bonded to the word line contact plugs WPLG.

[0132] Referring to ​ , each of the second lower metal pads LMP2 and the second upper metal pads UMP2 can be arranged to have a hexagonal shape. The second lower metal pads LMP2 and the second upper metal pads UMP2 can be arranged along directions diagonal to the first direction D1 and the second direction D2, and portions of the second lower metal pads LMP2 and the second upper metal pads UMP2 can be respectively bonded to the word line contact plugs WPLG.

[0133] According to various example embodiments, a bit line connection region of the cell array structure can be vertically overlapped with a first core region of the peripheral circuit structure, and a word line connection region of the cell array structure can be vertically overlapped with a second core region of the peripheral circuit structure. Accordingly, it can be possible to shorten signal transmission paths between the bit line and the sense amplifier and between the word line and the word line driver.

[0134] The memory cells on the first substrate and the core circuit and the peripheral circuit on the second substrate can be separately manufactured, and then the first substrate can be bonded to the second substrate. Accordingly, it can be possible to increase the integration density of the three-dimensional semiconductor memory device, reduce thermal budget applied to the core circuit and the peripheral circuit during a process of forming the memory cells, and reduce the size of the transistors.

[0135] Further, the control circuit can be vertically disposed at one side of the first substrate including the memory cells and at one side of the second substrate including the core circuit and the peripheral circuit, and thus, an area occupied by the control circuit can be reduced.

[0136] Although various example embodiments have been specifically illustrated and described, it will be appreciated by one of ordinary skill in the art that form and details can be varied without departing from the spirit and scope of the appended claims.

Claims

1. A three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: a first base including a bit line connection region and a word line connection region disposed at a side of the bit line connection region; a cell array structure on the first base; a second base including a first core region and a second core region, the first core region superposed with the bit line connection region, and the second core region superposed with the word line connection region; and a peripheral circuit structure on the second base, wherein the cell array structure includes word lines stacked on the first base, bit lines crossing the word lines in a first direction perpendicular to a top surface of the first base, first lower metal pads disposed on the bit line connection region and connected to the bit lines, and second lower metal pads disposed on the word line connection region and connected to the word lines, wherein the peripheral circuit structure includes sense amplifiers disposed on the first core region, sub word line drivers disposed on the second core region, first upper metal pads disposed on the first core region and connected to the sense amplifiers, and second upper metal pads disposed on the second core region and connected to the sub word line drivers, wherein the first lower metal pads are bonded to the first upper metal pads, and the second lower metal pads are bonded to the second upper metal pads. the cell array structure further includes memory cells respectively disposed at intersections of the word lines and the bit lines, 2. The three-dimensional semiconductor memory device of claim 1, wherein, each of the memory cells includes a cell transistor and a capacitor, the capacitor connected to one end of the cell transistor, the cell transistor includes a semiconductor pattern parallel to the top surface of the first base, and the capacitor is connected to one end of the semiconductor pattern and includes a storage electrode parallel to the top surface of the first base. the word lines extend in a second direction parallel to the top surface of the first base, and 3. The three-dimensional semiconductor memory device of claim 1, wherein, the bit lines are arranged to be spaced apart from each other in the second direction and a third direction intersecting the first direction and the second direction. the cell array structure further includes bit line connection lines disposed between the bit lines and the first lower metal pads when viewed in a cross-sectional view, 4. The three-dimensional semiconductor memory device of claim 3, wherein, the bit line connection lines extend in the third direction and are parallel to each other, and each of the bit line connection lines is connected to the bit lines arranged in the third direction. each of the first lower metal pads is superposed with at least two of the bit line connection lines when viewed in a plan view.

5. The three-dimensional semiconductor memory device of claim 4, wherein, the cell array structure further includes bonding conductive patterns disposed between the bit line connection lines and the first lower metal pads when viewed in a top view, and 6. The three-dimensional semiconductor memory device of claim 4, wherein, the bonding conductive patterns extend in the second direction to cross at least two of the bit line connection lines. each of the bonding conductive patterns is connected to a corresponding one of the bit line connection lines.

7. The three-dimensional semiconductor memory device of claim 6, wherein, each of the first lower metal pads has a first width and each of the bonding conductive patterns has a second width when measured in the first direction, and the first width is greater than the second width.

8. The three-dimensional semiconductor memory device of claim 6, wherein, the word lines extend in a second direction parallel to the top surface of the first base, 9. The three-dimensional semiconductor memory device of claim 1, wherein, each of the word lines has a word line pad on the word line connection region, the plurality of word line pads are stacked to form a staircase structure on the word line connection region, and the second lower metal pads are connected to the plurality of word line pads. word line pads among the plurality of word line pads located at the same level from the first base are spaced apart from each other in a third direction intersecting the second direction, and 10. The three-dimensional semiconductor memory device of claim 9, wherein, ​ Each of the plurality of word line pads has a first width when measured along the third direction, and each of the second lower metal pads has a second width that is greater than the first width.

11. A three-dimensional semiconductor memory device, comprising: a first base including a memory cell array region and a first peripheral region provided at a side of the memory cell array region, the memory cell array region including a bit line connection region and a word line connection region; a cell array structure including a memory cell array including memory cells arranged three-dimensionally on the bit line connection region and the word line connection region of the first base, and including a lower control circuit provided on the first peripheral region of the first base; a second base including a first core region, a second core region, and a second peripheral region, the first core region being superposed with the bit line connection region, the second core region being superposed with the word line connection region, and the second peripheral region being superposed with the first peripheral region; and a peripheral circuit structure including a sense amplifier provided on the first core region of the second base, a sub word line driver provided on the second core region of the second base, and an upper control circuit provided on the second peripheral region of the second base.

12. The three-dimensional semiconductor memory device of claim 11, wherein, The cell array structure includes lower metal pads, the peripheral circuit structure includes upper metal pads, and the cell array structure is bonded to the peripheral circuit structure by bonding between the lower metal pads and the upper metal pads.

13. The three-dimensional semiconductor memory device of claim 11, wherein, The cell array structure includes first lower metal pads, second lower metal pads, and third lower metal pads, the first lower metal pads being connected to bit lines of the memory cell array, the second lower metal pads being connected to word lines of the memory cell array, and the third lower metal pads being connected to the lower control circuit, The peripheral circuit structure includes first upper metal pads connected to the sense amplifier, second upper metal pads connected to the sub word line driver, and third upper metal pads connected to the upper control circuit, and The first lower metal pads are bonded to the first upper metal pads, the second lower metal pads are bonded to the second upper metal pads, and the third lower metal pads are bonded to the third upper metal pads.

14. The three-dimensional semiconductor memory device of claim 11, wherein, At least one of the upper control circuit and the lower control circuit includes a power capacitor.

15. The three-dimensional semiconductor memory device of claim 11, further comprising: a through plug penetrating the first base on the first peripheral region; and an input / output pad provided on an outer side surface of the first base and bonded to the through plug.

16. The three-dimensional semiconductor memory device of claim 11, further comprising: a through plug penetrating the second base on the second peripheral region; and an input / output pad provided on an outer side surface of the second base and bonded to the through plug.

17. A three-dimensional semiconductor memory device, comprising: a first base including a memory cell array region and a first peripheral region provided at a side of the memory cell array region, the memory cell array region including a bit line connection region and a word line connection region; a cell array structure including a memory cell array including memory cells arranged three-dimensionally on the bit line connection region and the word line connection region of the first base, and including a lower control circuit provided on the first peripheral region of the first base; a second base including a first core region, a second core region, and a second peripheral region, the first core region being superposed with the bit line connection region, the second core region being superposed with the word line connection region, and the second peripheral region being superposed with the first peripheral region; and a peripheral circuit structure including a sense amplifier provided on the first core region of the second base, a sub word line driver provided on the second core region of the second base, and an upper control circuit provided on the second peripheral region of the second base. The unit array structure is located on the first substrate and includes: bit lines extending in a first direction perpendicular to a top surface of the first substrate; word lines extending in a second direction parallel to the top surface of the first substrate to cross the bit lines; memory cells disposed at intersections of the bit lines and the word lines; first lower metal pads disposed on the bit line connection region and connected to the bit lines; second lower metal pads disposed on the word line connection region and connected to the word lines; and third lower metal pads disposed on the first peripheral region and connected to the lower control circuit; The second substrate includes a first core region, a second core region, and a second peripheral region, the first core region is superimposed with the bit line connection region, the second core region is superimposed with the word line connection region, and the second peripheral region is superimposed with the first peripheral region; and The peripheral circuit structure is located on the second substrate and includes: first upper metal pads disposed on the first core region and connected to the sense amplifiers; second upper metal pads disposed on the second core region and connected to the sub-word line drivers; and third upper metal pads disposed on the second peripheral region and connected to the upper control circuit, The first lower metal pads are bonded to the first upper metal pads, The second lower metal pads are bonded to the second upper metal pads, and The third lower metal pads are bonded to the third upper metal pads.

18. The three-dimensional semiconductor memory device of claim 17, wherein, At least one of the upper control circuit and the lower control circuit includes a power capacitor.

19. The three-dimensional semiconductor memory device of claim 17, wherein, The peripheral circuit structure further includes: A through plug disposed to penetrate the second substrate on the second peripheral region and electrically connected to the upper control circuit; A sidewall insulating layer covering sidewalls of the through plug; and An input / output pad disposed on an outer side surface of the second substrate and connected to the through plug.

20. The three-dimensional semiconductor memory device of claim 17, wherein, Each of the memory cells includes a cell transistor and a capacitor, the capacitor is connected to one end of the cell transistor, The cell transistor includes a semiconductor pattern parallel to the top surface of the first substrate, and The capacitor is connected to one end of the semiconductor pattern and includes a storage electrode parallel to the top surface of the first substrate.

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