Three-dimensional memory and methods of making the same

Abstract

The disclosure provides a three-dimensional memory and a preparation method thereof, and relates to the technical field of semiconductor chips, aiming to improve the yield of three-dimensional memories. The preparation method comprises the following steps: preparing a semiconductor structure; removing part of the side wall of the second dielectric layer covering the gate line gap; forming a filling structure in the gate line gap; removing the substrate; and forming a source layer on one side of the removed substrate of the laminated structure. The semiconductor structure comprises a substrate and a laminated structure arranged on the substrate. The laminated structure comprises alternately arranged first dielectric layers and gate layers. The semiconductor structure further comprises a gate line gap and a second dielectric layer. The gate line gap penetrates through the laminated structure in a direction perpendicular to the substrate and extends into the substrate. The second dielectric layer is arranged between the first dielectric layer and the gate layer and covers the side wall of the gate line gap. The disclosure is used for preparing three-dimensional memories.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a three-dimensional memory and its fabrication method. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate.

[0004] Improving the reliability of the 3D memory fabrication process and increasing the yield of 3D memory products are urgent problems to be solved. Summary of the Invention

[0005] The embodiments of this disclosure provide a three-dimensional memory and a method for fabricating the same.

[0006] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0007] On one hand, a method for fabricating a three-dimensional memory is provided. The method includes: fabricating a semiconductor structure; removing a portion of the sidewalls of a second dielectric layer covering the gate line slots; forming a filling structure within the gate line slots; removing the substrate; and forming a source layer on the side of the stacked structure where the substrate has been removed. The semiconductor structure includes a substrate, a stacked structure, and a second dielectric layer. The stacked structure includes a plurality of alternating first dielectric layers and a plurality of gate layers. The second dielectric layer is disposed between the gate layers and the first dielectric layers. The semiconductor structure further includes gate line slots that penetrate the stacked structure along a direction perpendicular to the substrate and extend into the substrate. The second dielectric layer also covers the sidewalls of the gate line slots.

[0008] In some embodiments, recesses are formed between adjacent first dielectric layers along a direction perpendicular to the substrate. The fabrication method further includes forming a protective layer within the recesses before removing portions of the second dielectric layer that cover the sidewalls of the gate line gaps. The protective layer covers the sides of the gate layer exposed by the gate line gaps.

[0009] In some embodiments, forming the protective layer in the recess comprises: forming an initial protective layer in the gate line gap, the initial protective layer filling the recess and covering sidewalls and a bottom of the gate line gap; removing portions of the initial protective layer covering the sidewalls and the bottom of the gate line gap, leaving portions filling in the recess, forming the protective layer.

[0010] In some embodiments, the second dielectric layer also covers surfaces of the stack structure away from the substrate and a bottom of the gate line gap. Before forming the protective layer in the recess, the method further comprises: removing portions of the second dielectric layer covering the surfaces of the stack structure away from the substrate and the bottom of the gate line gap.

[0011] In some embodiments, the method of preparing a semiconductor structure comprises: forming an initial stack structure on the substrate; forming a gate line gap through the initial stack structure in a direction perpendicular to the substrate; removing gate sacrificial layers in the initial stack structure through the gate line gap, forming a gate layer gap in communication with the gate line gap; sequentially forming a second dielectric layer and a gate layer in the gate layer gap through the gate line gap. Wherein, the initial stack structure comprises a plurality of first dielectric layers and a plurality of gate sacrificial layers arranged alternately.

[0012] In some embodiments, forming the gate layer comprises: forming an initial gate layer, the initial gate layer filling the gate layer gap and covering sidewalls of the gate line gap and surfaces of the stack structure away from the substrate; removing portions of the initial gate layer covering the sidewalls of the gate line gap and the surfaces of the stack structure away from the substrate; removing portions of the initial gate layer filling the gate layer gap close to the gate line gap, forming the gate layer.

[0013] In some embodiments, between forming the second dielectric layer and forming the gate layer, the method further comprises: forming an initial adhesion layer in the gate layer gap, the initial adhesion layer covering the second dielectric layer; in the process of removing the initial gate layer to form the gate layer, portions of the initial adhesion layer exposed by the gate layer are also removed, forming an adhesion layer.

[0014] In some embodiments, forming a filling structure in the gate line gap comprises: forming an isolation layer in the gate line gap, the isolation layer covering sidewalls of the gate line gap, forming a filling gap; forming a filling portion in the filling gap.

[0015] In some embodiments, the semiconductor structure further comprises a third dielectric layer and a semiconductor layer disposed between the substrate and the stack structure, the third dielectric layer being closer to the substrate than the semiconductor layer. Removing the substrate comprises etching the substrate to the third dielectric layer to expose a portion of the isolation layer of the filling structure extending into the substrate; between removing the substrate and forming the source layer, the preparation method further comprises etching the third dielectric layer and the exposed portion of the isolation layer to the semiconductor layer to expose a filling portion of the filling structure; the source layer covers the exposed portion of the filling portion and is in contact with the filling portion.

[0016] In some embodiments, the semiconductor structure further comprises a channel structure extending into the substrate, the channel structure comprising a channel hole and a functional layer and a channel layer sequentially formed in the channel hole. The etching the substrate to the third dielectric layer also exposes a portion of the functional layer of the channel structure extending into the substrate. In the process of etching the third dielectric layer and the exposed portion of the isolation layer to the semiconductor layer, the exposed portion of the functional layer is also etched to expose a portion of the channel layer extending into the substrate. The source layer also covers the exposed portion of the channel layer and is in electrical connection with the channel layer.

[0017] In some embodiments, the material of the third dielectric layer and the isolation layer of the filling structure both comprise silicon oxide; the material of the semiconductor layer and the filling portion of the filling structure both comprise polysilicon.

[0018] In some embodiments, the material of the second dielectric layer comprises a high dielectric constant material.

[0019] In another aspect, a method for manufacturing a three-dimensional memory is provided. The method includes providing a substrate; forming an initial stack structure on the substrate; forming a gate line slit; removing a gate sacrificial layer in the initial stack structure through the gate line slit to form a gate layer gap in communication with the gate line slit; forming a second dielectric layer; filling an initial gate layer, the initial gate layer filling the gate layer gap and covering sidewalls of the gate line slit; removing portions of the initial gate layer covering the sidewalls of the gate line slit and portions of the initial gate layer adjacent to the gate line slit to form a recess; forming a protection layer in the recess, the protection layer covering exposed sidewalls of the gate layer; removing portions of the second dielectric layer covering the sidewalls of the gate line slit; forming a filling structure in the gate line slit; removing the substrate; and forming a source layer on a side of the stack structure opposite to the substrate. The initial stack structure includes a plurality of first dielectric layers and a plurality of gate sacrificial layers arranged alternately. The gate line slit extends through the initial stack structure in a direction perpendicular to the substrate and into the substrate. The second dielectric layer covers sidewalls of the gate layer gap and sidewalls of the gate line slit.

[0020] The method for manufacturing a three-dimensional memory provided by the above embodiments of the present disclosure includes removing portions of the second dielectric layer covering the sidewalls of the gate line slit, so that the first dielectric layer can be in direct contact with the filling structure. The bonding force between the first dielectric layer and the filling structure is greater than the bonding force between the first dielectric layer and the second dielectric layer, thereby reducing the risk of a gap between the first dielectric layer and the filling structure, reducing damage to the stack structure (the first dielectric layer) during subsequent removal of the substrate, improving the reliability of the three-dimensional memory manufacturing process, and improving the yield of the three-dimensional memory.

[0021] In yet another aspect, a three-dimensional memory is provided. The three-dimensional memory includes a source layer, a stack structure, a channel structure, a second dielectric layer, and a gate line isolation structure. The stack structure is disposed on a side of the source layer and includes a plurality of first dielectric layers and a plurality of gate layers arranged alternately. The channel structure extends through the stack structure in a direction perpendicular to the source layer and into the source layer, and includes a functional layer and a semiconductor layer, the semiconductor layer being electrically connected to the source layer. The second dielectric layer is disposed between the gate layers and the first dielectric layers. The gate line isolation structure extends through the stack structure in a direction perpendicular to the source layer and into the source layer, and is in contact with the first dielectric layers.

[0022] In some embodiments, the first dielectric layers adjacent to each other have a recess therebetween in a direction perpendicular to the substrate. The gate line isolation structure is filled in the recess.

[0023] In some embodiments, the material of the second dielectric layer comprises a high dielectric constant material.

[0024] It can be understood that the three-dimensional memory provided by the above-described embodiments of the present disclosure has the beneficial effects that can be achieved by the method for manufacturing the three-dimensional memory, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0026] Figure 1 a three-dimensional memory provided by the embodiments of the present disclosure;

[0027] Figure 2 another three-dimensional memory provided by the embodiments of the present disclosure;

[0028] Figures 3A-3E a flowchart of the method for manufacturing the three-dimensional memory according to some embodiments;

[0029] Figures 4A-4L structure diagrams corresponding to each step in the method for manufacturing the three-dimensional memory according to some embodiments;

[0030] Figure 5 a structure diagram of the three-dimensional memory according to some embodiments;

[0031] Figure 6 a structure diagram of the three-dimensional memory according to some embodiments. DETAILED DESCRIPTION

[0032] The technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present disclosure.

[0033] In the description of the present disclosure, it needs to be understood that the terms "upper", "lower", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0034] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise", "comprising", and the like are to be construed in an open, inclusive and a non-exclusive sense; that is, as "comprising, but not limited to." In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplary", or "some examples" are intended to mean that a particular feature, structure, material, or characteristic included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any appropriate manner in any one or more embodiments or examples.

[0035] Hereinafter, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0036] In describing some embodiments, "connected" and its derivatives can be used. For example, the term "connected" can be used to describe some embodiments in which two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the context.

[0037] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0038] The use of "adapted for" or "configured for" herein means open and inclusive language that does not exclude devices adapted for or configured for performing additional tasks or steps.

[0039] In the present disclosure, the meaning of "on," "over," and "above" should be construed in the broadest context, such that "on" means not only "directly on" but also "on" with intervening features or layers therebetween, and "over" or "above" means not only "over" or "above" but also "over" or "above" with no intervening features or layers therebetween (i.e., directly on).

[0040] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

[0041] The term "three-dimensional memory" refers to a semiconductor device formed of memory cell transistor strings (referred to herein as "memory cell strings," e.g., NAND memory cell strings) that are arrayed on a major surface of a substrate and extend in a direction perpendicular to the substrate. As used herein, the term "perpendicular / perpendicularly" means nominally perpendicular to a major surface (i.e., lateral surface) of a substrate.

[0042] The steps provided in the embodiments of the present disclosure are not exclusive and other steps can be performed before, after, or between any of the steps. Further, some of the steps can be performed simultaneously or in an order different from that described in the embodiments.

[0043] Some embodiments of the present disclosure provide a three-dimensional memory 100, referring to Figure 1 including a substrate 10 and a third dielectric layer 11, a semiconductor layer 12, and a stack structure 21 formed successively above the substrate 10. The stack structure 21 includes a first dielectric layer 131 and a gate layer 19 disposed successively. The three-dimensional memory 100 further includes a gate line slit 16 extending into the substrate 10, a second dielectric layer 17 disposed between the first dielectric layer 131 and the gate layer 19, and an adhesion layer 18 disposed between the gate layer 19 and the second dielectric layer 17. The second dielectric layer 17 covers a sidewall of the gate line slit 16.

[0044] In the three-dimensional memory 100, the third dielectric layer 11 and the semiconductor layer 12 can be configured as etching stop layers in the etching process of removing the substrate 10. Specifically, the etching rate of the material of the third dielectric layer 11 can be different from the etching rate of the material of the semiconductor layer 12. Exemplarily, the material of the third dielectric layer 11 includes silicon oxide, and the material of the semiconductor layer 12 includes polysilicon. The bonding force between the second dielectric layer 17 and the third dielectric layer 11 and the semiconductor layer 12 is low, and under the action of stress, a gap 1001 can even appear between the second dielectric layer 17 and the third dielectric layer 11 and the semiconductor layer 12.

[0045] In the subsequent process of preparing the three-dimensional memory, it is necessary to remove the substrate 10 and the third dielectric layer 11 from the side of the substrate 10 away from the stack structure 21 by wet etching, and to form a source layer 24 (as shown in Figure 2 ) on the surface exposed after the substrate 10 and the third dielectric layer 11 are removed (the side of the semiconductor layer 12 away from the stack structure 21).

[0046] In the process of removing the substrate 10 by wet etching, the etching liquid can flow into the above-mentioned gap and come into contact with the semiconductor layer 12, thereby removing part of the semiconductor layer 12 and exposing part of the first dielectric layer 131.

[0047] In the process of removing the third dielectric layer 11 by wet etching, the etching liquid comes into contact with the exposed first dielectric layer 131 and removes part of the exposed first dielectric layer 131, resulting in a groove 1002 on the surface of the first dielectric layer 131.

[0048] Part of the source layer 24 formed is located in the above-mentioned groove 1002. In this way, the three-dimensional memory as shown in Figure 2 may be formed, and the spacing between the bottom gate layer 191 and the source layer 24 is small, resulting in a low breakdown voltage between the two and a risk of short circuit between the gate layer 191 and the source layer 24. That is, the preparation process of the above-mentioned three-dimensional memory has poor stability.

[0049] To solve the above-mentioned problems, referring to Figure 3A , embodiments of the present disclosure provide a preparation method of a three-dimensional memory, which comprises steps S100-S500.

[0050] S100: preparing a semiconductor structure 100.

[0051] Referring to Figure 3B and Figures 4A-4D , in some embodiments, the step of preparing the semiconductor structure comprises steps S110-S160. Among them, Figure 3B is a step diagram of a semiconductor structure preparation method; Figures 4A-4DA cross-sectional view corresponding to each step in the semiconductor structure preparation method.

[0052] S110: Referring to Figure 4A The third dielectric layer 11, the semiconductor layer 12, and the initial stack structure 13 are sequentially formed on the substrate 10.

[0053] In some embodiments, the material of the substrate 10 can include at least one of single crystal silicon (Si), single crystal germanium (Ge), a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials known in the art.

[0054] In other embodiments, the substrate 10 can be a composite substrate. For example, Figure 4A The substrate 10 can include a base 101, and a sacrificial insulating layer 102 and a sacrificial polysilicon layer 103 sequentially formed on the base 101. The material of the base 101 can include at least one of single crystal silicon (Si), single crystal germanium (Ge), a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials known in the art. The material of the sacrificial insulating layer 102 can include silicon oxide. The material of the sacrificial polysilicon layer 103 can include polysilicon.

[0055] The third dielectric layer 11 is formed on the substrate 110, and the semiconductor layer 12 is formed on the third dielectric layer 11. It should be understood that the third dielectric layer 11 and the semiconductor layer 12 can both be etching stop layers configured to stop etching at the corresponding film layer during the subsequent step S400 of removing the substrate 10. The materials (etching selectivity ratio) of the third dielectric layer 11 and the semiconductor layer 12 are different, so that etching can stop at the interface between the two.

[0056] For example, the third dielectric layer 11 and the semiconductor layer 12 can be prepared by one of a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In the case where the substrate 10 includes the base 101, the sacrificial insulating layer 102, and the sacrificial polysilicon layer 103, the material of the third dielectric layer 11 can include silicon oxide, and the material of the semiconductor layer 12 can include polysilicon.

[0057] The initial stack structure 13 includes a plurality of first dielectric layers 131 and a plurality of gate sacrificial layers 132 alternately arranged on the semiconductor layer 12. The formation method of the initial stack structure 13 can include one or more of CVD, PVD, and ALD.

[0058] In the initial stack structure 13, the stack of the first dielectric layer 131 and the gate sacrificial layer 132 can be 8 layers, 32 layers, 64 layers, 128 layers, etc., which is not limited herein. The more layers of the initial stack structure 13, the higher the integration, and the more the number of memory cells formed therefrom.

[0059] In some embodiments, the first dielectric layer 131 and the gate sacrificial layer 132 are of different materials, so that they have different etching selectivity ratios. In the subsequent step S130 of removing the gate sacrificial layer 132 in the initial stack structure 130, the first dielectric layer 131 will not be etched away. For example, the material of the first dielectric layer 131 can be silicon oxide, and the material of the gate sacrificial layer 132 can be silicon nitride.

[0060] In some embodiments, the step of preparing the semiconductor structure further comprises S111.

[0061] S111: Referring to Figure 4B , the channel structure 14 is made.

[0062] The channel structure 14 can be made specifically by: forming a channel hole 141 extending through the initial stack structure 13, the third dielectric layer 11, and the semiconductor layer 12, and extending into the substrate 10 (the vertical direction extending sidewall of the channel structure 14 in the initial stack structure 13); and sequentially forming a functional layer 142 and a channel layer 143 on the sidewall of the channel hole 141. Figure 4A

[0063] For example, the channel hole 141 can be formed in the initial stack structure 13 by a dry / wet etching process, and the channel hole 141 extends in a direction perpendicular to the substrate 10. In the case where the substrate 10 includes a base 101, a sacrificial insulating layer 102, and a sacrificial polysilicon layer 103, the channel hole 141 can extend to the sacrificial polysilicon layer 103 of the substrate 10, and the sacrificial polysilicon layer 103 can act as an etching stop layer to control the change of the gouging of the channel hole 141. For example, the etching of the channel hole 141 can be stopped by the sacrificial polysilicon layer 103, so that the channel hole 141 does not further extend into the sacrificial insulating layer 102 and the base 101.

[0064] For example, the barrier layer 1421, the charge storage layer 1422, the tunneling layer 1423, and the channel layer 143 can be sequentially formed on the inner wall of the channel hole 141 by one or more of CVD, PVD, and ALD processes. The barrier layer 1421, the charge storage layer 1422, and the tunneling layer 1423 constitute the functional layer 142. The middle of the channel layer 143 can form an air gap 144 to reduce the stress on the channel layer 143.

[0065] ​The materials of the blocking layer 1421, the charge storage layer 1422, the tunneling layer 1423 and the channel layer 143 can be silicon oxide, silicon nitride, silicon oxide and polysilicon, respectively, to form an "ONOP" structure.

[0066] In some embodiments, fabricating the channel structure 14 can further include forming a channel plug (not shown in the figure) at an end of the blocking layer 1421, the charge storage layer 1422, the tunneling layer 1423 and the channel layer 143 away from the substrate 10, the material of the channel plug can be the same as that of the channel layer 143. The channel plug is configured to form a drain of the channel structure 140.

[0067] In some embodiments, fabricating the channel structure 14 can further include forming a dummy channel structure 15 at the step region A, the dummy channel structure 15 is configured to provide a supporting force for the semiconductor structure 100. The material of the dummy channel structure 15 can be a dielectric material, for example, silicon oxide.

[0068] S120: referring to Figure 4C , forming a gate line gap 16 through the initial stack structure 13 in a direction perpendicular to the substrate.

[0069] For example, the gate line gap 16 can be formed in the initial stack structure 13 by a dry / wet etching process, the gate line gap 16 extends in a direction perpendicular to the substrate 10, and the gate line gap 16 extends into the substrate 10. The gate line gap 16 has a certain distance from the channel structure 14. The depth of the gate line gap 16 extending into the substrate 10 can be the same as or different from the depth of the channel structure 14 extending into the substrate 10.

[0070] S130: referring to Figure 4C , removing the gate sacrificial layer 132 in the initial stack structure 13 through the gate line gap 16 to form a gate interlayer gap 133 communicating with the gate line gap 16.

[0071] For example, the gate sacrificial layer 132 in the initial stack structure 13 is removed by a wet etching process through the gate line gap 16, and the gate interlayer gap 133 is formed at the position of the gate sacrificial layer 132. Under the support of the channel structure 14 and the dummy channel 15, the first dielectric layer 131 of the initial stack structure 13 will not collapse into the gate interlayer gap 133.

[0072] S140: referring to Figure 4D , sequentially forming the second dielectric layer 17 and the gate layer 19 in the gate interlayer gap 133 through the gate line gap 16.

[0073] Exemplarily, the second dielectric layer 17 can be formed by a thin film deposition process such as CVD, PVD, ALD, etc. The second dielectric layer 17 covers the inner wall of the gate layer gap 133, the side wall and the bottom wall of the gate line gap 16, the surface of the initial stack structure 13 away from the substrate 10, and the surface of the channel structure 14 exposed by the gate line gap 16. The material of the second dielectric layer 17 can include a material with high dielectric constant, such as aluminum oxide.

[0074] The gate layer 19 can also be formed by a thin film deposition process such as CVD, PVD, ALD, etc. The gate layer 19 is located in the gate layer gap 133. The material of the gate layer 19 can include at least one conductive material such as tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicide.

[0075] In some embodiments, between the formation of the second dielectric layer 17 and the gate layer 19, S140 further includes: forming an initial adhesion layer in the gate layer gap 133, the initial adhesion layer covering the second dielectric layer 17. Exemplarily, the initial adhesion layer 18 can be formed by a thin film deposition process such as CVD, PVD, ALD, etc. The material of the initial adhesion layer 127 can include tantalum nitride or titanium nitride. The initial adhesion layer 127 helps to increase the adhesion between the second dielectric layer 17 and the gate layer 19.

[0076] In some embodiments, referring to Figure 4D , a portion of the gate layer 19 near the edge of the gate line gap 16 is removed, so that the edge of the gate layer 19 near the gate line gap 16 is recessed relative to the edge of the first dielectric layer 131 near the gate line gap 16, thereby forming a recess 20 at the edge of the gate layer 19 near the gate line gap 16; that is, between the adjacent first dielectric layers 131 in a direction perpendicular to the substrate 10. In this way, referring to Figure 3C , the above step S140 of forming the gate layer 19 can include steps S141-S143.

[0077] S141: forming an initial gate layer. The initial gate layer fills the gate layer gap 133 and covers the side wall of the gate line gap 16 and the surface of the stack structure 21 away from the substrate 10.

[0078] Exemplarily, the initial gate layer can be formed by a thin film deposition process such as CVD, PVD, ALD, etc.

[0079] It should be understood that the initial adhesion layer is located between the second dielectric layer 17 and the initial gate layer.

[0080] S142: removing a portion of the initial gate layer covering the side wall of the gate line gap 16 and the surface of the stack structure 21 away from the substrate 10.

[0081] For example, the portions of the initial gate layer covering the sidewalls of the gate line gap 16 and the stack structure 21 away from the surface of the substrate 10 can be removed by an etching process.

[0082] S143: removing the portions of the initial gate layer filling the gate layer gap 133 to form the gate layer 19, and simultaneously forming the recess 20.

[0083] For example, the portions of the initial gate layer close to the gate line gap 16 and the portions of the adhesive layer 18 close to the gate line gap 16 can be removed by an etching process to form the recess 20.

[0084] In some embodiments, during the removal of the portions of the initial gate layer in S142 and S143, the portions of the initial adhesive layer exposed by the initial gate layer are also removed to form the adhesive layer 18.

[0085] For example, during the removal of the portions of the initial gate layer covering the sidewalls of the gate line gap 16 in S142, the portions of the initial adhesive layer covering the sidewalls of the gate line gap 16 are also removed. During the removal of the portions of the initial gate layer filling the gate layer gap 133 in S143, the portions of the initial adhesive layer close to the gate line gap 16 are also removed.

[0086] In other embodiments, the portions of the initial adhesive layer covering the sidewalls and the bottom wall of the gate line gap 16 and the portions of the initial adhesive layer covering the sidewalls of the recess 20 can also be removed by an etching process after the formation of the gate layer 19 in S140.

[0087] After the above steps S110-S140, the semiconductor structure 100 is formed as shown in Figure 4D The semiconductor structure 100 includes the substrate 10, and the third dielectric layer 11, the semiconductor layer 12 and the stack structure 21 disposed on the substrate 10 in sequence. The stack structure 21 includes the plurality of first dielectric layers 131 and the plurality of gate layers 19 disposed alternately. The semiconductor structure 100 also includes the gate line gap 16 extending into the substrate 10 and the second dielectric layer 17. The second dielectric layer 17 is between the gate layer 19 and the first dielectric layer 131, and covers the bottom wall and the sidewalls of the gate line gap 16 and the surface of the initial stack structure 13 away from the surface of the substrate 10.

[0088] In some embodiments, referring to Figure 3B After the above step S140, the method for manufacturing the semiconductor further includes a step S150.

[0089] S150: referring to Figure 4E , removing the portions of the second dielectric layer 17 covering the surface of the stack structure 13 and the bottom of the gate line gap 16.

[0090] Exemplarily, the portions of the second dielectric layer 17 covering the surfaces of the stack structure 13 away from the substrate 10 and the bottom of the gate line gap 16 can be removed by a dry etching process.

[0091] In the case that the recesses 20 are between the adjacent first dielectric layers 131, referring to Figure 3B , the method of manufacturing the three-dimensional memory further comprises a step S160.

[0092] S160: referring to Figure 4F and Figure 4G , forming a protection layer 22 in the recesses 20.

[0093] As shown in Figure 4G , the protection layer 22 covers the side of the gate layer 19 exposed by the gate line gap 16. The protection layer 22 can protect the side of the gate layer 19 exposed by the gate line gap 16 from damage in the subsequent step S200 of removing the portions of the second dielectric layer 17 covering the sidewalls of the gate line gap 16.

[0094] In some embodiments, referring to Figure 3D , the step S160 of forming the protection layer 22 in the recesses 20 can comprise steps S161-S162.

[0095] S161: referring to Figure 4F , forming an initial protection layer 22' in the gate line gap 16.

[0096] Exemplarily, the initial protection layer 22' can be formed by a thin film deposition process such as CVD, PVD, ALD, etc. The material of the protection layer 22 can comprise a dielectric material such as silicon oxide or silicon nitride. The initial protection layer 22' fills the recesses 20 and covers the sidewalls and the bottom of the gate line gap 16.

[0097] S162: referring to Figure 4G , removing the portions of the initial protection layer 22' covering the sidewalls and the bottom of the gate line gap 16, and leaving the portions filling in the recesses 20 to form the protection layer 22.

[0098] Exemplarily, the portions of the initial protection layer 22' covering the sidewalls and the bottom of the gate line gap 16 can be removed by an etching process to form the protection layer 22 in the recesses 20. The protection layer 22 can protect the side of the gate layer 19 exposed by the gate line gap 16 from damage in the subsequent step S200 of removing the portions of the second dielectric layer 17 covering the sidewalls of the gate line gap 16.

[0099] S200: referring to Figure 4H , removing the portions of the second dielectric layer 17 covering the sidewalls of the gate line gap 16.

[0100] In some embodiments, the part of the second dielectric layer 17 covering the sidewall of the gate line gap 16 can be removed by a wet etching process. The process flow is simple, has little impact on the existing process flow, is low in cost, and the etching process does not affect the stack structure 21 near the sidewall of the gate line gap 16.

[0101] S300: forming a filling structure 23 in the gate line gap 16.

[0102] In some embodiments, referring to Figure 3E S300 of forming the filling structure 23 in the gate line gap 16 includes steps S310-S330.

[0103] S310: referring to Figure 4I forming an isolation layer 231 in the gate line gap 16. The isolation layer 231 covers the inner surface (sidewall and bottom) of the gate line gap 16 to form a filling gap.

[0104] In some embodiments, the isolation layer 231 can be formed by a thin film deposition process such as CVD, PVD, ALD, etc., and the filling gap is located in the isolation layer 231. The material of the isolation layer 231 is a dielectric material, and the material of the isolation layer 231 can be silicon oxide or silicon nitride, etc. for example.

[0105] It should be understood that the material of the isolation layer 231 formed by the thin film deposition process also covers the surface of the stack structure 21 away from the substrate 10.

[0106] S320: forming a filling part 232 in the filling gap.

[0107] In some embodiments, the filling part 232 can be formed by a thin film deposition process such as CVD, PVD, ALD, etc., and the material of the filling part 232 can include at least one of tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicide.

[0108] In other embodiments, the material of the filling part 232 can also include a dielectric material such as silicon oxide or silicon nitride.

[0109] The filling part 232 can improve the structural strength of the filling structure 23 and improve the stress bearing capacity of the filling structure 23.

[0110] In other embodiments, the filling structure 23 can also only include the isolation layer 231, so that only the above step S310 can be included.

[0111] S330: removing the part of the isolation layer 231 covering the surface of the stack structure 21 away from the substrate 10.

[0112] Exemplarily, the portion of the isolation layer 231 covering the stack structure 21 away from the surface of the substrate 10 can be removed by dry etching.

[0113] S400: removing the substrate 10.

[0114] In some embodiments, the substrate 10 is removed. Figure 4I Exemplarily, the substrate 10 is removed by etching the substrate 10 to the third dielectric layer 11 to expose the portion of the isolation layer 231 of the fill structure 23 extending into the substrate 10.

[0115] In the case that the substrate 10 comprises the base 101, the sacrificial insulating layer 102 and the sacrificial polysilicon layer 103, the base 101 of the substrate 110 can be removed by a CMP, dry / wet etching process. Further, the sacrificial insulating layer 102 can be removed by a wet etching process with the sacrificial polysilicon layer 103 as the etching stop layer of the wet etching process. The sacrificial polysilicon layer 103 can be removed by a wet etching process with the third dielectric layer 11 as the etching stop layer of the wet etching process.

[0116] Exemplarily, the sacrificial polysilicon layer 113 of the substrate 110 can be removed by a wet etching process, and the etching can be stopped at the third dielectric layer 11 by selecting a predetermined etchant.

[0117] In the etching process of removing the substrate 10, the semiconductor layer 12 and the third dielectric layer 11 can be configured as etching stop layers. Specifically, the etching rate of the material of the third dielectric layer 11 can be different from the etching rate of the material of the semiconductor layer 12. Also, the etching rate of the material of the layer in the substrate 10 in contact with the third dielectric layer 11, such as the material of the sacrificial polysilicon layer 103, can be different from the etching rate of the material of the third dielectric layer 11. Exemplarily, the material of the third dielectric layer 11 comprises silicon oxide, and the material of the semiconductor layer 12 and the sacrificial polysilicon layer 103 are the same, both being polysilicon. Based on the above, in the three-dimensional memory 100 in Figure 4I In the three-dimensional memory 100 in, in the subsequent possible removal of the substrate 10 by an etching process, and / or removal of other materials with similar etching rate to the substrate 10, the third dielectric layer 11 can be exposed without further etching the semiconductor layer 12; in the subsequent possible removal of the third dielectric layer 11 by an etching process, and / or removal of other materials with similar etching rate to the third dielectric layer 11, the semiconductor layer 12 can be exposed without further etching the film layer disposed on the side of the semiconductor layer 12 away from the substrate 10, such as the first dielectric layer 131.

[0118] Further, in the process of forming the source layer 24, a laser annealing process can be performed. At this time, after the laser annealing process, the semiconductor layer 12 can serve as an interface layer, which can strengthen the combination of the source layer 24 and the stack structure 21.

[0119] In some embodiments, the third dielectric layer 11, the isolation layer 231 of the fill structure 23, and the barrier layer 1411 of the channel structure 14 are made of the same material, for example, all of them are made of silicon oxide. Removing the sacrificial polysilicon layer 113 in the substrate 110 by a wet etching process can expose the portion of the isolation layer 231 of the fill structure 23 extending into the substrate 10, and the portion of the functional layer 131 of the channel structure 14 extending into the substrate 10. The three-dimensional memory after the step S400 process is shown in Figure 4J .

[0120] In some embodiments, after the S400 removing the substrate 10, the method further comprises S410.

[0121] S410: referring to Figure 4K , etching the third dielectric layer 11 and the exposed portion of the isolation layer 231 to the semiconductor layer 12 to expose the filling portion 232 of the fill structure 23.

[0122] For example, the third dielectric layer 11 can be removed by a wet etching process, and a predetermined etchant is selected to stop the etching at the semiconductor layer 12.

[0123] In some embodiments, the semiconductor layer 12, the filling portion 232 of the fill structure 23, and the channel layer 143 of the channel structure 14 are made of the same material, for example, all of them are made of polysilicon. Removing the third dielectric layer 11 by a wet etching process can expose the portion of the filling portion 232 of the fill structure 23 extending into the substrate 10 (the portion protruding from the semiconductor layer 12), and the portion of the channel layer 143 of the channel structure 14 extending into the substrate 10 (the portion protruding from the semiconductor layer 12). The three-dimensional memory after the step S410 process is shown in Figure 4K .

[0124] S500: referring to Figure 4L , forming the source layer 24 on the side of the stack structure 21 where the substrate 10 is removed.

[0125] For example, the source layer 24 can be formed on the surface of the semiconductor layer 12, the filling portion 232 of the fill structure 23, and the channel layer 143 of the channel structure 14 away from the stack structure 21. The source layer 24 covers and is in contact with the exposed portion of the filling portion 232. The source layer 24 also covers and is in electrical connection with the exposed portion of the channel layer 143.

[0126] The three-dimensional memory 100 as shown in Figure 5 is formed by the above steps S100-S500, wherein, Figure 5 the three-dimensional memory 100 as shown in Figure 4LThe illustrated three-dimensional memory is flipped 180 degrees.

[0127] Referring to Figure 5 The three-dimensional memory 100 includes a source layer 24, a semiconductor layer 12, a stack structure 21, a channel structure 14, a second dielectric layer 17, and a gate line isolation structure 30. The semiconductor layer 12 is disposed on one side of the source layer 24. The stack structure 21 is disposed on a side of the semiconductor layer 12 away from the source layer 24, and includes a plurality of first dielectric layers 131 and a plurality of gate layers 19 disposed in an overlapping manner.

[0128] The three-dimensional memory 100 further includes the second dielectric layer 17, which is located between the first dielectric layer 131 and the gate layer 19.

[0129] The gate line isolation structure 30 penetrates the stack structure 21 in a direction perpendicular to the source layer 24 and extends into the source layer 24, and the gate line isolation structure 30 is in contact with the first dielectric layer 131.

[0130] For example, the gate line isolation structure 30 can include an isolation layer 231 and a filling portion 232 disposed in sequence; the isolation layer 231 is in contact with the first dielectric layer 131 and the semiconductor layer 12 on the side wall of the gate line gap 16; and the filling portion 232 extends into the source layer 24 and is in contact with the source layer 24.

[0131] In the three-dimensional memory 100 described above, the second dielectric layer 17 does not cover the side wall of the gate line gap 16, which can make the isolation layer 231 directly contact the first dielectric layer 131 and the semiconductor layer 12 on the side wall of the gate line gap 16. Compared with the bonding force between the semiconductor layer 12 and the second dielectric layer 17, the bonding force between the isolation layer 231 and the first dielectric layer 131 and the semiconductor layer 12 is higher, thereby reducing the risk of gaps between the isolation layer 231 and the first dielectric layer 131 and between the isolation layer 231 and the semiconductor layer 12.

[0132] In some embodiments, the first dielectric layer 131 has a recess 20 between adjacent first dielectric layers 131 in a direction perpendicular to the substrate 10. The three-dimensional memory 100 further includes a protective layer 22 disposed in the recess 20.

[0133] In some embodiments, referring to Figure 6 The three-dimensional memory 100 described above further includes an array interconnection layer 40 disposed on a side of the stack structure 21 away from the source layer 24, and a peripheral device 200 bonded to the array interconnection layer 40.

[0134] In some embodiments, the peripheral device 200 can include a peripheral circuit 210 and a peripheral interconnect layer 220 disposed on a side of the peripheral circuit 210 proximate to the array interconnect layer 50, the peripheral circuit 210 being electrically connected to the peripheral interconnect layer 220. The array interconnect layer 50 is bonded to the peripheral interconnect layer 220.

[0135] In some embodiments, referring to Figure 6 , the peripheral circuit 210 can include a second substrate 25 and an array of transistors 26 formed on the second substrate 25. The peripheral circuit 230 can include any active (or passive) components (e.g., transistors, diodes, resistors, capacitors, etc.) such as page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), or circuitry.

[0136] The above description is only specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any changes or replacements within the technical scope disclosed by the present application can be easily thought by those skilled in the art, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: Fabrication of semiconductor structures; The semiconductor structure includes: a substrate; a stacked structure disposed on the substrate, the stacked structure including a plurality of alternating first dielectric layers and gate layers; a gate line gap penetrating the stacked structure in a direction perpendicular to the substrate and extending into the substrate; a second dielectric layer disposed between the first dielectric layers and the gate layers, and covering the sidewalls of the gate line gap; and a recess between adjacent first dielectric layers in a direction perpendicular to the substrate. An initial protective layer is formed within the grid line slots, the initial protective layer filling the depressions and covering the sidewalls and bottom of the grid line slots; Remove the portion of the initial protective layer that covers the sidewalls and bottom of the grid line gaps, leaving the portion that fills the recesses, to form a protective layer; After the protective layer is formed, the portion of the sidewall covering the grid line gap in the second dielectric layer is removed; A filling structure is formed within the gaps in the grid lines; Remove the substrate; A source layer is formed on the side of the stacked structure where the substrate is removed.

2. The preparation method according to claim 1, characterized in that, The second dielectric layer also covers the surface of the stacked structure away from the substrate and the bottom of the gate gap; Before forming a protective layer within the depression, the preparation method further includes: Remove the portion of the second dielectric layer covering the surface of the stacked structure away from the substrate and the bottom of the gate line gap.

3. The preparation method according to claim 1, characterized in that, The fabrication of the semiconductor structure includes: An initial stacked structure is formed on the substrate; the initial stacked structure includes a plurality of alternating first dielectric layers and a plurality of gate sacrificial layers; A gate line slot is formed through the initial stacked structure along a direction perpendicular to the substrate; The gate sacrificial layer in the initial stacked structure is removed through the gate line gap to form a gate layer gap communicating with the gate line gap; A second dielectric layer and a gate layer are sequentially formed within the gate layer gap through the gate line gap.

4. The preparation method according to claim 3, characterized in that, Forming the gate layer includes: An initial gate layer is formed, which fills the gate layer gap and covers the sidewalls of the gate line gap and the surface of the initial stacked structure away from the substrate; Remove the sidewalls covering the gate line gaps and the portion of the stacked structure away from the substrate in the initial gate layer; The initial gate layer is formed by removing a portion of the gate layer gap that fills the gate layer gap.

5. The preparation method according to claim 4, characterized in that, Between forming the second dielectric layer and forming the gate layer, the fabrication method further includes: An initial adhesive layer is formed within the gate layer gap, and the initial adhesive layer covers the second dielectric layer; During the process of removing the initial gate layer to form the gate layer, the portion of the initial adhesive layer exposed by the gate layer is also removed to form an adhesive layer.

6. The preparation method according to any one of claims 1 to 5, characterized in that, A filling structure is formed within the grid line gaps, including: An isolation layer is formed within the grid line slots, and the isolation layer covers the sidewalls of the grid line slots to form a filling gap; A filling portion is formed within the filling gap.

7. The preparation method according to claim 6, characterized in that, The semiconductor structure further includes a third dielectric layer and a semiconductor layer disposed between the substrate and the stacked structure, wherein the third dielectric layer is closer to the substrate than the semiconductor layer; Removing the substrate includes: The substrate is etched down to the third dielectric layer to expose a portion of the isolation layer of the filling structure that extends into the substrate; Between removing the substrate and forming the source layer, the fabrication method further includes: The exposed portions of the third dielectric layer and the isolation layer are etched down to the semiconductor layer to expose the filling portion of the filling structure; The source layer covers the exposed portion of the filling portion and is in contact with the filling portion.

8. The preparation method according to claim 7, characterized in that, The semiconductor structure further includes a channel structure extending into the substrate, the channel structure including a channel hole and a functional layer and a channel layer sequentially formed in the channel hole; The etching of the substrate to the third dielectric layer also exposes a portion of the functional layer of the channel structure extending into the substrate; During the etching process from the exposed portions of the third dielectric layer and the isolation layer to the semiconductor layer, the exposed portions of the functional layer are also etched to expose the portion of the channel layer extending into the substrate; The source layer also covers the exposed portion of the channel layer.

9. The preparation method according to claim 7, characterized in that, Both the third dielectric layer and the isolation layer of the filling structure are made of silicon oxide. The materials of both the semiconductor layer and the filling portion of the filling structure include polycrystalline silicon.

10. The preparation method according to any one of claims 1 to 5, characterized in that, The material of the second dielectric layer includes a high dielectric constant material.

11. A method for fabricating a three-dimensional memory, characterized in that, include: Provide substrate; An initial stacked structure is formed on the substrate; the initial stacked structure includes a plurality of alternating first dielectric layers and a plurality of gate sacrificial layers; A gate line slot is formed; the gate line slot penetrates the initial stacked structure in a direction perpendicular to the substrate and extends into the substrate; The gate sacrificial layer in the initial stacked structure is removed through the gate line gap to form a gate layer gap communicating with the gate line gap; A second dielectric layer is formed, which covers the sidewalls of the gate layer gap and the sidewalls of the gate line slot; An initial gate layer is filled, wherein the initial gate layer fills the gate layer gap; Remove the portion of the initial gate layer near the gate line gap to form a recess; A protective layer is formed within the recess, the protective layer exposing the sidewalls and bottom of the grid line slot; After forming a protective layer in the recess, the portion of the sidewall covering the grid line gap in the second dielectric layer is removed; A filling structure is formed within the gaps in the grid lines; Remove the substrate; A source layer is formed on the side of the stacked structure where the substrate is removed.

12. A three-dimensional memory, characterized in that, include: Source layer; A stacked structure is disposed on one side of the source layer, comprising an overlapping first dielectric layer and a gate layer; A channel structure extends through the stacked structure and into the source layer along a direction perpendicular to the source layer. The channel structure includes a functional layer and a semiconductor layer, and the semiconductor layer and the source layer are electrically connected. A second dielectric layer is disposed between the first dielectric layer and the gate layer; A gate line isolation structure extends through the stacked structure in a direction perpendicular to the source layer and into the source layer, and the gate line isolation structure is in contact with the first dielectric layer. A protective layer is disposed between the gate layer and the gate line isolation structure, and is located between adjacent first dielectric layers in a direction perpendicular to the source layer.

13. The three-dimensional memory according to claim 12, characterized in that, The material of the second dielectric layer includes a high dielectric constant material.

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